56205 lines
2.3 MiB
56205 lines
2.3 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>LPC408x_7x</name>
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<version>0.7</version>
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<description>LPC408x/7x M4</description>
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<cpu>
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<name>CM4</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>0</mpuPresent>
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<fpuPresent>0</fpuPresent>
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<nvicPrioBits>3</nvicPrioBits>
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<vendorSystickConfig>0</vendorSystickConfig>
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</cpu>
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<!--
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<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix> -->
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<!--
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Software that is described herein is for illustrative purposes only
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which provides customers with programming information regarding the
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products. This software is supplied "AS IS" without any warranties.
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NXP Semiconductors assumes no responsibility or liability for the
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use of the software, conveys no license or title under any patent,
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copyright, or mask work right to the product. NXP Semiconductors
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reserves the right to make changes in the software without
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notification. NXP Semiconductors also make no representation or
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warranty that such application will be suitable for the specified
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use without further testing or modification.
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-->
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<!--
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V0.6 changes
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- renamed gpio bitfield names to be different from register names and removed port0 from register description
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- removed dim tags from PWM registers MR4 to MR6
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- added <readaction>modify</readaction> tags to uart rbr, lsr, msr, i2s rxfifo, and ssp dr registers.
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v0.7 changes
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- added EEADDR register in FLASHCTRL
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-->
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<peripherals>
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<peripheral>
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<name>FLASHCTRL</name>
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<description>EEPROM/flash</description>
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<groupName>FLASHCTRL</groupName>
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<baseAddress>0x00200000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0xFFF</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>EEPROM</name>
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<value>40</value>
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</interrupt>
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<registers>
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<register>
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<name>FMSSTART</name>
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<description>Signature start address register</description>
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<addressOffset>0x020</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>START</name>
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<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
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<bitRange>[16:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:17]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>FMSSTOP</name>
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<description>Signature stop-address register</description>
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<addressOffset>0x024</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>STOP</name>
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<description>BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).</description>
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<bitRange>[16:0]</bitRange>
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</field>
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<field>
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<name>SIG_START</name>
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<description>Start control bit for signature generation.</description>
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<bitRange>[17:17]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>STOP</name>
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<description>Signature generation is stopped</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>START</name>
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<description>Initiate signature generation</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:18]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>FMSW0</name>
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<description>128-bit signature Word 0</description>
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<addressOffset>0x02C</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>SW0_31_0</name>
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<description>Word 0 of 128-bit signature (bits 31 to 0).</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>FMSW1</name>
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<description>128-bit signature Word 1</description>
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<addressOffset>0x030</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>SW1_63_32</name>
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<description>Word 1 of 128-bit signature (bits 63 to 32).</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>FMSW2</name>
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<description>128-bit signature Word 2</description>
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<addressOffset>0x034</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>SW2_95_64</name>
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<description>Word 2 of 128-bit signature (bits 95 to 64).</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>FMSW3</name>
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<description>128-bit signature Word 3</description>
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<addressOffset>0x038</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>SW3_127_96</name>
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<description>Word 3 of 128-bit signature (bits 127 to 96).</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EECMD</name>
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<description>EEPROM command register</description>
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<addressOffset>0x080</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>CMD</name>
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<description>Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved</description>
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<bitRange>[2:0]</bitRange>
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</field>
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<field>
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<name>RDPREFETCH</name>
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<description>Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:4]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EEADDR</name>
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<description>EEPROM address register</description>
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<addressOffset>0x084</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>ADDR</name>
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<description>EEPROM Address. Lower 6 bits are don't care.</description>
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<bitRange>[11:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:12]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EEWDATA</name>
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<description>EEPROM write data register</description>
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<addressOffset>0x088</addressOffset>
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<access>write-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>WDATA</name>
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<description>Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data.</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EERDATA</name>
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<description>EEPROM read data register</description>
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<addressOffset>0x08C</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>RDATA</name>
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<description>Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data.</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EEWSTATE</name>
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<description>EEPROM wait state register</description>
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<addressOffset>0x090</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>PHASE3</name>
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<description>Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns.</description>
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<bitRange>[7:0]</bitRange>
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</field>
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<field>
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<name>PHASE2</name>
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<description>Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns.</description>
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<bitRange>[15:8]</bitRange>
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</field>
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<field>
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<name>PHASE1</name>
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<description>Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns.</description>
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<bitRange>[23:16]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:24]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EECLKDIV</name>
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<description>EEPROM clock divider register</description>
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<addressOffset>0x094</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>CLKDIV</name>
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<description>Division factor (minus 1 encoded).</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>EEPWRDWN</name>
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<description>EEPROM power-down register</description>
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<addressOffset>0x098</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>PWRDWN</name>
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<description>Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down).</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:1]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>STAT</name>
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<description>Signature generation status register</description>
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<addressOffset>0xFE0</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[1:0]</bitRange>
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</field>
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<field>
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<name>SIG_DONE</name>
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<description>When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[25:3]</bitRange>
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</field>
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<field>
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<name>END_OF_RDWR</name>
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<description>EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register.</description>
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<bitRange>[26:26]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[27:27]</bitRange>
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</field>
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<field>
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<name>END_OF_PROG1</name>
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<description>EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register.</description>
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<bitRange>[28:28]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:29]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>INTEN</name>
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<description>EEPROM interrupt enable</description>
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<addressOffset>0xFE4</addressOffset>
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<access>read-only</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[25:0]</bitRange>
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</field>
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<field>
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<name>EE_RW_DONE</name>
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<description>EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register.</description>
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<bitRange>[26:26]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[27:27]</bitRange>
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</field>
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<field>
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<name>EE_PROG_DONE</name>
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<description>EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register.</description>
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<bitRange>[28:28]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:29]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>STATCLR</name>
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<description>Signature generation status clear register</description>
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<addressOffset>0xFE8</addressOffset>
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<access>write-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[1:0]</bitRange>
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</field>
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<field>
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<name>SIG_DONE_CLR</name>
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<description>Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[25:3]</bitRange>
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</field>
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<field>
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<name>RDWR_CLR_ST</name>
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<description>Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit.</description>
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<bitRange>[26:26]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[27:27]</bitRange>
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</field>
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<field>
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<name>PROG1_CLR_ST</name>
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<description>Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit.</description>
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<bitRange>[28:28]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[31:29]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>ENCLR</name>
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<description>EEPROM interrupt enable clear</description>
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<addressOffset>0xFD8</addressOffset>
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<access>write-only</access>
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<resetValue>0</resetValue>
|
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<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
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<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
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<bitRange>[25:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDWR_CLR_EN</name>
|
|
<description>Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROG1_CLR_EN</name>
|
|
<description>Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENSET</name>
|
|
<description>EEPROM interrupt enable set</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[25:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDWR_SET_EN</name>
|
|
<description>Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROG1_SET_EN</name>
|
|
<description>Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPDMA</name>
|
|
<description>General Purpose DMA controller Modification</description>
|
|
<groupName>GPDMA</groupName>
|
|
<baseAddress>0x20080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPDMA</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>DMA Interrupt Status Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTAT0</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT1</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT2</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT3</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT4</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT5</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT6</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT7</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTTCSTAT</name>
|
|
<description>DMA Interrupt Terminal Count Request Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTTCSTAT0</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT1</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT2</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT3</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT4</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT5</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT6</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT7</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTTCCLEAR</name>
|
|
<description>DMA Interrupt Terminal Count Request Clear Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTTCCLEAR0</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR1</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR2</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR3</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR4</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR5</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR6</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR7</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTERRSTAT</name>
|
|
<description>DMA Interrupt Error Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRSTAT0</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT1</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT2</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT3</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT4</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT5</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT6</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT7</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTERRCLR</name>
|
|
<description>DMA Interrupt Error Clear Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRCLR0</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR1</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR2</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR3</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR4</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR5</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR6</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR7</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAWINTTCSTAT</name>
|
|
<description>DMA Raw Interrupt Terminal Count Status Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAWINTTCSTAT0</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT1</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT2</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT3</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT4</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT5</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT6</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT7</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAWINTERRSTAT</name>
|
|
<description>DMA Raw Error Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAWINTERRSTAT0</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT1</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT2</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT3</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT4</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT5</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT6</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT7</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENBLDCHNS</name>
|
|
<description>DMA Enabled Channel Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLEDCHANNELS0</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS1</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS2</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS3</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS4</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS5</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS6</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS7</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTBREQ</name>
|
|
<description>DMA Software Burst Request Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTBREQ0</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ1</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ2</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ3</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ4</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ5</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ6</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ7</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ8</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ9</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ10</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ11</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ12</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ13</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ14</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ15</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTSREQ</name>
|
|
<description>DMA Software Single Request Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTSREQ0</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ1</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ2</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ3</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ4</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ5</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ6</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ7</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ8</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ9</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ10</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ11</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ12</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ13</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ14</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ15</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTLBREQ</name>
|
|
<description>DMA Software Last Burst Request Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTLBREQ0</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ1</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ2</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ3</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ4</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ5</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ6</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ7</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ8</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ9</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ10</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ11</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ12</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ13</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ14</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ15</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTLSREQ</name>
|
|
<description>DMA Software Last Single Request Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTLSREQ0</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ1</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ2</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ3</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ4</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ5</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ6</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ7</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ8</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ9</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ10</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ11</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ12</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ13</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ14</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ15</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>DMA Configuration Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>DMA Synchronization Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMACSYNC0</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC1</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC2</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC3</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC4</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC5</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC6</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC7</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC8</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC9</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC10</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC11</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC12</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC13</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC14</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC15</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>SRCADDR%s</name>
|
|
|
|
<description>DMA Channel 0 Source Address Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRCADDR</name>
|
|
<description>DMA source address. Reading this register will return the current source address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DESTADDR%s</name>
|
|
|
|
<description>DMA Channel 0 Destination Address Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DESTADDR</name>
|
|
<description>DMA Destination address. Reading this register will return the current destination address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>LLI%s</name>
|
|
|
|
<description>DMA Channel 0 Linked List Item Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, and must be written as 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LLI</name>
|
|
<description>Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CONTROL%s</name>
|
|
|
|
<description>DMA Channel 0 Control Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRANSFERSIZE</name>
|
|
<description>Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBSIZE</name>
|
|
<description>Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DBSIZE</name>
|
|
<description>Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256</description>
|
|
<bitRange>[17:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SWIDTH</name>
|
|
<description>Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved</description>
|
|
<bitRange>[20:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DWIDTH</name>
|
|
<description>Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, and must be written as 0.</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SI</name>
|
|
<description>Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DI</name>
|
|
<description>Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROT2</name>
|
|
<description>This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROT3</name>
|
|
<description>This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I</name>
|
|
<description>Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CONFIG%s</name>
|
|
|
|
<description>DMA Channel 0 Configuration Register[1]</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRCPERIPHERAL</name>
|
|
<description>Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DESTPERIPHERAL</name>
|
|
<description>Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRANSFERTYPE</name>
|
|
<description>This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>A</name>
|
|
<description>Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>H</name>
|
|
<description>Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>ETHERNET</name>
|
|
<description>Ethernet</description>
|
|
<groupName>ETHERNET</groupName>
|
|
<baseAddress>0x20084000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ETHERNET</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MAC1</name>
|
|
<description>MAC configuration register 1.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENABLE</name>
|
|
<description>RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARF</name>
|
|
<description>PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFLOWCTRL</name>
|
|
<description>RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFLOWCTRL</name>
|
|
<description>TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESETTX</name>
|
|
<description>Setting this bit will put the Transmit Function logic in reset.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESETMCSTX</name>
|
|
<description>Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESETRX</name>
|
|
<description>Setting this bit will put the Ethernet receive logic in reset.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESETMCSRX</name>
|
|
<description>Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIMRESET</name>
|
|
<description>SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTRESET</name>
|
|
<description>SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC2</name>
|
|
<description>MAC configuration register 2.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FULLDUPLEX</name>
|
|
<description>When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLC</name>
|
|
<description>FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HFEN</name>
|
|
<description>HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELAYEDCRC</name>
|
|
<description>DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PADCRCEN</name>
|
|
<description>PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLANPADEN</name>
|
|
<description>VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTODETPADEN</name>
|
|
<description>AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPENF</name>
|
|
<description>PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LPENF</name>
|
|
<description>LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOBACKOFF</name>
|
|
<description>When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BP_NOBACKOFF</name>
|
|
<description>BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXCESSDEFER</name>
|
|
<description>When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPGT</name>
|
|
<description>Back-to-Back Inter-Packet-Gap register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BTOBINTEGAP</name>
|
|
<description>BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPGR</name>
|
|
<description>Non Back-to-Back Inter-Packet-Gap register.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBTOBINTEGAP2</name>
|
|
<description>NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NBTOBINTEGAP1</name>
|
|
<description>NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLRT</name>
|
|
<description>Collision window / Retry register.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x370F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RETRANSMAX</name>
|
|
<description>RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COLLWIN</name>
|
|
<description>COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXF</name>
|
|
<description>Maximum Frame register.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0600</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXFLEN</name>
|
|
<description>MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUPP</name>
|
|
<description>PHY Support register.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<description>Test register.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCPQ</name>
|
|
<description>SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TESTPAUSE</name>
|
|
<description>This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TESTBP</name>
|
|
<description>TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFG</name>
|
|
<description>MII Mgmt Configuration register.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANINC</name>
|
|
<description>SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SUPPPREAMBLE</name>
|
|
<description>SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLOCKSEL</name>
|
|
<description>CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field.</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESETMIIMGMT</name>
|
|
<description>RESET MII MGMT. This bit resets the MII Management hardware.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMD</name>
|
|
<description>MII Mgmt Command register.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>READ</name>
|
|
<description>This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MADR</name>
|
|
<description>MII Mgmt Address register.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGADDR</name>
|
|
<description>REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PHYADDR</name>
|
|
<description>PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MWTD</name>
|
|
<description>MII Mgmt Write Data register.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRITEDATA</name>
|
|
<description>WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRDD</name>
|
|
<description>MII Mgmt Read Data register.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>READDATA</name>
|
|
<description>READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIND</name>
|
|
<description>MII Mgmt Indicators register.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCANNING</name>
|
|
<description>When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTVALID</name>
|
|
<description>When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MIILINKFAIL</name>
|
|
<description>When 1 is returned - indicates that an MII Mgmt link fail has occurred.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SA0</name>
|
|
<description>Station Address 0 register.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR2</name>
|
|
<description>STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SADDR1</name>
|
|
<description>STATION ADDRESS, 1st octet. This field holds the first octet of the station address.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SA1</name>
|
|
<description>Station Address 1 register.</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR4</name>
|
|
<description>STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SADDR3</name>
|
|
<description>STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SA2</name>
|
|
<description>Station Address 2 register.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR6</name>
|
|
<description>STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SADDR5</name>
|
|
<description>STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMMAND</name>
|
|
<description>Command register.</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENABLE</name>
|
|
<description>Enable receive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXENABLE</name>
|
|
<description>Enable transmit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REGRESET</name>
|
|
<description>When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRESET</name>
|
|
<description>When a 1 is written, the transmit datapath is reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRESET</name>
|
|
<description>When a 1 is written, the receive datapath is reset.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PASSRUNTFRAME</name>
|
|
<description>When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PASSRXFILTER</name>
|
|
<description>When set to 1 , disables receive filtering i.e. all frames received are written to memory.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFLOWCONTROL</name>
|
|
<description>Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RMII</name>
|
|
<description>When set to 1 , RMII mode is selected; if 0, MII mode is selected.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FULLDUPLEX</name>
|
|
<description>When set to 1 , indicates full duplex operation.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status register.</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXSTATUS</name>
|
|
<description>If 1, the receive channel is active. If 0, the receive channel is inactive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSTATUS</name>
|
|
<description>If 1, the transmit channel is active. If 0, the transmit channel is inactive.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDESCRIPTOR</name>
|
|
<description>Receive descriptor base address register.</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Fixed to 00</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDESCRIPTOR</name>
|
|
<description>MSBs of receive descriptor base address.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXSTATUS</name>
|
|
<description>Receive status base address register.</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Fixed to 000</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSTATUS</name>
|
|
<description>MSBs of receive status base address.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDESCRIPTORNUMBER</name>
|
|
<description>Receive number of descriptors register.</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDESCRIPTORN</name>
|
|
<description>RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPRODUCEINDEX</name>
|
|
<description>Receive produce index register.</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRODUCEIX</name>
|
|
<description>Index of the descriptor that is going to be filled next by the receive datapath.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCONSUMEINDEX</name>
|
|
<description>Receive consume index register.</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCONSUMEIX</name>
|
|
<description>Index of the descriptor that is going to be processed next by the receive</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDESCRIPTOR</name>
|
|
<description>Transmit descriptor base address register.</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Fixed to 00</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TxDescriptor. MSBs of transmit descriptor base address.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXSTATUS</name>
|
|
<description>Transmit status base address register.</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Fixed to 00</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSTAT</name>
|
|
<description>TxStatus. MSBs of transmit status base address.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDESCRIPTORNUMBER</name>
|
|
<description>Transmit number of descriptors register.</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDN</name>
|
|
<description>TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXPRODUCEINDEX</name>
|
|
<description>Transmit produce index register.</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXPI</name>
|
|
<description>TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCONSUMEINDEX</name>
|
|
<description>Transmit consume index register.</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCI</name>
|
|
<description>TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSV0</name>
|
|
<description>Transmit status vector 0 register.</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC error. The attached CRC in the packet did not match the internally generated CRC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCE</name>
|
|
<description>Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOR</name>
|
|
<description>Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Transmission of packet was completed.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULTICAST</name>
|
|
<description>Packet's destination was a multicast address.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BROADCAST</name>
|
|
<description>Packet's destination was a broadcast address.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PACKETDEFER</name>
|
|
<description>Packet was deferred for at least one attempt, but less than an excessive defer.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXDF</name>
|
|
<description>Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXCOL</name>
|
|
<description>Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCOL</name>
|
|
<description>Late Collision. Collision occurred beyond collision window, 512 bit times.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GIANT</name>
|
|
<description>Byte count in frame was greater than can be represented in the transmit byte count field in TSV1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UNDERRUN</name>
|
|
<description>Host side caused buffer underrun.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TOTALBYTES</name>
|
|
<description>The total number of bytes transferred including collided attempts.</description>
|
|
<bitRange>[27:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CONTROLFRAME</name>
|
|
<description>The frame was a control frame.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PAUSE</name>
|
|
<description>The frame was a control frame with a valid PAUSE opcode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BACKPRESSURE</name>
|
|
<description>Carrier-sense method backpressure was previously applied.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLAN</name>
|
|
<description>Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSV1</name>
|
|
<description>Transmit status vector 1 register.</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBC</name>
|
|
<description>Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TCC</name>
|
|
<description>Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSV</name>
|
|
<description>Receive status vector register.</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBC</name>
|
|
<description>Received byte count. Indicates length of received frame.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPI</name>
|
|
<description>Packet previously ignored. Indicates that a packet was dropped.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDVSEEN</name>
|
|
<description>RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CESEEN</name>
|
|
<description>Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCV</name>
|
|
<description>Receive code violation. Indicates that received PHY data does not represent a valid receive code.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC error. The attached CRC in the packet did not match the internally generated CRC.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCERR</name>
|
|
<description>Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOR</name>
|
|
<description>Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROK</name>
|
|
<description>Receive OK. The packet had valid CRC and no symbol errors.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULTICAST</name>
|
|
<description>The packet destination was a multicast address.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BROADCAST</name>
|
|
<description>The packet destination was a broadcast address.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRIBBLENIBBLE</name>
|
|
<description>Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CONTROLFRAME</name>
|
|
<description>The frame was a control frame.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PAUSE</name>
|
|
<description>The frame was a control frame with a valid PAUSE opcode.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UO</name>
|
|
<description>Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VLAN</name>
|
|
<description>Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCONTROLCOUNTER</name>
|
|
<description>Flow control counter register.</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCONTROLSTATUS</name>
|
|
<description>Flow control status register.</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCC</name>
|
|
<description>MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFILTERCTRL</name>
|
|
<description>Receive filter control register.</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUE</name>
|
|
<description>AcceptUnicastEn. When set to 1, all unicast frames are accepted.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABE</name>
|
|
<description>AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AME</name>
|
|
<description>AcceptMulticastEn. When set to 1, all multicast frames are accepted.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUHE</name>
|
|
<description>AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMHE</name>
|
|
<description>AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APE</name>
|
|
<description>AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPEW</name>
|
|
<description>MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFEW</name>
|
|
<description>RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFILTERWOLSTATUS</name>
|
|
<description>Receive filter WoL status register.</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUW</name>
|
|
<description>AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABW</name>
|
|
<description>AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMW</name>
|
|
<description>AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUHW</name>
|
|
<description>AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMHW</name>
|
|
<description>AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APW</name>
|
|
<description>AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFW</name>
|
|
<description>RxFilterWoL. When the value is 1, the receive filter caused WoL.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPW</name>
|
|
<description>MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFILTERWOLCLEAR</name>
|
|
<description>Receive filter WoL clear register.</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUWCLR</name>
|
|
<description>AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABWCLR</name>
|
|
<description>AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMWCLR</name>
|
|
<description>AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUHWCLR</name>
|
|
<description>AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMHWCLR</name>
|
|
<description>AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APWCLR</name>
|
|
<description>AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFWCLR</name>
|
|
<description>RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPWCLR</name>
|
|
<description>MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HASHFILTERL</name>
|
|
<description>Hash filter table LSBs register.</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFL</name>
|
|
<description>HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HASHFILTERH</name>
|
|
<description>Hash filter table MSBs register.</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFH</name>
|
|
<description>Bits 63:32 of the imperfect filter hash table for receive filtering.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status register.</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXOVERRUNINT</name>
|
|
<description>Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXERRORINT</name>
|
|
<description>Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFINISHEDINT</name>
|
|
<description>Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDONEINT</name>
|
|
<description>Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUNINT</name>
|
|
<description>Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXERRORINT</name>
|
|
<description>Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFINISHEDINT</name>
|
|
<description>Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDONEINT</name>
|
|
<description>Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTINT</name>
|
|
<description>Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPINT</name>
|
|
<description>Interrupt triggered by a Wake-up event detected by the receive filter.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENABLE</name>
|
|
<description>Interrupt enable register.</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXOVERRUNINTEN</name>
|
|
<description>Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXERRORINTEN</name>
|
|
<description>Enable for interrupt trigger on receive errors.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFINISHEDINTEN</name>
|
|
<description>Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDONEINTEN</name>
|
|
<description>Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUNINTEN</name>
|
|
<description>Enable for interrupt trigger on transmit buffer or descriptor underrun situations.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXERRORINTEN</name>
|
|
<description>Enable for interrupt trigger on transmit errors.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFINISHEDINTEN</name>
|
|
<description>Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDONEINTEN</name>
|
|
<description>Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTINTEN</name>
|
|
<description>Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPINTEN</name>
|
|
<description>Enable for interrupt triggered by a Wake-up event detected by the receive filter.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLEAR</name>
|
|
<description>Interrupt clear register.</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXOVERRUNINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXERRORINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFINISHEDINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDONEINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUNINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXERRORINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFINISHEDINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDONEINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPINTCLR</name>
|
|
<description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>Interrupt set register.</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXOVERRUNINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXERRORINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFINISHEDINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDONEINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUNINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXERRORINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFINISHEDINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDONEINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPINTSET</name>
|
|
<description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWERDOWN</name>
|
|
<description>Power-down register.</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LCD</name>
|
|
<description>LCD controller Modification </description>
|
|
<groupName>LCD</groupName>
|
|
<baseAddress>0x20088000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LCD</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMH</name>
|
|
<description>Horizontal Timing Control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPL</name>
|
|
<description>Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HSW</name>
|
|
<description>Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HFP</name>
|
|
<description>Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HBP</name>
|
|
<description>Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMV</name>
|
|
<description>Vertical Timing Control register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPP</name>
|
|
<description>Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VSW</name>
|
|
<description>Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VFP</name>
|
|
<description>Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VBP</name>
|
|
<description>Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Clock and Signal Polarity Control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCD_LO</name>
|
|
<description>Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACB</name>
|
|
<description>AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal.</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IVS</name>
|
|
<description>Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IHS</name>
|
|
<description>Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IPC</name>
|
|
<description>Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IOE</name>
|
|
<description>Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly.</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BCD</name>
|
|
<description>Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCD_HI</name>
|
|
<description>Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register.</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LE</name>
|
|
<description>Line End Control register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LED</name>
|
|
<description>Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LEE</name>
|
|
<description>LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UPBASE</name>
|
|
<description>Upper Panel Frame Base Address register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDUPBASE</name>
|
|
<description>LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPBASE</name>
|
|
<description>Lower Panel Frame Base Address register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDLPBASE</name>
|
|
<description>LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LCD Control register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDEN</name>
|
|
<description>LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDBPP</name>
|
|
<description>LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDBW</name>
|
|
<description>STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDTFT</name>
|
|
<description>LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDMONO8</name>
|
|
<description>Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDDUAL</name>
|
|
<description>Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BGR</name>
|
|
<description>Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BEBO</name>
|
|
<description>Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BEPO</name>
|
|
<description>Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDPWR</name>
|
|
<description>LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDVCOMP</name>
|
|
<description>LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WATERMARK</name>
|
|
<description>LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTMSK</name>
|
|
<description>Interrupt Mask register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFIM</name>
|
|
<description>FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUIM</name>
|
|
<description>LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPIM</name>
|
|
<description>Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERIM</name>
|
|
<description>AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTRAW</name>
|
|
<description>Raw Interrupt Status register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFRIS</name>
|
|
<description>FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBURIS</name>
|
|
<description>LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPRIS</name>
|
|
<description>Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERRAW</name>
|
|
<description>AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Masked Interrupt Status register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFMIS</name>
|
|
<description>FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUMIS</name>
|
|
<description>LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPMIS</name>
|
|
<description>Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERMIS</name>
|
|
<description>AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>Interrupt Clear register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFIC</name>
|
|
<description>FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUIC</name>
|
|
<description>LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPIC</name>
|
|
<description>Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERIC</name>
|
|
<description>AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UPCURR</name>
|
|
<description>Upper Panel Current Address Value register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDUPCURR</name>
|
|
<description>LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPCURR</name>
|
|
<description>Lower Panel Current Address Value register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDLPCURR</name>
|
|
<description>LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>128</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-127</dimIndex>
|
|
<name>PAL[%s]</name>
|
|
<displayName>PAL[%s]</displayName>
|
|
<description>256x16-bit Color Palette registers</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R04_0</name>
|
|
<description>Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>G04_0</name>
|
|
<description>Green palette data.</description>
|
|
<bitRange>[9:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>B04_0</name>
|
|
<description>Blue palette data.</description>
|
|
<bitRange>[14:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I0</name>
|
|
<description>Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>R14_0</name>
|
|
<description>Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>G14_0</name>
|
|
<description>Green palette data.</description>
|
|
<bitRange>[25:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>B14_0</name>
|
|
<description>Blue palette data.</description>
|
|
<bitRange>[30:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I1</name>
|
|
<description>Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>CRSR_IMG[%s]</name>
|
|
<displayName>CRSR_IMG[%s]</displayName>
|
|
<description>Cursor Image registers</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSR_IMG</name>
|
|
<description>Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CTRL</name>
|
|
<description>Cursor Control register</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRON</name>
|
|
<description>Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRNUM1_0</name>
|
|
<description>Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CFG</name>
|
|
<description>Cursor Configuration register</description>
|
|
<addressOffset>0xC04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRSIZE</name>
|
|
<description>Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMESYNC</name>
|
|
<description>Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_PAL0</name>
|
|
<description>Cursor Palette register 0</description>
|
|
<addressOffset>0xC08</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red color component</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green color component</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue color component.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_PAL1</name>
|
|
<description>Cursor Palette register 1</description>
|
|
<addressOffset>0xC0C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red color component</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green color component</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue color component.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_XY</name>
|
|
<description>Cursor XY Position register</description>
|
|
<addressOffset>0xC10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRX</name>
|
|
<description>X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRY</name>
|
|
<description>Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display.</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CLIP</name>
|
|
<description>Cursor Clip Position register</description>
|
|
<addressOffset>0xC14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRCLIPX</name>
|
|
<description>Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRCLIPY</name>
|
|
<description>Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTMSK</name>
|
|
<description>Cursor Interrupt Mask register</description>
|
|
<addressOffset>0xC20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRIM</name>
|
|
<description>Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTCLR</name>
|
|
<description>Cursor Interrupt Clear register</description>
|
|
<addressOffset>0xC24</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRIC</name>
|
|
<description>Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTRAW</name>
|
|
<description>Cursor Raw Interrupt Status register</description>
|
|
<addressOffset>0xC28</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRRIS</name>
|
|
<description>Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTSTAT</name>
|
|
<description>Cursor Masked Interrupt Status register</description>
|
|
<addressOffset>0xC2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRMIS</name>
|
|
<description>Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description> USB device controller </description>
|
|
<groupName>USB</groupName>
|
|
<baseAddress>0x2008C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_NEED_CLK</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTST</name>
|
|
<description>OTG Interrupt Status</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR</name>
|
|
<description>Timer time-out.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REMOVE_PU</name>
|
|
<description>Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_FAILURE</name>
|
|
<description>HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_SUCCESS</name>
|
|
<description>HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>OTG Interrupt Enable</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR_EN</name>
|
|
<description>1 = enable the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REMOVE_PU_EN</name>
|
|
<description>1 = enable the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_FAILURE_EN</name>
|
|
<description>1 = enable the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_SUCCES_EN</name>
|
|
<description>1 = enable the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSET</name>
|
|
<description>OTG Interrupt Set</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR_SET</name>
|
|
<description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REMOVE_PU_SET</name>
|
|
<description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_FAILURE_SET</name>
|
|
<description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_SUCCES_SET</name>
|
|
<description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INCLR</name>
|
|
<description>OTG Interrupt Clear</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR_CLR</name>
|
|
<description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REMOVE_PU_CLR</name>
|
|
<description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_FAILURE_CLR</name>
|
|
<description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HNP_SUCCES_CLR</name>
|
|
<description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSEL</name>
|
|
<description>USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2.</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORTSEL</name>
|
|
<description>Selects which USB port the device controller signals are mapped to. Other values are reserved.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORTU1</name>
|
|
<description>The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTU2</name>
|
|
<description>The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMR_SCALE</name>
|
|
<description>Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMR_MODE</name>
|
|
<description>Timer mode selection. 0: monoshot 1: free running</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMR_EN</name>
|
|
<description>Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMR_RST</name>
|
|
<description>Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>B_HNP_TRACK</name>
|
|
<description>Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>A_HNP_TRACK</name>
|
|
<description>Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PU_REMOVED</name>
|
|
<description>When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TMR_CNT</name>
|
|
<description>Current timer count value.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR</name>
|
|
<description>OTG Timer</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUT_CNT</name>
|
|
<description>The TMR interrupt is set when TMR_CNT reaches this value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
<register>
|
|
<name>DEVINTST</name>
|
|
<description>USB Device Interrupt Status</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_FAST</name>
|
|
<description>Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_SLOW</name>
|
|
<description>Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_STAT</name>
|
|
<description>Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CCEMPTY</name>
|
|
<description>The command code register (USBCmdCode) is empty (New command can be written).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDFULL</name>
|
|
<description>Command data register (USBCmdData) is full (Data can be read now).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RxENDPKT</name>
|
|
<description>The current packet in the endpoint buffer is transferred to the CPU.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TxENDPKT</name>
|
|
<description>The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_RLZED</name>
|
|
<description>Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVINTEN</name>
|
|
<description>USB Device Interrupt Enable</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMEEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_FASTEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_SLOWEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_STATEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CCEMPTYEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDFULLEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RxENDPKTEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TxENDPKTEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_RLZEDEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INTEN</name>
|
|
<description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVINTCLR</name>
|
|
<description>USB Device Interrupt Clear</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMECLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_FASTCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_SLOWCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_STATCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CCEMPTYCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDFULLCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RxENDPKTCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TxENDPKTCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_RLZEDCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INTCLR</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVINTSET</name>
|
|
<description>USB Device Interrupt Set</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMESET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_FASTSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_SLOWSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_STATSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CCEMPTYSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDFULLSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RxENDPKTSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TxENDPKTSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_RLZEDSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INTSET</name>
|
|
<description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVINTPRI</name>
|
|
<description>USB Device Interrupt Priority</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Frame interrupt routing</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LP</name>
|
|
<description>FRAME interrupt is routed to USB_INT_REQ_LP.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP</name>
|
|
<description>FRAME interrupt is routed to USB_INT_REQ_HP.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP_FAST</name>
|
|
<description>Fast endpoint interrupt routing</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LP</name>
|
|
<description>EP_FAST interrupt is routed to USB_INT_REQ_LP.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP</name>
|
|
<description>EP_FAST interrupt is routed to USB_INT_REQ_HP.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTST</name>
|
|
<description>USB Endpoint Interrupt Status</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPST0</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST1</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST2</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST3</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST4</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST5</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST6</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST7</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST8</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST9</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST10</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST11</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST12</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST13</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST14</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST15</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST16</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST17</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST18</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST19</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST20</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST21</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST22</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST23</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST24</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST25</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST26</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST27</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST28</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST29</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST30</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPST31</name>
|
|
<description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTEN</name>
|
|
<description>USB Endpoint Interrupt Enable</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN0</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN1</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN2</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN3</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN4</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN5</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN6</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN7</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN8</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN9</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN10</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN11</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN12</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN13</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN14</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN15</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN16</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN17</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN18</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN19</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN20</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN21</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN22</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN23</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN24</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN25</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN26</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN27</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN28</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN29</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN30</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPEN31</name>
|
|
<description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTCLR</name>
|
|
<description>USB Endpoint Interrupt Clear</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPCLR0</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR1</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR2</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR3</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR4</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR5</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR6</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR7</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR8</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR9</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR10</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR11</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR12</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR13</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR14</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR15</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR16</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR17</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR18</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR19</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR20</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR21</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR22</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR23</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR24</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR25</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR26</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR27</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR28</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR29</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR30</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPCLR31</name>
|
|
<description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTSET</name>
|
|
<description>USB Endpoint Interrupt Set</description>
|
|
<addressOffset>0x23C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPSET0</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET1</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET2</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET3</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET4</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET5</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET6</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET7</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET8</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET9</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET10</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET11</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET12</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET13</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET14</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET15</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET16</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET17</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET18</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET19</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET20</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET21</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET22</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET23</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET24</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET25</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET26</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET27</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET28</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET29</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET30</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPSET31</name>
|
|
<description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINTPRI</name>
|
|
<description>USB Endpoint Priority</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPPRI0</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI1</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI2</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI3</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI4</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI5</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI6</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI7</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI8</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI9</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI10</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI11</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI12</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI13</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI14</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI15</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI16</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI17</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI18</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI19</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI20</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI21</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI22</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI23</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI24</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI25</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI26</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI27</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI28</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI29</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI30</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPPRI31</name>
|
|
<description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REEP</name>
|
|
<description>USB Realize Endpoint</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPR0</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR1</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR2</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR3</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR4</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR5</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR6</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR7</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR8</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR9</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR10</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR11</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR12</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR13</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR14</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR15</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR16</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR17</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR18</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR19</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR20</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR21</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR22</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR23</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR24</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR25</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR26</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR27</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR28</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR29</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR30</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPR31</name>
|
|
<description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPIN</name>
|
|
<description>USB Endpoint Index</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHY_EP</name>
|
|
<description>Physical endpoint number (0-31)</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXPSIZE</name>
|
|
<description>USB MaxPacketSize</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>The maximum packet size value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>USB Receive Data</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DATA</name>
|
|
<description>Data received.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPLEN</name>
|
|
<description>USB Receive Packet Length</description>
|
|
<addressOffset>220</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKT_LNGTH</name>
|
|
<description>The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DV</name>
|
|
<description>Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DATA_IS_INVALID_</name>
|
|
<description>Data is invalid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_IS_VALID_</name>
|
|
<description>Data is valid.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKT_RDY</name>
|
|
<description>The PKT_LNGTH field is valid and the packet is ready for reading.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>USB Transmit Data</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_DATA</name>
|
|
<description>Transmit Data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXPLEN</name>
|
|
<description>USB Transmit Packet Length</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKT_LNGTH</name>
|
|
<description>The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>USB Control</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD_EN</name>
|
|
<description>Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_EN</name>
|
|
<description>Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOG_ENDPOINT</name>
|
|
<description>Logical Endpoint number.</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDCODE</name>
|
|
<description>USB Command Code</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMD_PHASE</name>
|
|
<description>The command phase:</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Write</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMMAND</name>
|
|
<description>Command</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD_CODE_WDATA</name>
|
|
<description>This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDDATA</name>
|
|
<description>USB Command Data</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD_RDATA</name>
|
|
<description>Command Read Data.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMARST</name>
|
|
<description>USB DMA Request Status</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRST0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRST31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMARCLR</name>
|
|
<description>USB DMA Request Clear</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRCLR0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR2</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR3</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR4</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR5</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR6</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR7</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR8</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR9</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR10</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR11</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR12</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR13</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR14</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR15</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR16</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR17</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR18</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR19</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR20</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR21</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR22</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR23</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR24</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR25</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR26</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR27</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR28</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR29</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR30</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRCLR31</name>
|
|
<description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMARSET</name>
|
|
<description>USB DMA Request Set</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRSET0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET2</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET3</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET4</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET5</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET6</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET7</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET8</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET9</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET10</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET11</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET12</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET13</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET14</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET15</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET16</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET17</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET18</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET19</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET20</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET21</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET22</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET23</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET24</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET25</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET26</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET27</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET28</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET29</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET30</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRSET31</name>
|
|
<description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UDCAH</name>
|
|
<description>USB UDCA Head</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDCA_ADDR</name>
|
|
<description>Start address of the UDCA.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPDMAST</name>
|
|
<description>USB Endpoint DMA Status</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_DMA_ST0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_ST31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPDMAEN</name>
|
|
<description>USB Endpoint DMA Enable</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_DMA_EN0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_EN1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_EN</name>
|
|
<description>Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPDMADIS</name>
|
|
<description>USB Endpoint DMA Disable</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_DMA_DIS0</name>
|
|
<description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS1</name>
|
|
<description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_DMA_DIS31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTST</name>
|
|
<description>USB DMA Interrupt Status</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EOT</name>
|
|
<description>End of Transfer Interrupt bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALL_BITS_IN_THE_USBE</name>
|
|
<description>All bits in the USBEoTIntSt register are 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_BIT_IN_</name>
|
|
<description>At least one bit in the USBEoTIntSt is set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDDR</name>
|
|
<description>New DD Request Interrupt bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALL_BITS_IN_THE_USBN</name>
|
|
<description>All bits in the USBNDDRIntSt register are 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_BIT_IN_</name>
|
|
<description>At least one bit in the USBNDDRIntSt is set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>System Error Interrupt bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALL_BITS_IN_THE_USBS</name>
|
|
<description>All bits in the USBSysErrIntSt register are 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_BIT_IN_</name>
|
|
<description>At least one bit in the USBSysErrIntSt is set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<description>USB DMA Interrupt Enable</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EOT</name>
|
|
<description>End of Transfer Interrupt enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDDR</name>
|
|
<description>New DD Request Interrupt enable bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>System Error Interrupt enable bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EOTINTST</name>
|
|
<description>USB End of Transfer Interrupt Status</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPTXINTST0</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST1</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTST31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EOTINTCLR</name>
|
|
<description>USB End of Transfer Interrupt Clear</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPTXINTCLR0</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR1</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR2</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR3</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR4</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR5</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR6</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR7</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR8</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR9</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR10</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR11</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR12</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR13</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR14</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR15</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR16</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR17</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR18</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR19</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR20</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR21</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR22</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR23</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR24</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR25</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR26</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR27</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR28</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR29</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR30</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTCLR31</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EOTINTSET</name>
|
|
<description>USB End of Transfer Interrupt Set</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPTXINTSET0</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET1</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET2</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET3</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET4</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET5</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET6</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET7</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET8</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET9</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET10</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET11</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET12</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET13</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET14</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET15</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET16</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET17</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET18</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET19</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET20</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET21</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET22</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET23</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET24</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET25</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET26</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET27</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET28</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET29</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET30</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPTXINTSET31</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NDDRINTST</name>
|
|
<description>USB New DD Request Interrupt Status</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPNDDINTST0</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST1</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTST31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NDDRINTCLR</name>
|
|
<description>USB New DD Request Interrupt Clear</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPNDDINTCLR0</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR1</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR2</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR3</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR4</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR5</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR6</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR7</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR8</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR9</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR10</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR11</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR12</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR13</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR14</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR15</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR16</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR17</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR18</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR19</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR20</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR21</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR22</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR23</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR24</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR25</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR26</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR27</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR28</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR29</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR30</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTCLR31</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NDDRINTSET</name>
|
|
<description>USB New DD Request Interrupt Set</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPNDDINTSET0</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET1</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET2</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET3</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET4</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET5</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET6</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET7</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET8</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET9</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET10</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET11</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET12</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET13</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET14</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET15</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET16</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET17</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET18</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET19</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET20</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET21</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET22</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET23</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET24</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET25</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET26</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET27</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET28</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET29</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET30</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPNDDINTSET31</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSERRINTST</name>
|
|
<description>USB System Error Interrupt Status</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPERRINTST0</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST1</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST2</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST3</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST4</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST5</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST6</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST7</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST8</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST9</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST10</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST11</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST12</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST13</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST14</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST15</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST16</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST17</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST18</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST19</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST20</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST21</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST22</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST23</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST24</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST25</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST26</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST27</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST28</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST29</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST30</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTST31</name>
|
|
<description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSERRINTCLR</name>
|
|
<description>USB System Error Interrupt Clear</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPERRINTCLR0</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR1</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR2</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR3</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR4</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR5</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR6</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR7</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR8</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR9</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR10</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR11</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR12</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR13</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR14</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR15</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR16</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR17</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR18</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR19</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR20</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR21</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR22</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR23</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR24</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR25</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR26</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR27</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR28</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR29</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR30</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTCLR31</name>
|
|
<description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSERRINTSET</name>
|
|
<description>USB System Error Interrupt Set</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPERRINTSET0</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET1</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET2</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET3</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET4</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET5</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET6</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET7</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET8</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET9</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET10</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET11</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET12</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET13</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET14</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET15</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET16</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET17</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET18</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET19</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET20</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET21</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET22</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET23</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET24</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET25</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET26</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET27</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET28</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET29</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET30</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EPERRINTSET31</name>
|
|
<description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
<register>
|
|
<name>I2C_RX</name>
|
|
<description>I2C Receive</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DATA</name>
|
|
<description>Receive data.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C_TX</name>
|
|
<description>I2C Transmit</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Transmit data.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>When 1, issue a START condition before transmitting this byte.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>When 1, issue a STOP condition after transmitting this byte.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C_STS</name>
|
|
<description>I2C Status</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0A00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDI</name>
|
|
<description>Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSACTION_HAS_NOT_</name>
|
|
<description>Transaction has not completed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSACTION_COMPLETE</name>
|
|
<description>Transaction completed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AFI</name>
|
|
<description>Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ARBITRATION_FAILU</name>
|
|
<description>No arbitration failure on last transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBITRATION_FAILURE_</name>
|
|
<description>Arbitration failure occurred on last transmission.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NAI</name>
|
|
<description>No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LAST_TRANSMISSION_RE</name>
|
|
<description>Last transmission received an acknowledge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LAST_TRANSMISSION_DI</name>
|
|
<description>Last transmission did not receive an acknowledge.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRMI</name>
|
|
<description>Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MASTER_TRANSMITTER_D</name>
|
|
<description>Master transmitter does not need data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_TRANSMITTER_N</name>
|
|
<description>Master transmitter needs data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRSI</name>
|
|
<description>Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE_TRANSMITTER_DO</name>
|
|
<description>Slave transmitter does not need data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_TRANSMITTER_NE</name>
|
|
<description>Slave transmitter needs data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Active</name>
|
|
<description>Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen..</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SCL</name>
|
|
<description>The current value of the SCL signal.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SDA</name>
|
|
<description>The current value of the SDA signal.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RX_FIFO_IS_NOT_FULL</name>
|
|
<description>RX FIFO is not full</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RX_FIFO_IS_FULL</name>
|
|
<description>RX FIFO is full</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RX_FIFO_CONTAINS_DAT</name>
|
|
<description>RX FIFO contains data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RX_FIFO_IS_EMPTY</name>
|
|
<description>RX FIFO is empty</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFF</name>
|
|
<description>Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TX_FIFO_IS_NOT_FULL_</name>
|
|
<description>TX FIFO is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TX_FIFO_IS_FULL</name>
|
|
<description>TX FIFO is full</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TX_FIFO_CONTAINS_VAL</name>
|
|
<description>TX FIFO contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TX_FIFO_IS_EMPTY</name>
|
|
<description>TX FIFO is empty</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C_CTL</name>
|
|
<description>I2C Control</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_TDI_INTE</name>
|
|
<description>Disable the TDI interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_TDI_INTER</name>
|
|
<description>Enable the TDI interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AFIE</name>
|
|
<description>Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_AFI_</name>
|
|
<description>Disable the AFI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_AFI_</name>
|
|
<description>Enable the AFI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NAIE</name>
|
|
<description>Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_NAI_</name>
|
|
<description>Disable the NAI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_NAI_</name>
|
|
<description>Enable the NAI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRMIE</name>
|
|
<description>Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_DRMI_INT</name>
|
|
<description>Disable the DRMI interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_DRMI_INTE</name>
|
|
<description>Enable the DRMI interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRSIE</name>
|
|
<description>Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_DRSI_INT</name>
|
|
<description>Disable the DRSI interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_DRSI_INTE</name>
|
|
<description>Enable the DRSI interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFIE</name>
|
|
<description>Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RFFI_</name>
|
|
<description>Disable the RFFI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RFFI_</name>
|
|
<description>Enable the RFFI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDAIE</name>
|
|
<description>Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_DAI_</name>
|
|
<description>Disable the DAI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_DAI_</name>
|
|
<description>Enable the DAI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFIE</name>
|
|
<description>Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_TFFI_</name>
|
|
<description>Disable the TFFI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_TFFI_</name>
|
|
<description>Enable the TFFI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRST</name>
|
|
<description>Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SEE_THE_TEXT_</name>
|
|
<description>See the text.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_THE_I2C_TO_IDL</name>
|
|
<description>Reset the I2C to idle state. Self clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C_CLKHI</name>
|
|
<description>I2C Clock High</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xB9</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDHI</name>
|
|
<description>Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C_CLKLO</name>
|
|
<description>I2C Clock Low</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0xB9</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDLO</name>
|
|
<description>Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKCTRL</name>
|
|
<description>OTG clock controller</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOST_CLK_EN</name>
|
|
<description>Host clock enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_HOST_CLO</name>
|
|
<description>Disable the Host clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_HOST_CLOC</name>
|
|
<description>Enable the Host clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEV_CLK_EN</name>
|
|
<description>Device clock enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_DEVICE_C</name>
|
|
<description>Disable the Device clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_DEVICE_CL</name>
|
|
<description>Enable the Device clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C_CLK_EN</name>
|
|
<description>I2C clock enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_I2C_CLOC</name>
|
|
<description>Disable the I2C clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_I2C_CLOCK</name>
|
|
<description>Enable the I2C clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTG_CLK_EN</name>
|
|
<description>OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_OTG_CLOC</name>
|
|
<description>Disable the OTG clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_OTG_CLOCK</name>
|
|
<description>Enable the OTG clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHB_CLK_EN</name>
|
|
<description>AHB master clock enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_AHB_CLOC</name>
|
|
<description>Disable the AHB clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_AHB_CLOCK</name>
|
|
<description>Enable the AHB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGClkSt</name>
|
|
<description>OTG clock status</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOST_CLK_ON</name>
|
|
<description>Host clock status.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HOST_CLOCK_IS_NOT_AV</name>
|
|
<description>Host clock is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST_CLOCK_IS_AVAILA</name>
|
|
<description>Host clock is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEV_CLK_ON</name>
|
|
<description>Device clock status.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CLOCK_IS_NOT_</name>
|
|
<description>Device clock is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CLOCK_IS_AVAI</name>
|
|
<description>Device clock is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C_CLK_ON</name>
|
|
<description>I2C clock status.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2C_CLOCK_IS_NOT_AVA</name>
|
|
<description>I2C clock is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_CLOCK_IS_AVAILAB</name>
|
|
<description>I2C clock is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTG_CLK_ON</name>
|
|
<description>OTG clock status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OTG_CLOCK_IS_NOT_AVA</name>
|
|
<description>OTG clock is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTG_CLOCK_IS_AVAILAB</name>
|
|
<description>OTG clock is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHB_CLK_ON</name>
|
|
<description>AHB master clock status.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AHB_CLOCK_IS_NOT_AVA</name>
|
|
<description>AHB clock is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_CLOCK_IS_AVAILAB</name>
|
|
<description>AHB clock is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>CRC engine </description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x20090000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>CRC mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_POLY</name>
|
|
<description>Select CRC polynomial</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CRC_CCITT_POLYNOMIAL</name>
|
|
<description>CRC-CCITT polynomial</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_16_POLYNOMIAL</name>
|
|
<description>CRC-16 polynomial</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_32_POLYNOMIAL</name>
|
|
<description>CRC-32 polynomial</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIT_RVS_WR</name>
|
|
<description>Select bit order for CRC_WR_DATA</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_BIT_ORDER_REVERSE</name>
|
|
<description>No bit order reverse for CRC_WR_DATA (per byte)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT_ORDER_REVERSE_FO</name>
|
|
<description>Bit order reverse for CRC_WR_DATA (per byte)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPL_WR</name>
|
|
<description>Select one's complement for CRC_WR_DATA</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ONES_COMPLEMENT_</name>
|
|
<description>No one's complement for CRC_WR_DATA</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONES_COMPLEMENT_FOR</name>
|
|
<description>One's complement for CRC_WR_DATA</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIT_RVS_SUM</name>
|
|
<description>Select bit order revers for CRC_SUM</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_BIT_ORDER_REVERSE</name>
|
|
<description>No bit order reverse for CRC_SUM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT_ORDER_REVERSE_FO</name>
|
|
<description>Bit order reverse for CRC_SUM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPL_SUM</name>
|
|
<description>Select one's complement for CRC_SUM</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ONES_COMPLEMENT_</name>
|
|
<description>No one's complement for CRC_SUM</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONES_COMPLEMENT_FOR</name>
|
|
<description>One's complement for CRC_SUM</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>Reserved</name>
|
|
<description>Always 0 when read</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEED</name>
|
|
<description>CRC seed register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_SEED</name>
|
|
<description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUM</name>
|
|
<description>CRC checksum register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_SUM</name>
|
|
<description>The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>CRC data register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_WR_DATA</name>
|
|
<description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x20098000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>DIR%s</name>
|
|
|
|
<description>GPIO Port Direction control register.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDIR0</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR1</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR2</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR3</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR4</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR5</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR6</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR7</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR8</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR9</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR10</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR11</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR12</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR13</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR14</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR15</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR16</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR17</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR18</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR19</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR20</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR21</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR22</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR23</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR24</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR25</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR26</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR27</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR28</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR29</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR30</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDIR31</name>
|
|
<description>Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>MASK%s</name>
|
|
|
|
<description>Mask register for Port.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMASK0</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK1</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK2</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK3</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK4</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK5</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK6</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK7</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK8</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK9</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK10</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK11</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK12</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK13</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK14</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK15</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK16</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK17</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK18</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK19</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK20</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK21</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK22</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK23</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK24</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK25</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK26</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK27</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK28</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK29</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK30</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMASK31</name>
|
|
<description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>PIN%s</name>
|
|
<displayName>PIN[%s]</displayName>
|
|
<description>Port Pin value register using MASK.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL0</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL1</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL2</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL3</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL4</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL5</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL6</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL7</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL8</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL9</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL10</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL11</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL12</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL13</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL14</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL15</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL16</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL17</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL18</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL19</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL20</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL21</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL22</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL23</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL24</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL25</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL26</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL27</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL28</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL29</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL30</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VAL31</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>SET%s</name>
|
|
|
|
<description>Port Output Set register using MASK.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSET0</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET1</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET2</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET3</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET4</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET5</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET6</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET7</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET8</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET9</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET10</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET11</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET12</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET13</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET14</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET15</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET16</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET17</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET18</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET19</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET20</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET21</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET22</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET23</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET24</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET25</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET26</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET27</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET28</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET29</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET30</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSET31</name>
|
|
<description>Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>CLR%s</name>
|
|
|
|
<description>Port Output Clear register using MASK.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCLR0</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR1</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR2</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR3</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR4</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR5</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR6</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR7</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR8</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR9</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR10</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR11</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR12</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR13</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR14</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR15</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR16</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR17</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR18</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR19</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR20</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR21</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR22</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR23</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR24</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR25</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR26</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR27</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR28</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR29</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR30</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCLR31</name>
|
|
<description>Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EMC</name>
|
|
<description>External Memory Controller (EMC)</description>
|
|
<groupName>EMC</groupName>
|
|
<baseAddress>0X2009C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Controls operation of the memory controller.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>EMC Enable. Indicates if the EMC is enabled or disabled:</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled
|
|
(POR and warm reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>Address mirror. Indicates normal or reset memory map:</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal memory map.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset memory map. Static memory EMC_CS1 is
|
|
mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Low-power mode. Indicates normal, or low-power mode:</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WARMRESET</name>
|
|
<description>Normal mode (warm
|
|
reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWPOWER</name>
|
|
<description>Low-power
|
|
mode. Entering low-power mode reduces memory controller power consumption.
|
|
Dynamic memory is refreshed as necessary. The memory controller
|
|
returns to normal functional mode by clearing the low-power mode
|
|
bit (L), or by POR. This bit must only be modified when the EMC
|
|
is in idle state.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Provides EMC status information.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>EMC
|
|
is idle (warm reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>EMC
|
|
is busy performing memory transactions, commands, auto-refresh cycles,
|
|
or is in self-refresh mode (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Write buffers
|
|
empty (POR reset value)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Write
|
|
buffers contain data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Self-refresh acknowledge. This bit indicates the operating mode of the EMC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELFREFRESH</name>
|
|
<description>Self-refresh mode (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configures operation of the memory controller</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM</name>
|
|
<description>Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLEENDIAN</name>
|
|
<description>Little-endian
|
|
mode (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIGENDIAN</name>
|
|
<description>Big-endian
|
|
mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKR</name>
|
|
<description>CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORRESET</name>
|
|
<description>1:1(POR reset value)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DONOTUSE</name>
|
|
<description>1:2 (this option is not available on the LPC178x/177x)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICCONTROL</name>
|
|
<description>Controls dynamic memory operation.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Dynamic memory clock enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERSAVE</name>
|
|
<description>Clock enable of idle devices are deasserted to save power (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>All clock enables are driven HIGH continuously.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>CLKOUT stops when all SDRAMs are idle and during self-refresh mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>CLKOUT runs continuously (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_MODE_</name>
|
|
<description>Normal mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENTER_SELF_REFRESH_M</name>
|
|
<description>Enter self-refresh mode (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MMC</name>
|
|
<description>Memory clock control.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLKOUT_ENABLED_POR_</name>
|
|
<description>CLKOUT enabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT_DISABLED</name>
|
|
<description>CLKOUT disabled.[3]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I</name>
|
|
<description>SDRAM initialization.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Issue SDRAM NORMAL operation command (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE</name>
|
|
<description>Issue SDRAM MODE command.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PALL</name>
|
|
<description>Issue SDRAM PALL (precharge all) command.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>Issue SDRAM NOP (no operation) command)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[13:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICREFRESH</name>
|
|
<description>Configures dynamic memory refresh.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFRESH</name>
|
|
<description>Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICREADCONFIG</name>
|
|
<description>Configures dynamic memory read strategy.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Read data strategy</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLOCK_OUT_DELAYED_ST</name>
|
|
<description>Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMMAND_DELAYED_STRA</name>
|
|
<description>Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMMAND_DELAYED_STRA</name>
|
|
<description>Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMMAND_DELAYED_STRA</name>
|
|
<description>Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRP</name>
|
|
<description>Precharge command period.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRP</name>
|
|
<description>Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRAS</name>
|
|
<description>Active to precharge command period.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRAS</name>
|
|
<description>Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICSREX</name>
|
|
<description>Self-refresh exit time.</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSREX</name>
|
|
<description>Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICAPR</name>
|
|
<description>Last-data-out to active command time.</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAPR</name>
|
|
<description>Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICDAL</name>
|
|
<description>Data-in to active command time.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDAL</name>
|
|
<description>Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICWR</name>
|
|
<description>Write recovery time.</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TWR</name>
|
|
<description>Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRC</name>
|
|
<description>Selects the active to active command period.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRC</name>
|
|
<description>Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRFC</name>
|
|
<description>Selects the auto-refresh period.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICXSR</name>
|
|
<description>Time for exit self-refresh to active command.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXSR</name>
|
|
<description>Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRRD</name>
|
|
<description>Latency for active bank A to active bank B.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRRD</name>
|
|
<description>Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICMRD</name>
|
|
<description>Time for load mode register to active command.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMRD</name>
|
|
<description>Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATICEXTENDEDWAIT</name>
|
|
<description>Time for long static memory read and write transfers.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTENDEDWAIT</name>
|
|
<description>Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>DYNAMICCONFIG%s</name>
|
|
|
|
<description>Configuration information for EMC_DYCS0.</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Memory device.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SDRAM_POR_RESET_VAL</name>
|
|
<description>SDRAM (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_POWER_SDRAM_</name>
|
|
<description>Low-power SDRAM.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AM0</name>
|
|
<description>See Table 133. 000000 = reset value.[1]</description>
|
|
<bitRange>[12:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AM1</name>
|
|
<description>See Table 133. 0 = reset value.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[18:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Buffer enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUFFER_DISABLED_FOR_</name>
|
|
<description>Buffer disabled for accesses to this chip select (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFFER_ENABLED_FOR_A</name>
|
|
<description>Buffer enabled for accesses to this chip select.[2]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>Write protect.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WRITES_NOT_PROTECTED</name>
|
|
<description>Writes not protected (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITES_PROTECTED_</name>
|
|
<description>Writes protected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>DYNAMICRASCAS%s</name>
|
|
|
|
<description>RAS and CAS latencies for EMC_DYCS0.</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x303</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAS</name>
|
|
<description>RAS latency (active to read/write delay).</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_CCLK_CYCLE_</name>
|
|
<description>One CCLK cycle.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_CCLK_CYCLES_</name>
|
|
<description>Two CCLK cycles.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE_CCLK_CYCLES_P</name>
|
|
<description>Three CCLK cycles (POR reset value).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CAS</name>
|
|
<description>CAS latency.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_CCLK_CYCLE_</name>
|
|
<description>One CCLK cycle.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_CCLK_CYCLES_</name>
|
|
<description>Two CCLK cycles.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE_CCLK_CYCLES_P</name>
|
|
<description>Three CCLK cycles (POR reset value).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICCONFIG%s</name>
|
|
|
|
<description>Configuration for EMC_CS0.</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MW</name>
|
|
<description>Memory width.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_POR_RESET_VAL</name>
|
|
<description>8 bit (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_</name>
|
|
<description>16 bit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_BIT_</name>
|
|
<description>32 bit.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_POR_RESET_</name>
|
|
<description>Disabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS_PAGE_MO</name>
|
|
<description>Asynchronous page mode enabled (page length four).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Chip select polarity. The value of the chip select polarity on power-on reset is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_LOW_CHIP_SELE</name>
|
|
<description>Active LOW chip select.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH_CHIP_SEL</name>
|
|
<description>Active HIGH chip select.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BLSHIGH</name>
|
|
<description>For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BLSLOW</name>
|
|
<description>For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EXTENDED_WAIT_DISABL</name>
|
|
<description>Extended wait disabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTENDED_WAIT_ENABLE</name>
|
|
<description>Extended wait enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[18:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Buffer enable [2]</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUFFER_DISABLED_POR</name>
|
|
<description>Buffer disabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFFER_ENABLED_</name>
|
|
<description>Buffer enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>Write protect</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WRITES_NOT_PROTECTED</name>
|
|
<description>Writes not protected (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE_PROTECTED_</name>
|
|
<description>Write protected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITWEN%s</name>
|
|
|
|
<description>Delay from EMC_CS0 to write enable.</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITWEN</name>
|
|
<description>Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITOEN%s</name>
|
|
|
|
<description>Delay from EMC_CS0 or address change, whichever is later, to output enable.</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITOEN</name>
|
|
<description>Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITRD%s</name>
|
|
|
|
<description>Delay from EMC_CS0 to a read access.</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITRD</name>
|
|
<description>Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITPAGE%s</name>
|
|
|
|
<description>Delay for asynchronous page mode sequential accesses for EMC_CS0.</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITPAGE</name>
|
|
<description>Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITWR%s</name>
|
|
|
|
<description>Delay from EMC_CS0 to a write access.</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITWR</name>
|
|
<description>Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITTURN%s</name>
|
|
|
|
<description>Number of bus turnaround cycles EMC_CS0.</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITTURN</name>
|
|
<description>Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>WWDT</name>
|
|
<description> Windowed Watchdog Timer (WWDT) </description>
|
|
<groupName>WWDT</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WWDT</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDEN</name>
|
|
<description>Watchdog enable bit. This bit is Set Only. See Table 652.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>The watchdog timer is stopped.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The watchdog timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDRESET</name>
|
|
<description>Watchdog reset enable bit. This bit is Set Only. See Table 652.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORESET</name>
|
|
<description>A watchdog timeout will not cause a chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>A watchdog timeout will cause a chip reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOF</name>
|
|
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section WDTOF.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDINT</name>
|
|
<description>Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section WDINT.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDPROTECT</name>
|
|
<description>Watchdog update mode. This bit is Set Only. See Section WDPROTECT.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANGE</name>
|
|
<description>The watchdog reload value (WDTC) can be changed at any time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANGE_W_CNT</name>
|
|
<description>The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Watchdog timer constant register. The value in this register determines the time-out value.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Count</name>
|
|
<description>Watchdog time-out interval.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEED</name>
|
|
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Feed</name>
|
|
<description>Feed value should be 0xAA followed by 0x55.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TV</name>
|
|
<description>Watchdog timer value register. This register reads out the current value of the Watchdog timer.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Count</name>
|
|
<description>Counter timer value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog Warning Interrupt compare value.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog warning interrupt compare value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog Window compare value.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog window value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description> Timer0/1/2/3 </description>
|
|
<groupName>TIMER0</groupName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Prescale counter maximum value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_GENERAT</name>
|
|
<description>Interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_DISABLE</name>
|
|
<description>Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_WILL_BE_RESET_IF_</name>
|
|
<description>TC will be reset if MR0 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_AND_PC_WILL_BE_ST</name>
|
|
<description>TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_GENERAT</name>
|
|
<description>Interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_DISABLE</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_WILL_BE_RESET_IF_</name>
|
|
<description>TC will be reset if MR1 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_AND_PC_WILL_BE_ST</name>
|
|
<description>TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_GENERAT</name>
|
|
<description>Interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_DISABLE</name>
|
|
<description>Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_WILL_BE_RESET_IF_</name>
|
|
<description>TC will be reset if MR2 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_AND_PC_WILL_BE_ST</name>
|
|
<description>TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_IS_GENERAT</name>
|
|
<description>Interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_IS_DI</name>
|
|
<description>This interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_WILL_BE_RESET_IF_</name>
|
|
<description>TC will be reset if MR3 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TC_AND_PC_WILL_BE_ST</name>
|
|
<description>TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_DISABLED_</name>
|
|
<description>Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR[%s]</name>
|
|
<displayName>MR[%s]</displayName>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CAPn.0 rising edge</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CAPn.0 falling edge</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CAPn.0 event</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A CR0 load due to a CAPn.0 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CAPn.1 rising edge</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CAPn.1 falling edge</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CAPn.1 event</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>A CR1 load due to a CAPn.1 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>CR[%s]</name>
|
|
<displayName>CR[%s]</displayName>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the external match pins.</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTMODE</name>
|
|
<description>Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUALEDGE</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINSEL</name>
|
|
<description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CAPN_0_FOR_TIMERN</name>
|
|
<description>CAPn.0 for TIMERn</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPN_1_FOR_TIMERN</name>
|
|
<description>CAPn.1 for TIMERn</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER1</name>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER1</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>UART0/2/3 </description>
|
|
<groupName>UART0</groupName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read (DLAB =0).</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RDA_INTE</name>
|
|
<description>Disable the RDA interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RDA_INTER</name>
|
|
<description>Enable the RDA interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_THRE_INT</name>
|
|
<description>Disable the THRE interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_THRE_INTE</name>
|
|
<description>Enable the THRE interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RX_LINE_</name>
|
|
<description>Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RX_LINE_S</name>
|
|
<description>Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTEN</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_END_OF_AUTO_</name>
|
|
<description>Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_END_OF_AUTO_B</name>
|
|
<description>Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTEN</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_BAUD_TI</name>
|
|
<description>Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_BAUD_TIM</name>
|
|
<description>Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_INTERRU</name>
|
|
<description>At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_IS_PEND</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_RECEIVE_LINE_S</name>
|
|
<description>1 - Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2A__RECEIVE_DATA_AV</name>
|
|
<description>2a - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2B__CHARACTER_TIME_</name>
|
|
<description>2b - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_THRE_INTERRUPT</name>
|
|
<description>3 - THRE Interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>Copies of UnFCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls UART FIFO usage and modes.</description>
|
|
<alternateRegister>IIR</alternateRegister>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UARTN_FIFOS_ARE_DISA</name>
|
|
<description>UARTn FIFOs are disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH_ENABLE_F</name>
|
|
<description>Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UARTn FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UARTn FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMODE</name>
|
|
<description>DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGLVL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_0_1_C</name>
|
|
<description>Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_1_4_C</name>
|
|
<description>Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_2_8_C</name>
|
|
<description>Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_3_14_</name>
|
|
<description>Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT_</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS_1_5_IF_</name>
|
|
<description>2 stop bits (1.5 if UnLCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY_NUMBER_O</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY_NUMBER_</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_1_STICK_PARIT</name>
|
|
<description>Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_0_STICK_PARIT</name>
|
|
<description>Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BREAK_TRANSM</name>
|
|
<description>Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BREAK_TRANSMI</name>
|
|
<description>Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ACCESS_TO_DI</name>
|
|
<description>Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ACCESS_TO_DIV</name>
|
|
<description>Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>The UARTn receiver FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOTEMPTY</name>
|
|
<description>The UARTn receiver FIFO is not empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALIDDATA</name>
|
|
<description>UnTHR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>UnTHR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALIDDATA</name>
|
|
<description>UnTHR and/or the UnTSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>UnTHR and the UnTSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>UnRBR contains no UARTn RX errors or UnFCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERRORS</name>
|
|
<description>UARTn RBR contains at least one UARTn RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. 8-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PAD</name>
|
|
<description>A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_STOP_AUTO</name>
|
|
<description>Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_START_AUT</name>
|
|
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0_</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1_</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Restart bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART_</name>
|
|
<description>No restart.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART_IN_CASE_OF_T</name>
|
|
<description>Restart in case of time-out (counter restarts at next UARTn Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_</name>
|
|
<description>No impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_</name>
|
|
<description>No impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>NMM enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>AAD enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Auto Address Detect (AAD) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto Address Detect (AAD) is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Direction control enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_DIRECTI</name>
|
|
<description>Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_DIRECTIO</name>
|
|
<description>Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRLOW</name>
|
|
<description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIRHIGH</name>
|
|
<description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>UART1</name>
|
|
<description>UART1</description>
|
|
<groupName>UART1</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>DLAB =0 Receiver Buffer Register. Contains the next received character to be read.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RDA_INTE</name>
|
|
<description>Disable the RDA interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RDA_INTER</name>
|
|
<description>Enable the RDA interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_THRE_INT</name>
|
|
<description>Disable the THRE interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_THRE_INTE</name>
|
|
<description>Enable the THRE interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RX_LINE_</name>
|
|
<description>Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RX_LINE_S</name>
|
|
<description>Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSIE</name>
|
|
<description>Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_MODEM_IN</name>
|
|
<description>Disable the modem interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_MODEM_INT</name>
|
|
<description>Enable the modem interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_CTS_INTE</name>
|
|
<description>Disable the CTS interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_CTS_INTER</name>
|
|
<description>Enable the CTS interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABEOIE</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_END_OF_AUTO_</name>
|
|
<description>Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_END_OF_AUTO_B</name>
|
|
<description>Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOIE</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_BAUD_TI</name>
|
|
<description>Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_BAUD_TIM</name>
|
|
<description>Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_INTERRU</name>
|
|
<description>At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_IS_PEND</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RLS</name>
|
|
<description>1 - Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDA</name>
|
|
<description>2a - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTI</name>
|
|
<description>2b - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRE</name>
|
|
<description>3 - THRE Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODEM</name>
|
|
<description>4 - Modem Interrupt.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>Copies of FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls UART1 FIFO usage and modes.</description>
|
|
<alternateRegister>IIR</alternateRegister>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MUST_NOT_BE_USED_IN_</name>
|
|
<description>Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH_ENABLE_F</name>
|
|
<description>Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UART1 FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UART1 FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMODE</name>
|
|
<description>DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGLVL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_0_1_C</name>
|
|
<description>Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_1_4_C</name>
|
|
<description>Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_2_8_C</name>
|
|
<description>Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_3_14_</name>
|
|
<description>Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT_</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS_1_5_IF_</name>
|
|
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY_NUMBER_O</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY_NUMBER_</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED1STICK_PAR</name>
|
|
<description>Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED0STICK_PAR</name>
|
|
<description>Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BREAK_TRANSM</name>
|
|
<description>Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BREAK_TRANSMI</name>
|
|
<description>Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit (DLAB)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ACCESS_TO_DI</name>
|
|
<description>Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ACCESS_TO_DIV</name>
|
|
<description>Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Modem Control Register. Contains controls for flow control handshaking and loopback mode.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTRCTRL</name>
|
|
<description>DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSCTRL</name>
|
|
<description>RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LMS</name>
|
|
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_MODEM_LOOPBA</name>
|
|
<description>Disable modem loopback mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_MODEM_LOOPBAC</name>
|
|
<description>Enable modem loopback mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_RTS_FLO</name>
|
|
<description>Disable auto-rts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_RTS_FLOW</name>
|
|
<description>Enable auto-rts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_CTS_FLO</name>
|
|
<description>Disable auto-cts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_CTS_FLOW</name>
|
|
<description>Enable auto-cts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>The UART1 receiver FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOTEMPTY</name>
|
|
<description>The UART1 receiver FIFO is not empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>THR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THR_IS_EMPTY_</name>
|
|
<description>THR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>THR and/or the TSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>THR and the TSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>RBR contains no UART1 RX errors or FCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERRORS</name>
|
|
<description>UART1 RBR contains at least one UART1 RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Modem Status Register. Contains handshake signal status flags.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DCTS</name>
|
|
<description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDSR</name>
|
|
<description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, DSR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, DSR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERI</name>
|
|
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, RI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH_TRANSITI</name>
|
|
<description>Low-to-high transition detected on RI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDCD</name>
|
|
<description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, DCD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, DCD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. 8-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Pad</name>
|
|
<description>A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Auto-baud start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0_</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1_</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Auto-baud restart bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART</name>
|
|
<description>No restart</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART_IN_CASE_OF_T</name>
|
|
<description>Restart in case of time-out (counter restarts at next UART1 Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write-only).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_0_HAS_NO_I</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_1_WILL_CLE</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write-only).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_0_HAS_NO_I</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_1_WILL_CLE</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_IN_THIS_MOD</name>
|
|
<description>Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receive enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>Auto Address Detect (AAD) enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Direction control.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RTS_IF_DIRECTION_CO</name>
|
|
<description>RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR_IF_DIRECTION_CO</name>
|
|
<description>DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Direction control enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_DIRECTI</name>
|
|
<description>Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_DIRECTIO</name>
|
|
<description>Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_THE_DIRECTION_C</name>
|
|
<description>LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_THE_DIRECTION_</name>
|
|
<description>HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>PWM0</name>
|
|
<description>Pulse Width Modulators (PWM0/1)</description>
|
|
<groupName>PWM</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWM0</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMMR0INT</name>
|
|
<description>Interrupt flag for PWM match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR1INT</name>
|
|
<description>Interrupt flag for PWM match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR2INT</name>
|
|
<description>Interrupt flag for PWM match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR3INT</name>
|
|
<description>Interrupt flag for PWM match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMCAP0INT</name>
|
|
<description>Interrupt flag for capture input 0</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMCAP1INT</name>
|
|
<description>Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR4INT</name>
|
|
<description>Interrupt flag for PWM match channel 4.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR5INT</name>
|
|
<description>Interrupt flag for PWM match channel 5.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR6INT</name>
|
|
<description>Interrupt flag for PWM match channel 6.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Counter Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_TIMER_COUNTE</name>
|
|
<description>The PWM Timer Counter and PWM Prescale Counter are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTERS_ARE_DIS</name>
|
|
<description>The counters are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CR</name>
|
|
<description>Counter Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_TIMER_COUNTE</name>
|
|
<description>The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_RESET_</name>
|
|
<description>Clear reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PWMEN</name>
|
|
<description>PWM Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_IS_ENABLE</name>
|
|
<description>Timer mode is enabled (counter resets to 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MASTER_USE_PWM0_IS_</name>
|
|
<description>Master use. PWM0 is the master, and both PWMs are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INDIVIDUAL_USE_THE_</name>
|
|
<description>Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. Determines how often the PWM counter is incremented.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Prescale counter maximum value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. Prescaler for the main PWM counter.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMMR0I</name>
|
|
<description>Interrupt PWM0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR0</name>
|
|
<description>Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR0R</name>
|
|
<description>Reset PWM0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR0_THE</name>
|
|
<description>Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR0S</name>
|
|
<description>Stop PWM0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR0_THE_</name>
|
|
<description>Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR1I</name>
|
|
<description>Interrupt PWM1</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR1</name>
|
|
<description>Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR1R</name>
|
|
<description>Reset PWM1</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR1_THE</name>
|
|
<description>Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR1S</name>
|
|
<description>Stop PWM1</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR1_THE_</name>
|
|
<description>Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR2I</name>
|
|
<description>Interrupt PWM0</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR2</name>
|
|
<description>Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR2R</name>
|
|
<description>Reset PWM0</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR2_THE</name>
|
|
<description>Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR2S</name>
|
|
<description>Stop PWM0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR2_THE_</name>
|
|
<description>Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR3I</name>
|
|
<description>Interrupt PWM3</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR3</name>
|
|
<description>Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR3R</name>
|
|
<description>Reset PWM3</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR3_THE</name>
|
|
<description>Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR3S</name>
|
|
<description>Stop PWM0</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR3_THE_</name>
|
|
<description>Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR4I</name>
|
|
<description>Interrupt PWM4</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR4</name>
|
|
<description>Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR4R</name>
|
|
<description>Reset PWM4</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR4_THE</name>
|
|
<description>Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR4S</name>
|
|
<description>Stop PWM4</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR4_THE_</name>
|
|
<description>Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR5I</name>
|
|
<description>Interrupt PWM5</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR5</name>
|
|
<description>Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR5R</name>
|
|
<description>Reset PWM5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR5_THE</name>
|
|
<description>Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR5S</name>
|
|
<description>Stop PWM5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR5_THE_</name>
|
|
<description>Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR6I</name>
|
|
<description>Interrupt PWM6</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ON_PWMMR6</name>
|
|
<description>Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR6R</name>
|
|
<description>Reset PWM6</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_PWMMR6_THE</name>
|
|
<description>Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMR6S</name>
|
|
<description>Stop PWM6</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_ON_PWMMR6_THE_</name>
|
|
<description>Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
|
|
<description>Match Register. Match registers
|
|
are continuously compared to the PWM counter in order to control PWM
|
|
output edges.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0_R</name>
|
|
<description>Capture on PWMn_CAP0 rising edge</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_A_SYNCH</name>
|
|
<description>Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0_F</name>
|
|
<description>Capture on PWMn_CAP0 falling edge</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_A_SYNC</name>
|
|
<description>Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0_I</name>
|
|
<description>Interrupt on PWMn_CAP0 event</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_A_CR0_LOA</name>
|
|
<description>Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1_R</name>
|
|
<description>Capture on PWMn_CAP1 rising edge. Reserved for PWM0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_A_SYNCH</name>
|
|
<description>Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1_F</name>
|
|
<description>Capture on PWMn_CAP1 falling edge. Reserved for PWM0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_A_SYNC</name>
|
|
<description>Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1_I</name>
|
|
<description>Interrupt on PWMn_CAP1 event. Reserved for PWM0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_THIS_FEATU</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_A_CR1_LOA</name>
|
|
<description>Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>CR[%s]</name>
|
|
<displayName>CR[%s]</displayName>
|
|
<description>PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL2</name>
|
|
<description>PWM[2] output single/double edge mode control.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL3</name>
|
|
<description>PWM[3] output edge control.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL4</name>
|
|
<description>PWM[4] output edge control.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL5</name>
|
|
<description>PWM[5] output edge control.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL6</name>
|
|
<description>PWM[6] output edge control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PWMENA1</name>
|
|
<description>PWM[1] output enable control.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA2</name>
|
|
<description>PWM[2] output enable control.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA3</name>
|
|
<description>PWM[3] output enable control.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA4</name>
|
|
<description>PWM[4] output enable control.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA5</name>
|
|
<description>PWM[5] output enable control.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA6</name>
|
|
<description>PWM[6] output enable control. See PWMENA1 for details.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused, always zero.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>MR4</name>
|
|
|
|
<description>Match Register. Match registers
|
|
are continuously compared to the PWM counter in order to control PWM
|
|
output edges.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
|
|
<name>MR5</name>
|
|
|
|
<description>Match Register. Match registers
|
|
are continuously compared to the PWM counter in order to control PWM
|
|
output edges.</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>MR6</name>
|
|
|
|
<description>Match Register. Match registers
|
|
are continuously compared to the PWM counter in order to control PWM
|
|
output edges.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR</name>
|
|
<description>PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL2</name>
|
|
<description>PWM[2] output single/double edge mode control.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL3</name>
|
|
<description>PWM[3] output edge control.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL4</name>
|
|
<description>PWM[4] output edge control.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL5</name>
|
|
<description>PWM[5] output edge control.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSEL6</name>
|
|
<description>PWM[6] output edge control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_EDGE_CONTROLL</name>
|
|
<description>Single edge controlled mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE_EDGE_CONTROLL</name>
|
|
<description>Double edge controlled mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PWMENA1</name>
|
|
<description>PWM[1] output enable control.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA2</name>
|
|
<description>PWM[2] output enable control.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA3</name>
|
|
<description>PWM[3] output enable control.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA4</name>
|
|
<description>PWM[4] output enable control.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA5</name>
|
|
<description>PWM[5] output enable control.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMENA6</name>
|
|
<description>PWM[6] output enable control. See PWMENA1 for details.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_DI</name>
|
|
<description>The PWM output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PWM_OUTPUT_IS_EN</name>
|
|
<description>The PWM output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused, always zero.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
<register>
|
|
<name>LER</name>
|
|
<description>Load Enable Register. Enables use of updated PWM match values.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAT0LATCHEN</name>
|
|
<description>Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT1LATCHEN</name>
|
|
<description>Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT2LATCHEN</name>
|
|
<description>Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT3LATCHEN</name>
|
|
<description>Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT4LATCHEN</name>
|
|
<description>Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT5LATCHEN</name>
|
|
<description>Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAT6LATCHEN</name>
|
|
<description>Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Counter/ Timer Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_THE_TC_I</name>
|
|
<description>Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_COUNTER_</name>
|
|
<description>Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_COUNTER</name>
|
|
<description>Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUAL_EDGE_COUNTER_MO</name>
|
|
<description>Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FOR_PWM0_00_EQ_PWM0_</name>
|
|
<description>For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="PWM0">
|
|
<name>PWM1</name>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWM1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>I2C bus interface</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>10</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONSET</name>
|
|
<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AA</name>
|
|
<description>Assert acknowledge flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SI</name>
|
|
<description>I2C interrupt flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STO</name>
|
|
<description>STOP flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STA</name>
|
|
<description>START flag.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2EN</name>
|
|
<description>I2C interface enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xF8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are unused and are always 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Status</name>
|
|
<description>These bits give the actual status information about the I 2C interface.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAT</name>
|
|
<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds data values that have been received or are to be transmitted.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADR0</name>
|
|
<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLH</name>
|
|
<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLH</name>
|
|
<description>Count for SCL HIGH time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLL</name>
|
|
<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>Count for SCL low time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONCLR</name>
|
|
<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAC</name>
|
|
<description>Assert acknowledge Clear bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIC</name>
|
|
<description>I2C interrupt Clear bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STAC</name>
|
|
<description>START flag Clear bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2ENC</name>
|
|
<description>I2C interface Disable bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCTRL</name>
|
|
<description>Monitor mode control register.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MM_ENA</name>
|
|
<description>Monitor mode enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MONITOR_MODE_DISABLE</name>
|
|
<description>Monitor mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_I_2C_MODULE_WILL</name>
|
|
<description>The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA_SCL</name>
|
|
<description>SCL output enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_CLE</name>
|
|
<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_SET</name>
|
|
<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_ALL</name>
|
|
<description>Select interrupt register match.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_CLE</name>
|
|
<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_SET</name>
|
|
<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from reserved bits is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>ADR%s</name>
|
|
<description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_BUFFER</name>
|
|
<description>Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MASK[%s]</name>
|
|
<displayName>MASK[%s]</displayName>
|
|
<description>I2C Slave address mask register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask bits.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMPARATOR</name>
|
|
<description>Comparators</description>
|
|
<groupName>COMPARATOR</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CMP1</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Comparator block control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMP_PD_IREF</name>
|
|
<description>Controls the current source used by the comparators. These bits must be set when either comparator is used.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The comparator current source is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The comparator current source is powered up.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_PD_VBG</name>
|
|
<description>Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The comparator bandgap reference is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The comparator bandgap reference is powered up.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_VTEMP</name>
|
|
<description>Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The temperature sensor voltage reference is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The temperature sensor voltage reference is powered up.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_TEMPSEN</name>
|
|
<description>Enables the temperature sensor. These bits must be set when the temperature sensor is used.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Temperature sensor is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Temperature sensor is enabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_ROSCCTL</name>
|
|
<description>Selects the inputs for the flip/flops that provide the CMP_ROSC output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP1</name>
|
|
<description>The CMP_ROSC output is set by CMP1 and reset by CMP0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0</name>
|
|
<description>The CMP_ROSC output is set by CMP0 and reset by CMP1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_EXT_RESET</name>
|
|
<description>Selects the reset source for the CMP_ROSC output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTRESET</name>
|
|
<description>The CMP_ROSC output is reset by the internal chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_RESETIN</name>
|
|
<description>The CMP_ROSC output is reset by the CMP_RESET input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP_T0CAP2</name>
|
|
<description>Selects the input for Timer 0 capture input 2.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>COMP0</name>
|
|
<description>T0CAP2 is connected to comparator 0 level output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP1</name>
|
|
<description>T0CAP2 is connected to comparator 1 level output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_T0CAP3</name>
|
|
<description>Selects the input for Timer 0 capture input 3.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>COMP0</name>
|
|
<description>T0CAP3 is connected to comparator 0 edge output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP1</name>
|
|
<description>T0CAP3 is connected to comparator 1 edge output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_T1CAP2</name>
|
|
<description>Selects the input for Timer 1 capture input 2.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>COMP1</name>
|
|
<description>T1CAP2 is connected to comparator 1 edge output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP0</name>
|
|
<description>T1CAP2 is connected to comparator 0 level output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP_T1CAP3</name>
|
|
<description>Selects the input for Timer 1 capture input 3.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>COMP1</name>
|
|
<description>T1CAP3 is connected to comparator 1 level output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP0</name>
|
|
<description>T1CAP3 is connected to comparator 0 edge output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL0</name>
|
|
<description>Comparator 0 control register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMP0_EN</name>
|
|
<description>Comparator 0 enable control.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Comparator 0 disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Comparator 0 is enabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_OE</name>
|
|
<description>Comparator 0 output enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Comparator 0 output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Comparator 0 output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_STAT</name>
|
|
<description>Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP0_VM</name>
|
|
<description>Comparator 0 VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_0_</name>
|
|
<description>Vref divider 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN0</name>
|
|
<description>CMP0_IN[0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN1</name>
|
|
<description>CMP0_IN[1].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN2</name>
|
|
<description>CMP0_IN[2].</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN3</name>
|
|
<description>CMP0_IN[3].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN0</name>
|
|
<description>CMP1_IN[0].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0_9_V_BAND_</name>
|
|
<description>internal 0.9 V band gap reference.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMPERATURE_SENSOR_</name>
|
|
<description>temperature sensor.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP0_VP</name>
|
|
<description>Comparator 0 VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_0_</name>
|
|
<description>Vref divider 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN0</name>
|
|
<description>CMP0_IN[0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN1</name>
|
|
<description>CMP0_IN[1].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN2</name>
|
|
<description>CMP0_IN[2].</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN3</name>
|
|
<description>CMP0_IN[3].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN0</name>
|
|
<description>CMP1_IN[0].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0_9_V_BAND_</name>
|
|
<description>internal 0.9 V band gap reference.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMPERATURE_SENSOR_</name>
|
|
<description>temperature sensor.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP0_SYNC</name>
|
|
<description>Comparator 0 output synchronization control.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECT</name>
|
|
<description>The comparator 0 output is used directly.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCH</name>
|
|
<description>The comparator 0 output is synchronized with the internal bus clock for output to other peripherals.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_HYS</name>
|
|
<description>Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESISOFF</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV_</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV_</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV_</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_INTPOL</name>
|
|
<description>Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOTINVERTED</name>
|
|
<description>The CMP0 output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The CMP0 output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_INTTYPE</name>
|
|
<description>Select comparator 0 interrupt type. See Table 412.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Comparator 0 interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Comparator 0 interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Comparator 0 interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Comparator 0 interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUALEDGE</name>
|
|
<description>Comparator 0 Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_INTFLAG</name>
|
|
<description>Comparator 0 interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOTPENDING</name>
|
|
<description>The Comparator 0 interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 0.</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The Comparator 0 voltage ladder is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The Comparator 0 voltage ladder is enabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0_VLADREF</name>
|
|
<description>Voltage reference select for comparator 0 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN_</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN_</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP0_VSEL</name>
|
|
<description>Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL1</name>
|
|
<description>Comparator 1 control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1_EN</name>
|
|
<description>Comparator 1 enable control.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Comparator 1 disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Comparator 1 is enabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_OE</name>
|
|
<description>Comparator 1 output enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Comparator 1 output is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Comparator 1 output is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_STAT</name>
|
|
<description>Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP1_VM</name>
|
|
<description>Comparator 1 VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_1_</name>
|
|
<description>Vref divider 1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN0</name>
|
|
<description>CMP1_IN[0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN1</name>
|
|
<description>CMP1_IN[1].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN2</name>
|
|
<description>CMP1_IN[2].</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN3</name>
|
|
<description>CMP1_IN[3].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN0</name>
|
|
<description>CMP0_IN[0].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0_9_V_BAND_</name>
|
|
<description>internal 0.9 V band gap reference.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMPERATURE_SENSOR_</name>
|
|
<description>temperature sensor.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP1_VP</name>
|
|
<description>Comparator 1 VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_0_</name>
|
|
<description>Vref divider 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN0</name>
|
|
<description>CMP1_IN[0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN1</name>
|
|
<description>CMP1_IN[1].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN2</name>
|
|
<description>CMP1_IN[2].</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN3</name>
|
|
<description>CMP1_IN[3].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN0</name>
|
|
<description>CMP0_IN[0].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0_9_V_BAND_</name>
|
|
<description>internal 0.9 V band gap reference.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMPERATURE_SENSOR_</name>
|
|
<description>temperature sensor.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP1_SYNC</name>
|
|
<description>Comparator 1 output synchronization control.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECT</name>
|
|
<description>The comparator 1 output is used directly.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCH</name>
|
|
<description>The comparator 1 output is synchronized with the internal bus clock for output to other peripherals.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_HYS</name>
|
|
<description>Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESISOFF</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV_</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV_</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV_</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_INTPOL</name>
|
|
<description>Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOTINVERTED</name>
|
|
<description>The CMP1 output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The CMP1 output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_INTTYPE</name>
|
|
<description>Select comparator 1 interrupt type. See Table 412.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Comparator 1 interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Comparator 1 interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Comparator 1 interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Comparator 1 interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUALEDGE</name>
|
|
<description>Comparator 1 Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_INTFLAG</name>
|
|
<description>Comparator 1 interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOTPENDING</name>
|
|
<description>The Comparator 1 interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 1.</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The Comparator 1 voltage ladder is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_DEEPSLP_PWRDWN</name>
|
|
<description>The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PWRDWN</name>
|
|
<description>The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The Comparator 1 voltage ladder is enabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1_VLADREF</name>
|
|
<description>Voltage reference select for comparator 1 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN_</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN_</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CMP1_VSel</name>
|
|
<description>Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description> Real Time Clock (RTC) </description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ILR</name>
|
|
<description>Interrupt Location Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCCIF</name>
|
|
<description>When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTCALF</name>
|
|
<description>When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Clock Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TIME_COUNTERS_AR</name>
|
|
<description>The time counters are enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIME_COUNTERS_AR</name>
|
|
<description>The time counters are disabled so that they may be initialized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTCRST</name>
|
|
<description>CTC Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT_</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Internal test mode controls. These bits must be 0 for normal RTC operation.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CCALEN</name>
|
|
<description>Calibration counter enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_CALIBRATION_COUN</name>
|
|
<description>The calibration counter is disabled and reset to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_CALIBRATION_COUN</name>
|
|
<description>The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIIR</name>
|
|
<description>Counter Increment Interrupt Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMSEC</name>
|
|
<description>When 1, an increment of the Second value generates an interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMMIN</name>
|
|
<description>When 1, an increment of the Minute value generates an interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMHOUR</name>
|
|
<description>When 1, an increment of the Hour value generates an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOM</name>
|
|
<description>When 1, an increment of the Day of Month value generates an interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOW</name>
|
|
<description>When 1, an increment of the Day of Week value generates an interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOY</name>
|
|
<description>When 1, an increment of the Day of Year value generates an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMMON</name>
|
|
<description>When 1, an increment of the Month value generates an interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMYEAR</name>
|
|
<description>When 1, an increment of the Year value generates an interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMR</name>
|
|
<description>Alarm Mask Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMRSEC</name>
|
|
<description>When 1, the Second value is not compared for the alarm.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRMIN</name>
|
|
<description>When 1, the Minutes value is not compared for the alarm.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRHOUR</name>
|
|
<description>When 1, the Hour value is not compared for the alarm.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOM</name>
|
|
<description>When 1, the Day of Month value is not compared for the alarm.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOW</name>
|
|
<description>When 1, the Day of Week value is not compared for the alarm.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOY</name>
|
|
<description>When 1, the Day of Year value is not compared for the alarm.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRMON</name>
|
|
<description>When 1, the Month value is not compared for the alarm.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRYEAR</name>
|
|
<description>When 1, the Year value is not compared for the alarm.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
<register>
|
|
<name>CTIME0</name>
|
|
<description>Consolidated Time Register 0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIME1</name>
|
|
<description>Consolidated Time Register 1</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIME2</name>
|
|
<description>Consolidated Time Register 2</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEC</name>
|
|
<description>Seconds Counter</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIN</name>
|
|
<description>Minutes Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRS</name>
|
|
<description>Hours Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOM</name>
|
|
<description>Day of Month Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOW</name>
|
|
<description>Day of Week Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOY</name>
|
|
<description>Day of Year Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MONTH</name>
|
|
<description>Months Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YEAR</name>
|
|
<description>Years Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIBRATION</name>
|
|
<description>Calibration Value Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CALVAL</name>
|
|
<description>If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CALDIR</name>
|
|
<description>Calibration direction</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BACKWARD_CALIBRATION</name>
|
|
<description>Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORWARD_CALIBRATION_</name>
|
|
<description>Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-4</dimIndex>
|
|
<name>GPREG%s</name>
|
|
<description>General Purpose Register 0</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GP</name>
|
|
<description>General purpose storage.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTC_AUX</name>
|
|
<description>RTC Auxiliary control register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_OSCF</name>
|
|
<description>RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_PDOUT</name>
|
|
<description>When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTC_AUXEN</name>
|
|
<description>RTC Auxiliary Enable register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_OSCFEN</name>
|
|
<description>Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASEC</name>
|
|
<description>Alarm value for Seconds</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMIN</name>
|
|
<description>Alarm value for Minutes</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHRS</name>
|
|
<description>Alarm value for Hours</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOM</name>
|
|
<description>Alarm value for Day of Month</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOW</name>
|
|
<description>Alarm value for Day of Week</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOY</name>
|
|
<description>Alarm value for Day of Year</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMON</name>
|
|
<description>Alarm value for Months</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AYRS</name>
|
|
<description>Alarm value for Year</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERCONTROL</name>
|
|
<description>Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup.</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTWAKE_EN0</name>
|
|
<description>Interrupt and wakeup enable for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_OR_WAKE</name>
|
|
<description>No interrupt or wakeup will be generated by event channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_EVENT_IN_CHANNEL_</name>
|
|
<description>An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN0</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOGPREG</name>
|
|
<description>Channel 0 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRGPREG</name>
|
|
<description>An event in channel 0 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Selects the polarity of an event on input pin RTC_EV0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEG</name>
|
|
<description>A channel 0 event is defined as a negative edge on RTC_EV0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS</name>
|
|
<description>A channel 0 event is defined as a positive edge on RTC_EV0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV0_INPUT_EN</name>
|
|
<description>Event enable control for channel 0.[1]</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 0 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 0 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTWAKE_EN1</name>
|
|
<description>Interrupt and wakeup enable for channel 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_OR_WAKE</name>
|
|
<description>No interrupt or wakeup will be generated by event channel 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKEUP</name>
|
|
<description>An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN1</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOGPREG</name>
|
|
<description>Channel 1 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRGPREG</name>
|
|
<description>A n event in channel 1 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Selects the polarity of an event on input pin RTC_EV1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEG</name>
|
|
<description>A channel 1 event is defined as a negative edge on RTC_EV1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS</name>
|
|
<description>A channel 1 event is defined as a positive edge on RTC_EV1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV1_INPUT_EN</name>
|
|
<description>Event enable control for channel 1.[1]</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 1 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 1 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[19:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTWAKE_EN2</name>
|
|
<description>Interrupt and wakeup enable for channel 2.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_OR_WAKE</name>
|
|
<description>No interrupt or wakeup will be generated by event channel 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKEUP</name>
|
|
<description>An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN2</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOGPREG</name>
|
|
<description>Channel 2 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRGPREG</name>
|
|
<description>An event in channel 2 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Selects the polarity of an event on input pin RTC_EV2.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEG</name>
|
|
<description>A channel 2 event is defined as a negative edge on RTC_EV2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS</name>
|
|
<description>A channel 2 event is defined as a positive edge on RTC_EV2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV2_INPUT_EN</name>
|
|
<description>Event enable control for channel 2.[1]</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 2 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 2 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERMODE</name>
|
|
<description>Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_EVENT_MONITOR16HZ</name>
|
|
<description>Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_EVENT_MONITOR64HZ</name>
|
|
<description>Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_EVENT_MONITOR1KHZ</name>
|
|
<description>Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERSTATUS</name>
|
|
<description>Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EV0</name>
|
|
<description>Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EVENT_CHANGE_ON_C</name>
|
|
<description>No event change on channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_EVENT_H</name>
|
|
<description>At least one event has occurred on channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV1</name>
|
|
<description>Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EVENT_CHANGE_ON_C</name>
|
|
<description>No event change on channel 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_EVENT_H</name>
|
|
<description>At least one event has occurred on channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV2</name>
|
|
<description>Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EVENT_CHANGE_ON_C</name>
|
|
<description>No event change on channel 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_EVENT_H</name>
|
|
<description>At least one event has occurred on channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GP_CLEARED</name>
|
|
<description>General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOGPCLR</name>
|
|
<description>General purpose registers have not been asynchronous cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPCLR</name>
|
|
<description>General purpose registers have been asynchronous cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[30:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPTWAKEUP_</name>
|
|
<description>No interrupt/wakeup request is pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTWAKEUP_PEND</name>
|
|
<description>An interrupt/wakeup request is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERCOUNTERS</name>
|
|
<description>Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels.</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER0</name>
|
|
<description>Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COUNTER1</name>
|
|
<description>Value of the counter for event 1. See description for COUNTER0.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COUNTER2</name>
|
|
<description>Value of the counter for event 2. See description for COUNTER0.</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>ERFIRSTSTAMP%s</name>
|
|
<description>Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0.</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Seconds value in the range of 0 to 59.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Minutes value in the range of 0 to 59.</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hours value in the range of 0 to 23.</description>
|
|
<bitRange>[16:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of Year value in the range of 1 to 366.</description>
|
|
<bitRange>[25:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>ERLASTSTAMP%s</name>
|
|
<description>Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0.</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Seconds value in the range of 0 to 59.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Minutes value in the range of 0 to 59.</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hours value in the range of 0 to 23.</description>
|
|
<bitRange>[16:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of Year value in the range of 1 to 366.</description>
|
|
<bitRange>[25:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPIOINT</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIOINT</groupName>
|
|
<!-- change this to base address 0x40028080 to be backwards compatible -->
|
|
<baseAddress>0x40028080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIOINT</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>GPIO overall Interrupt Status.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0Int</name>
|
|
<description>Port 0 GPIO interrupt pending.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupts on Port 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_PENDING</name>
|
|
<description>At least one pending interrupt on Port 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>P2Int</name>
|
|
<description>Port 2 GPIO interrupt pending.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupts on Port 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_PENDING</name>
|
|
<description>At least one pending interrupt on Port 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATR0</name>
|
|
<description>GPIO Interrupt Status for Rising edge for Port 0.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0_0REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_1REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_2REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_3REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_4REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_5REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_6REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_7REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_8REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_9REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_10REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_11REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_12REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_13REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_14REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_15REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_16REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_17REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_18REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_19REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_20REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_21REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_22REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_23REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_24REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_25REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_26REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_27REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_28REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_29REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_30REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_31REI</name>
|
|
<description>Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATF0</name>
|
|
<description>GPIO Interrupt Status for Falling edge for Port 0.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0_0FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_1FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_2FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_3FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_4FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_5FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_6FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_7FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_8FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_9FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_10FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_11FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_12FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_13FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_14FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_15FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_16FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_17FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_18FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_19FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_20FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_21FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_22FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_23FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_24FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_25FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_26FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_27FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_28FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_29FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_30FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_31FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR0</name>
|
|
<description>GPIO Interrupt Clear.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0_0CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_1CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_2CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_3CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_4CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_5CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_6CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_7CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_8CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_9CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_10CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_11CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_12CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_13CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_14CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_15CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_16CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_17CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_18CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_19CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_20CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_21CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_22CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_23CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_24CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_25CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_26CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_27CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_28CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_29CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_30CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_31CI</name>
|
|
<description>Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENR0</name>
|
|
<description>GPIO Interrupt Enable for Rising edge for Port 0.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0_0ER</name>
|
|
<description>Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_1ER</name>
|
|
<description>Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_2ER</name>
|
|
<description>Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_3ER</name>
|
|
<description>Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_4ER</name>
|
|
<description>Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_5ER</name>
|
|
<description>Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_6ER</name>
|
|
<description>Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_7ER</name>
|
|
<description>Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_8ER</name>
|
|
<description>Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_9ER</name>
|
|
<description>Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_10ER</name>
|
|
<description>Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_11ER</name>
|
|
<description>Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_12ER</name>
|
|
<description>Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_13ER</name>
|
|
<description>Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_14ER</name>
|
|
<description>Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_15ER</name>
|
|
<description>Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_16ER</name>
|
|
<description>Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_17ER</name>
|
|
<description>Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_18ER</name>
|
|
<description>Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_19ER</name>
|
|
<description>Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_20ER</name>
|
|
<description>Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_21ER</name>
|
|
<description>Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_22ER</name>
|
|
<description>Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_23ER</name>
|
|
<description>Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_24ER</name>
|
|
<description>Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_25ER</name>
|
|
<description>Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_26ER</name>
|
|
<description>Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_27ER</name>
|
|
<description>Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_28ER</name>
|
|
<description>Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_29ER</name>
|
|
<description>Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_30ER</name>
|
|
<description>Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_31ER</name>
|
|
<description>Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENF0</name>
|
|
<description>GPIO Interrupt Enable for Falling edge for Port 0.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P0_0EF</name>
|
|
<description>Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_1EF</name>
|
|
<description>Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_2EF</name>
|
|
<description>Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_3EF</name>
|
|
<description>Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_4EF</name>
|
|
<description>Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_5EF</name>
|
|
<description>Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_6EF</name>
|
|
<description>Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_7EF</name>
|
|
<description>Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_8EF</name>
|
|
<description>Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_9EF</name>
|
|
<description>Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_10EF</name>
|
|
<description>Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_11EF</name>
|
|
<description>Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_12EF</name>
|
|
<description>Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_13EF</name>
|
|
<description>Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_14EF</name>
|
|
<description>Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_15EF</name>
|
|
<description>Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_16EF</name>
|
|
<description>Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_17EF</name>
|
|
<description>Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_18EF</name>
|
|
<description>Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_19EF</name>
|
|
<description>Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_20EF</name>
|
|
<description>Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_21EF</name>
|
|
<description>Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_22EF</name>
|
|
<description>Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_23EF</name>
|
|
<description>Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_24EF</name>
|
|
<description>Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_25EF</name>
|
|
<description>Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_26EF</name>
|
|
<description>Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_27EF</name>
|
|
<description>Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_28EF</name>
|
|
<description>Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_29EF</name>
|
|
<description>Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_30EF</name>
|
|
<description>Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P0_31EF</name>
|
|
<description>Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATR2</name>
|
|
<description>GPIO Interrupt Status for Rising edge for Port 0.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2_0REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_1REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_2REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_3REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_4REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_5REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_6REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_7REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_8REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_9REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_10REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_11REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_12REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_13REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_14REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_15REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_16REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_17REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_18REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_19REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_20REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_21REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_22REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_23REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_24REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_25REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_26REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_27REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_28REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_29REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_30REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_31REI</name>
|
|
<description>Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATF2</name>
|
|
<description>GPIO Interrupt Status for Falling edge for Port 0.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2_0FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_1FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_2FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_3FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_4FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_5FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_6FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_7FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_8FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_9FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_10FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_11FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_12FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_13FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_14FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_15FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_16FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_17FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_18FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_19FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_20FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_21FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_22FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_23FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_24FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_25FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_26FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_27FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_28FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_29FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_30FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_31FEI</name>
|
|
<description>Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR2</name>
|
|
<description>GPIO Interrupt Clear.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2_0CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_1CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_2CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_3CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_4CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_5CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_6CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_7CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_8CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_9CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_10CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_11CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_12CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_13CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_14CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_15CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_16CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_17CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_18CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_19CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_20CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_21CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_22CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_23CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_24CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_25CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_26CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_27CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_28CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_29CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_30CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_31CI</name>
|
|
<description>Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENR2</name>
|
|
<description>GPIO Interrupt Enable for Rising edge for Port 0.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2_0ER</name>
|
|
<description>Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_1ER</name>
|
|
<description>Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_2ER</name>
|
|
<description>Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_3ER</name>
|
|
<description>Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_4ER</name>
|
|
<description>Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_5ER</name>
|
|
<description>Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_6ER</name>
|
|
<description>Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_7ER</name>
|
|
<description>Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_8ER</name>
|
|
<description>Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_9ER</name>
|
|
<description>Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_10ER</name>
|
|
<description>Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_11ER</name>
|
|
<description>Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_12ER</name>
|
|
<description>Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_13ER</name>
|
|
<description>Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_14ER</name>
|
|
<description>Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_15ER</name>
|
|
<description>Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_16ER</name>
|
|
<description>Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_17ER</name>
|
|
<description>Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_18ER</name>
|
|
<description>Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_19ER</name>
|
|
<description>Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_20ER</name>
|
|
<description>Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_21ER</name>
|
|
<description>Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_22ER</name>
|
|
<description>Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_23ER</name>
|
|
<description>Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_24ER</name>
|
|
<description>Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_25ER</name>
|
|
<description>Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_26ER</name>
|
|
<description>Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_27ER</name>
|
|
<description>Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_28ER</name>
|
|
<description>Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_29ER</name>
|
|
<description>Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_30ER</name>
|
|
<description>Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_31ER</name>
|
|
<description>Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENF2</name>
|
|
<description>GPIO Interrupt Enable for Falling edge for Port 0.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P2_0EF</name>
|
|
<description>Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_1EF</name>
|
|
<description>Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_2EF</name>
|
|
<description>Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_3EF</name>
|
|
<description>Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_4EF</name>
|
|
<description>Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_5EF</name>
|
|
<description>Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_6EF</name>
|
|
<description>Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_7EF</name>
|
|
<description>Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_8EF</name>
|
|
<description>Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_9EF</name>
|
|
<description>Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_10EF</name>
|
|
<description>Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_11EF</name>
|
|
<description>Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_12EF</name>
|
|
<description>Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_13EF</name>
|
|
<description>Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_14EF</name>
|
|
<description>Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_15EF</name>
|
|
<description>Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_16EF</name>
|
|
<description>Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_17EF</name>
|
|
<description>Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_18EF</name>
|
|
<description>Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_19EF</name>
|
|
<description>Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_20EF</name>
|
|
<description>Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_21EF</name>
|
|
<description>Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_22EF</name>
|
|
<description>Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_23EF</name>
|
|
<description>Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_24EF</name>
|
|
<description>Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_25EF</name>
|
|
<description>Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_26EF</name>
|
|
<description>Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_27EF</name>
|
|
<description>Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_28EF</name>
|
|
<description>Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_29EF</name>
|
|
<description>Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_30EF</name>
|
|
<description>Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>P2_31EF</name>
|
|
<description>Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>IOCON</name>
|
|
<description>IOCON pin configuration</description>
|
|
<baseAddress>0x4002C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
|
|
|
|
<registers>
|
|
<register>
|
|
<name>P0_0</name>
|
|
<description>I/O configuration register for pin P0[0]</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_RD1</name>
|
|
<description>CAN1 receiver input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_TXD</name>
|
|
<description>Transmitter output for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SDA</name>
|
|
<description>I2C1 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U0_TXD</name>
|
|
<description>Transmitter output for UART0.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_1</name>
|
|
<description>I/O configuration register for pin P0[1]</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TD1</name>
|
|
<description>CAN1 transmitter output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_RXD</name>
|
|
<description>Receiver input for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SCL</name>
|
|
<description>I2C1 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U0_RXD</name>
|
|
<description>Receiver input for UART0.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_2</name>
|
|
<description>I/O configuration register for pin P0[2]</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U0_TXD</name>
|
|
<description>Transmitter output for UART0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_TXD</name>
|
|
<description>Transmitter output for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_3</name>
|
|
<description>I/O configuration register for pin P0[3]</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U0_RXD</name>
|
|
<description>Receiver input for UART0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_RXD</name>
|
|
<description>Receiver input for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_4</name>
|
|
<description>I/O configuration register for pin P0[4]</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[4]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_SCK</name>
|
|
<description>I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_RD2</name>
|
|
<description>CAN2 receiver input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP0</name>
|
|
<description>Capture input for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_ROSC</name>
|
|
<description>Comparator relaxation oscillator for 555 timer applications.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_0</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_5</name>
|
|
<description>I/O configuration register for pin P0[5]</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[5]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_5</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_WS</name>
|
|
<description>I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TD2</name>
|
|
<description>CAN2 transmitter output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP1</name>
|
|
<description>Capture input for Timer 2, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_RESET</name>
|
|
<description>Comparator reset.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_1</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_6</name>
|
|
<description>I/O configuration register for pin P0[6]</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[6]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_6</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_SDA</name>
|
|
<description>I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SSEL</name>
|
|
<description>Slave Select for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT0</name>
|
|
<description>Match output for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RTS</name>
|
|
<description>Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_ROSC</name>
|
|
<description>Comparator relaxation oscillator for 555 timer applications.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_8</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_7</name>
|
|
<description>I/O configuration register for pin P0[7] </description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[7] </description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_7</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_SCK</name>
|
|
<description>I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SCK</name>
|
|
<description>Serial Clock for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT1</name>
|
|
<description>Match output for Timer 2, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_EV0</name>
|
|
<description>Event input 0 to Event Monitor/Recorder.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_VREF</name>
|
|
<description>Comparator reference voltage.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_9</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Glitch filter control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Noise pulses below approximately 10 ns are filtered
|
|
out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No input filtering is done.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_8</name>
|
|
<description>I/O configuration register for pin P0[8] </description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[8] </description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_8</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_WS</name>
|
|
<description>I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MISO</name>
|
|
<description>Master In Slave Out for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT2</name>
|
|
<description>Match output for Timer 2, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_EV1</name>
|
|
<description>Event input 1 to Event Monitor/Recorder.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN_3</name>
|
|
<description>Comparator 1, input 3.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_16</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Glitch filter control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Noise pulses below approximately 10 ns are filtered
|
|
out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No input filtering is done.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_9</name>
|
|
<description>I/O configuration register for pin P0[9]</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[9]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_9</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_SDA</name>
|
|
<description>I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MOSI</name>
|
|
<description>Master Out Slave In for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT3</name>
|
|
<description>Match output for Timer 2, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_EV2</name>
|
|
<description>Event input 2 to Event Monitor/Recorder.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN_2</name>
|
|
<description>Comparator 1, input 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_17</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FILTER</name>
|
|
<description>Glitch filter control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Noise pulses below approximately 10 ns are filtered
|
|
out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No input filtering is done.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_10</name>
|
|
<description>I/O configuration register for pin P0[10]</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[10]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_10</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_TXD</name>
|
|
<description>Transmitter output for UART2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SDA</name>
|
|
<description>I2C2 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT0</name>
|
|
<description>Match output for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_5</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_11</name>
|
|
<description>I/O configuration register for pin P0[11]</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[11]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_11</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_RXD</name>
|
|
<description>Receiver input for UART2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SCL</name>
|
|
<description>I2C2 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT1</name>
|
|
<description>Match output for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_10</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_12</name>
|
|
<description>I/O configuration register for pin P0[12]</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[12]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_12</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PPWR2</name>
|
|
<description>Port Power enable signal for USB port 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MISO</name>
|
|
<description>Master In Slave Out for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_6</name>
|
|
<description>A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_13</name>
|
|
<description>I/O configuration register for pin P0[13]</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[13]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_13</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_UP_LED2</name>
|
|
<description>USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MOSI</name>
|
|
<description>Master Out Slave In for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_7</name>
|
|
<description>A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_14</name>
|
|
<description>I/O configuration register for pin P0[14]</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[14]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_14</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_HSTEN2</name>
|
|
<description>Host Enabled status for USB port 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SSEL</name>
|
|
<description>Slave Select for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_CONNECT2</name>
|
|
<description>SoftConnect control for USB port 2. Signal used to switch an external 1.5 kW resistor under software control. Used with the SoftConnect USB feature.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_15</name>
|
|
<description>I/O configuration register for pin P0[15]</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[15]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_15</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_TXD</name>
|
|
<description>Transmitter output for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SCK</name>
|
|
<description>Serial clock for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_IO_2</name>
|
|
<description>Data bit 0 for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_16</name>
|
|
<description>I/O configuration register for pin P0[16]</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[16]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_16</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RXD</name>
|
|
<description>Receiver input for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SSEL</name>
|
|
<description>Slave Select for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_IO_3</name>
|
|
<description>Data bit 0 for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_17</name>
|
|
<description>I/O configuration register for pin P0[17]</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[17]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_17</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_CTS</name>
|
|
<description>Clear to Send input for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MISO</name>
|
|
<description>Master In Slave Out for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_IO_1</name>
|
|
<description>Data bit 0 for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_18</name>
|
|
<description>I/O configuration register for pin P0[18]</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[18]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_18</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DCD</name>
|
|
<description>Data Carrier Detect input for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MOSI</name>
|
|
<description>Master Out Slave In for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_IO_0</name>
|
|
<description>Data bit 0 for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_19</name>
|
|
<description>I/O configuration register for pin P0[19]</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[19]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_19</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DSR</name>
|
|
<description>Data Set Ready input for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_CLK</name>
|
|
<description>Clock output line for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SDA</name>
|
|
<description>I2C1 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_13</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_20</name>
|
|
<description>I/O configuration register for pin P0[20]</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[20]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_20</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DTR</name>
|
|
<description>Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_CMD</name>
|
|
<description>Command line for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SCL</name>
|
|
<description>I2C1 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_14</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_21</name>
|
|
<description>I/O configuration register for pin P0[21]</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[21]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_21</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RI</name>
|
|
<description>Ring Indicator input for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_PWR</name>
|
|
<description>Power Supply Enable for external SD card power supply.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_OE</name>
|
|
<description>RS-485/EIA-485 output enable signal for UART4.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_RD1</name>
|
|
<description>CAN1 receiver input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_SCLK</name>
|
|
<description>USART 4 clock input or output in synchronous mode.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_22</name>
|
|
<description>I/O configuration register for pin P0[22]</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001B0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[22]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_22</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RTS</name>
|
|
<description>Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_0</name>
|
|
<description>Data line 0 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_TXD</name>
|
|
<description>Transmitter output for USART4 (input/output in smart card mode).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TD1</name>
|
|
<description>CAN1 transmitter output.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_CLK</name>
|
|
<description>Clock output for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_23</name>
|
|
<description>I/O configuration register for pin P0[23]</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[23]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_23</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_0</name>
|
|
<description>A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_SCK</name>
|
|
<description>Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP0</name>
|
|
<description>Capture input for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_24</name>
|
|
<description>I/O configuration register for pin P0[24]</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[24]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_24</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_1</name>
|
|
<description>A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_WS</name>
|
|
<description>Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP1</name>
|
|
<description>Capture input for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_25</name>
|
|
<description>I/O configuration register for pin P0[25]</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[25]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_25</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_2</name>
|
|
<description>A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_SDA</name>
|
|
<description>Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_TXD</name>
|
|
<description>Transmitter output for UART3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_26</name>
|
|
<description>I/O configuration register for pin P0[26]</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[26]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_26</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_3</name>
|
|
<description>A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC_OUT</name>
|
|
<description>D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_RXD</name>
|
|
<description>Receiver input for UART3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC output enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>DAC disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>DAC enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_27</name>
|
|
<description>I/O configuration register for pin P0[27]</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[27]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_27</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SDA</name>
|
|
<description>I2C0 data input/output. (This pin uses a specialized I2C pad).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_SDA1</name>
|
|
<description>I2C serial data for communication with an external USB transceiver.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>Configures I2C features for standard mode, fast mode, and Fast Mode
|
|
Plus operation.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIDRIVE</name>
|
|
<description>Controls sink current capability of the pin, only for P5[2] and
|
|
P5[3].</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOWDRIVE</name>
|
|
<description>Output drive sink is 4 mA. This is sufficient for standard
|
|
and fast mode I2C.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHDRIVE</name>
|
|
<description>Output drive sink is 20 mA. This is needed for Fast Mode
|
|
Plus I2C. Refer to the appropriate specific device data sheet for
|
|
details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_28</name>
|
|
<description>I/O configuration register for pin P0[28]</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[28]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_28</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SCL</name>
|
|
<description>I2C0 clock input/output (this pin uses a specialized I2C pad.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_SCL1</name>
|
|
<description>I2C serial clock for communication with an external USB transceiver.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>Configures I2C features for standard mode, fast mode, and Fast Mode
|
|
Plus operation.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIDRIVE</name>
|
|
<description>Controls sink current capability of the pin, only for P5[2] and
|
|
P5[3].</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOWDRIVE</name>
|
|
<description>Output drive sink is 4 mA. This is sufficient for standard
|
|
and fast mode I2C.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHDRIVE</name>
|
|
<description>Output drive sink is 20 mA. This is needed for Fast Mode
|
|
Plus I2C. Refer to the appropriate specific device data sheet for
|
|
details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_29</name>
|
|
<description>I/O configuration register for pin P0[29]</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[29]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_29</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DP1</name>
|
|
<description>USB port 1 bidirectional D+ line.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT0</name>
|
|
<description>External interrupt 0 input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_30</name>
|
|
<description>I/O configuration register for pin P0[30]</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[30]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_30</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DM1</name>
|
|
<description>USB port 1 bidirectional D- line.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT1</name>
|
|
<description>External interrupt 1 input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P0_31</name>
|
|
<description>I/O configuration register for pin P0[31]</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P0[31]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P0_31</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DP2</name>
|
|
<description>USB port 2 bidirectional D+ line.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_0</name>
|
|
<description>I/O configuration register for pin P1[0]</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TXD0</name>
|
|
<description>Ethernet transmit data 0 (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP1</name>
|
|
<description>Capture input for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_SCK</name>
|
|
<description>Serial clock for SSP2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_1</name>
|
|
<description>I/O configuration register for pin P1[1]</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TXD1</name>
|
|
<description>Ethernet transmit data 1 (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT3</name>
|
|
<description>Match output for Timer 3, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_MOSI</name>
|
|
<description>Master Out Slave In for SSP2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_2</name>
|
|
<description>I/O configuration register for pin P1[2]</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TXD2</name>
|
|
<description>Ethernet transmit data 2 (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_CLK</name>
|
|
<description>Clock output line for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_1</name>
|
|
<description>Pulse Width Modulator 0, output 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_3</name>
|
|
<description>I/O configuration register for pin P1[3]</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TXD3</name>
|
|
<description>Ethernet transmit data 3 (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_CMD</name>
|
|
<description>Command line for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_2</name>
|
|
<description>Pulse Width Modulator 0, output 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_4</name>
|
|
<description>I/O configuration register for pin P1[4] </description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[4] </description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_EN</name>
|
|
<description>Ethernet transmit data enable (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT2</name>
|
|
<description>Match output for Timer 3, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_MISO</name>
|
|
<description>Master In Slave Out for SSP2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_5</name>
|
|
<description>I/O configuration register for pin P1[5]</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[5]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_5</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_ER</name>
|
|
<description>Ethernet Transmit Error (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_PWR</name>
|
|
<description>Power Supply Enable for external SD card power supply.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_3</name>
|
|
<description>Pulse Width Modulator 0, output 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN_1</name>
|
|
<description>Comparator 1, input 1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_6</name>
|
|
<description>I/O configuration register for pin P1[6]</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[6]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_6</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>Ethernet Transmit Clock (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_0</name>
|
|
<description>Data line 0 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_4</name>
|
|
<description>Pulse Width Modulator 0, output 4.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN_3</name>
|
|
<description>Comparator 0, input 3.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_7</name>
|
|
<description>I/O configuration register for pin P1[7]</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[7]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_7</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_COL</name>
|
|
<description>Ethernet Collision detect (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_1</name>
|
|
<description>Data line 1 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_5</name>
|
|
<description>Pulse Width Modulator 0, output 5.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_IN_0</name>
|
|
<description>Comparator 1, input 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_8</name>
|
|
<description>I/O configuration register for pin P1[8]</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[8]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_8</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_CRS_CRS_DV</name>
|
|
<description>Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT1</name>
|
|
<description>Match output for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_SSEL</name>
|
|
<description>Slave Select for SSP2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_9</name>
|
|
<description>I/O configuration register for pin P1[9]</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[9]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_9</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RXD0</name>
|
|
<description>Ethernet receive data 0 (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT0</name>
|
|
<description>Match output for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_10</name>
|
|
<description>I/O configuration register for pin P1[10]</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[10]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_10</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RXD1</name>
|
|
<description>Ethernet receive data 1 (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP0</name>
|
|
<description>Capture input for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_11</name>
|
|
<description>I/O configuration register for pin P1[11]</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[11]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_11</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RXD2</name>
|
|
<description>Ethernet Receive Data 2 (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_2</name>
|
|
<description>Data line 2 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_6</name>
|
|
<description>Pulse Width Modulator 0, output 6.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_12</name>
|
|
<description>I/O configuration register for pin P1[12]</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[12]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_12</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RXD3</name>
|
|
<description>Ethernet Receive Data (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_3</name>
|
|
<description>Data line 3 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_CAP0</name>
|
|
<description>Capture input for PWM0, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP1_OUT</name>
|
|
<description>Comparator 1, output.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_13</name>
|
|
<description>I/O configuration register for pin P1[13]</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[13]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_13</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_DV</name>
|
|
<description>Ethernet Receive Data Valid (MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_14</name>
|
|
<description>I/O configuration register for pin P1[14]</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[14]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_14</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_ER</name>
|
|
<description>Ethernet receive error (RMII/MII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP0</name>
|
|
<description>Capture input for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN_0</name>
|
|
<description>Comparator 0, input 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_15</name>
|
|
<description>I/O configuration register for pin P1[15]</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[15]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_15</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK_REF_CLK</name>
|
|
<description>Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SDA</name>
|
|
<description>I2C2 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_16</name>
|
|
<description>I/O configuration register for pin P1[16]</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[16]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_16</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_MDC</name>
|
|
<description>Ethernet MIIM clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_MCLK</name>
|
|
<description>I2S transmit master clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN_1</name>
|
|
<description>Comparator 0, input 1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_17</name>
|
|
<description>I/O configuration register for pin P1[17]</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[17]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_17</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_MDIO</name>
|
|
<description>Ethernet MIIM data input and output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_RX_MCLK</name>
|
|
<description>I2S receive master clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_IN_2</name>
|
|
<description>Comparator 0, input 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_18</name>
|
|
<description>I/O configuration register for pin P1[18]</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[18]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_18</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_UP_LED1</name>
|
|
<description>It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_1</name>
|
|
<description>Pulse Width Modulator 1, channel 1 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP0</name>
|
|
<description>Capture input for Timer 1, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MISO</name>
|
|
<description>Master In Slave Out for SSP1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_19</name>
|
|
<description>I/O configuration register for pin P1[19]</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[19]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_19</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TX_E1</name>
|
|
<description>Transmit Enable signal for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PPWR1</name>
|
|
<description>Port Power enable signal for USB port 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP1</name>
|
|
<description>Capture input for Timer 1, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_0A</name>
|
|
<description>Motor control PWM channel 0, output A.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SCK</name>
|
|
<description>Serial clock for SSP1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_OE</name>
|
|
<description>RS-485/EIA-485 output enable signal for UART2.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_20</name>
|
|
<description>I/O configuration register for pin P1[20]</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[20]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_20</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TX_DP1</name>
|
|
<description>D+ transmit data for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_2</name>
|
|
<description>Pulse Width Modulator 1, channel 2 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_PHA</name>
|
|
<description>Quadrature Encoder Interface PHA input.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_FB0</name>
|
|
<description>Motor control PWM channel 0 feedback input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SCK</name>
|
|
<description>Serial clock for SSP0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_6</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_10</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_21</name>
|
|
<description>I/O configuration register for pin P1[21]</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[21]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_21</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TX_DM1</name>
|
|
<description>D- transmit data for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_3</name>
|
|
<description>Pulse Width Modulator 1, channel 3 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SSEL</name>
|
|
<description>Slave Select for SSP0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_ABORT</name>
|
|
<description>Motor control PWM, active low fast abort.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_7</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_11</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_22</name>
|
|
<description>I/O configuration register for pin P1[22]</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[22]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_22</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RCV1</name>
|
|
<description>Differential receive data for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PWRD1</name>
|
|
<description>Power Status for USB port 1 (host power switch).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT0</name>
|
|
<description>Match output for Timer 1, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_0B</name>
|
|
<description>Motor control PWM channel 0, output B.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MOSI</name>
|
|
<description>Master Out Slave In for SSP1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_8</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_12</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_23</name>
|
|
<description>I/O configuration register for pin P1[23]</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[23]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_23</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RX_DP1</name>
|
|
<description>D+ receive data for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_4</name>
|
|
<description>Pulse Width Modulator 1, channel 4 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_PHB</name>
|
|
<description>Quadrature Encoder Interface PHB input.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_FB1</name>
|
|
<description>Motor control PWM channel 1 feedback input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MISO</name>
|
|
<description>Master In Slave Out for SSP0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_9</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_13</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_24</name>
|
|
<description>I/O configuration register for pin P1[24]</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[24]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_24</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RX_DM1</name>
|
|
<description>D- receive data for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_5</name>
|
|
<description>Pulse Width Modulator 1, channel 5 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_IDX</name>
|
|
<description>Quadrature Encoder Interface INDEX input.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_FB2</name>
|
|
<description>Motor control PWM channel 2 feedback input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MOSI</name>
|
|
<description>Master Out Slave in for SSP0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_10</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_14</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_25</name>
|
|
<description>I/O configuration register for pin P1[25]</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[25]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_25</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_LS1</name>
|
|
<description>Low Speed status for USB port 1 (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_HSTEN1</name>
|
|
<description>Host Enabled status for USB port 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT1</name>
|
|
<description>Match output for Timer 1, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1A</name>
|
|
<description>Motor control PWM channel 1, output A.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Selectable clock output.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_11</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_15</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_26</name>
|
|
<description>I/O configuration register for pin P1[26]</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[26]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_26</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_SSPND1</name>
|
|
<description>USB port 1 Bus Suspend status (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_6</name>
|
|
<description>Pulse Width Modulator 1, channel 6 output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP0</name>
|
|
<description>Capture input for Timer 0, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_1B</name>
|
|
<description>Motor control PWM channel 1, output B.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SSEL</name>
|
|
<description>Slave Select for SSP1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_12</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_20</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_27</name>
|
|
<description>I/O configuration register for pin P1[27]</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[27]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_27</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_INT1</name>
|
|
<description>USB port 1 OTG transceiver interrupt (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OVRCR1</name>
|
|
<description>USB port 1 Over-Current status.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP1</name>
|
|
<description>Capture input for Timer 0, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT</name>
|
|
<description>Selectable clock output.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_13</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_21</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_28</name>
|
|
<description>I/O configuration register for pin P1[28]</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[28]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_28</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_SCL1</name>
|
|
<description>USB port 1 I2C serial clock (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_CAP0</name>
|
|
<description>Capture input for PWM1, channel 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT0</name>
|
|
<description>Match output for Timer 0, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2A</name>
|
|
<description>Motor control PWM channel 2, output A.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SSEL</name>
|
|
<description>Slave Select for SSP0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_14</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_22</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_29</name>
|
|
<description>I/O configuration register for pin P1[29]</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[29]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_29</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_SDA1</name>
|
|
<description>USB port 1 I2C serial data (OTG transceiver).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_CAP1</name>
|
|
<description>Capture input for PWM1, channel 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT1</name>
|
|
<description>Match output for Timer 0, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_2B</name>
|
|
<description>Motor control PWM channel 2, output B.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_TXD</name>
|
|
<description>Transmitter output for USART4 (input/output in smart card mode).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_15</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_23</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_30</name>
|
|
<description>I/O configuration register for pin P1[30]</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[30]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_30</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PWRD2</name>
|
|
<description>Power Status for USB port 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_VBUS</name>
|
|
<description>Monitors the presence of USB bus power.This signal must be HIGH for USB reset to occur.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_4</name>
|
|
<description>A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SDA</name>
|
|
<description>I2C0 data input/output (this pin does not use a specialized I2C pad.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_OE</name>
|
|
<description>RS-485/EIA-485 output enable signal for UART3.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P1_31</name>
|
|
<description>I/O configuration register for pin P1[31]</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P1[31]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P1_31</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OVRCR2</name>
|
|
<description>Over-Current status for USB port 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SCK</name>
|
|
<description>Serial Clock for SSP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_IN_5</name>
|
|
<description>A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SCL</name>
|
|
<description>I2C0 clock input/output (this pin does not use a specialized I2C pad.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_0</name>
|
|
<description>I/O configuration register for pin P2[0]</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_1</name>
|
|
<description>Pulse Width Modulator 1, channel 1 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_TXD</name>
|
|
<description>Transmitter output for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_PWR</name>
|
|
<description>LCD panel power enable.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_1</name>
|
|
<description>I/O configuration register for pin P2[1]</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_2</name>
|
|
<description>Pulse Width Modulator 1, channel 2 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RXD</name>
|
|
<description>Receiver input for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_LE</name>
|
|
<description>Line end signal.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_2</name>
|
|
<description>I/O configuration register for pin P2[2]</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_3</name>
|
|
<description>Pulse Width Modulator 1, channel 3 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_CTS</name>
|
|
<description>Clear to Send input for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT3</name>
|
|
<description>Match output for Timer 2, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACEDATA_3</name>
|
|
<description>Trace data, bit 3.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_DCLK</name>
|
|
<description>LCD panel clock.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_3</name>
|
|
<description>I/O configuration register for pin P2[3]</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_4</name>
|
|
<description>Pulse Width Modulator 1, channel 4 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DCD</name>
|
|
<description>Data Carrier Detect input for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT2</name>
|
|
<description>Match output for Timer 2, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACEDATA_2</name>
|
|
<description>Trace data, bit 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_FP</name>
|
|
<description>Frame pulse (STN). Vertical synchronization pulse (TFT).</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_4</name>
|
|
<description>I/O configuration register for pin P2[4]</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[4]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_5</name>
|
|
<description>Pulse Width Modulator 1, channel 5 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DSR</name>
|
|
<description>Data Set Ready input for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT1</name>
|
|
<description>Match output for Timer 2, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACEDATA_1</name>
|
|
<description>Trace data, bit 1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_ENAB_M</name>
|
|
<description>STN AC bias drive or TFT data enable output.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_5</name>
|
|
<description>I/O configuration register for pin P2[5]</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[5]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_5</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_6</name>
|
|
<description>Pulse Width Modulator 1, channel 6 output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DTR</name>
|
|
<description>Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT0</name>
|
|
<description>Match output for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACEDATA_0</name>
|
|
<description>Trace data, bit 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_LP</name>
|
|
<description>Line synchronization pulse (STN). Horizontal synchronization pulse (TFT).</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_6</name>
|
|
<description>I/O configuration register for pin P2[6]</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[6]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_6</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_CAP0</name>
|
|
<description>Capture input for PWM1, channel 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RI</name>
|
|
<description>Ring Indicator input for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP0</name>
|
|
<description>Capture input for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_OE</name>
|
|
<description>RS-485/EIA-485 output enable signal for UART2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACECLK</name>
|
|
<description>Trace clock.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_0</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_4</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_7</name>
|
|
<description>I/O configuration register for pin P2[7]</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[7]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_7</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_RD2</name>
|
|
<description>CAN2 receiver input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RTS</name>
|
|
<description>Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIFI_CS</name>
|
|
<description>Chip select output for SPIFI.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_1</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_5</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_8</name>
|
|
<description>I/O configuration register for pin P2[8]</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[8]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_8</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TD2</name>
|
|
<description>CAN2 transmitter output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_TXD</name>
|
|
<description>Transmitter output for UART2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_CTS</name>
|
|
<description>Clear to Send input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_MDC</name>
|
|
<description>Ethernet MIIM clock.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_2</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_6</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_9</name>
|
|
<description>I/O configuration register for pin P2[9]</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[9]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_9</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_CONNECT1</name>
|
|
<description>USB1 SoftConnect control. Signal used to switch an external 1.5 kW resistor under the software control. Used with the SoftConnect USB feature.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_RXD</name>
|
|
<description>Receiver input for UART2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_RXD</name>
|
|
<description>Receiver input for USART4.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_MDIO</name>
|
|
<description>Ethernet MIIM data input and output.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_3</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_7</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_10</name>
|
|
<description>I/O configuration register for pin P2[10]</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[10]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_10</name>
|
|
<description>General purpose digital input/output pin. This pin
|
|
includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip
|
|
boot loader to take over control of the part after a reset and
|
|
go into ISP mode. </description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT0</name>
|
|
<description>External interrupt 0 input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NMI</name>
|
|
<description>Non-maskable interrupt input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_11</name>
|
|
<description>I/O configuration register for pin P2[11]</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[11]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_11</name>
|
|
<description>General purpose digital input/output pin. This pin
|
|
includes a 5 ns input glitch filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT1</name>
|
|
<description>External interrupt 1 input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_1</name>
|
|
<description>Data line 1 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_SCK</name>
|
|
<description>Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_CLKIN</name>
|
|
<description>LCD clock.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_12</name>
|
|
<description>I/O configuration register for pin P2[12]</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[12]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_12</name>
|
|
<description>General purpose digital input/output pin. This pin
|
|
includes a 5 ns input glitch filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT2</name>
|
|
<description>External interrupt 2 input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_2</name>
|
|
<description>Data line 2 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_WS</name>
|
|
<description>Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_4</name>
|
|
<description>LCD data.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_3</name>
|
|
<description>LCD data.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_8</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_18</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_13</name>
|
|
<description>I/O configuration register for pin P2[13]</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<access>read-write</access>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[13]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_13</name>
|
|
<description>General purpose digital input/output pin. This pin
|
|
includes a 5 ns input glitch filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EINT3</name>
|
|
<description>External interrupt 3 input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_DAT_3</name>
|
|
<description>Data line 3 for SD card interface.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S_TX_SDA</name>
|
|
<description>Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_5</name>
|
|
<description>LCD data.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_9</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_19</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_14</name>
|
|
<description>I/O configuration register for pin P2[14]</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[14]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_14</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CS2</name>
|
|
<description>LOW active Chip Select 2 signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SDA</name>
|
|
<description>I2C1 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP0</name>
|
|
<description>Capture input for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_15</name>
|
|
<description>I/O configuration register for pin P2[15]</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[15]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_15</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CS3</name>
|
|
<description>LOW active Chip Select 3 signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1_SCL</name>
|
|
<description>I2C1 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP1</name>
|
|
<description>Capture input for Timer 2, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_16</name>
|
|
<description>I/O configuration register for pin P2[16]</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[16]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_16</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CAS</name>
|
|
<description>LOW active SDRAM Column Address Strobe.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_17</name>
|
|
<description>I/O configuration register for pin P2[17]</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[17]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_17</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_RAS</name>
|
|
<description>LOW active SDRAM Row Address Strobe.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_18</name>
|
|
<description>I/O configuration register for pin P2[18]</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001B0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[18]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_18</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CLK_0</name>
|
|
<description>SDRAM clock 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_19</name>
|
|
<description>I/O configuration register for pin P2[19]</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001B0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[19]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_19</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CLK_1</name>
|
|
<description>SDRAM clock 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_20</name>
|
|
<description>I/O configuration register for pin P2[20]</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[20]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_20</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DYCS0</name>
|
|
<description>SDRAM chip select 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_21</name>
|
|
<description>I/O configuration register for pin P2[21]</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[21]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_21</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DYCS1</name>
|
|
<description>SDRAM chip select 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_22</name>
|
|
<description>I/O configuration register for pin P2[22]</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[22]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_22</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DYCS2</name>
|
|
<description>SDRAM chip select 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SCK</name>
|
|
<description>Serial clock for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP0</name>
|
|
<description>Capture input for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_23</name>
|
|
<description>I/O configuration register for pin P2[23]</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[23]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_23</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DYCS3</name>
|
|
<description>SDRAM chip select 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_SSEL</name>
|
|
<description>Slave Select for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP1</name>
|
|
<description>Capture input for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_24</name>
|
|
<description>I/O configuration register for pin P2[24]</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[24]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_24</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CKE0</name>
|
|
<description>SDRAM clock enable 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_25</name>
|
|
<description>I/O configuration register for pin P2[25]</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[25]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_25</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CKE1</name>
|
|
<description>SDRAM clock enable 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_26</name>
|
|
<description>I/O configuration register for pin P2[26]</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[26]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_26</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CKE2</name>
|
|
<description>SDRAM clock enable 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MISO</name>
|
|
<description>Master In Slave Out for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT0</name>
|
|
<description>Match output for Timer 3, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_27</name>
|
|
<description>I/O configuration register for pin P2[27]</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[27]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_27</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CKE3</name>
|
|
<description>SDRAM clock enable 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_MOSI</name>
|
|
<description>Master Out Slave In for SSP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT1</name>
|
|
<description>Match output for Timer 3, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_28</name>
|
|
<description>I/O configuration register for pin P2[28]</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[28]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_28</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DQM0</name>
|
|
<description>Data mask 0 used with SDRAM and static devices.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_29</name>
|
|
<description>I/O configuration register for pin P2[29]</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[29]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_29</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DQM1</name>
|
|
<description>Data mask 1 used with SDRAM and static devices.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_30</name>
|
|
<description>I/O configuration register for pin P2[30]</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[30]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_30</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DQM2</name>
|
|
<description>Data mask 2 used with SDRAM and static devices.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SDA</name>
|
|
<description>I2C2 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT2</name>
|
|
<description>Match output for Timer 3, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P2_31</name>
|
|
<description>I/O configuration register for pin P2[31]</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P2[31]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P2_31</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_DQM3</name>
|
|
<description>Data mask 3 used with SDRAM and static devices.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SCL</name>
|
|
<description>I2C2 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT3</name>
|
|
<description>Match output for Timer 3, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_0</name>
|
|
<description>I/O configuration register for pin P3[0]</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_0</name>
|
|
<description>External memory data line 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_1</name>
|
|
<description>I/O configuration register for pin P3[1]</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_1</name>
|
|
<description>External memory data line 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_2</name>
|
|
<description>I/O configuration register for pin P3[2]</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_2</name>
|
|
<description>External memory data line 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_3</name>
|
|
<description>I/O configuration register for pin P3[3]</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_3</name>
|
|
<description>External memory data line 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_4</name>
|
|
<description>I/O configuration register for pin P3[4]</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[4]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_4</name>
|
|
<description>External memory data line 4.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_5</name>
|
|
<description>I/O configuration register for pin P3[5]</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[5]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_5</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_5</name>
|
|
<description>External memory data line 5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_6</name>
|
|
<description>I/O configuration register for pin P3[6]</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[6]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_6</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_6</name>
|
|
<description>External memory data line 6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_7</name>
|
|
<description>I/O configuration register for pin P3[7]</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[7]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_7</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_7</name>
|
|
<description>External memory data line 7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_8</name>
|
|
<description>I/O configuration register for pin P3[8]</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[8]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_8</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_8</name>
|
|
<description>External memory data line 8.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_9</name>
|
|
<description>I/O configuration register for pin P3[9]</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[9]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_9</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_9</name>
|
|
<description>External memory data line 9.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_10</name>
|
|
<description>I/O configuration register for pin P3[10]</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[10]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_10</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_10</name>
|
|
<description>External memory data line 10.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_11</name>
|
|
<description>I/O configuration register for pin P3[11]</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[11]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_11</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_11</name>
|
|
<description>External memory data line 11.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_12</name>
|
|
<description>I/O configuration register for pin P3[12]</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[12]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_12</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_12</name>
|
|
<description>External memory data line 12.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_13</name>
|
|
<description>I/O configuration register for pin P3[13]</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[13]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_13</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_13</name>
|
|
<description>External memory data line 13.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_14</name>
|
|
<description>I/O configuration register for pin P3[14]</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[14]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_14</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_14</name>
|
|
<description>External memory data line 14. </description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_15</name>
|
|
<description>I/O configuration register for pin P3[15]</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[15]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_15</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_15</name>
|
|
<description>External memory data line 15. </description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_16</name>
|
|
<description>I/O configuration register for pin P3[16]</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[16]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_16</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_16</name>
|
|
<description>External memory data line 16.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_1</name>
|
|
<description>Pulse Width Modulator 0, output 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_TXD</name>
|
|
<description>Transmitter output for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_17</name>
|
|
<description>I/O configuration register for pin P3[17]</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[17]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_17</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_17</name>
|
|
<description>External memory data line 17.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_2</name>
|
|
<description>Pulse Width Modulator 0, output 2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RXD</name>
|
|
<description>Receiver input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_18</name>
|
|
<description>I/O configuration register for pin P3[18]</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[18]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_18</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_18</name>
|
|
<description>External memory data line 18.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_3</name>
|
|
<description>Pulse Width Modulator 0, output 3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_CTS</name>
|
|
<description>Clear to Send input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_19</name>
|
|
<description>I/O configuration register for pin P3[19]</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[19]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_19</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_19</name>
|
|
<description>External memory data line 19.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_4</name>
|
|
<description>Pulse Width Modulator 0, output 4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DCD</name>
|
|
<description>Data Carrier Detect input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_20</name>
|
|
<description>I/O configuration register for pin P3[20]</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[20]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_20</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_20</name>
|
|
<description>External memory data line 20.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_5</name>
|
|
<description>Pulse Width Modulator 0, output 5.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DSR</name>
|
|
<description>Data Set Ready input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_21</name>
|
|
<description>I/O configuration register for pin P3[21]</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[21]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_21</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_21</name>
|
|
<description>External memory data line 21.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_6</name>
|
|
<description>Pulse Width Modulator 0, output 6.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_DTR</name>
|
|
<description>Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_22</name>
|
|
<description>I/O configuration register for pin P3[22]</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[22]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_22</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_22</name>
|
|
<description>External memory data line 22.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM0_CAP0</name>
|
|
<description>Capture input for PWM0, channel 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RI</name>
|
|
<description>Ring Indicator input for UART1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_23</name>
|
|
<description>I/O configuration register for pin P3[23]</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[23]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_23</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_23</name>
|
|
<description>External memory data line 23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_CAP0</name>
|
|
<description>Capture input for PWM1, channel 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP0</name>
|
|
<description>Capture input for Timer 0, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_24</name>
|
|
<description>I/O configuration register for pin P3[24]</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[24]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_24</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_24</name>
|
|
<description>External memory data line 24.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_1</name>
|
|
<description>Pulse Width Modulator 1, output 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP1</name>
|
|
<description>Capture input for Timer 0, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_25</name>
|
|
<description>I/O configuration register for pin P3[25]</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[25]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_25</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_25</name>
|
|
<description>External memory data line 25.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_2</name>
|
|
<description>Pulse Width Modulator 1, output 2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT0</name>
|
|
<description>Match output for Timer 0, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_26</name>
|
|
<description>I/O configuration register for pin P3[26]</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[26]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_26</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_26</name>
|
|
<description>External memory data line 26.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_3</name>
|
|
<description>Pulse Width Modulator 1, output 3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT1</name>
|
|
<description>Match output for Timer 0, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STCLK</name>
|
|
<description>System tick timer clock input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_27</name>
|
|
<description>I/O configuration register for pin P3[27]</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[27]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_27</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_27</name>
|
|
<description>External memory data line 27.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_4</name>
|
|
<description>Pulse Width Modulator 1, output 4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP0</name>
|
|
<description>Capture input for Timer 1, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_28</name>
|
|
<description>I/O configuration register for pin P3[28]</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[28]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_28</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_28</name>
|
|
<description>External memory data line 28.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_5</name>
|
|
<description>Pulse Width Modulator 1, output 5.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP1</name>
|
|
<description>Capture input for Timer 1, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_29</name>
|
|
<description>I/O configuration register for pin P3[29]</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[29]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_29</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_29</name>
|
|
<description>External memory data line 29.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM1_6</name>
|
|
<description>Pulse Width Modulator 1, output 6.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT0</name>
|
|
<description>Match output for Timer 1, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_30</name>
|
|
<description>I/O configuration register for pin P3[30]</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[30]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_30</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_30</name>
|
|
<description>External memory data line 30.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U1_RTS</name>
|
|
<description>Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT1</name>
|
|
<description>Match output for Timer 1, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P3_31</name>
|
|
<description>I/O configuration register for pin P3[31]</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P3[31]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P3_31</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_D_31</name>
|
|
<description>External memory data line 31.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT2</name>
|
|
<description>Match output for Timer 1, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_0</name>
|
|
<description>I/O configuration register for pin P4[0]</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_0</name>
|
|
<description>External memory address line 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_1</name>
|
|
<description>I/O configuration register for pin P4[1]</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_1</name>
|
|
<description>External memory address line 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_2</name>
|
|
<description>I/O configuration register for pin P4[2]</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_2</name>
|
|
<description>External memory address line 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_3</name>
|
|
<description>I/O configuration register for pin P4[3]</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_3</name>
|
|
<description>External memory address line 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_4</name>
|
|
<description>I/O configuration register for pin P4[4]</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[4]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_4</name>
|
|
<description>External memory address line 4.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_5</name>
|
|
<description>I/O configuration register for pin P4[5]</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[5]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_5</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_5</name>
|
|
<description>External memory address line 5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_6</name>
|
|
<description>I/O configuration register for pin P4[6]</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[6]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_6</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_6</name>
|
|
<description>External memory address line 6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_7</name>
|
|
<description>I/O configuration register for pin P4[7]</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[7]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_7</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_7</name>
|
|
<description>External memory address line 7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_8</name>
|
|
<description>I/O configuration register for pin P4[8]</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[8]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_8</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_8</name>
|
|
<description>External memory address line 8.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_9</name>
|
|
<description>I/O configuration register for pin P4[9]</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[9]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_9</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_9</name>
|
|
<description>External memory address line 9.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_10</name>
|
|
<description>I/O configuration register for pin P4[10]</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[10]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_10</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_10</name>
|
|
<description>External memory address line 10.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_11</name>
|
|
<description>I/O configuration register for pin P4[11]</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[11]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_11</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_11</name>
|
|
<description>External memory address line 11.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_12</name>
|
|
<description>I/O configuration register for pin P4[12]</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[12]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_12</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_12</name>
|
|
<description>External memory address line 12.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_13</name>
|
|
<description>I/O configuration register for pin P4[13]</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[13]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_13</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_13</name>
|
|
<description>External memory address line 13.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_14</name>
|
|
<description>I/O configuration register for pin P4[14]</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[14]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_14</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_14</name>
|
|
<description>External memory address line 14.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_15</name>
|
|
<description>I/O configuration register for pin P4[15]</description>
|
|
<addressOffset>0x23C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[15]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_15</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_15</name>
|
|
<description>External memory address line 15.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_16</name>
|
|
<description>I/O configuration register for pin P4[16]</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[16]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_16</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_16</name>
|
|
<description>External memory address line 16.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_17</name>
|
|
<description>I/O configuration register for pin P4[17]</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[17]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_17</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_17</name>
|
|
<description>External memory address line 17.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_18</name>
|
|
<description>I/O configuration register for pin P4[18]</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[18]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_18</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_18</name>
|
|
<description>External memory address line 18.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_19</name>
|
|
<description>I/O configuration register for pin P4[19]</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[19]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_19</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_19</name>
|
|
<description>External memory address line 19.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_20</name>
|
|
<description>I/O configuration register for pin P4[20]</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[20]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_20</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_20</name>
|
|
<description>External memory address line 20.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SDA</name>
|
|
<description>I2C2 data input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SCK</name>
|
|
<description>Serial Clock for SSP1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_21</name>
|
|
<description>I/O configuration register for pin P4[21]</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[21]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_21</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_21</name>
|
|
<description>External memory address line 21.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SCL</name>
|
|
<description>I2C2 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_SSEL</name>
|
|
<description>Slave Select for SSP1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_22</name>
|
|
<description>I/O configuration register for pin P4[22]</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[22]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_22</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_22</name>
|
|
<description>External memory address line 22.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_TXD</name>
|
|
<description>Transmitter output for UART2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MISO</name>
|
|
<description>Master In Slave Out for SSP1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_23</name>
|
|
<description>I/O configuration register for pin P4[23]</description>
|
|
<addressOffset>0x25C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[23]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_23</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_23</name>
|
|
<description>External memory address line 23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U2_RXD</name>
|
|
<description>Receiver input for UART2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_MOSI</name>
|
|
<description>Master Out Slave In for SSP1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_24</name>
|
|
<description>I/O configuration register for pin P4[24]</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[24]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_24</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_OE</name>
|
|
<description>LOW active Output Enable signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_25</name>
|
|
<description>I/O configuration register for pin P4[25]</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[25]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_25</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_WE</name>
|
|
<description>LOW active Write Enable signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_26</name>
|
|
<description>I/O configuration register for pin P4[26]</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[26]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_26</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_BLS0</name>
|
|
<description>LOW active Byte Lane select signal 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_27</name>
|
|
<description>I/O configuration register for pin P4[27]</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[27]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_27</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_BLS1</name>
|
|
<description>LOW active Byte Lane select signal 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_28</name>
|
|
<description>I/O configuration register for pin P4[28]</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[28]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_28</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_BLS2</name>
|
|
<description>LOW active Byte Lane select signal 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_TXD</name>
|
|
<description>Transmitter output for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT0</name>
|
|
<description>Match output for Timer 2, channel 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_6</name>
|
|
<description>LCD data.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_10</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_2</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_29</name>
|
|
<description>I/O configuration register for pin P4[29]</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[29]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_29</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_BLS3</name>
|
|
<description>LOW active Byte Lane select signal 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U3_RXD</name>
|
|
<description>Receiver input for UART3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT1</name>
|
|
<description>Match output for Timer 2, channel 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C2_SCL</name>
|
|
<description>I2C2 clock input/output (this pin does not use a specialized I2C pad).</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_7</name>
|
|
<description>LCD data.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_11</name>
|
|
<description>LCD data.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LCD_VD_3</name>
|
|
<description>LCD data.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_30</name>
|
|
<description>I/O configuration register for pin P4[30]</description>
|
|
<addressOffset>0x278</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[30]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_30</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CS0</name>
|
|
<description>LOW active Chip Select 0 signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP0_OUT</name>
|
|
<description>Comparator 0, output.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P4_31</name>
|
|
<description>I/O configuration register for pin P4[31]</description>
|
|
<addressOffset>0x27C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P4[31]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P4_31</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_CS1</name>
|
|
<description>LOW active Chip Select 1 signal.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5_0</name>
|
|
<description>I/O configuration register for pin P5[0]</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P5[0]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P5_0</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_24</name>
|
|
<description>External memory address line 24.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_MOSI</name>
|
|
<description>Master Out Slave In for SSP2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT2</name>
|
|
<description>Match output for Timer 2, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5_1</name>
|
|
<description>I/O configuration register for pin P5[1]</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P5[1]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P5_1</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMC_A_25</name>
|
|
<description>External memory address line 25.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP2_MISO</name>
|
|
<description>Master In Slave Out for SSP2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT3</name>
|
|
<description>Match output for Timer 2, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5_2</name>
|
|
<description>I/O configuration register for pin P5[2]</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P5[2]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P5_2</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT2</name>
|
|
<description>Match output for Timer 3, channel 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SDA</name>
|
|
<description>I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>Configures I2C features for standard mode, fast mode, and Fast Mode
|
|
Plus operation.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIDRIVE</name>
|
|
<description>Controls sink current capability of the pin, only for P5[2] and
|
|
P5[3].</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOWDRIVE</name>
|
|
<description>Output drive sink is 4 mA. This is sufficient for standard
|
|
and fast mode I2C.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHDRIVE</name>
|
|
<description>Output drive sink is 20 mA. This is needed for Fast Mode
|
|
Plus I2C. Refer to the appropriate specific device data sheet for
|
|
details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5_3</name>
|
|
<description>I/O configuration register for pin P5[3]</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P5[3]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P5_3</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_RXD</name>
|
|
<description>Receiver input for USART4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_SCL</name>
|
|
<description>I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>Configures I2C features for standard mode, fast mode, and Fast Mode
|
|
Plus operation.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>I2C 50ns glitch filter and slew rate control
|
|
disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIDRIVE</name>
|
|
<description>Controls sink current capability of the pin, only for P5[2] and
|
|
P5[3].</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOWDRIVE</name>
|
|
<description>Output drive sink is 4 mA. This is sufficient for standard
|
|
and fast mode I2C.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHDRIVE</name>
|
|
<description>Output drive sink is 20 mA. This is needed for Fast Mode
|
|
Plus I2C. Refer to the appropriate specific device data sheet for
|
|
details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P5_4</name>
|
|
<description>I/O configuration register for pin P5[4]</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000030</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function for pin P5[4]</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P5_4</name>
|
|
<description>General purpose digital input/output pin.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U0_OE</name>
|
|
<description>RS-485/EIA-485 output enable signal for UART0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT3</name>
|
|
<description>Match output for Timer 3, channel 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>U4_TXD</name>
|
|
<description>Transmitter output for USART4 (input/output in smart card mode).</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor
|
|
control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor
|
|
enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin
|
|
reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as
|
|
1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLEW</name>
|
|
<description>Driver slew rate</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard mode, output slew rate control is enabled. More
|
|
outputs can be switched simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast mode, slew rate control is disabled. Refer to the
|
|
appropriate specific device data sheet for details.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain
|
|
mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSP1</name>
|
|
<description>SSP1 controller</description>
|
|
<baseAddress>0x40030000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSP1</name>
|
|
<value>15</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSS</name>
|
|
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>4_BIT_TRANSFER</name>
|
|
<description>4-bit transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT_TRANSFER</name>
|
|
<description>5-bit transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_TRANSFER</name>
|
|
<description>6-bit transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_TRANSFER</name>
|
|
<description>7-bit transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_TRANSFER</name>
|
|
<description>8-bit transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT_TRANSFER</name>
|
|
<description>9-bit transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BIT_TRANSFER</name>
|
|
<description>10-bit transfer</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BIT_TRANSFER</name>
|
|
<description>11-bit transfer</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BIT_TRANSFER</name>
|
|
<description>12-bit transfer</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BIT_TRANSFER</name>
|
|
<description>13-bit transfer</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BIT_TRANSFER</name>
|
|
<description>14-bit transfer</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BIT_TRANSFER</name>
|
|
<description>15-bit transfer</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_TRANSFER</name>
|
|
<description>16-bit transfer</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame Format.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>SPI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TI</name>
|
|
<description>TI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MICROWIRE</name>
|
|
<description>Microwire</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIS_COMBINATION_IS_</name>
|
|
<description>This combination is not supported and should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUS_LOW</name>
|
|
<description>SSP controller maintains the bus clock low between frames.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUS_HIGH</name>
|
|
<description>SSP controller maintains the bus clock high between frames.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FIRST_CLOCK</name>
|
|
<description>SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECOND_CLOCK</name>
|
|
<description>SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCR</name>
|
|
<description>Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Control Register 1. Selects master/slave and other modes.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loop Back Mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>During normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUPTU</name>
|
|
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SSP Enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The SSP controller is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>Clock Prescale Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPSDVSR</name>
|
|
<description>This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>Interrupt Mask Set and Clear Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORRIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORMIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSPICR Interrupt Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIC</name>
|
|
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACR</name>
|
|
<description>SSP0 DMA control register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAE</name>
|
|
<description>Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAE</name>
|
|
<description>Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<description>Analog-to-Digital Converter (ADC)</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x40034000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BURST</name>
|
|
<description>The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SW</name>
|
|
<description>Conversions are software controlled and require 31 clocks.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[20:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDN</name>
|
|
<description>Power down mode</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>The A/D converter is operational.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERDOWN</name>
|
|
<description>The A/D converter is in power-down mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>When the BURST bit is 0, these bits control whether and when an A/D conversion is started:</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_START_THIS_VALUE</name>
|
|
<description>No start (this value should be used when clearing PDN to 0).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_CONVERSION_NOW</name>
|
|
<description>Start conversion now.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P2_10</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on the P2[10] pin.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P1_27</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on the P1[27] pin.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAT0_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAT0_3</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAT1_0</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAT1_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>This bit is significant only when the START field contains 010-111. In these cases:</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLLING</name>
|
|
<description>Start conversion on a falling edge on the selected CAP/MAT signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Start conversion on a rising edge on the selected CAP/MAT signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDR</name>
|
|
<description>A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADINTEN0</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 0 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 0 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN1</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 1 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 1 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN2</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 2 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 2 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN3</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 3 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 3 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN4</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 4 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 4 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN5</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 5 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 5 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN6</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 6 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 6 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADINTEN7</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Completion of a conversion on ADC channel 7 will not generate an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Completion of a conversion on ADC channel 7 will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADGINTEN</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNELS</name>
|
|
<description>Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GLOBAL</name>
|
|
<description>The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DR[%s]</name>
|
|
<displayName>DR[%s]</displayName>
|
|
<description>A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE0</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE1</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE2</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE3</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE4</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 4.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE5</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 5.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE6</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 6.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE7</name>
|
|
<description>This bit mirrors the DONE status flag from the result register for A/D channel 7.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN0</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN1</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN2</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN3</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN4</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN5</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN6</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN7</name>
|
|
<description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADINT</name>
|
|
<description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRM</name>
|
|
<description>ADC trim register.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADCOFFS</name>
|
|
<description>Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>CANAFRAM</name>
|
|
<description>CAN acceptance filter RAM</description>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>512</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-511</dimIndex>
|
|
<name>MASK[%s]</name>
|
|
|
|
<displayName>MASK[%s]</displayName>
|
|
<description>CAN AF ram access register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>CAN AF RAM mask</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>CANAF</name>
|
|
<description>CAN controller</description>
|
|
<groupName>CANAF</groupName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>AFMR</name>
|
|
<description>Acceptance Filter Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACCOFF</name>
|
|
<description>if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACCBP</name>
|
|
<description>All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EFCAN</name>
|
|
<description>FullCAN mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOFTWARE_MUST_READ_A</name>
|
|
<description>Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_ACCEPTANCE_FILTE</name>
|
|
<description>The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFF_SA</name>
|
|
<description>Standard Frame Individual Start Address Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SFF_SA</name>
|
|
<description>The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM.</description>
|
|
<bitRange>[10:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFF_GRP_SA</name>
|
|
<description>Standard Frame Group Start Address Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SFF_GRP_SA</name>
|
|
<description>The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.</description>
|
|
<bitRange>[11:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EFF_SA</name>
|
|
<description>Extended Frame Start Address Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EFF_SA</name>
|
|
<description>The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register.</description>
|
|
<bitRange>[10:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EFF_GRP_SA</name>
|
|
<description>Extended Frame Group Start Address Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EFF_GRP_SA</name>
|
|
<description>The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.</description>
|
|
<bitRange>[11:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDOFTABLE</name>
|
|
<description>End of AF Tables register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDOFTABLE</name>
|
|
<description>The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table.</description>
|
|
<bitRange>[11:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LUTERRAD</name>
|
|
<description>LUT Error Address register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LUTERRAD</name>
|
|
<description>It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables.</description>
|
|
<bitRange>[10:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LUTERR</name>
|
|
<description>LUT Error Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LUTERR</name>
|
|
<description>This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCANIE</name>
|
|
<description>FullCAN interrupt enable register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCANIE</name>
|
|
<description>Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCANIC0</name>
|
|
<description>FullCAN interrupt and capture register0</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPND</name>
|
|
<description>FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCANIC1</name>
|
|
<description>FullCAN interrupt and capture register1</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IntPnd32</name>
|
|
<description>FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCAN</name>
|
|
<description> CAN controller</description>
|
|
<groupName>CCAN</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TXSR</name>
|
|
<description>CAN Central Transmit Status Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00030300</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS1</name>
|
|
<description>When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TS2</name>
|
|
<description>When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TBS1</name>
|
|
<description>When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TBS2</name>
|
|
<description>When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TCS1</name>
|
|
<description>When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TCS2</name>
|
|
<description>When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXSR</name>
|
|
<description>CAN Central Receive Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS1</name>
|
|
<description>When 1, CAN1 is receiving a message (same as RS in CAN1GSR).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RS2</name>
|
|
<description>When 1, CAN2 is receiving a message (same as RS in CAN2GSR).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RB1</name>
|
|
<description>When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RB2</name>
|
|
<description>When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOS1</name>
|
|
<description>When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR).</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOS2</name>
|
|
<description>When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR).</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>CAN Central Miscellaneous Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E1</name>
|
|
<description>When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>E2</name>
|
|
<description>When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN1</name>
|
|
<description>CAN controller </description>
|
|
<groupName>CAN</groupName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CAN</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Controls the operating mode of the CAN Controller.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RM</name>
|
|
<description>Reset Mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_THE_CAN_CONTR</name>
|
|
<description>Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_CAN_OPERATION</name>
|
|
<description>Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOM</name>
|
|
<description>Listen Only Mode.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_THE_CAN_CONT</name>
|
|
<description>Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LISTEN_ONLY_THE_CON</name>
|
|
<description>Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STM</name>
|
|
<description>Self Test Mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_A_TRANSMITTE</name>
|
|
<description>Normal. A transmitted message must be acknowledged to be considered successful.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELF_TEST_THE_CONTR</name>
|
|
<description>Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM</name>
|
|
<description>Transmit Priority Mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CAN_ID_THE_TRANSMIT</name>
|
|
<description>CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCAL_PRIORITY_THE_</name>
|
|
<description>Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM</name>
|
|
<description>Sleep Mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_NORMAL_OPER</name>
|
|
<description>Wake-up. Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEP_THE_CAN_CONTR</name>
|
|
<description>Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPM</name>
|
|
<description>Receive Polarity Mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_ACTIVE_RD_INPUT</name>
|
|
<description>Low active. RD input is active Low (dominant bit = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_ACTIVE_RD_INPU</name>
|
|
<description>High active. RD input is active High (dominant bit = 1) -- reverse polarity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Test Mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_NORMAL_OPE</name>
|
|
<description>Disabled. Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_THE_TD_PIN_</name>
|
|
<description>Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR</name>
|
|
<description>Command bits that affect the state of the CAN Controller</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Transmission Request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ABSENT_NO_TRANSMISSI</name>
|
|
<description>Absent.No transmission request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT_THE_MESSAGE</name>
|
|
<description>Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AT</name>
|
|
<description>Abort Transmission.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ACTION_DO_NOT_AB</name>
|
|
<description>No action. Do not abort the transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT_IF_NOT_ALRE</name>
|
|
<description>Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRB</name>
|
|
<description>Release Receive Buffer.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ACTION_DO_NOT_RE</name>
|
|
<description>No action. Do not release the receive buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELEASED_THE_INFORM</name>
|
|
<description>Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDO</name>
|
|
<description>Clear Data Overrun.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ACTION_DO_NOT_CL</name>
|
|
<description>No action. Do not clear the data overrun bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_DATA_OVER</name>
|
|
<description>Clear. The Data Overrun bit in Status Register(s) is cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRR</name>
|
|
<description>Self Reception Request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ABSENT_NO_SELF_RECE</name>
|
|
<description>Absent. No self reception request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESENT_THE_MESSAGE</name>
|
|
<description>Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STB1</name>
|
|
<description>Select Tx Buffer 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_SELECTED_TX_BUF</name>
|
|
<description>Not selected. Tx Buffer 1 is not selected for transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTED_TX_BUFFER_</name>
|
|
<description>Selected. Tx Buffer 1 is selected for transmission.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STB2</name>
|
|
<description>Select Tx Buffer 2.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_SELECTED_TX_BUF</name>
|
|
<description>Not selected. Tx Buffer 2 is not selected for transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTED_TX_BUFFER_</name>
|
|
<description>Selected. Tx Buffer 2 is selected for transmission.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STB3</name>
|
|
<description>Select Tx Buffer 3.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_SELECTED_TX_BUF</name>
|
|
<description>Not selected. Tx Buffer 3 is not selected for transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTED_TX_BUFFER_</name>
|
|
<description>Selected. Tx Buffer 3 is selected for transmission.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GSR</name>
|
|
<description>Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x3C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBS</name>
|
|
<description>Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY_NO_MESSAGE_IS</name>
|
|
<description>Empty. No message is available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_AT_LEAST_ONE_C</name>
|
|
<description>Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOS</name>
|
|
<description>Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ABSENT_NO_DATA_OVER</name>
|
|
<description>Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRUN_A_MESSAGE_W</name>
|
|
<description>Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBS</name>
|
|
<description>Transmit Buffer Status.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOCKED_AT_LEAST_ONE</name>
|
|
<description>Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELEASED_ALL_THREE_</name>
|
|
<description>Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCS</name>
|
|
<description>Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INCOMPLETE_AT_LEAST</name>
|
|
<description>Incomplete. At least one requested transmission has not been successfully completed yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPLETE_ALL_REQUES</name>
|
|
<description>Complete. All requested transmission(s) has (have) been successfully completed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_THE_CAN_CONTRO</name>
|
|
<description>Idle. The CAN controller is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RECEIVE_THE_CAN_CON</name>
|
|
<description>Receive. The CAN controller is receiving a message.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_THE_CAN_CONTRO</name>
|
|
<description>Idle. The CAN controller is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT_THE_CAN_CO</name>
|
|
<description>Transmit. The CAN controller is sending a message.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OK_BOTH_ERROR_COUNT</name>
|
|
<description>OK. Both error counters are below the Error Warning Limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR_ONE_OR_BOTH_O</name>
|
|
<description>Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BS</name>
|
|
<description>Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUS_ON_THE_CAN_CONT</name>
|
|
<description>Bus-on. The CAN Controller is involved in bus activities</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUS_OFF_THE_CAN_CON</name>
|
|
<description>Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXERR</name>
|
|
<description>The current value of the Rx Error Counter (an 8-bit value).</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXERR</name>
|
|
<description>The current value of the Tx Error Counter (an 8-bit value).</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>Interrupt status, Arbitration Lost Capture, Error Code Capture</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TI1</name>
|
|
<description>Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EI</name>
|
|
<description>Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOI</name>
|
|
<description>Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUI</name>
|
|
<description>Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI</name>
|
|
<description>Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALI</name>
|
|
<description>Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEI</name>
|
|
<description>Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDI</name>
|
|
<description>ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TI2</name>
|
|
<description>Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TI3</name>
|
|
<description>Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERRBIT4_0</name>
|
|
<description>Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERRDIR</name>
|
|
<description>When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ERROR_OCCURRED_DURIN</name>
|
|
<description>Error occurred during transmitting.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR_OCCURRED_DURIN</name>
|
|
<description>Error occurred during receiving.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRC1_0</name>
|
|
<description>When the CAN controller detects a bus error, the type of error is captured in this field:</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BIT_ERROR</name>
|
|
<description>Bit error</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORM_ERROR</name>
|
|
<description>Form error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STUFF_ERROR</name>
|
|
<description>Stuff error</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTHER_ERROR</name>
|
|
<description>Other error</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALCBIT</name>
|
|
<description>Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIE1</name>
|
|
<description>Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOIE</name>
|
|
<description>Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WUIE</name>
|
|
<description>Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDIE</name>
|
|
<description>ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIE2</name>
|
|
<description>Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIE3</name>
|
|
<description>Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR</name>
|
|
<description>Bus Timing. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1C0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRP</name>
|
|
<description>Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>The Synchronization Jump Width is (this value plus one) CAN clocks.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TESG1</name>
|
|
<description>The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TESG2</name>
|
|
<description>The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks.</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SAM</name>
|
|
<description>Sampling</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_BUS_IS_SAMPLED_O</name>
|
|
<description>The bus is sampled once (recommended for high speed buses)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_BUS_IS_SAMPLED_3</name>
|
|
<description>The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EWL</name>
|
|
<description>Error Warning Limit. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWL</name>
|
|
<description>During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x3C3C3C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBS_1</name>
|
|
<description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOS_1</name>
|
|
<description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TBS1_1</name>
|
|
<description>Transmit Buffer Status 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOCKED_SOFTWARE_CAN</name>
|
|
<description>Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELEASED_SOFTWARE_M</name>
|
|
<description>Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCS1_1</name>
|
|
<description>Transmission Complete Status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INCOMPLETE_THE_PREV</name>
|
|
<description>Incomplete. The previously requested transmission for Tx Buffer 1 is not complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPLETE_THE_PREVIO</name>
|
|
<description>Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS_1</name>
|
|
<description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TS1_1</name>
|
|
<description>Transmit Status 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_THERE_IS_NO_TR</name>
|
|
<description>Idle. There is no transmission from Tx Buffer 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT_THE_CAN_CO</name>
|
|
<description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES_1</name>
|
|
<description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BS_1</name>
|
|
<description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RBS_2</name>
|
|
<description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOS_2</name>
|
|
<description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TBS2_2</name>
|
|
<description>Transmit Buffer Status 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOCKED_SOFTWARE_CAN</name>
|
|
<description>Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELEASED_SOFTWARE_M</name>
|
|
<description>Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCS2_2</name>
|
|
<description>Transmission Complete Status.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INCOMPLETE_THE_PREV</name>
|
|
<description>Incomplete. The previously requested transmission for Tx Buffer 2 is not complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPLETE_THE_PREVIO</name>
|
|
<description>Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS_2</name>
|
|
<description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TS2_2</name>
|
|
<description>Transmit Status 2.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_THERE_IS_NO_TR</name>
|
|
<description>Idle. There is no transmission from Tx Buffer 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT_THE_CAN_CO</name>
|
|
<description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES_2</name>
|
|
<description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BS_2</name>
|
|
<description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RBS_3</name>
|
|
<description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOS_3</name>
|
|
<description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TBS3_3</name>
|
|
<description>Transmit Buffer Status 3.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOCKED_SOFTWARE_CAN</name>
|
|
<description>Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELEASED_SOFTWARE_M</name>
|
|
<description>Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCS3_3</name>
|
|
<description>Transmission Complete Status.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INCOMPLETE_THE_PREV</name>
|
|
<description>Incomplete. The previously requested transmission for Tx Buffer 3 is not complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPLETE_THE_PREVIO</name>
|
|
<description>Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS_3</name>
|
|
<description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TS3_3</name>
|
|
<description>Transmit Status 3.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_THERE_IS_NO_TR</name>
|
|
<description>Idle. There is no transmission from Tx Buffer 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT_THE_CAN_CO</name>
|
|
<description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES_3</name>
|
|
<description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BS_3</name>
|
|
<description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFS</name>
|
|
<description>Receive frame status. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDINDEX</name>
|
|
<description>ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BP</name>
|
|
<description>If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RID</name>
|
|
<description>Received Identifier. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18.</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDA</name>
|
|
<description>Received data bytes 1-4. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDB</name>
|
|
<description>Received data bytes 5-8. Can only be written when RM in CANMOD is 1.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA8</name>
|
|
<description>Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>TFI%s</name>
|
|
<description>Transmit frame info (Tx Buffer )</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>TID%s</name>
|
|
<description>Transmit
|
|
Identifier (Tx Buffer)</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>The 11-bit Identifier to be sent in the next transmit message.</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>TDA%s</name>
|
|
<description>Transmit
|
|
data bytes 1-4 (Tx Buffer)</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>TDB%s</name>
|
|
<description>Transmit
|
|
data bytes 5-8 (Tx Buffer )</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA8</name>
|
|
<description>Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CAN1">
|
|
<name>CAN2</name>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C1</name>
|
|
<baseAddress>0x4005C000</baseAddress>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>11</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="SSP1">
|
|
<name>SSP0</name>
|
|
<description>SSP controller</description>
|
|
<groupName>SSP</groupName>
|
|
<baseAddress>0x40088000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSP0</name>
|
|
<value>14</value>
|
|
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>Digital-to-Analog Converter (DAC) Modification</description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x4008C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIAS</name>
|
|
<description>Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLOW</name>
|
|
<description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DAC Control register. This register controls DMA and timer operation.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_DMA_REQ</name>
|
|
<description>DMA interrupt request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_ON_ANY_WRITE_T</name>
|
|
<description>Clear on any write to the DACR register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_BY_HARDWARE_WHEN</name>
|
|
<description>Set by hardware when the timer times out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLBUF_ENA</name>
|
|
<description>Double buffering</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_WHEN_THIS_BI</name>
|
|
<description>Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNT_ENA</name>
|
|
<description>Time-out counter operation</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA_ENA</name>
|
|
<description>DMA access</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_DMA_BURST_RE</name>
|
|
<description>Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTVAL</name>
|
|
<description>DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>16-bit reload value for the DAC interrupt/DMA timer.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER2</name>
|
|
<baseAddress>0x40090000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER2</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER3</name>
|
|
<baseAddress>0x40094000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER3</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART2</name>
|
|
<baseAddress>0x40098000</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART2</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART3</name>
|
|
<baseAddress>0x4009C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART3</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C2</name>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<interrupt>
|
|
<name>I2C2</name>
|
|
<value>12</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART4</name>
|
|
<description>UART4 </description>
|
|
<groupName>UART4</groupName>
|
|
<baseAddress>0x400A4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART4</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read (DLAB =0).</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. The next character to be transmitted is written here (DLAB =0).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RDA_INTE</name>
|
|
<description>Disable the RDA interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RDA_INTER</name>
|
|
<description>Enable the RDA interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_THRE_INT</name>
|
|
<description>Disable the THRE interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_THRE_INTE</name>
|
|
<description>Enable the THRE interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RX_LINE_</name>
|
|
<description>Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RX_LINE_S</name>
|
|
<description>Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTEN</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_END_OF_AUTO_</name>
|
|
<description>Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_END_OF_AUTO_B</name>
|
|
<description>Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTEN</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_BAUD_TI</name>
|
|
<description>Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_BAUD_TIM</name>
|
|
<description>Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_INTERRU</name>
|
|
<description>At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_IS_PEND</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_RECEIVE_LINE_S</name>
|
|
<description>1 - Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2A__RECEIVE_DATA_AV</name>
|
|
<description>2a - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2B__CHARACTER_TIME_</name>
|
|
<description>2b - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_THRE_INTERRUPT</name>
|
|
<description>3 - THRE Interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>Copies of U4FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls UART FIFO usage and modes.</description>
|
|
<alternateRegister>IIR</alternateRegister>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UARTN_FIFOS_ARE_DISA</name>
|
|
<description>UARTn FIFOs are disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH_ENABLE_F</name>
|
|
<description>Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UARTn FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UARTn FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_LOGIC_1_TO</name>
|
|
<description>Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMODE</name>
|
|
<description>DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGLVL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_0_1_C</name>
|
|
<description>Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_1_4_C</name>
|
|
<description>Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_2_8_C</name>
|
|
<description>Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_3_14_</name>
|
|
<description>Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT_</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS_1_5_IF_</name>
|
|
<description>2 stop bits (1.5 if UnLCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY_NUMBER_O</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY_NUMBER_</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_1_STICK_PARIT</name>
|
|
<description>Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_0_STICK_PARIT</name>
|
|
<description>Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BREAK_TRANSM</name>
|
|
<description>Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BREAK_TRANSMI</name>
|
|
<description>Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ACCESS_TO_DI</name>
|
|
<description>Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ACCESS_TO_DIV</name>
|
|
<description>Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_UARTN_RECEIVER_F</name>
|
|
<description>The UARTn receiver FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_UARTN_RECEIVER_F</name>
|
|
<description>The UARTn receiver FIFO is not empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OVERRUN_ERROR_STATUS</name>
|
|
<description>Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRUN_ERROR_STATUS</name>
|
|
<description>Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PARITY_ERROR_STATUS_</name>
|
|
<description>Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARITY_ERROR_STATUS_</name>
|
|
<description>Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FRAMING_ERROR_STATUS</name>
|
|
<description>Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAMING_ERROR_STATUS</name>
|
|
<description>Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BREAK_INTERRUPT_STAT</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BREAK_INTERRUPT_STAT</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNTHR_CONTAINS_VALID</name>
|
|
<description>UnTHR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNTHR_IS_EMPTY_</name>
|
|
<description>UnTHR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID_DATA</name>
|
|
<description>UnTHR and/or the UnTSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>UnTHR and the UnTSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNRBR_CONTAINS_NO_UA</name>
|
|
<description>UnRBR contains no UARTn RX errors or UnFCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UARTN_RBR_CONTAINS_A</name>
|
|
<description>UARTn RBR contains at least one UARTn RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. 8-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Pad</name>
|
|
<description>A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_STOP_AUTO</name>
|
|
<description>Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_START_AUT</name>
|
|
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0_</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1_</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Restart bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART_</name>
|
|
<description>No restart.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART_IN_CASE_OF_T</name>
|
|
<description>Restart in case of time-out (counter restarts at next UARTn Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_</name>
|
|
<description>No impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_</name>
|
|
<description>No impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>IrDA Control Register. Enables and configures the IrDA mode.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRDAEN</name>
|
|
<description>IrDA mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_IRDA_MODE_</name>
|
|
<description>Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_IRDA_MODE_O</name>
|
|
<description>Enabled. IrDA mode on UART4 is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRDAINV</name>
|
|
<description>Serial input direction.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED_</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED_THIS_HAS_N</name>
|
|
<description>Inverted. This has no effect on the serial output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIXPULSEEN</name>
|
|
<description>IrDA fixed pulse width mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSEDIV</name>
|
|
<description>Configures the pulse when FixPulseEn = 1.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>2XTPCLK</name>
|
|
<description>2xTPCLK</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4XTPCLK</name>
|
|
<description>4xTPCLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8XTPCLK</name>
|
|
<description>8xTPCLK</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16XTPCLK</name>
|
|
<description>16xTPCLK</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32XTPCLK</name>
|
|
<description>32xTPCLK</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64XTPCLK</name>
|
|
<description>64xTPCLK</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128XTPCLK</name>
|
|
<description>128xTPCLK</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256XTPCLK</name>
|
|
<description>256xTPCLK</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Oversampling register. Controls the degree of oversampling during each bit time.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSFRAC</name>
|
|
<description>Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSINT</name>
|
|
<description>Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDINT</name>
|
|
<description>In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCICTRL</name>
|
|
<description>Smart Card Interface control register. Enables and configures the smartcard Interface feature.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCIEN</name>
|
|
<description>Smart Card Interface Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SMART_CARD_INTERFACE</name>
|
|
<description>Smart card interface disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS_HALF_DU</name>
|
|
<description>Asynchronous half duplex smart card interface is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKDIS</name>
|
|
<description>NACK response disable. Only applicable in T=0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_NACK_RESPONSE_IS_E</name>
|
|
<description>A NACK response is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A_NACK_RESPONSE_IS_I</name>
|
|
<description>A NACK response is inhibited.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTSEL</name>
|
|
<description>Protocol selection as defined in the ISO7816-3 standard.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>T_EQ_0</name>
|
|
<description>T = 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T_EQ_1</name>
|
|
<description>T = 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRETRY</name>
|
|
<description>Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GUARDTIME</name>
|
|
<description>Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>NMM enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>AAD enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Direction control for DIR pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_DIRECTI</name>
|
|
<description>Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_DIRECTIO</name>
|
|
<description>Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_THE_DIRECTION_C</name>
|
|
<description>Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_THE_DIRECTION_</name>
|
|
<description>High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCCTRL</name>
|
|
<description>Synchronous mode control register.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Enables synchronous mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRC</name>
|
|
<description>Clock source select.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_SLAVE_MO</name>
|
|
<description>Synchronous slave mode (SCLK in)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_MASTER_M</name>
|
|
<description>Synchronous master mode (SCLK out)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FES</name>
|
|
<description>Falling edge sampling.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RXD_IS_SAMPLED_ON_TH</name>
|
|
<description>RxD is sampled on the rising edge of SCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXD_IS_SAMPLED_ON_TH</name>
|
|
<description>RxD is sampled on the falling edge of SCLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSBYPASS</name>
|
|
<description>Transmit synchronization bypass in synchronous slave mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_INPUT_CLOCK_IS_S</name>
|
|
<description>The input clock is synchronized prior to being used in clock edge detection logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_INPUT_CLOCK_IS_N</name>
|
|
<description>The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCEN</name>
|
|
<description>Continuous master clock enable (used only when CSRC is 1)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SCLK_CYCLES_ONLY_WHE</name>
|
|
<description>SCLK cycles only when characters are being sent on TxD</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCLK_RUNS_CONTINUOUS</name>
|
|
<description>SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSSDIS</name>
|
|
<description>Start/stop bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SEND_START_AND_STOP_</name>
|
|
<description>Send start and stop bits as in other modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOSTARTSTOPBIT</name>
|
|
<description>Do not send start/stop bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCCLR</name>
|
|
<description>Continuous clock clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CSCEN_IS_UNDER_SOFTW</name>
|
|
<description>CSCEN is under software control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HARDWARE_CLEARS_CSCE</name>
|
|
<description>Hardware clears CSCEN after each character is received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>I2S</name>
|
|
<description>I2S interface</description>
|
|
<groupName>I2S</groupName>
|
|
<baseAddress>0x400A8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2S</name>
|
|
<value>27</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DAO</name>
|
|
<description>I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x87E1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WORDWIDTH</name>
|
|
<description>Selects the number of bytes in data as follows:</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_DATA</name>
|
|
<description>8-bit data</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_DATA</name>
|
|
<description>16-bit data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
|
|
<enumeratedValue>
|
|
<name>32_BIT_DATA</name>
|
|
<description>32-bit data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>When 1, asynchronously resets the transmit channel and FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_SEL</name>
|
|
<description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_HALFPERIOD</name>
|
|
<description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MUTE</name>
|
|
<description>When 1, the transmit channel sends only zeroes.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAI</name>
|
|
<description>I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x07E1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WORDWIDTH</name>
|
|
<description>Selects the number of bytes in data as follows:</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_DATA</name>
|
|
<description>8-bit data</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_DATA</name>
|
|
<description>16-bit data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
|
|
<enumeratedValue>
|
|
<name>32_BIT_DATA</name>
|
|
<description>32-bit data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>When 1, asynchronously reset the transmit channel and FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_SEL</name>
|
|
<description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_HALFPERIOD</name>
|
|
<description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFO</name>
|
|
<description>I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2STXFIFO</name>
|
|
<description>8 x 32-bit transmit FIFO.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFO</name>
|
|
<description>I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>I2SRXFIFO</name>
|
|
<description>8 x 32-bit transmit FIFO.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>I2S Status Feedback Register. Contains status information about the I2S interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMAREQ1</name>
|
|
<description>This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMAREQ2</name>
|
|
<description>This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_LEVEL</name>
|
|
<description>Reflects the current level of the Receive FIFO.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_LEVEL</name>
|
|
<description>Reflects the current level of the Transmit FIFO.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA1</name>
|
|
<description>I2S DMA Configuration Register 1. Contains control information for DMA request 1.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DMA1_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S receive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DMA1_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S transmit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_DMA1</name>
|
|
<description>Set the FIFO level that triggers a receive DMA request on DMA1.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_DMA1</name>
|
|
<description>Set the FIFO level that triggers a transmit DMA request on DMA1.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA2</name>
|
|
<description>I2S DMA Configuration Register 2. Contains control information for DMA request 2.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DMA2_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S receive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DMA2_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S transmit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_DMA2</name>
|
|
<description>Set the FIFO level that triggers a receive DMA request on DMA2.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_DMA2</name>
|
|
<description>Set the FIFO level that triggers a transmit DMA request on DMA2.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ</name>
|
|
<description>I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_IRQ_ENABLE</name>
|
|
<description>When 1, enables I2S receive interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_IRQ_ENABLE</name>
|
|
<description>When 1, enables I2S transmit interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_IRQ</name>
|
|
<description>Set the FIFO level on which to create an irq request.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_IRQ</name>
|
|
<description>Set the FIFO level on which to create an irq request.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXRATE</name>
|
|
<description>I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Y_DIVIDER</name>
|
|
<description>I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>X_DIVIDER</name>
|
|
<description>I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXRATE</name>
|
|
<description>I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>Y_DIVIDER</name>
|
|
<description>I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>X_DIVIDER</name>
|
|
<description>I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBITRATE</name>
|
|
<description>I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_BITRATE</name>
|
|
<description>I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXBITRATE</name>
|
|
<description>I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_BITRATE</name>
|
|
<description>I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMODE</name>
|
|
<description>I2S Transmit mode control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCLKSEL</name>
|
|
<description>Clock source selection for the transmit bit clock divider.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_TX_FRACTI</name>
|
|
<description>Select the TX fractional rate divider clock output as the source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_RX_MCLK_S</name>
|
|
<description>Select the RX_MCLK signal as the TX_MCLK clock source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX4PIN</name>
|
|
<description>Transmit 4-pin mode selection. When 1, enables 4-pin mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXMCENA</name>
|
|
<description>Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMODE</name>
|
|
<description>I2S Receive mode control.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCLKSEL</name>
|
|
<description>Clock source selection for the receive bit clock divider.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_RX_FRACTI</name>
|
|
<description>Select the RX fractional rate divider clock output as the source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_TX_MCLK_S</name>
|
|
<description>Select the TX_MCLK signal as the RX_MCLK clock source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX4PIN</name>
|
|
<description>Receive 4-pin mode selection. When 1, enables 4-pin mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXMCENA</name>
|
|
<description>Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSP0">
|
|
<name>SSP2</name>
|
|
<baseAddress>0x400AC000</baseAddress>
|
|
<interrupt>
|
|
<name>SSP2</name>
|
|
<value>36</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCPWM</name>
|
|
<description>Motor Control PWM</description>
|
|
<groupName>MCPWM</groupName>
|
|
<baseAddress>0x400B8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MCPWM</name>
|
|
<value>30</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CON</name>
|
|
<description>PWM Control read address</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0</name>
|
|
<description>Stops/starts timer channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0</name>
|
|
<description>Edge/center aligned operation for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA0</name>
|
|
<description>Selects polarity of the MCOA0 and MCOB0 pins.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE0</name>
|
|
<description>Controls the dead-time feature for channel 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0</name>
|
|
<description>Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RUN1</name>
|
|
<description>Stops/starts timer channel 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1</name>
|
|
<description>Edge/center aligned operation for channel 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA1</name>
|
|
<description>Selects polarity of the MCOA1 and MCOB1 pins.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE1</name>
|
|
<description>Controls the dead-time feature for channel 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1</name>
|
|
<description>Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RUN2</name>
|
|
<description>Stops/starts timer channel 2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2</name>
|
|
<description>Edge/center aligned operation for channel 2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA2</name>
|
|
<description>Selects polarity of the MCOA2 and MCOB2 pins.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE2</name>
|
|
<description>Controls the dead-time feature for channel 1.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2</name>
|
|
<description>Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INVBDC</name>
|
|
<description>Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OPPOSITE</name>
|
|
<description>The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAME</name>
|
|
<description>The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMODE</name>
|
|
<description>3-phase AC mode select (see Section 24.8.7).</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_AC_MODE_OFF</name>
|
|
<description>3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_AC_MODE_ON_</name>
|
|
<description>3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE</name>
|
|
<description>3-phase DC mode select (see Section 24.8.6).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_DC_MODE_OFF</name>
|
|
<description>3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_DC_MODE_ON_</name>
|
|
<description>3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CON_SET</name>
|
|
<description>PWM Control set address</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVBDC_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMODE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CON_CLR</name>
|
|
<description>PWM Control clear address</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVBDC_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMOD_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON</name>
|
|
<description>Capture Control read address</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0</name>
|
|
<description>If this bit is 1, TC0 is reset by a channel 0 capture event.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1</name>
|
|
<description>If this bit is 1, TC1 is reset by a channel 1 capture event.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2</name>
|
|
<description>If this bit is 1, TC2 is reset by a channel 2 capture event.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON_SET</name>
|
|
<description>Capture Control set address</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON_CLR</name>
|
|
<description>Event Control clear address</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>TC[%s]</name>
|
|
<displayName>TC[%s]</displayName>
|
|
<description>Timer Counter register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCTC</name>
|
|
<description>Timer/Counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>LIM[%s]</name>
|
|
<displayName>LIM[%s]</displayName>
|
|
<description>Limit register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCLIM</name>
|
|
<description>Limit value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>MAT[%s]</name>
|
|
<displayName>MAT[%s]</displayName>
|
|
<description>Match register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCMAT</name>
|
|
<description>Match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT</name>
|
|
<description>Dead time register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3FFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DT0</name>
|
|
<description>Dead time for channel 0.[1]</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DT1</name>
|
|
<description>Dead time for channel 1.[2]</description>
|
|
<bitRange>[19:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DT2</name>
|
|
<description>Dead time for channel 2.[2]</description>
|
|
<bitRange>[29:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCP</name>
|
|
<description>Communication Pattern register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCPA0</name>
|
|
<description>Communication pattern output A, channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA0_PASSIVE_</name>
|
|
<description>MCOA0 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_MCOA0_</name>
|
|
<description>internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB0</name>
|
|
<description>Communication pattern output B, channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB0_PASSIVE_</name>
|
|
<description>MCOB0 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB0_TRACKS_INTERNA</name>
|
|
<description>MCOB0 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPA1</name>
|
|
<description>Communication pattern output A, channel 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA1_PASSIVE_</name>
|
|
<description>MCOA1 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOA1_TRACKS_INTERNA</name>
|
|
<description>MCOA1 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB1</name>
|
|
<description>Communication pattern output B, channel 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB1_PASSIVE_</name>
|
|
<description>MCOB1 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB1_TRACKS_INTERNA</name>
|
|
<description>MCOB1 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPA2</name>
|
|
<description>Communication pattern output A, channel 2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA2_PASSIVE_</name>
|
|
<description>MCOA2 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOA2_TRACKS_INTERNA</name>
|
|
<description>MCOA2 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB2</name>
|
|
<description>Communication pattern output B, channel 2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB2_PASSIVE_</name>
|
|
<description>MCOB2 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB2_TRACKS_INTERNA</name>
|
|
<description>MCOB2 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>CAP[%s]</name>
|
|
<displayName>CAP[%s]</displayName>
|
|
<description>Capture register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Current TC value at a capture event.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable read address</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0</name>
|
|
<description>Limit interrupt for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0</name>
|
|
<description>Match interrupt for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0</name>
|
|
<description>Capture interrupt for channel 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM1</name>
|
|
<description>Limit interrupt for channel 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1</name>
|
|
<description>Match interrupt for channel 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1</name>
|
|
<description>Capture interrupt for channel 1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM2</name>
|
|
<description>Limit interrupt for channel 2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2</name>
|
|
<description>Match interrupt for channel 2.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2</name>
|
|
<description>Capture interrupt for channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Fast abort interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN_SET</name>
|
|
<description>Interrupt Enable set address</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN_CLR</name>
|
|
<description>Interrupt Enable clear address</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<description>Interrupt flags read address</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F</name>
|
|
<description>Limit interrupt flag for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F</name>
|
|
<description>Match interrupt flag for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F</name>
|
|
<description>Capture interrupt flag for channel 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F</name>
|
|
<description>Limit interrupt flag for channel 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F</name>
|
|
<description>Match interrupt flag for channel 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F</name>
|
|
<description>Capture interrupt flag for channel 1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F</name>
|
|
<description>Limit interrupt flag for channel 2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F</name>
|
|
<description>Match interrupt flag for channel 2.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F</name>
|
|
<description>Capture interrupt flag for channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F</name>
|
|
<description>Fast abort interrupt flag.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF_SET</name>
|
|
<description>Interrupt flags set address</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF_CLR</name>
|
|
<description>Interrupt flags clear address</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON</name>
|
|
<description>Count Control read address</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI1 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI1 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI1 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI2 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 2.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI2 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI0 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI0 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI1 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI1 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_RISING_EDGE_ON_MCI</name>
|
|
<description>A rising edge on MCI2 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISIING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_FALLING_EDGE_ON_MC</name>
|
|
<description>A falling edge on MCI2 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CNTR0</name>
|
|
<description>Channel 0 counter/timer mode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_0_IS_IN_TIME</name>
|
|
<description>Channel 0 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_0_IS_IN_COUN</name>
|
|
<description>Channel 0 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1</name>
|
|
<description>Channel 1 counter/timer mode.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_1_IS_IN_TIME</name>
|
|
<description>Channel 1 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_1_IS_IN_COUN</name>
|
|
<description>Channel 1 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2</name>
|
|
<description>Channel 2 counter/timer mode.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_2_IS_IN_TIME</name>
|
|
<description>Channel 2 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_2_IS_IN_COUN</name>
|
|
<description>Channel 2 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON_SET</name>
|
|
<description>Count Control set address</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON_CLR</name>
|
|
<description>Count Control clear address</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP_CLR</name>
|
|
<description>Capture clear address</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP_CLR0</name>
|
|
<description>Writing a 1 to this bit clears the CAP0 register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP_CLR1</name>
|
|
<description>Writing a 1 to this bit clears the CAP1 register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP_CLR2</name>
|
|
<description>Writing a 1 to this bit clears the CAP2 register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>QEI</name>
|
|
<description>Quadrature Encoder Interface (QEI) </description>
|
|
<groupName>QEI</groupName>
|
|
<baseAddress>0x400BC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>QEI</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CON</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESP</name>
|
|
<description>Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESPI</name>
|
|
<description>Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESV</name>
|
|
<description>Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESI</name>
|
|
<description>Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRINV</name>
|
|
<description>Direction invert. When 1, complements the DIR bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIGMODE</name>
|
|
<description>Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPMODE</name>
|
|
<description>Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVINX</name>
|
|
<description>Invert Index. When 1, inverts the sense of the index input.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRESPI</name>
|
|
<description>Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INXGATE</name>
|
|
<description>Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POS</name>
|
|
<description>Position register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>Current position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXPOS</name>
|
|
<description>Maximum position register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXPOS</name>
|
|
<description>Current maximum position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS0</name>
|
|
<description>Position compare register 0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP0</name>
|
|
<description>Position compare value 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS1</name>
|
|
<description>Position compare register 1</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP1</name>
|
|
<description>Position compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS2</name>
|
|
<description>Position compare register 2</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP2</name>
|
|
<description>Position compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCNT</name>
|
|
<description>Index count register 0</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENCPOS</name>
|
|
<description>Current index counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP0</name>
|
|
<description>Index compare register 0</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP0</name>
|
|
<description>Index compare value 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<description>Velocity timer reload register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELLOAD</name>
|
|
<description>Current velocity timer load value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIME</name>
|
|
<description>Velocity timer register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELVAL</name>
|
|
<description>Current velocity timer value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VEL</name>
|
|
<description>Velocity counter register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELPC</name>
|
|
<description>Current velocity pulse count.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP</name>
|
|
<description>Velocity capture register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELCAP</name>
|
|
<description>Last velocity capture.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VELCOMP</name>
|
|
<description>Velocity compare register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELPC</name>
|
|
<description>Compare velocity pulse count.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHA</name>
|
|
<description>Digital filter register on PHA</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTA</name>
|
|
<description>Digital filter sampling delay for PhA.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHB</name>
|
|
<description>Digital filter register on PHB</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTB</name>
|
|
<description>Digital filter sampling delay for PhB.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERINX</name>
|
|
<description>Digital filter register on IDX</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FITLINX</name>
|
|
<description>Digital filter sampling delay for the index.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window width.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP1</name>
|
|
<description>Index compare register 1</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP1</name>
|
|
<description>Index compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP2</name>
|
|
<description>Index compare register 2</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP2</name>
|
|
<description>Index compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare 0 value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index compare 1value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index compare 2 value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET</name>
|
|
<description>Interrupt status set register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Writing a 1 sets the INX_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Writing a 1 sets the TIN_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Writing a 1 sets the VELC_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Writing a 1 sets the DIR_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Writing a 1 sets the ERR_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Writing a 1 sets the POS0_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Writing a 1 sets the POS1_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Writing a 1 sets the POS2_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Writing a 1 sets the REV0_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Writing a 1 sets the REV1_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Writing a 1 sets the REV2_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR</name>
|
|
<description>Interrupt status clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Writing a 1 clears the INX_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Writing a 1 clears the TIN_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Writing a 1 clears the VELC_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Writing a 1 clears the DIR_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Writing a 1 clears the ERR_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Writing a 1 clears the POS0_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Writing a 1 clears the POS1_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Writing a 1 clears the POS2_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Writing a 1 clears the REV0_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Writing a 1 clears the REV1_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Writing a 1 clears the REV2_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>When 1, the INX_Int interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>When 1, the TIN_Int interrupt is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>When 1, the VELC_Int interrupt is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>When 1, the DIR_Int interrupt is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>When 1, the ERR_Int interrupt is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>When 1, the ENCLK_Int interrupt is enabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>When 1, the POS0_Int interrupt is enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>When 1, the POS1_Int interrupt is enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>When 1, the POS2_Int interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>When 1, the REV0_Int interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>When 1, the POS0REV_Int interrupt is enabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>When 1, the POS1REV_Int interrupt is enabled.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>When 1, the POS2REV_Int interrupt is enabled.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>When 1, the REV1_Int interrupt is enabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>When 1, the REV2_Int interrupt is enabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>When 1, the MAXPOS_Int interrupt is enabled.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IES</name>
|
|
<description>Interrupt enable set register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Writing a 1 enables the INX_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Writing a 1 enables the TIN_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Writing a 1 enables the VELC_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Writing a 1 enables the DIR_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Writing a 1 enables the ERR_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Writing a 1 enables the POS0_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Writing a 1 enables the POS1_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Writing a 1 enables the POS2_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Writing a 1 enables the REV0_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Writing a 1 enables the REV1_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Writing a 1 enables the REV2_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEC</name>
|
|
<description>Interrupt enable clear register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Writing a 1 disables the INX_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Writing a 1 disables the TIN_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Writing a 1 disables the VELC_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Writing a 1 disables the DIR_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Writing a 1 disables the ERR_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Writing a 1 disables the POS0_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Writing a 1 disables the POS1_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Writing a 1 disables the POS2_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Writing a 1 disables the REV0_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Writing a 1 disables the REV1_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Writing a 1 disables the REV2_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>SDMMC</name>
|
|
<description>SD card</description>
|
|
<groupName>SDMMC</groupName>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SDMMC</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PWR</name>
|
|
<description>Power control register.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>Power control</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWER_OFF</name>
|
|
<description>Power-off</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_UP</name>
|
|
<description>Power-up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_ON</name>
|
|
<description>Power-on</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OPENDRAIN</name>
|
|
<description>SD_CMD output control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ROD</name>
|
|
<description>Rod control.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK</name>
|
|
<description>Clock control register.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)].</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable SD card bus clock:</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLOCK_DISABLED_</name>
|
|
<description>Clock disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK_ENABLED_</name>
|
|
<description>Clock enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRSAVE</name>
|
|
<description>Disable SD_CLK output when bus is idle:</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALWAYS_ENABLED_</name>
|
|
<description>Always enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCK_ENABLED_WHEN_B</name>
|
|
<description>Clock enabled when bus is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Enable bypass of clock divide logic:</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BYPASS_</name>
|
|
<description>Disable bypass.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BYPASS_MCLK_</name>
|
|
<description>Enable bypass. MCLK driven to card bus output (SD_CLK).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIDEBUS</name>
|
|
<description>Enable wide bus mode.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_BUS_MODE_O</name>
|
|
<description>Standard bus mode (only SD_DAT[0] used).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIDE_BUS_MODE_SD_DA</name>
|
|
<description>Wide bus mode (SD_DAT[3:0] used)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARGUMENT</name>
|
|
<description>Argument register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CmdArg</name>
|
|
<description>Command argument</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMMAND</name>
|
|
<description>Command register.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CmdIndex</name>
|
|
<description>Command index.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Response</name>
|
|
<description>If set, CPSM waits for a response.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LongRsp</name>
|
|
<description>If set, CPSM receives a 136 bit long response.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Interrupt</name>
|
|
<description>If set, CPSM disables command timer and waits for interrupt request.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Pending</name>
|
|
<description>If set, CPSM waits for CmdPend before it starts sending a command.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Enable</name>
|
|
<description>If set, CPSM is enabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESPCMD</name>
|
|
<description>Response command register.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPCMD</name>
|
|
<description>Response command index</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>RESPONSE%s</name>
|
|
<description>Response register.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>Card status</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATATIMER</name>
|
|
<description>Data Timer.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATATIME</name>
|
|
<description>Data timeout period.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALENGTH</name>
|
|
<description>Data length register.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALENGTH</name>
|
|
<description>Data length value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATACTRL</name>
|
|
<description>Data control register.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Data transfer enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTION</name>
|
|
<description>Data transfer direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FROM_CONTROLLER_TO_C</name>
|
|
<description>From controller to card.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FROM_CARD_TO_CONTROL</name>
|
|
<description>From card to controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Data transfer mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BLOCK_DATA_TRANSFER_</name>
|
|
<description>Block data transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STREAM_DATA_TRANSFER</name>
|
|
<description>Stream data transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAENABLE</name>
|
|
<description>Enable DMA</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DMA_DISABLED_</name>
|
|
<description>DMA disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA_ENABLED_</name>
|
|
<description>DMA enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLOCKSIZE</name>
|
|
<description>Data block length</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATACNT</name>
|
|
<description>Data counter.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATACOUNT</name>
|
|
<description>Remaining data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status register.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDCRCFAIL</name>
|
|
<description>Command response received (CRC check failed).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATACRCFAIL</name>
|
|
<description>Data block sent/received (CRC check failed).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDTIMEOUT</name>
|
|
<description>Command response timeout.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATATIMEOUT</name>
|
|
<description>Data timeout.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUN</name>
|
|
<description>Transmit FIFO underrun error.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVERRUN</name>
|
|
<description>Receive FIFO overrun error.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDRESPEND</name>
|
|
<description>Command response received (CRC check passed).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDSENT</name>
|
|
<description>Command sent (no response required).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAEND</name>
|
|
<description>Data end (data counter is zero).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTBITERR</name>
|
|
<description>Start bit not detected on all data signals in wide bus mode.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATABLOCKEND</name>
|
|
<description>Data block sent/received (CRC check passed).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDACTIVE</name>
|
|
<description>Command transfer in progress.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXACTIVE</name>
|
|
<description>Data transmit in progress.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXACTIVE</name>
|
|
<description>Data receive in progress.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOHALFEMPTY</name>
|
|
<description>Transmit FIFO half empty.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOHALFFULL</name>
|
|
<description>Receive FIFO half full.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOFULL</name>
|
|
<description>Transmit FIFO full.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOFULL</name>
|
|
<description>Receive FIFO full.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOEMPTY</name>
|
|
<description>Transmit FIFO empty.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOEMPTY</name>
|
|
<description>Receive FIFO empty.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDATAAVLBL</name>
|
|
<description>Data available in transmit FIFO.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAAVLBL</name>
|
|
<description>Data available in receive FIFO.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR</name>
|
|
<description>Clear register.</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDCRCFAILCLR</name>
|
|
<description>Clears CmdCrcFail flag.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATACRCFAILCLR</name>
|
|
<description>Clears DataCrcFail flag.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDTIMEOUTCLR</name>
|
|
<description>Clears CmdTimeOut flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATATIMEOUTCLR</name>
|
|
<description>Clears DataTimeOut flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDERRUNCLR</name>
|
|
<description>Clears TxUnderrun flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVERRUNCLR</name>
|
|
<description>Clears RxOverrun flag.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDRESPENDCLR</name>
|
|
<description>Clears CmdRespEnd flag.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDSENTCLR</name>
|
|
<description>Clears CmdSent flag.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAENDCLR</name>
|
|
<description>Clears DataEnd flag.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTBITERRCLR</name>
|
|
<description>Clears StartBitErr flag.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATABLOCKENDCLR</name>
|
|
<description>Clears DataBlockEnd flag.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK0</name>
|
|
<description>Interrupt 0 mask register.</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK0</name>
|
|
<description>Mask CmdCrcFail flag.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK1</name>
|
|
<description>Mask DataCrcFail flag.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK2</name>
|
|
<description>Mask CmdTimeOut flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK3</name>
|
|
<description>Mask DataTimeOut flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK4</name>
|
|
<description>Mask TxUnderrun flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK5</name>
|
|
<description>Mask RxOverrun flag.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK6</name>
|
|
<description>Mask CmdRespEnd flag.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK7</name>
|
|
<description>Mask CmdSent flag.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK8</name>
|
|
<description>Mask DataEnd flag.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK9</name>
|
|
<description>Mask StartBitErr flag.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK10</name>
|
|
<description>Mask DataBlockEnd flag.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK11</name>
|
|
<description>Mask CmdActive flag.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK12</name>
|
|
<description>Mask TxActive flag.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK13</name>
|
|
<description>Mask RxActive flag.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK14</name>
|
|
<description>Mask TxFifoHalfEmpty flag.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK15</name>
|
|
<description>Mask RxFifoHalfFull flag.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK16</name>
|
|
<description>Mask TxFifoFull flag.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK17</name>
|
|
<description>Mask RxFifoFull flag.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK18</name>
|
|
<description>Mask TxFifoEmpty flag.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK19</name>
|
|
<description>Mask RxFifoEmpty flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK20</name>
|
|
<description>Mask TxDataAvlbl flag.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK21</name>
|
|
<description>Mask RxDataAvlbl flag.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCNT</name>
|
|
<description>FIFO Counter.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATACOUNT</name>
|
|
<description>Remaining data</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>FIFO%s</name>
|
|
<description>Data FIFO Register.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>FIFO data.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCON</name>
|
|
<description> System and clock control </description>
|
|
<groupName>SYSCON</groupName>
|
|
<baseAddress>0x400FC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EINT0</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EINT1</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EINT2</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EINT3</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>BOD</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FLASHCFG</name>
|
|
<description>Flash Accelerator Configuration Register. Controls flash access timing.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not change these bits from the reset value.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASHTIM</name>
|
|
<description>Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_1</name>
|
|
<description>Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_2</name>
|
|
<description>Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_3</name>
|
|
<description>Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_4</name>
|
|
<description>Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_5</name>
|
|
<description>Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ACCESSES_USE_6</name>
|
|
<description>Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PLLCON%s</name>
|
|
<description>PLL0 Control register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLE</name>
|
|
<description>PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PLLCFG%s</name>
|
|
<description>PLL0 Configuration register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>PLL Divider value. Supplies the value "P" in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PLLSTAT%s</name>
|
|
<description>PLL0 Status register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Read-back for the PLL Multiplier value. This is the value currently used by the related PLL.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Read-back for the PLL Divider value. This is the value currently used by the related PLL.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PLLE_STAT</name>
|
|
<description>Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PLOCK</name>
|
|
<description>Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PLLFEED%s</name>
|
|
<description>PLL0 Feed register</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLFEED</name>
|
|
<description>The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCON</name>
|
|
<description>Power Control register</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM0</name>
|
|
<description>Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PM1</name>
|
|
<description>Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRPM</name>
|
|
<description>Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOGD</name>
|
|
<description>Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BORD</name>
|
|
<description>Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SMFLAG</name>
|
|
<description>Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DSFLAG</name>
|
|
<description>Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PDFLAG</name>
|
|
<description>Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDFLAG</name>
|
|
<description>Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCONP0</name>
|
|
<description>Power Control for Peripherals</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0408829E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCLCD</name>
|
|
<description>LCD controller power/clock control bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCTIM0</name>
|
|
<description>Timer/Counter 0 power/clock control bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCTIM1</name>
|
|
<description>Timer/Counter 1 power/clock control bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUART0</name>
|
|
<description>UART0 power/clock control bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUART1</name>
|
|
<description>UART1 power/clock control bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCPWM0</name>
|
|
<description>PWM0 power/clock control bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCPWM1</name>
|
|
<description>PWM1 power/clock control bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCI2C0</name>
|
|
<description>I2C0 interface power/clock control bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUART4</name>
|
|
<description>UART4 power/clock control bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCRTC</name>
|
|
<description>RTC and Event Monitor/Recorder power/clock control bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCSSP1</name>
|
|
<description>SSP 1 interface power/clock control bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCEMC</name>
|
|
<description>External Memory Controller power/clock control bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCADC</name>
|
|
<description>A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCCAN1</name>
|
|
<description>CAN Controller 1 power/clock control bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCCAN2</name>
|
|
<description>CAN Controller 2 power/clock control bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCGPIO</name>
|
|
<description>Power/clock control bit for IOCON, GPIO, and GPIO interrupts.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCSPIFI</name>
|
|
<description>SPI Flash Interface power/clock control bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCMCPWM</name>
|
|
<description>Motor Control PWM power/clock control bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCQEI</name>
|
|
<description>Quadrature Encoder Interface power/clock control bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCI2C1</name>
|
|
<description>I2C1 interface power/clock control bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCSSP2</name>
|
|
<description>SSP2 interface power/clock control bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCSSP0</name>
|
|
<description>SSP0 interface power/clock control bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCTIM2</name>
|
|
<description>Timer 2 power/clock control bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCTIM3</name>
|
|
<description>Timer 3 power/clock control bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUART2</name>
|
|
<description>UART 2 power/clock control bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUART3</name>
|
|
<description>UART 3 power/clock control bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCI2C2</name>
|
|
<description>I2C interface 2 power/clock control bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCI2S</name>
|
|
<description>I2S interface power/clock control bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCSDC</name>
|
|
<description>SD Card interface power/clock control bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCGPDMA</name>
|
|
<description>GPDMA function power/clock control bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCENET</name>
|
|
<description>Ethernet block power/clock control bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCUSB</name>
|
|
<description>USB interface power/clock control bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCONP1</name>
|
|
<description>Power Control for Peripherals</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCCMP</name>
|
|
<description>comparator 0/1 power/clock control bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMCCLKSEL</name>
|
|
<description>External Memory Controller Clock Selection register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMCDIV</name>
|
|
<description>Selects the EMC clock rate relative to the CPU clock.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_EMC_USES_THE_SAM</name>
|
|
<description>The EMC uses the same clock as the CPU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_EMC_USES_A_CLOCK</name>
|
|
<description>The EMC uses a clock at half the rate of the CPU.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCLKSEL</name>
|
|
<description>CPU Clock Selection register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLKDIV</name>
|
|
<description>Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CCLKSEL</name>
|
|
<description>Selects the input clock for the CPU clock divider.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYSCLK_IS_USED_AS_TH</name>
|
|
<description>Sysclk is used as the input to the CPU clock divider.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_OUTPUT_OF_THE_MA</name>
|
|
<description>The output of the Main PLL is used as the input to the CPU clock divider.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKSEL</name>
|
|
<description>USB Clock Selection register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBDIV</name>
|
|
<description>Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_DIVIDER_IS_TURNE</name>
|
|
<description>The divider is turned off, no clock will be provided to the USB subsystem.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_OUTPUT_IS_DIVID</name>
|
|
<description>PLL0 output is divided by 4. PLL0 output must be 192 MHz.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_OUTPUT_IS_DIVID</name>
|
|
<description>PLL0 output is divided by 6. PLL0 output must be 288 MHz.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USBSEL</name>
|
|
<description>Selects the input clock for the USB clock divider.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYSCLK</name>
|
|
<description>Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAINPLLOUT</name>
|
|
<description>The output of the Main PLL is used as the input to the USB clock divider.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTPLLOOUT</name>
|
|
<description>The output of the Alt PLL is used as the input to the USB clock divider.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, this setting should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSRCSEL</name>
|
|
<description>Clock Source Select Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKSRC</name>
|
|
<description>Selects the clock source for sysclk and PLL0 as follows:</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_INTERNAL</name>
|
|
<description>Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_MAIN_OSC</name>
|
|
<description>Selects the main oscillator as the sysclk and PLL0 clock source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANSLEEPCLR</name>
|
|
<description>Allows clearing the current CAN channel sleep state as well as reading that state.</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1SLEEP</name>
|
|
<description>Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN2SLEEP</name>
|
|
<description>Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANWAKEFLAGS</name>
|
|
<description>Allows reading the wake-up state of the CAN channels.</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1WAKE</name>
|
|
<description>Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN2WAKE</name>
|
|
<description>Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTINT</name>
|
|
<description>External Interrupt Flag Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EINT0</name>
|
|
<description>In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EINT1</name>
|
|
<description>In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EINT2</name>
|
|
<description>In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EINT3</name>
|
|
<description>In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTMODE</name>
|
|
<description>External Interrupt Mode register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTMODE0</name>
|
|
<description>Level or edge sensitivity select for EINT0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_SENSITIVE_</name>
|
|
<description>Level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_SENSITIVE_</name>
|
|
<description>Edge sensitive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTMODE1</name>
|
|
<description>Level or edge sensitivity select for EINT1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_SENSITIVE_</name>
|
|
<description>Level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_SENSITIVE_</name>
|
|
<description>Edge sensitive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTMODE2</name>
|
|
<description>Level or edge sensitivity select for EINT2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_SENSITIVE_</name>
|
|
<description>Level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_SENSITIVE_</name>
|
|
<description>Edge sensitive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTMODE3</name>
|
|
<description>Level or edge sensitivity select for EINT3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_SENSITIVE_</name>
|
|
<description>Level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_SENSITIVE_</name>
|
|
<description>Edge sensitive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTPOLAR</name>
|
|
<description>External Interrupt Polarity Register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTPOLAR0</name>
|
|
<description>External interrupt polarity for EINT0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_ACTIVE_OR_FALLIN</name>
|
|
<description>Low-active or falling-edge sensitive (depending on EXTMODE0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_ACTIVE_OR_RISIN</name>
|
|
<description>High-active or rising-edge sensitive (depending on EXTMODE0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTPOLAR1</name>
|
|
<description>External interrupt polarity for EINT1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_ACTIVE_OR_FALLIN</name>
|
|
<description>Low-active or falling-edge sensitive (depending on EXTMODE1).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_ACTIVE_OR_RISIN</name>
|
|
<description>High-active or rising-edge sensitive (depending on EXTMODE1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTPOLAR2</name>
|
|
<description>External interrupt polarity for EINT2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_ACTIVE_OR_FALLIN</name>
|
|
<description>Low-active or falling-edge sensitive (depending on EXTMODE2).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_ACTIVE_OR_RISIN</name>
|
|
<description>High-active or rising-edge sensitive (depending on EXTMODE2).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTPOLAR3</name>
|
|
<description>External interrupt polarity for EINT3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_ACTIVE_OR_FALLIN</name>
|
|
<description>Low-active or falling-edge sensitive (depending on EXTMODE3).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_ACTIVE_OR_RISIN</name>
|
|
<description>High-active or rising-edge sensitive (depending on EXTMODE3).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSID</name>
|
|
<description>Reset Source Identification Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EXTR</name>
|
|
<description>Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDTR</name>
|
|
<description>This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODR</name>
|
|
<description>This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESET</name>
|
|
<description>This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>This bit is set if the processor has been reset due to a "lockup". The lockup state causes a chip reset. This bit is cleared only by software or POR.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATRIXARB</name>
|
|
<description>Matrix arbitration register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_ICODE</name>
|
|
<description>I-Code bus priority. Should be lower than PRI_DCODE for proper operation.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_DCODE</name>
|
|
<description>D-Code bus priority.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_SYS</name>
|
|
<description>System bus priority.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_GPDMA</name>
|
|
<description>General Purpose DMA controller priority.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_ETH</name>
|
|
<description>Ethernet DMA priority.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_LCD</name>
|
|
<description>LCD DMA priority.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PRI_USB</name>
|
|
<description>USB DMA priority.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROM_LAT</name>
|
|
<description>ROM latency select. Should always be 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>SCS</name>
|
|
<description>System Control and Status</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMCSC</name>
|
|
<description>EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STATIC_MEMORY_ADDRES</name>
|
|
<description>Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATIC_MEMORY_ADDRES</name>
|
|
<description>Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMCRD</name>
|
|
<description>EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BOTH_EMC_RESETS_ARE_</name>
|
|
<description>Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MANY_PORTIONS_OF_THE</name>
|
|
<description>Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMCBC</name>
|
|
<description>External Memory Controller burst control. Also see Section 9.10 in the EMC chapter.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BURST_ENABLED_</name>
|
|
<description>Burst enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_DISABLED_THIS</name>
|
|
<description>Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCIPWRAL</name>
|
|
<description>MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SD_PWR_IS_ACTIVE_LOW</name>
|
|
<description>SD_PWR is active low (inverted output of the SD Card interface block).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SD_PWR_IS_ACTIVE_HIG</name>
|
|
<description>SD_PWR is active high (follows the output of the SD Card interface block).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCRS</name>
|
|
<description>Main oscillator range select.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_FREQUENCY_RANGE_</name>
|
|
<description>The frequency range of the main oscillator is 1 MHz to 20 MHz.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_FREQUENCY_RANGE_</name>
|
|
<description>The frequency range of the main oscillator is 15 MHz to 25 MHz.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCEN</name>
|
|
<description>Main oscillator enable.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MAIN_OSCILLATOR_</name>
|
|
<description>The main oscillator is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MAIN_OSCILLATOR_</name>
|
|
<description>The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCSTAT</name>
|
|
<description>Main oscillator status.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MAIN_OSCILLATOR_</name>
|
|
<description>The main oscillator is not ready to be used as a clock source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MAIN_OSCILLATOR_</name>
|
|
<description>The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCLKSEL</name>
|
|
<description>Peripheral Clock Selection register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCLKDIV</name>
|
|
<description>Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOOST</name>
|
|
<description>Power boost register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Boost</name>
|
|
<description>Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPIFICLKSEL</name>
|
|
<description>SPIFI Clock Selection register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPIFIDIV</name>
|
|
<description>Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SPIFISEL</name>
|
|
<description>Selects the input clock for the USB clock divider.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYSCLK</name>
|
|
<description>Sysclk is used as the input to the SPIFI clock divider.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAINPLLOUT</name>
|
|
<description>The output of the Main PLL is used as the input to the SPIFI clock divider.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTPLLOUT</name>
|
|
<description>The output of the Alt PLL is used as the input to the SPIFI clock divider.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, this setting should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCD_CFG</name>
|
|
<description>LCD Clock configuration register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTST</name>
|
|
<description>USB Interrupt Status</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_INT_REQ_LP</name>
|
|
<description>Low priority interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_INT_REQ_HP</name>
|
|
<description>High priority interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_INT_REQ_DMA</name>
|
|
<description>DMA interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_HOST_INT</name>
|
|
<description>USB host interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_ATX_INT</name>
|
|
<description>External ATX interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_OTG_INT</name>
|
|
<description>OTG interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_I2C_INT</name>
|
|
<description>I2C module interrupt line status. This bit is read-only.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_NEED_CLK</name>
|
|
<description>USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 "Wake-up from Reduced Power Modes" for details). Also see Section 3.10.3 "PLLs and Power-down mode" and Section 3.3.7 "Power Control for Peripherals registers" for considerations about the PLL and invoking the Power-down mode. This bit is read-only.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[30:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EN_USB_INTS</name>
|
|
<description>Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACREQSEL</name>
|
|
<description>Selects between alternative requests on DMA channels 0 through 7 and 10 through 15</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMASEL00</name>
|
|
<description>Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL01</name>
|
|
<description>Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL02</name>
|
|
<description>Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL03</name>
|
|
<description>Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL04</name>
|
|
<description>Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL05</name>
|
|
<description>Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL06</name>
|
|
<description>Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL07</name>
|
|
<description>Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL10</name>
|
|
<description>Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL11</name>
|
|
<description>Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL12</name>
|
|
<description>Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL13</name>
|
|
<description>Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL14</name>
|
|
<description>Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMASEL15</name>
|
|
<description>Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTCFG</name>
|
|
<description>Clock Output Configuration register</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKOUTSEL</name>
|
|
<description>Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUTDIV</name>
|
|
<description>Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUT_EN</name>
|
|
<description>CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUT_ACT</name>
|
|
<description>CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCON0</name>
|
|
<description>Individual peripheral reset control bits</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTLCD</name>
|
|
<description>LCD controller reset control bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTTIM0</name>
|
|
<description>Timer/Counter 0 reset control bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTTIM1</name>
|
|
<description>Timer/Counter 1 reset control bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUART0</name>
|
|
<description>UART0 reset control bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUART1</name>
|
|
<description>UART1 reset control bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTPWM0</name>
|
|
<description>PWM0 reset control bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTPWM1</name>
|
|
<description>PWM1 reset control bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTI2C0</name>
|
|
<description>The I2C0 interface reset control bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUART4</name>
|
|
<description>UART4 reset control bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTRTC</name>
|
|
<description>RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 "Register overview: Real-Time Clock (base address 0x4002 4000)" for details.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTSSP1</name>
|
|
<description>The SSP 1 interface reset control bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTEMC</name>
|
|
<description>External Memory Controller reset control bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTADC</name>
|
|
<description>A/D converter (ADC) reset control bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTCAN1</name>
|
|
<description>CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTCAN2</name>
|
|
<description>CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTGPIO</name>
|
|
<description>Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTSPIFI</name>
|
|
<description>SPI Flash Interface reset control bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTMCPWM</name>
|
|
<description>Motor Control PWM reset control bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTQEI</name>
|
|
<description>Quadrature Encoder Interface reset control bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTI2C1</name>
|
|
<description>The I2C1 interface reset control bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTSSP2</name>
|
|
<description>The SSP2 interface reset control bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTSSP0</name>
|
|
<description>The SSP0 interface reset control bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTTIM2</name>
|
|
<description>Timer 2 reset control bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTTIM3</name>
|
|
<description>Timer 3 reset control bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUART2</name>
|
|
<description>UART 2 reset control bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUART3</name>
|
|
<description>UART 3 reset control bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTI2C2</name>
|
|
<description>I2C interface 2 reset control bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTI2S</name>
|
|
<description>I2S interface reset control bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTSDC</name>
|
|
<description>SD Card interface reset control bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTGPDMA</name>
|
|
<description>GPDMA function reset control bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTENET</name>
|
|
<description>Ethernet block reset control bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTUSB</name>
|
|
<description>USB interface reset control bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCON1</name>
|
|
<description>Individual peripheral reset control bits</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTIOCON</name>
|
|
<description>Reset control bit for the IOCON registers.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTDAC</name>
|
|
<description>D/A converter (DAC) reset control bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTCANACC</name>
|
|
<description>CAN acceptance filter reset control bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSTCMP</name>
|
|
<description>Comparator 0/1 reset control bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMCDLYCTL</name>
|
|
<description>Values for the 4 programmable delays associated with SDRAM operation.</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x210</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMDDLY</name>
|
|
<description>Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBCLKDLY</name>
|
|
<description>Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds.</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUT0DLY</name>
|
|
<description>Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUT1DLY</name>
|
|
<description>Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMCCAL</name>
|
|
<description>Controls the calibration counter for programmable delays and returns the result value.</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CALVALUE</name>
|
|
<description>Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
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|
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|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</peripherals>
|
|
</device>
|