LPC408x_7x 0.7 LPC408x/7x M4 CM4 r0p0 little 0 0 3 0 8 32 32 FLASHCTRL EEPROM/flash FLASHCTRL 0x00200000 0x0 0xFFF registers EEPROM 40 FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). [16:0] SIG_START Start control bit for signature generation. [17:17] ENUM STOP Signature generation is stopped 0 START Initiate signature generation 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:18] FMSW0 128-bit signature Word 0 0x02C read-only 0 0x00000000 SW0_31_0 Word 0 of 128-bit signature (bits 31 to 0). [31:0] FMSW1 128-bit signature Word 1 0x030 read-only 0 0x00000000 SW1_63_32 Word 1 of 128-bit signature (bits 63 to 32). [31:0] FMSW2 128-bit signature Word 2 0x034 read-only 0 0x00000000 SW2_95_64 Word 2 of 128-bit signature (bits 95 to 64). [31:0] FMSW3 128-bit signature Word 3 0x038 read-only 0 0x00000000 SW3_127_96 Word 3 of 128-bit signature (bits 127 to 96). [31:0] EECMD EEPROM command register 0x080 read-write 0 0xFFFFFFFF CMD Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved [2:0] RDPREFETCH Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] EEADDR EEPROM address register 0x084 read-write 0 0xFFFFFFFF ADDR EEPROM Address. Lower 6 bits are don't care. [11:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] EEWDATA EEPROM write data register 0x088 write-only 0 0x00000000 WDATA Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data. [31:0] EERDATA EEPROM read data register 0x08C read-only 0 0x00000000 RDATA Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data. [31:0] EEWSTATE EEPROM wait state register 0x090 read-write 0 0xFFFFFFFF PHASE3 Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns. [7:0] PHASE2 Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns. [15:8] PHASE1 Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns. [23:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] EECLKDIV EEPROM clock divider register 0x094 read-write 0 0xFFFFFFFF CLKDIV Division factor (minus 1 encoded). [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] EEPWRDWN EEPROM power-down register 0x098 read-write 0 0xFFFFFFFF PWRDWN Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down). [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] STAT Signature generation status register 0xFE0 read-only 0 0xFFFFFFFF RESERVED Reserved. The value read from a reserved bit is not defined. [1:0] SIG_DONE When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. [2:2] RESERVED Reserved. The value read from a reserved bit is not defined. [25:3] END_OF_RDWR EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register. [26:26] RESERVED Reserved. The value read from a reserved bit is not defined. [27:27] END_OF_PROG1 EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register. [28:28] RESERVED Reserved. The value read from a reserved bit is not defined. [31:29] INTEN EEPROM interrupt enable 0xFE4 read-only 0 0xFFFFFFFF RESERVED Reserved. The value read from a reserved bit is not defined. [25:0] EE_RW_DONE EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register. [26:26] RESERVED Reserved. The value read from a reserved bit is not defined. [27:27] EE_PROG_DONE EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register. [28:28] RESERVED Reserved. The value read from a reserved bit is not defined. [31:29] STATCLR Signature generation status clear register 0xFE8 write-only 0 0x00000000 RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [25:3] RDWR_CLR_ST Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit. [26:26] RESERVED Reserved. Read value is undefined, only zero should be written. [27:27] PROG1_CLR_ST Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit. [28:28] RESERVED Reserved. Read value is undefined, only zero should be written. [31:29] ENCLR EEPROM interrupt enable clear 0xFD8 write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [25:0] RDWR_CLR_EN Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit. [26:26] RESERVED Reserved. Read value is undefined, only zero should be written. [27:27] PROG1_CLR_EN Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit. [28:28] RESERVED Reserved. Read value is undefined, only zero should be written. [31:29] ENSET EEPROM interrupt enable set 0xFDC write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [25:0] RDWR_SET_EN Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit. [26:26] RESERVED Reserved. Read value is undefined, only zero should be written. [27:27] PROG1_SET_EN Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit. [28:28] RESERVED Reserved. Read value is undefined, only zero should be written. [31:29] GPDMA General Purpose DMA controller Modification GPDMA 0x20080000 0x0 0xFFF registers GPDMA 26 INTSTAT DMA Interrupt Status Register 0x000 read-only 0 0xFFFFFFFF INTSTAT0 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [0:0] INTSTAT1 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [1:1] INTSTAT2 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [2:2] INTSTAT3 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [3:3] INTSTAT4 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [4:4] INTSTAT5 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [5:5] INTSTAT6 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [6:6] INTSTAT7 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] INTTCSTAT DMA Interrupt Terminal Count Request Status Register 0x004 read-only 0 0xFFFFFFFF INTTCSTAT0 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [0:0] INTTCSTAT1 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [1:1] INTTCSTAT2 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [2:2] INTTCSTAT3 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [3:3] INTTCSTAT4 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [4:4] INTTCSTAT5 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [5:5] INTTCSTAT6 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [6:6] INTTCSTAT7 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] INTTCCLEAR DMA Interrupt Terminal Count Request Clear Register 0x008 write-only 0 0x00000000 INTTCCLEAR0 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [0:0] INTTCCLEAR1 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [1:1] INTTCCLEAR2 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [2:2] INTTCCLEAR3 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [3:3] INTTCCLEAR4 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [4:4] INTTCCLEAR5 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [5:5] INTTCCLEAR6 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [6:6] INTTCCLEAR7 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] INTERRSTAT DMA Interrupt Error Status Register 0x00C read-only 0 0xFFFFFFFF INTERRSTAT0 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [0:0] INTERRSTAT1 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [1:1] INTERRSTAT2 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [2:2] INTERRSTAT3 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [3:3] INTERRSTAT4 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [4:4] INTERRSTAT5 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [5:5] INTERRSTAT6 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [6:6] INTERRSTAT7 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] INTERRCLR DMA Interrupt Error Clear Register 0x010 write-only 0 0x00000000 INTERRCLR0 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [0:0] INTERRCLR1 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [1:1] INTERRCLR2 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [2:2] INTERRCLR3 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [3:3] INTERRCLR4 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [4:4] INTERRCLR5 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [5:5] INTERRCLR6 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [6:6] INTERRCLR7 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RAWINTTCSTAT DMA Raw Interrupt Terminal Count Status Register 0x014 read-only 0 0xFFFFFFFF RAWINTTCSTAT0 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [0:0] RAWINTTCSTAT1 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [1:1] RAWINTTCSTAT2 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [2:2] RAWINTTCSTAT3 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [3:3] RAWINTTCSTAT4 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [4:4] RAWINTTCSTAT5 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [5:5] RAWINTTCSTAT6 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [6:6] RAWINTTCSTAT7 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] RAWINTERRSTAT DMA Raw Error Interrupt Status Register 0x018 read-only 0 0xFFFFFFFF RAWINTERRSTAT0 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [0:0] RAWINTERRSTAT1 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [1:1] RAWINTERRSTAT2 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [2:2] RAWINTERRSTAT3 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [3:3] RAWINTERRSTAT4 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [4:4] RAWINTERRSTAT5 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [5:5] RAWINTERRSTAT6 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [6:6] RAWINTERRSTAT7 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ENBLDCHNS DMA Enabled Channel Register 0x01C read-only 0 0xFFFFFFFF ENABLEDCHANNELS0 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [0:0] ENABLEDCHANNELS1 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [1:1] ENABLEDCHANNELS2 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [2:2] ENABLEDCHANNELS3 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [3:3] ENABLEDCHANNELS4 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [4:4] ENABLEDCHANNELS5 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [5:5] ENABLEDCHANNELS6 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [6:6] ENABLEDCHANNELS7 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SOFTBREQ DMA Software Burst Request Register 0x020 read-write 0 0xFFFFFFFF SOFTBREQ0 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [0:0] SOFTBREQ1 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [1:1] SOFTBREQ2 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [2:2] SOFTBREQ3 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [3:3] SOFTBREQ4 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [4:4] SOFTBREQ5 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [5:5] SOFTBREQ6 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [6:6] SOFTBREQ7 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [7:7] SOFTBREQ8 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [8:8] SOFTBREQ9 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [9:9] SOFTBREQ10 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [10:10] SOFTBREQ11 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [11:11] SOFTBREQ12 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [12:12] SOFTBREQ13 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [13:13] SOFTBREQ14 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [14:14] SOFTBREQ15 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] SOFTSREQ DMA Software Single Request Register 0x024 read-write 0x00000000 0xFFFFFFFF SOFTSREQ0 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [0:0] SOFTSREQ1 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [1:1] SOFTSREQ2 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [2:2] SOFTSREQ3 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [3:3] SOFTSREQ4 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [4:4] SOFTSREQ5 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [5:5] SOFTSREQ6 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [6:6] SOFTSREQ7 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [7:7] SOFTSREQ8 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [8:8] SOFTSREQ9 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [9:9] SOFTSREQ10 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [10:10] SOFTSREQ11 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [11:11] SOFTSREQ12 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [12:12] SOFTSREQ13 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [13:13] SOFTSREQ14 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [14:14] SOFTSREQ15 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] SOFTLBREQ DMA Software Last Burst Request Register 0x028 read-write 0 0xFFFFFFFF SOFTLBREQ0 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [0:0] SOFTLBREQ1 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [1:1] SOFTLBREQ2 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [2:2] SOFTLBREQ3 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [3:3] SOFTLBREQ4 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [4:4] SOFTLBREQ5 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [5:5] SOFTLBREQ6 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [6:6] SOFTLBREQ7 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [7:7] SOFTLBREQ8 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [8:8] SOFTLBREQ9 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [9:9] SOFTLBREQ10 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [10:10] SOFTLBREQ11 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [11:11] SOFTLBREQ12 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [12:12] SOFTLBREQ13 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [13:13] SOFTLBREQ14 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [14:14] SOFTLBREQ15 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] SOFTLSREQ DMA Software Last Single Request Register 0x02C read-write 0 0xFFFFFFFF SOFTLSREQ0 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [0:0] SOFTLSREQ1 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [1:1] SOFTLSREQ2 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [2:2] SOFTLSREQ3 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [3:3] SOFTLSREQ4 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [4:4] SOFTLSREQ5 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [5:5] SOFTLSREQ6 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [6:6] SOFTLSREQ7 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [7:7] SOFTLSREQ8 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [8:8] SOFTLSREQ9 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [9:9] SOFTLSREQ10 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [10:10] SOFTLSREQ11 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [11:11] SOFTLSREQ12 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [12:12] SOFTLSREQ13 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [13:13] SOFTLSREQ14 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [14:14] SOFTLSREQ15 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] CONFIG DMA Configuration Register 0x030 read-write 0 0xFFFFFFFF E DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled. [0:0] M AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. [1:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] SYNC DMA Synchronization Register 0x034 read-write 0 0xFFFFFFFF DMACSYNC0 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [0:0] DMACSYNC1 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [1:1] DMACSYNC2 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [2:2] DMACSYNC3 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [3:3] DMACSYNC4 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [4:4] DMACSYNC5 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [5:5] DMACSYNC6 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [6:6] DMACSYNC7 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [7:7] DMACSYNC8 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [8:8] DMACSYNC9 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [9:9] DMACSYNC10 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [10:10] DMACSYNC11 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [11:11] DMACSYNC12 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [12:12] DMACSYNC13 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [13:13] DMACSYNC14 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [14:14] DMACSYNC15 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] 8 0x20 0-7 SRCADDR%s DMA Channel 0 Source Address Register 0x100 read-write 0 0xFFFFFFFF SRCADDR DMA source address. Reading this register will return the current source address. [31:0] 8 0x20 0-7 DESTADDR%s DMA Channel 0 Destination Address Register 0x104 read-write 0 0xFFFFFFFF DESTADDR DMA Destination address. Reading this register will return the current destination address. [31:0] 8 0x20 0-7 LLI%s DMA Channel 0 Linked List Item Register 0x108 read-write 0 0xFFFFFFFF RESERVED Reserved, and must be written as 0. [1:0] LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. [31:2] 8 0x20 0-7 CONTROL%s DMA Channel 0 Control Register 0x10C read-write 0 0xFFFFFFFF TRANSFERSIZE Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller. [11:0] SBSIZE Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 [14:12] DBSIZE Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 [17:15] SWIDTH Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved [20:18] DWIDTH Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved [23:21] RESERVED Reserved, and must be written as 0. [25:24] SI Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. [26:26] DI Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. [27:27] PROT1 This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode. [28:28] PROT2 This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable. [29:29] PROT3 This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable. [30:30] I Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. [31:31] 8 0x20 0-7 CONFIG%s DMA Channel 0 Configuration Register[1] 0x110 read-write 0 0xFFFFFFFF E Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. [0:0] SRCPERIPHERAL Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification. [5:1] DESTPERIPHERAL Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification. [10:6] TRANSFERTYPE This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field. [13:11] IE Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. [14:14] ITC Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. [15:15] L Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x. [16:16] A Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. [17:17] H Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. [18:18] RESERVED Reserved. Read value is undefined, only zero should be written. [31:19] ETHERNET Ethernet ETHERNET 0x20084000 0x0 0xFFF registers ETHERNET 28 MAC1 MAC configuration register 1. 0x000 read-write 0x8000 0xFFFFFFFF RXENABLE RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. [0:0] PARF PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. [1:1] RXFLOWCTRL RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. [2:2] TXFLOWCTRL TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. [3:3] LOOPBACK Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation. [4:4] RESERVED Unused [7:5] RESETTX Setting this bit will put the Transmit Function logic in reset. [8:8] RESETMCSTX Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. [9:9] RESETRX Setting this bit will put the Ethernet receive logic in reset. [10:10] RESETMCSRX Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [13:12] SIMRESET SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function. [14:14] SOFTRESET SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] MAC2 MAC configuration register 2. 0x004 read-write 0 0xFFFFFFFF FULLDUPLEX When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. [0:0] FLC FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. [1:1] HFEN HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received. [2:2] DELAYEDCRC DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. [3:3] CRCEN CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. [4:4] PADCRCEN PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function. [5:5] VLANPADEN VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. [6:6] AUTODETPADEN AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. [7:7] PPENF PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. [8:8] LPENF LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. [9:9] RESERVED Reserved. Read value is undefined, only zero should be written. [11:10] NOBACKOFF When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. [12:12] BP_NOBACKOFF BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. [13:13] EXCESSDEFER When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. [14:14] RESERVED Reserved. Read value is undefined, only zero should be written. [31:15] IPGT Back-to-Back Inter-Packet-Gap register. 0x008 read-write 0 0xFFFFFFFF BTOBINTEGAP BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). [6:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] IPGR Non Back-to-Back Inter-Packet-Gap register. 0x00C read-write 0 0xFFFFFFFF NBTOBINTEGAP2 NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). [6:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] NBTOBINTEGAP1 NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) [14:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:15] CLRT Collision window / Retry register. 0x010 read-write 0x370F 0xFFFFFFFF RETRANSMAX RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. [3:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:4] COLLWIN COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. [13:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:14] MAXF Maximum Frame register. 0x014 read-write 0x0600 0xFFFFFFFF MAXFLEN MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. [15:0] RESERVED Unused [31:16] SUPP PHY Support register. 0x018 read-write 0 0xFFFFFFFF RESERVED Unused [7:0] SPEED This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. [8:8] RESERVED Unused [31:9] TEST Test register. 0x01C read-write 0 0xFFFFFFFF SCPQ SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. [0:0] TESTPAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. [1:1] TESTBP TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. [2:2] RESERVED Unused [31:3] MCFG MII Mgmt Configuration register. 0x020 read-write 0 0xFFFFFFFF SCANINC SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. [0:0] SUPPPREAMBLE SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. [1:1] CLOCKSEL CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field. [5:2] RESERVED Unused [14:6] RESETMIIMGMT RESET MII MGMT. This bit resets the MII Management hardware. [15:15] RESERVED Unused [31:16] MCMD MII Mgmt Command register. 0x024 read-write 0 0xFFFFFFFF READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). [0:0] SCAN This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. [1:1] RESERVED Unused [31:2] MADR MII Mgmt Address register. 0x028 read-write 0 0xFFFFFFFF REGADDR REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. [4:0] RESERVED Unused [7:5] PHYADDR PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). [12:8] RESERVED Unused [31:13] MWTD MII Mgmt Write Data register. 0x02C write-only 0 0xFFFFFFFF WRITEDATA WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). [15:0] RESERVED Unused [31:16] MRDD MII Mgmt Read Data register. 0x030 read-only 0 0xFFFFFFFF READDATA READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. [15:0] RESERVED Unused [31:16] MIND MII Mgmt Indicators register. 0x034 read-only 0 0xFFFFFFFF BUSY When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle. [0:0] SCANNING When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. [1:1] NOTVALID When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. [2:2] MIILINKFAIL When 1 is returned - indicates that an MII Mgmt link fail has occurred. [3:3] RESERVED Unused [31:4] SA0 Station Address 0 register. 0x040 read-write 0 0xFFFFFFFF SADDR2 STATION ADDRESS, 2nd octet. This field holds the second octet of the station address. [7:0] SADDR1 STATION ADDRESS, 1st octet. This field holds the first octet of the station address. [15:8] RESERVED Unused [31:16] SA1 Station Address 1 register. 0x044 read-write 0 0xFFFFFFFF SADDR4 STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address. [7:0] SADDR3 STATION ADDRESS, 3rd octet. This field holds the third octet of the station address. [15:8] RESERVED Unused [31:16] SA2 Station Address 2 register. 0x048 read-write 0 0xFFFFFFFF SADDR6 STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address. [7:0] SADDR5 STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address. [15:8] RESERVED Unused [31:16] COMMAND Command register. 0x100 read-write 0 0xFFFFFFFF RXENABLE Enable receive. [0:0] TXENABLE Enable transmit. [1:1] RESERVED Unused [2:2] REGRESET When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. [3:3] TXRESET When a 1 is written, the transmit datapath is reset. [4:4] RXRESET When a 1 is written, the receive datapath is reset. [5:5] PASSRUNTFRAME When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out. [6:6] PASSRXFILTER When set to 1 , disables receive filtering i.e. all frames received are written to memory. [7:7] TXFLOWCONTROL Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. [8:8] RMII When set to 1 , RMII mode is selected; if 0, MII mode is selected. [9:9] FULLDUPLEX When set to 1 , indicates full duplex operation. [10:10] RESERVED Unused [31:11] STATUS Status register. 0x104 read-only 0 0xFFFFFFFF RXSTATUS If 1, the receive channel is active. If 0, the receive channel is inactive. [0:0] TXSTATUS If 1, the transmit channel is active. If 0, the transmit channel is inactive. [1:1] RESERVED Unused [31:2] RXDESCRIPTOR Receive descriptor base address register. 0x108 read-write 0 0xFFFFFFFF RESERVED Fixed to 00 [1:0] RXDESCRIPTOR MSBs of receive descriptor base address. [31:2] RXSTATUS Receive status base address register. 0x10C read-write 0 0xFFFFFFFF RESERVED Fixed to 000 [2:0] RXSTATUS MSBs of receive status base address. [31:3] RXDESCRIPTORNUMBER Receive number of descriptors register. 0x110 read-write 0 0xFFFFFFFF RXDESCRIPTORN RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. [15:0] RESERVED Unused [31:16] RXPRODUCEINDEX Receive produce index register. 0x114 read-only 0 0xFFFFFFFF RXPRODUCEIX Index of the descriptor that is going to be filled next by the receive datapath. [15:0] RESERVED Unused [31:16] RXCONSUMEINDEX Receive consume index register. 0x118 read-write 0 0xFFFFFFFF RXCONSUMEIX Index of the descriptor that is going to be processed next by the receive [15:0] RESERVED Unused [31:16] TXDESCRIPTOR Transmit descriptor base address register. 0x11C read-write 0 0xFFFFFFFF RESERVED Fixed to 00 [1:0] TXD TxDescriptor. MSBs of transmit descriptor base address. [31:2] TXSTATUS Transmit status base address register. 0x120 read-write 0 0xFFFFFFFF RESERVED Fixed to 00 [1:0] TXSTAT TxStatus. MSBs of transmit status base address. [31:2] TXDESCRIPTORNUMBER Transmit number of descriptors register. 0x124 read-write 0 0xFFFFFFFF TXDN TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. [15:0] RESERVED Unused [31:16] TXPRODUCEINDEX Transmit produce index register. 0x128 read-write 0 0xFFFFFFFF TXPI TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver. [15:0] RESERVED Unused [31:16] TXCONSUMEINDEX Transmit consume index register. 0x12C read-only 0 0xFFFFFFFF TXCI TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath. [15:0] RESERVED Unused [31:16] TSV0 Transmit status vector 0 register. 0x158 read-only 0 0xFFFFFFFF CRCERR CRC error. The attached CRC in the packet did not match the internally generated CRC. [0:0] LCE Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. [1:1] LOR Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. [2:2] DONE Transmission of packet was completed. [3:3] MULTICAST Packet's destination was a multicast address. [4:4] BROADCAST Packet's destination was a broadcast address. [5:5] PACKETDEFER Packet was deferred for at least one attempt, but less than an excessive defer. [6:6] EXDF Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. [7:7] EXCOL Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions. [8:8] LCOL Late Collision. Collision occurred beyond collision window, 512 bit times. [9:9] GIANT Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. [10:10] UNDERRUN Host side caused buffer underrun. [11:11] TOTALBYTES The total number of bytes transferred including collided attempts. [27:12] CONTROLFRAME The frame was a control frame. [28:28] PAUSE The frame was a control frame with a valid PAUSE opcode. [29:29] BACKPRESSURE Carrier-sense method backpressure was previously applied. [30:30] VLAN Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. [31:31] TSV1 Transmit status vector 1 register. 0x15C read-only 0 0xFFFFFFFF TBC Transmit byte count. The total number of bytes in the frame, not counting the collided bytes. [15:0] TCC Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented. [19:16] RESERVED Unused [31:20] RSV Receive status vector register. 0x160 read-only 0 0xFFFFFFFF RBC Received byte count. Indicates length of received frame. [15:0] PPI Packet previously ignored. Indicates that a packet was dropped. [16:16] RXDVSEEN RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet. [17:17] CESEEN Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected. [18:18] RCV Receive code violation. Indicates that received PHY data does not represent a valid receive code. [19:19] CRCERR CRC error. The attached CRC in the packet did not match the internally generated CRC. [20:20] LCERR Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field. [21:21] LOR Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. [22:22] ROK Receive OK. The packet had valid CRC and no symbol errors. [23:23] MULTICAST The packet destination was a multicast address. [24:24] BROADCAST The packet destination was a broadcast address. [25:25] DRIBBLENIBBLE Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out. [26:26] CONTROLFRAME The frame was a control frame. [27:27] PAUSE The frame was a control frame with a valid PAUSE opcode. [28:28] UO Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode. [29:29] VLAN Frame's length/type field contained 0x8100 which is the VLAN protocol identifier. [30:30] RESERVED Unused [31:31] FLOWCONTROLCOUNTER Flow control counter register. 0x170 read-write 0 0xFFFFFFFF MC MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame. [15:0] PT PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. [31:16] FLOWCONTROLSTATUS Flow control status register. 0x174 read-only 0 0xFFFFFFFF MCC MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. [15:0] RESERVED Unused [31:16] RXFILTERCTRL Receive filter control register. 0x200 read-write 0 0xFFFFFFFF AUE AcceptUnicastEn. When set to 1, all unicast frames are accepted. [0:0] ABE AcceptBroadcastEn. When set to 1, all broadcast frames are accepted. [1:1] AME AcceptMulticastEn. When set to 1, all multicast frames are accepted. [2:2] AUHE AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted. [3:3] AMHE AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted. [4:4] APE AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [11:6] MPEW MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match. [12:12] RFEW RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. [13:13] RESERVED Unused [31:14] RXFILTERWOLSTATUS Receive filter WoL status register. 0x204 read-only 0 0xFFFFFFFF AUW AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL. [0:0] ABW AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL. [1:1] AMW AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL. [2:2] AUHW AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL. [3:3] AMHW AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL. [4:4] APW AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL. [5:5] RESERVED Unused [6:6] RFW RxFilterWoL. When the value is 1, the receive filter caused WoL. [7:7] MPW MagicPacketWoL. When the value is 1, the magic packet filter caused WoL. [8:8] RESERVED Unused [31:9] RXFILTERWOLCLEAR Receive filter WoL clear register. 0x208 write-only 0 0xFFFFFFFF AUWCLR AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [0:0] ABWCLR AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [1:1] AMWCLR AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [2:2] AUHWCLR AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [3:3] AMHWCLR AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [4:4] APWCLR AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [5:5] RESERVED Unused [6:6] RFWCLR RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [7:7] MPWCLR MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared. [8:8] RESERVED Unused [31:9] HASHFILTERL Hash filter table LSBs register. 0x210 read-write 0 0xFFFFFFFF HFL HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering. [31:0] HASHFILTERH Hash filter table MSBs register. 0x214 read-write 0 0xFFFFFFFF HFH Bits 63:32 of the imperfect filter hash table for receive filtering. [31:0] INTSTATUS Interrupt status register. 0xFE0 read-only 0 0xFFFFFFFF RXOVERRUNINT Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. [0:0] RXERRORINT Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun. [1:1] RXFINISHEDINT Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. [2:2] RXDONEINT Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. [3:3] TXUNDERRUNINT Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. [4:4] TXERRORINT Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. [5:5] TXFINISHEDINT Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. [6:6] TXDONEINT Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. [7:7] RESERVED Unused [11:8] SOFTINT Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register. [12:12] WAKEUPINT Interrupt triggered by a Wake-up event detected by the receive filter. [13:13] RESERVED Unused [31:14] INTENABLE Interrupt enable register. 0xFE4 read-write 0 0xFFFFFFFF RXOVERRUNINTEN Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. [0:0] RXERRORINTEN Enable for interrupt trigger on receive errors. [1:1] RXFINISHEDINTEN Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. [2:2] RXDONEINTEN Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set. [3:3] TXUNDERRUNINTEN Enable for interrupt trigger on transmit buffer or descriptor underrun situations. [4:4] TXERRORINTEN Enable for interrupt trigger on transmit errors. [5:5] TXFINISHEDINTEN Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. [6:6] TXDONEINTEN Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. [7:7] RESERVED Unused [11:8] SOFTINTEN Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. [12:12] WAKEUPINTEN Enable for interrupt triggered by a Wake-up event detected by the receive filter. [13:13] RESERVED Unused [31:14] INTCLEAR Interrupt clear register. 0xFE8 write-only 0 0xFFFFFFFF RXOVERRUNINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [0:0] RXERRORINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [1:1] RXFINISHEDINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [2:2] RXDONEINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [3:3] TXUNDERRUNINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [4:4] TXERRORINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [5:5] TXFINISHEDINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [6:6] TXDONEINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [7:7] RESERVED Unused [11:8] SOFTINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [12:12] WAKEUPINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus. [13:13] RESERVED Unused [31:14] INTSET Interrupt set register. 0xFEC write-only 0 0xFFFFFFFF RXOVERRUNINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [0:0] RXERRORINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [1:1] RXFINISHEDINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [2:2] RXDONEINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [3:3] TXUNDERRUNINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [4:4] TXERRORINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [5:5] TXFINISHEDINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [6:6] TXDONEINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [7:7] RESERVED Unused [11:8] SOFTINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [12:12] WAKEUPINTSET Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus. [13:13] RESERVED Unused [31:14] POWERDOWN Power-down register. 0xFF4 read-write 0 0xFFFFFFFF RESERVED Unused [30:0] PD PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. [31:31] LCD LCD controller Modification LCD 0x20088000 0x0 0xFFF registers LCD 37 TIMH Horizontal Timing Control register 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] PPL Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19. [7:2] HSW Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1. [15:8] HFP Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1. [23:16] HBP Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1. [31:24] TIMV Vertical Timing Control register 0x004 read-write 0 0xFFFFFFFF LPP Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels. [9:0] VSW Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs. [15:10] VFP Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast. [23:16] VBP Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast. [31:24] POL Clock and Signal Polarity Control register 0x008 read-write 0 0xFFFFFFFF PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16). [4:0] CLKSEL Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD). [5:5] ACB AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal. [10:6] IVS Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH. [11:11] IHS Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH. [12:12] IPC Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK. [13:13] IOE Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode. [14:14] RESERVED Reserved. Read value is undefined, only zero should be written. [15:15] CPL Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly. [25:16] BCD Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays. [26:26] PCD_HI Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register. [31:27] LE Line End Control register 0x00C read-write 0 0xFFFFFFFF LED Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1. [6:0] RESERVED Reserved. Read value is undefined, only zero should be written. [15:7] LEE LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] UPBASE Upper Panel Frame Base Address register 0x010 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [2:0] LCDUPBASE LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned. [31:3] LPBASE Lower Panel Frame Base Address register 0x014 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [2:0] LCDLPBASE LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned. [31:3] CTRL LCD Control register 0x018 read-write 0 0xFFFFFFFF LCDEN LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing. [0:0] LCDBPP LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode. [3:1] LCDBW STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode. [4:4] LCDTFT LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler. [5:5] LCDMONO8 Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface. [6:6] LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel. [7:7] BGR Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped. [8:8] BEBO Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order. [9:9] BEPO Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format. [10:10] LCDPWR LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing. [11:11] LCDVCOMP LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch. [13:12] RESERVED Reserved. Read value is undefined, only zero should be written. [15:14] WATERMARK LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] INTMSK Interrupt Mask register 0x01C read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] FUFIM FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows. [1:1] LNBUIM LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers. [2:2] VCOMPIM Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached. [3:3] BERIM AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] INTRAW Raw Interrupt Status register 0x020 read-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] FUFRIS FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set. [1:1] LNBURIS LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set. [2:2] VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set. [3:3] BERRAW AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] INTSTAT Masked Interrupt Status register 0x024 read-only 0 0xFFFFFFFF RESERVED Reserved. The value read from a reserved bit is not defined. [0:0] FUFMIS FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set. [1:1] LNBUMIS LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set. [2:2] VCOMPMIS Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set. [3:3] BERMIS AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] INTCLR Interrupt Clear register 0x028 write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] FUFIC FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt. [1:1] LNBUIC LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt. [2:2] VCOMPIC Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt. [3:3] BERIC AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] UPCURR Upper Panel Current Address Value register 0x02C read-only 0 0xFFFFFFFF LCDUPCURR LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address. [31:0] LPCURR Lower Panel Current Address Value register 0x030 read-only 0 0xFFFFFFFF LCDLPCURR LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address. [31:0] 128 0x4 0-127 PAL[%s] PAL[%s] 256x16-bit Color Palette registers 0x200 read-write 0 0xFFFFFFFF R04_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. [4:0] G04_0 Green palette data. [9:5] B04_0 Blue palette data. [14:10] I0 Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. [15:15] R14_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. [20:16] G14_0 Green palette data. [25:21] B14_0 Blue palette data. [30:26] I1 Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. [31:31] 256 0x4 0-255 CRSR_IMG[%s] CRSR_IMG[%s] Cursor Image registers 0x800 read-write 0 0xFFFFFFFF CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors. [31:0] CRSR_CTRL Cursor Control register 0xC00 read-write 0 0xFFFFFFFF CRSRON Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [3:1] CRSRNUM1_0 Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3. [5:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] CRSR_CFG Cursor Configuration register 0xC04 read-write 0 0xFFFFFFFF CRSRSIZE Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor. [0:0] FRAMESYNC Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse. [1:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] CRSR_PAL0 Cursor Palette register 0 0xC08 read-write 0 0xFFFFFFFF RED Red color component [7:0] GREEN Green color component [15:8] BLUE Blue color component. [23:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] CRSR_PAL1 Cursor Palette register 1 0xC0C read-write 0 0xFFFFFFFF RED Red color component [7:0] GREEN Green color component [15:8] BLUE Blue color component. [23:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] CRSR_XY Cursor XY Position register 0xC10 read-write 0 0xFFFFFFFF CRSRX X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [15:10] CRSRY Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display. [25:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] CRSR_CLIP Cursor Clip Position register 0xC14 read-write 0 0xFFFFFFFF CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed. [5:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:6] CRSRCLIPY Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image. [13:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:14] CRSR_INTMSK Cursor Interrupt Mask register 0xC20 read-write 0x0 0xFFFFFFFF CRSRIM Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] CRSR_INTCLR Cursor Interrupt Clear register 0xC24 write-only 0 0xFFFFFFFF CRSRIC Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] CRSR_INTRAW Cursor Raw Interrupt Status register 0xC28 read-only 0 0xFFFFFFFF CRSRRIS Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] CRSR_INTSTAT Cursor Masked Interrupt Status register 0xC2C read-only 0 0xFFFFFFFF CRSRMIS Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] USB USB device controller USB 0x2008C000 0x0 0xFFF registers USB 24 USB_NEED_CLK 33 INTST OTG Interrupt Status 0x100 read-only 0 0xFFFFFFFF TMR Timer time-out. [0:0] REMOVE_PU Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor. [1:1] HNP_FAILURE HNP failed. This bit is set by hardware to indicate that the HNP switching has failed. [2:2] HNP_SUCCESS HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] INTEN OTG Interrupt Enable 0x104 read-write 0 0xFFFFFFFF TMR_EN 1 = enable the corresponding bit in the IntSt register. [0:0] REMOVE_PU_EN 1 = enable the corresponding bit in the IntSt register. [1:1] HNP_FAILURE_EN 1 = enable the corresponding bit in the IntSt register. [2:2] HNP_SUCCES_EN 1 = enable the corresponding bit in the IntSt register. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] INTSET OTG Interrupt Set 0x108 write-only 0 0x00000000 TMR_SET 0 = no effect. 1 = set the corresponding bit in the IntSt register. [0:0] REMOVE_PU_SET 0 = no effect. 1 = set the corresponding bit in the IntSt register. [1:1] HNP_FAILURE_SET 0 = no effect. 1 = set the corresponding bit in the IntSt register. [2:2] HNP_SUCCES_SET 0 = no effect. 1 = set the corresponding bit in the IntSt register. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] INCLR OTG Interrupt Clear 0x10C write-only 0 0x00000000 TMR_CLR 0 = no effect. 1 = clear the corresponding bit in the IntSt register. [0:0] REMOVE_PU_CLR 0 = no effect. 1 = clear the corresponding bit in the IntSt register. [1:1] HNP_FAILURE_CLR 0 = no effect. 1 = clear the corresponding bit in the IntSt register. [2:2] HNP_SUCCES_CLR 0 = no effect. 1 = clear the corresponding bit in the IntSt register. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] PORTSEL USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2. 0x110 read-write 0 0xFFFFFFFF PORTSEL Selects which USB port the device controller signals are mapped to. Other values are reserved. [1:0] ENUM PORTU1 The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 0x0 PORTU2 The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2. 0x3 TMR_SCALE Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved [3:2] TMR_MODE Timer mode selection. 0: monoshot 1: free running [4:4] TMR_EN Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0. [5:5] TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. [8:8] A_HNP_TRACK Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. [9:9] PU_REMOVED When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. [10:10] RESERVED Reserved. Read value is undefined, only zero should be written. [15:11] TMR_CNT Current timer count value. [31:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] TMR OTG Timer 0x114 read-write 0xFFFF 0xFFFFFFFF TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] DEVINTST USB Device Interrupt Status 0x200 read-only 0x10 0xFFFFFFFF FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. [0:0] EP_FAST Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit. [1:1] EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. [2:2] DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366. [3:3] CCEMPTY The command code register (USBCmdCode) is empty (New command can be written). [4:4] CDFULL Command data register (USBCmdData) is full (Data can be read now). [5:5] RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. [6:6] TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). [7:7] EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed. [8:8] ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368 [9:9] RESERVED Reserved. The value read from a reserved bit is not defined. [31:10] DEVINTEN USB Device Interrupt Enable 0x204 read-write 0 0xFFFFFFFF FRAMEEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [0:0] EP_FASTEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [1:1] EP_SLOWEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [2:2] DEV_STATEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [3:3] CCEMPTYEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [4:4] CDFULLEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [5:5] RxENDPKTEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [6:6] TxENDPKTEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [7:7] EP_RLZEDEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [8:8] ERR_INTEN 0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. [9:9] RESERVED Reserved [31:10] DEVINTCLR USB Device Interrupt Clear 0x208 write-only 0 0xFFFFFFFF FRAMECLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [0:0] EP_FASTCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [1:1] EP_SLOWCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [2:2] DEV_STATCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [3:3] CCEMPTYCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [4:4] CDFULLCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [5:5] RxENDPKTCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [6:6] TxENDPKTCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [7:7] EP_RLZEDCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [8:8] ERR_INTCLR 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared. [9:9] RESERVED Reserved [31:10] DEVINTSET USB Device Interrupt Set 0x20C write-only 0 0xFFFFFFFF FRAMESET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [0:0] EP_FASTSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [1:1] EP_SLOWSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [2:2] DEV_STATSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [3:3] CCEMPTYSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [4:4] CDFULLSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [5:5] RxENDPKTSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [6:6] TxENDPKTSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [7:7] EP_RLZEDSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [8:8] ERR_INTSET 0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set. [9:9] RESERVED Reserved [31:10] DEVINTPRI USB Device Interrupt Priority 0x22C write-only 0 0xFFFFFFFF FRAME Frame interrupt routing [0:0] ENUM LP FRAME interrupt is routed to USB_INT_REQ_LP. 0 HP FRAME interrupt is routed to USB_INT_REQ_HP. 1 EP_FAST Fast endpoint interrupt routing [1:1] ENUM LP EP_FAST interrupt is routed to USB_INT_REQ_LP. 0 HP EP_FAST interrupt is routed to USB_INT_REQ_HP. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] EPINTST USB Endpoint Interrupt Status 0x230 read-only 0 0xFFFFFFFF EPST0 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [0:0] EPST1 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [1:1] EPST2 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [2:2] EPST3 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [3:3] EPST4 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [4:4] EPST5 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [5:5] EPST6 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [6:6] EPST7 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [7:7] EPST8 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [8:8] EPST9 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [9:9] EPST10 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [10:10] EPST11 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [11:11] EPST12 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [12:12] EPST13 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [13:13] EPST14 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [14:14] EPST15 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [15:15] EPST16 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [16:16] EPST17 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [17:17] EPST18 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [18:18] EPST19 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [19:19] EPST20 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [20:20] EPST21 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [21:21] EPST22 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [22:22] EPST23 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [23:23] EPST24 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [24:24] EPST25 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [25:25] EPST26 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [26:26] EPST27 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [27:27] EPST28 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [28:28] EPST29 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [29:29] EPST30 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [30:30] EPST31 1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received. [31:31] EPINTEN USB Endpoint Interrupt Enable 0x234 read-write 0 0xFFFFFFFF EPEN0 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [0:0] EPEN1 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [1:1] EPEN2 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [2:2] EPEN3 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [3:3] EPEN4 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [4:4] EPEN5 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [5:5] EPEN6 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [6:6] EPEN7 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [7:7] EPEN8 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [8:8] EPEN9 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [9:9] EPEN10 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [10:10] EPEN11 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [11:11] EPEN12 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [12:12] EPEN13 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [13:13] EPEN14 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [14:14] EPEN15 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [15:15] EPEN16 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [16:16] EPEN17 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [17:17] EPEN18 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [18:18] EPEN19 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [19:19] EPEN20 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [20:20] EPEN21 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [21:21] EPEN22 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [22:22] EPEN23 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [23:23] EPEN24 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [24:24] EPEN25 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [25:25] EPEN26 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [26:26] EPEN27 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [27:27] EPEN28 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [28:28] EPEN29 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [29:29] EPEN30 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [30:30] EPEN31 0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. [31:31] EPINTCLR USB Endpoint Interrupt Clear 0x238 write-only 0 0xFFFFFFFF EPCLR0 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [0:0] EPCLR1 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [1:1] EPCLR2 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [2:2] EPCLR3 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [3:3] EPCLR4 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [4:4] EPCLR5 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [5:5] EPCLR6 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [6:6] EPCLR7 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [7:7] EPCLR8 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [8:8] EPCLR9 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [9:9] EPCLR10 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [10:10] EPCLR11 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [11:11] EPCLR12 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [12:12] EPCLR13 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [13:13] EPCLR14 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [14:14] EPCLR15 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [15:15] EPCLR16 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [16:16] EPCLR17 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [17:17] EPCLR18 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [18:18] EPCLR19 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [19:19] EPCLR20 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [20:20] EPCLR21 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [21:21] EPCLR22 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [22:22] EPCLR23 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [23:23] EPCLR24 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [24:24] EPCLR25 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [25:25] EPCLR26 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [26:26] EPCLR27 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [27:27] EPCLR28 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [28:28] EPCLR29 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [29:29] EPCLR30 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [30:30] EPCLR31 0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. [31:31] EPINTSET USB Endpoint Interrupt Set 0x23C write-only 0 0xFFFFFFFF EPSET0 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [0:0] EPSET1 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [1:1] EPSET2 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [2:2] EPSET3 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [3:3] EPSET4 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [4:4] EPSET5 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [5:5] EPSET6 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [6:6] EPSET7 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [7:7] EPSET8 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [8:8] EPSET9 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [9:9] EPSET10 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [10:10] EPSET11 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [11:11] EPSET12 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [12:12] EPSET13 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [13:13] EPSET14 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [14:14] EPSET15 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [15:15] EPSET16 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [16:16] EPSET17 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [17:17] EPSET18 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [18:18] EPSET19 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [19:19] EPSET20 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [20:20] EPSET21 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [21:21] EPSET22 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [22:22] EPSET23 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [23:23] EPSET24 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [24:24] EPSET25 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [25:25] EPSET26 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [26:26] EPSET27 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [27:27] EPSET28 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [28:28] EPSET29 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [29:29] EPSET30 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [30:30] EPSET31 0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt. [31:31] EPINTPRI USB Endpoint Priority 0x240 write-only 0 0xFFFFFFFF EPPRI0 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [0:0] EPPRI1 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [1:1] EPPRI2 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [2:2] EPPRI3 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [3:3] EPPRI4 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [4:4] EPPRI5 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [5:5] EPPRI6 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [6:6] EPPRI7 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [7:7] EPPRI8 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [8:8] EPPRI9 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [9:9] EPPRI10 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [10:10] EPPRI11 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [11:11] EPPRI12 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [12:12] EPPRI13 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [13:13] EPPRI14 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [14:14] EPPRI15 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [15:15] EPPRI16 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [16:16] EPPRI17 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [17:17] EPPRI18 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [18:18] EPPRI19 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [19:19] EPPRI20 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [20:20] EPPRI21 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [21:21] EPPRI22 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [22:22] EPPRI23 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [23:23] EPPRI24 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [24:24] EPPRI25 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [25:25] EPPRI26 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [26:26] EPPRI27 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [27:27] EPPRI28 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [28:28] EPPRI29 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [29:29] EPPRI30 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [30:30] EPPRI31 0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt [31:31] REEP USB Realize Endpoint 0x244 read-write 0x3 0xFFFFFFFF EPR0 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [0:0] EPR1 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [1:1] EPR2 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [2:2] EPR3 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [3:3] EPR4 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [4:4] EPR5 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [5:5] EPR6 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [6:6] EPR7 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [7:7] EPR8 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [8:8] EPR9 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [9:9] EPR10 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [10:10] EPR11 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [11:11] EPR12 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [12:12] EPR13 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [13:13] EPR14 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [14:14] EPR15 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [15:15] EPR16 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [16:16] EPR17 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [17:17] EPR18 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [18:18] EPR19 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [19:19] EPR20 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [20:20] EPR21 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [21:21] EPR22 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [22:22] EPR23 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [23:23] EPR24 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [24:24] EPR25 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [25:25] EPR26 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [26:26] EPR27 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [27:27] EPR28 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [28:28] EPR29 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [29:29] EPR30 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [30:30] EPR31 0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized. [31:31] EPIN USB Endpoint Index 0x248 write-only 0 0xFFFFFFFF PHY_EP Physical endpoint number (0-31) [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] MAXPSIZE USB MaxPacketSize 0x24C read-write 0x8 0xFFFFFFFF MPS The maximum packet size value. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] RXDATA USB Receive Data 0x218 read-only 0 0xFFFFFFFF RX_DATA Data received. [31:0] RXPLEN USB Receive Packet Length 220 read-only 0 0xFFFFFFFF PKT_LNGTH The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. [9:0] DV Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. [10:10] ENUM DATA_IS_INVALID_ Data is invalid. 0 DATA_IS_VALID_ Data is valid. 1 PKT_RDY The PKT_LNGTH field is valid and the packet is ready for reading. [11:11] RESERVED Reserved. The value read from a reserved bit is not defined. [31:12] TXDATA USB Transmit Data 0x21C write-only 0 0xFFFFFFFF TX_DATA Transmit Data. [31:0] TXPLEN USB Transmit Packet Length 0x224 write-only 0 0xFFFFFFFF PKT_LNGTH The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] CTRL USB Control 0x228 read-write 0 0xFFFFFFFF RD_EN Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. [0:0] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 WR_EN Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. [1:1] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 LOG_ENDPOINT Logical Endpoint number. [5:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] CMDCODE USB Command Code 0x210 write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [7:0] CMD_PHASE The command phase: [15:8] ENUM READ Read 0x02 WRITE Write 0x01 COMMAND Command 0x05 CMD_CODE_WDATA This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). [23:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] CMDDATA USB Command Data 0x214 read-only 0 0xFFFFFFFF CMD_RDATA Command Read Data. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DMARST USB DMA Request Status 0x250 read-only 0 0xFFFFFFFF EPRST0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). [0:0] EPRST1 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). [1:1] EPRST2 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [2:2] EPRST3 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [3:3] EPRST4 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [4:4] EPRST5 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [5:5] EPRST6 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [6:6] EPRST7 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [7:7] EPRST8 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [8:8] EPRST9 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [9:9] EPRST10 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [10:10] EPRST11 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [11:11] EPRST12 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [12:12] EPRST13 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [13:13] EPRST14 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [14:14] EPRST15 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [15:15] EPRST16 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [16:16] EPRST17 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [17:17] EPRST18 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [18:18] EPRST19 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [19:19] EPRST20 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [20:20] EPRST21 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [21:21] EPRST22 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [22:22] EPRST23 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [23:23] EPRST24 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [24:24] EPRST25 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [25:25] EPRST26 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [26:26] EPRST27 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [27:27] EPRST28 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [28:28] EPRST29 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [29:29] EPRST30 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [30:30] EPRST31 Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx. [31:31] DMARCLR USB DMA Request Clear 0x254 write-only 0 0xFFFFFFFF EPRCLR0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). [0:0] EPRCLR1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). [1:1] EPRCLR2 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [2:2] EPRCLR3 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [3:3] EPRCLR4 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [4:4] EPRCLR5 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [5:5] EPRCLR6 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [6:6] EPRCLR7 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [7:7] EPRCLR8 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [8:8] EPRCLR9 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [9:9] EPRCLR10 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [10:10] EPRCLR11 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [11:11] EPRCLR12 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [12:12] EPRCLR13 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [13:13] EPRCLR14 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [14:14] EPRCLR15 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [15:15] EPRCLR16 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [16:16] EPRCLR17 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [17:17] EPRCLR18 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [18:18] EPRCLR19 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [19:19] EPRCLR20 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [20:20] EPRCLR21 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [21:21] EPRCLR22 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [22:22] EPRCLR23 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [23:23] EPRCLR24 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [24:24] EPRCLR25 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [25:25] EPRCLR26 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [26:26] EPRCLR27 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [27:27] EPRCLR28 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [28:28] EPRCLR29 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [29:29] EPRCLR30 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [30:30] EPRCLR31 Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt. [31:31] DMARSET USB DMA Request Set 0x258 write-only 0 0xFFFFFFFF EPRSET0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0). [0:0] EPRSET1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0). [1:1] EPRSET2 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [2:2] EPRSET3 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [3:3] EPRSET4 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [4:4] EPRSET5 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [5:5] EPRSET6 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [6:6] EPRSET7 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [7:7] EPRSET8 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [8:8] EPRSET9 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [9:9] EPRSET10 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [10:10] EPRSET11 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [11:11] EPRSET12 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [12:12] EPRSET13 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [13:13] EPRSET14 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [14:14] EPRSET15 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [15:15] EPRSET16 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [16:16] EPRSET17 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [17:17] EPRSET18 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [18:18] EPRSET19 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [19:19] EPRSET20 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [20:20] EPRSET21 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [21:21] EPRSET22 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [22:22] EPRSET23 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [23:23] EPRSET24 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [24:24] EPRSET25 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [25:25] EPRSET26 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [26:26] EPRSET27 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [27:27] EPRSET28 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [28:28] EPRSET29 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [29:29] EPRSET30 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [30:30] EPRSET31 Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt. [31:31] UDCAH USB UDCA Head 0x280 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries. [6:0] UDCA_ADDR Start address of the UDCA. [31:7] EPDMAST USB Endpoint DMA Status 0x284 read-only 0 0xFFFFFFFF EP_DMA_ST0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0). [0:0] EP_DMA_ST1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). [1:1] EP_DMA_ST2 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [2:2] EP_DMA_ST3 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [3:3] EP_DMA_ST4 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [4:4] EP_DMA_ST5 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [5:5] EP_DMA_ST6 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [6:6] EP_DMA_ST7 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [7:7] EP_DMA_ST8 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [8:8] EP_DMA_ST9 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [9:9] EP_DMA_ST10 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [10:10] EP_DMA_ST11 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [11:11] EP_DMA_ST12 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [12:12] EP_DMA_ST13 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [13:13] EP_DMA_ST14 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [14:14] EP_DMA_ST15 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [15:15] EP_DMA_ST16 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [16:16] EP_DMA_ST17 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [17:17] EP_DMA_ST18 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [18:18] EP_DMA_ST19 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [19:19] EP_DMA_ST20 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [20:20] EP_DMA_ST21 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [21:21] EP_DMA_ST22 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [22:22] EP_DMA_ST23 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [23:23] EP_DMA_ST24 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [24:24] EP_DMA_ST25 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [25:25] EP_DMA_ST26 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [26:26] EP_DMA_ST27 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [27:27] EP_DMA_ST28 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [28:28] EP_DMA_ST29 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [29:29] EP_DMA_ST30 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [30:30] EP_DMA_ST31 Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled. [31:31] EPDMAEN USB Endpoint DMA Enable 0x288 write-only 0 0xFFFFFFFF EP_DMA_EN0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0). [0:0] EP_DMA_EN1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0). [1:1] EP_DMA_EN Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx. [31:2] EPDMADIS USB Endpoint DMA Disable 0x28C write-only 0 0xFFFFFFFF EP_DMA_DIS0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0). [0:0] EP_DMA_DIS1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0). [1:1] EP_DMA_DIS2 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [2:2] EP_DMA_DIS3 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [3:3] EP_DMA_DIS4 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [4:4] EP_DMA_DIS5 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [5:5] EP_DMA_DIS6 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [6:6] EP_DMA_DIS7 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [7:7] EP_DMA_DIS8 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [8:8] EP_DMA_DIS9 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [9:9] EP_DMA_DIS10 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [10:10] EP_DMA_DIS11 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [11:11] EP_DMA_DIS12 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [12:12] EP_DMA_DIS13 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [13:13] EP_DMA_DIS14 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [14:14] EP_DMA_DIS15 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [15:15] EP_DMA_DIS16 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [16:16] EP_DMA_DIS17 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [17:17] EP_DMA_DIS18 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [18:18] EP_DMA_DIS19 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [19:19] EP_DMA_DIS20 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [20:20] EP_DMA_DIS21 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [21:21] EP_DMA_DIS22 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [22:22] EP_DMA_DIS23 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [23:23] EP_DMA_DIS24 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [24:24] EP_DMA_DIS25 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [25:25] EP_DMA_DIS26 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [26:26] EP_DMA_DIS27 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [27:27] EP_DMA_DIS28 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [28:28] EP_DMA_DIS29 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [29:29] EP_DMA_DIS30 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [30:30] EP_DMA_DIS31 Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx. [31:31] DMAINTST USB DMA Interrupt Status 0x290 read-only 0 0xFFFFFFFF EOT End of Transfer Interrupt bit. [0:0] ENUM ALL_BITS_IN_THE_USBE All bits in the USBEoTIntSt register are 0. 0 AT_LEAST_ONE_BIT_IN_ At least one bit in the USBEoTIntSt is set. 1 NDDR New DD Request Interrupt bit. [1:1] ENUM ALL_BITS_IN_THE_USBN All bits in the USBNDDRIntSt register are 0. 0 AT_LEAST_ONE_BIT_IN_ At least one bit in the USBNDDRIntSt is set. 1 ERR System Error Interrupt bit. [2:2] ENUM ALL_BITS_IN_THE_USBS All bits in the USBSysErrIntSt register are 0. 0 AT_LEAST_ONE_BIT_IN_ At least one bit in the USBSysErrIntSt is set. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:3] DMAINTEN USB DMA Interrupt Enable 0x294 read-write 0 0xFFFFFFFF EOT End of Transfer Interrupt enable bit. [0:0] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 NDDR New DD Request Interrupt enable bit. [1:1] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 ERR System Error Interrupt enable bit. [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] EOTINTST USB End of Transfer Interrupt Status 0x2A0 read-only 0 0xFFFFFFFF EPTXINTST0 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [0:0] EPTXINTST1 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [1:1] EPTXINTST2 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [2:2] EPTXINTST3 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [3:3] EPTXINTST4 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [4:4] EPTXINTST5 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [5:5] EPTXINTST6 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [6:6] EPTXINTST7 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [7:7] EPTXINTST8 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [8:8] EPTXINTST9 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [9:9] EPTXINTST10 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [10:10] EPTXINTST11 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [11:11] EPTXINTST12 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [12:12] EPTXINTST13 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [13:13] EPTXINTST14 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [14:14] EPTXINTST15 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [15:15] EPTXINTST16 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [16:16] EPTXINTST17 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [17:17] EPTXINTST18 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [18:18] EPTXINTST19 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [19:19] EPTXINTST20 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [20:20] EPTXINTST21 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [21:21] EPTXINTST22 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [22:22] EPTXINTST23 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [23:23] EPTXINTST24 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [24:24] EPTXINTST25 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [25:25] EPTXINTST26 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [26:26] EPTXINTST27 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [27:27] EPTXINTST28 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [28:28] EPTXINTST29 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [29:29] EPTXINTST30 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [30:30] EPTXINTST31 Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx. [31:31] EOTINTCLR USB End of Transfer Interrupt Clear 0x2A4 write-only 0 0xFFFFFFFF EPTXINTCLR0 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [0:0] EPTXINTCLR1 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [1:1] EPTXINTCLR2 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [2:2] EPTXINTCLR3 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [3:3] EPTXINTCLR4 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [4:4] EPTXINTCLR5 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [5:5] EPTXINTCLR6 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [6:6] EPTXINTCLR7 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [7:7] EPTXINTCLR8 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [8:8] EPTXINTCLR9 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [9:9] EPTXINTCLR10 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [10:10] EPTXINTCLR11 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [11:11] EPTXINTCLR12 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [12:12] EPTXINTCLR13 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [13:13] EPTXINTCLR14 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [14:14] EPTXINTCLR15 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [15:15] EPTXINTCLR16 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [16:16] EPTXINTCLR17 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [17:17] EPTXINTCLR18 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [18:18] EPTXINTCLR19 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [19:19] EPTXINTCLR20 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [20:20] EPTXINTCLR21 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [21:21] EPTXINTCLR22 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [22:22] EPTXINTCLR23 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [23:23] EPTXINTCLR24 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [24:24] EPTXINTCLR25 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [25:25] EPTXINTCLR26 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [26:26] EPTXINTCLR27 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [27:27] EPTXINTCLR28 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [28:28] EPTXINTCLR29 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [29:29] EPTXINTCLR30 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [30:30] EPTXINTCLR31 Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [31:31] EOTINTSET USB End of Transfer Interrupt Set 0x2A8 write-only 0 0xFFFFFFFF EPTXINTSET0 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [0:0] EPTXINTSET1 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [1:1] EPTXINTSET2 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [2:2] EPTXINTSET3 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [3:3] EPTXINTSET4 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [4:4] EPTXINTSET5 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [5:5] EPTXINTSET6 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [6:6] EPTXINTSET7 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [7:7] EPTXINTSET8 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [8:8] EPTXINTSET9 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [9:9] EPTXINTSET10 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [10:10] EPTXINTSET11 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [11:11] EPTXINTSET12 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [12:12] EPTXINTSET13 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [13:13] EPTXINTSET14 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [14:14] EPTXINTSET15 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [15:15] EPTXINTSET16 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [16:16] EPTXINTSET17 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [17:17] EPTXINTSET18 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [18:18] EPTXINTSET19 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [19:19] EPTXINTSET20 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [20:20] EPTXINTSET21 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [21:21] EPTXINTSET22 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [22:22] EPTXINTSET23 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [23:23] EPTXINTSET24 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [24:24] EPTXINTSET25 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [25:25] EPTXINTSET26 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [26:26] EPTXINTSET27 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [27:27] EPTXINTSET28 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [28:28] EPTXINTSET29 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [29:29] EPTXINTSET30 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [30:30] EPTXINTSET31 Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. [31:31] NDDRINTST USB New DD Request Interrupt Status 0x2AC read-only 0 0xFFFFFFFF EPNDDINTST0 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [0:0] EPNDDINTST1 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [1:1] EPNDDINTST2 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [2:2] EPNDDINTST3 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [3:3] EPNDDINTST4 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [4:4] EPNDDINTST5 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [5:5] EPNDDINTST6 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [6:6] EPNDDINTST7 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [7:7] EPNDDINTST8 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [8:8] EPNDDINTST9 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [9:9] EPNDDINTST10 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [10:10] EPNDDINTST11 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [11:11] EPNDDINTST12 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [12:12] EPNDDINTST13 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [13:13] EPNDDINTST14 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [14:14] EPNDDINTST15 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [15:15] EPNDDINTST16 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [16:16] EPNDDINTST17 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [17:17] EPNDDINTST18 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [18:18] EPNDDINTST19 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [19:19] EPNDDINTST20 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [20:20] EPNDDINTST21 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [21:21] EPNDDINTST22 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [22:22] EPNDDINTST23 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [23:23] EPNDDINTST24 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [24:24] EPNDDINTST25 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [25:25] EPNDDINTST26 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [26:26] EPNDDINTST27 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [27:27] EPNDDINTST28 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [28:28] EPNDDINTST29 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [29:29] EPNDDINTST30 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [30:30] EPNDDINTST31 Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx. [31:31] NDDRINTCLR USB New DD Request Interrupt Clear 0x2B0 write-only 0 0xFFFFFFFF EPNDDINTCLR0 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [0:0] EPNDDINTCLR1 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [1:1] EPNDDINTCLR2 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [2:2] EPNDDINTCLR3 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [3:3] EPNDDINTCLR4 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [4:4] EPNDDINTCLR5 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [5:5] EPNDDINTCLR6 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [6:6] EPNDDINTCLR7 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [7:7] EPNDDINTCLR8 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [8:8] EPNDDINTCLR9 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [9:9] EPNDDINTCLR10 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [10:10] EPNDDINTCLR11 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [11:11] EPNDDINTCLR12 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [12:12] EPNDDINTCLR13 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [13:13] EPNDDINTCLR14 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [14:14] EPNDDINTCLR15 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [15:15] EPNDDINTCLR16 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [16:16] EPNDDINTCLR17 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [17:17] EPNDDINTCLR18 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [18:18] EPNDDINTCLR19 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [19:19] EPNDDINTCLR20 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [20:20] EPNDDINTCLR21 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [21:21] EPNDDINTCLR22 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [22:22] EPNDDINTCLR23 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [23:23] EPNDDINTCLR24 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [24:24] EPNDDINTCLR25 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [25:25] EPNDDINTCLR26 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [26:26] EPNDDINTCLR27 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [27:27] EPNDDINTCLR28 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [28:28] EPNDDINTCLR29 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [29:29] EPNDDINTCLR30 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [30:30] EPNDDINTCLR31 Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register. [31:31] NDDRINTSET USB New DD Request Interrupt Set 0x2B4 write-only 0 0xFFFFFFFF EPNDDINTSET0 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [0:0] EPNDDINTSET1 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [1:1] EPNDDINTSET2 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [2:2] EPNDDINTSET3 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [3:3] EPNDDINTSET4 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [4:4] EPNDDINTSET5 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [5:5] EPNDDINTSET6 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [6:6] EPNDDINTSET7 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [7:7] EPNDDINTSET8 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [8:8] EPNDDINTSET9 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [9:9] EPNDDINTSET10 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [10:10] EPNDDINTSET11 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [11:11] EPNDDINTSET12 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [12:12] EPNDDINTSET13 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [13:13] EPNDDINTSET14 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [14:14] EPNDDINTSET15 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [15:15] EPNDDINTSET16 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [16:16] EPNDDINTSET17 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [17:17] EPNDDINTSET18 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [18:18] EPNDDINTSET19 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [19:19] EPNDDINTSET20 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [20:20] EPNDDINTSET21 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [21:21] EPNDDINTSET22 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [22:22] EPNDDINTSET23 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [23:23] EPNDDINTSET24 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [24:24] EPNDDINTSET25 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [25:25] EPNDDINTSET26 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [26:26] EPNDDINTSET27 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [27:27] EPNDDINTSET28 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [28:28] EPNDDINTSET29 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [29:29] EPNDDINTSET30 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [30:30] EPNDDINTSET31 Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register. [31:31] SYSERRINTST USB System Error Interrupt Status 0x2B8 read-only 0 0xFFFFFFFF EPERRINTST0 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [0:0] EPERRINTST1 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [1:1] EPERRINTST2 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [2:2] EPERRINTST3 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [3:3] EPERRINTST4 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [4:4] EPERRINTST5 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [5:5] EPERRINTST6 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [6:6] EPERRINTST7 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [7:7] EPERRINTST8 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [8:8] EPERRINTST9 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [9:9] EPERRINTST10 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [10:10] EPERRINTST11 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [11:11] EPERRINTST12 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [12:12] EPERRINTST13 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [13:13] EPERRINTST14 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [14:14] EPERRINTST15 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [15:15] EPERRINTST16 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [16:16] EPERRINTST17 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [17:17] EPERRINTST18 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [18:18] EPERRINTST19 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [19:19] EPERRINTST20 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [20:20] EPERRINTST21 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [21:21] EPERRINTST22 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [22:22] EPERRINTST23 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [23:23] EPERRINTST24 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [24:24] EPERRINTST25 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [25:25] EPERRINTST26 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [26:26] EPERRINTST27 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [27:27] EPERRINTST28 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [28:28] EPERRINTST29 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [29:29] EPERRINTST30 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [30:30] EPERRINTST31 Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx. [31:31] SYSERRINTCLR USB System Error Interrupt Clear 0x2BC write-only 0 0xFFFFFFFF EPERRINTCLR0 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [0:0] EPERRINTCLR1 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [1:1] EPERRINTCLR2 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [2:2] EPERRINTCLR3 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [3:3] EPERRINTCLR4 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [4:4] EPERRINTCLR5 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [5:5] EPERRINTCLR6 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [6:6] EPERRINTCLR7 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [7:7] EPERRINTCLR8 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [8:8] EPERRINTCLR9 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [9:9] EPERRINTCLR10 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [10:10] EPERRINTCLR11 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [11:11] EPERRINTCLR12 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [12:12] EPERRINTCLR13 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [13:13] EPERRINTCLR14 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [14:14] EPERRINTCLR15 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [15:15] EPERRINTCLR16 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [16:16] EPERRINTCLR17 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [17:17] EPERRINTCLR18 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [18:18] EPERRINTCLR19 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [19:19] EPERRINTCLR20 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [20:20] EPERRINTCLR21 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [21:21] EPERRINTCLR22 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [22:22] EPERRINTCLR23 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [23:23] EPERRINTCLR24 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [24:24] EPERRINTCLR25 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [25:25] EPERRINTCLR26 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [26:26] EPERRINTCLR27 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [27:27] EPERRINTCLR28 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [28:28] EPERRINTCLR29 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [29:29] EPERRINTCLR30 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [30:30] EPERRINTCLR31 Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. [31:31] SYSERRINTSET USB System Error Interrupt Set 0x2C0 write-only 0 0xFFFFFFFF EPERRINTSET0 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [0:0] EPERRINTSET1 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [1:1] EPERRINTSET2 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [2:2] EPERRINTSET3 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [3:3] EPERRINTSET4 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [4:4] EPERRINTSET5 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [5:5] EPERRINTSET6 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [6:6] EPERRINTSET7 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [7:7] EPERRINTSET8 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [8:8] EPERRINTSET9 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [9:9] EPERRINTSET10 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [10:10] EPERRINTSET11 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [11:11] EPERRINTSET12 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [12:12] EPERRINTSET13 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [13:13] EPERRINTSET14 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [14:14] EPERRINTSET15 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [15:15] EPERRINTSET16 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [16:16] EPERRINTSET17 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [17:17] EPERRINTSET18 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [18:18] EPERRINTSET19 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [19:19] EPERRINTSET20 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [20:20] EPERRINTSET21 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [21:21] EPERRINTSET22 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [22:22] EPERRINTSET23 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [23:23] EPERRINTSET24 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [24:24] EPERRINTSET25 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [25:25] EPERRINTSET26 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [26:26] EPERRINTSET27 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [27:27] EPERRINTSET28 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [28:28] EPERRINTSET29 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [29:29] EPERRINTSET30 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [30:30] EPERRINTSET31 Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register. [31:31] I2C_RX I2C Receive 0x300 read-only 0 0x00000000 RX_DATA Receive data. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] I2C_TX I2C Transmit 0x300 write-only 0 0x00000000 TXDATA Transmit data. [7:0] START When 1, issue a START condition before transmitting this byte. [8:8] STOP When 1, issue a STOP condition after transmitting this byte. [9:9] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] I2C_STS I2C Status 0x304 read-only 0x0A00 0xFFFFFFFF TDI Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. [0:0] ENUM TRANSACTION_HAS_NOT_ Transaction has not completed. 0 TRANSACTION_COMPLETE Transaction completed. 1 AFI Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. [1:1] ENUM NO_ARBITRATION_FAILU No arbitration failure on last transmission. 0 ARBITRATION_FAILURE_ Arbitration failure occurred on last transmission. 1 NAI No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. [2:2] ENUM LAST_TRANSMISSION_RE Last transmission received an acknowledge. 0 LAST_TRANSMISSION_DI Last transmission did not receive an acknowledge. 1 DRMI Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. [3:3] ENUM MASTER_TRANSMITTER_D Master transmitter does not need data. 0 MASTER_TRANSMITTER_N Master transmitter needs data. 1 DRSI Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. [4:4] ENUM SLAVE_TRANSMITTER_DO Slave transmitter does not need data. 0 SLAVE_TRANSMITTER_NE Slave transmitter needs data. 1 Active Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.. [5:5] SCL The current value of the SCL signal. [6:6] SDA The current value of the SDA signal. [7:7] RFF Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. [8:8] ENUM RX_FIFO_IS_NOT_FULL RX FIFO is not full 0 RX_FIFO_IS_FULL RX FIFO is full 1 RFE Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. [9:9] ENUM RX_FIFO_CONTAINS_DAT RX FIFO contains data. 0 RX_FIFO_IS_EMPTY RX FIFO is empty 1 TFF Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. [10:10] ENUM TX_FIFO_IS_NOT_FULL_ TX FIFO is not full. 0 TX_FIFO_IS_FULL TX FIFO is full 1 TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. [11:11] ENUM TX_FIFO_CONTAINS_VAL TX FIFO contains valid data. 0 TX_FIFO_IS_EMPTY TX FIFO is empty 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] I2C_CTL I2C Control 0x308 read-write 0 0xFFFFFFFF TDIE Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition. [0:0] ENUM DISABLE_THE_TDI_INTE Disable the TDI interrupt. 0 ENABLE_THE_TDI_INTER Enable the TDI interrupt. 1 AFIE Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device. [1:1] ENUM DISABLE_THE_AFI_ Disable the AFI. 0 ENABLE_THE_AFI_ Enable the AFI. 1 NAIE Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged. [2:2] ENUM DISABLE_THE_NAI_ Disable the NAI. 0 ENABLE_THE_NAI_ Enable the NAI. 1 DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. [3:3] ENUM DISABLE_THE_DRMI_INT Disable the DRMI interrupt. 0 ENABLE_THE_DRMI_INTE Enable the DRMI interrupt. 1 DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low. [4:4] ENUM DISABLE_THE_DRSI_INT Disable the DRSI interrupt. 0 ENABLE_THE_DRSI_INTE Enable the DRSI interrupt. 1 REFIE Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data. [5:5] ENUM DISABLE_THE_RFFI_ Disable the RFFI. 0 ENABLE_THE_RFFI_ Enable the RFFI. 1 RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). [6:6] ENUM DISABLE_THE_DAI_ Disable the DAI. 0 ENABLE_THE_DAI_ Enable the DAI. 1 TFFIE Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register. [7:7] ENUM DISABLE_THE_TFFI_ Disable the TFFI. 0 ENABLE_THE_TFFI_ Enable the TFFI. 1 SRST Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset. [8:8] ENUM SEE_THE_TEXT_ See the text. 0 RESET_THE_I2C_TO_IDL Reset the I2C to idle state. Self clearing. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] I2C_CLKHI I2C Clock High 0x30C read-write 0xB9 0xFFFFFFFF CDHI Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] I2C_CLKLO I2C Clock Low 0x310 write-only 0xB9 0xFFFFFFFF CDLO Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] CLKCTRL OTG clock controller 0xFF4 read-write 0 0xFFFFFFFF HOST_CLK_EN Host clock enable [0:0] ENUM DISABLE_THE_HOST_CLO Disable the Host clock. 0 ENABLE_THE_HOST_CLOC Enable the Host clock. 1 DEV_CLK_EN Device clock enable [1:1] ENUM DISABLE_THE_DEVICE_C Disable the Device clock. 0 ENABLE_THE_DEVICE_CL Enable the Device clock. 1 I2C_CLK_EN I2C clock enable [2:2] ENUM DISABLE_THE_I2C_CLOC Disable the I2C clock. 0 ENABLE_THE_I2C_CLOCK Enable the I2C clock. 1 OTG_CLK_EN OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register. [3:3] ENUM DISABLE_THE_OTG_CLOC Disable the OTG clock. 0 ENABLE_THE_OTG_CLOCK Enable the OTG clock. 1 AHB_CLK_EN AHB master clock enable [4:4] ENUM DISABLE_THE_AHB_CLOC Disable the AHB clock. 0 ENABLE_THE_AHB_CLOCK Enable the AHB clock. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] OTGClkSt OTG clock status 0xFF8 read-only 0 0xFFFFFFFF HOST_CLK_ON Host clock status. [0:0] ENUM HOST_CLOCK_IS_NOT_AV Host clock is not available. 0 HOST_CLOCK_IS_AVAILA Host clock is available. 1 DEV_CLK_ON Device clock status. [1:1] ENUM DEVICE_CLOCK_IS_NOT_ Device clock is not available. 0 DEVICE_CLOCK_IS_AVAI Device clock is available. 1 I2C_CLK_ON I2C clock status. [2:2] ENUM I2C_CLOCK_IS_NOT_AVA I2C clock is not available. 0 I2C_CLOCK_IS_AVAILAB I2C clock is available. 1 OTG_CLK_ON OTG clock status. [3:3] ENUM OTG_CLOCK_IS_NOT_AVA OTG clock is not available. 0 OTG_CLOCK_IS_AVAILAB OTG clock is available. 1 AHB_CLK_ON AHB master clock status. [4:4] ENUM AHB_CLOCK_IS_NOT_AVA AHB clock is not available. 0 AHB_CLOCK_IS_AVAILAB AHB clock is available. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] CRC CRC engine CRC 0x20090000 0x0 0xFFF registers MODE CRC mode register 0x000 read-write 0 0xFFFFFFFF CRC_POLY Select CRC polynomial [1:0] ENUM CRC_CCITT_POLYNOMIAL CRC-CCITT polynomial 0x0 CRC_16_POLYNOMIAL CRC-16 polynomial 0x1 CRC_32_POLYNOMIAL CRC-32 polynomial 0x2 BIT_RVS_WR Select bit order for CRC_WR_DATA [2:2] ENUM NO_BIT_ORDER_REVERSE No bit order reverse for CRC_WR_DATA (per byte) 0 BIT_ORDER_REVERSE_FO Bit order reverse for CRC_WR_DATA (per byte) 1 CMPL_WR Select one's complement for CRC_WR_DATA [3:3] ENUM NO_ONES_COMPLEMENT_ No one's complement for CRC_WR_DATA 0 ONES_COMPLEMENT_FOR One's complement for CRC_WR_DATA 1 BIT_RVS_SUM Select bit order revers for CRC_SUM [4:4] ENUM NO_BIT_ORDER_REVERSE No bit order reverse for CRC_SUM 0 BIT_ORDER_REVERSE_FO Bit order reverse for CRC_SUM 1 CMPL_SUM Select one's complement for CRC_SUM [5:5] ENUM NO_ONES_COMPLEMENT_ No one's complement for CRC_SUM 0 ONES_COMPLEMENT_FOR One's complement for CRC_SUM 1 Reserved Always 0 when read [31:6] SEED CRC seed register 0x004 read-write 0xFFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. [31:0] SUM CRC checksum register 0x008 read-only 0xFFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. [31:0] DATA CRC data register 0x008 write-only 0 0x00000000 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. [31:0] GPIO GPIO GPIO 0x20098000 0x0 0xFFF registers 6 0x20 0-5 DIR%s GPIO Port Direction control register. 0x000 read-write 0 0xFFFFFFFF PDIR0 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [0:0] PDIR1 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [1:1] PDIR2 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [2:2] PDIR3 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [3:3] PDIR4 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [4:4] PDIR5 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [5:5] PDIR6 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [6:6] PDIR7 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [7:7] PDIR8 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [8:8] PDIR9 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [9:9] PDIR10 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [10:10] PDIR11 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [11:11] PDIR12 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [12:12] PDIR13 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [13:13] PDIR14 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [14:14] PDIR15 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [15:15] PDIR16 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [16:16] PDIR17 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [17:17] PDIR18 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [18:18] PDIR19 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [19:19] PDIR20 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [20:20] PDIR21 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [21:21] PDIR22 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [22:22] PDIR23 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [23:23] PDIR24 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [24:24] PDIR25 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [25:25] PDIR26 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [26:26] PDIR27 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [27:27] PDIR28 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [28:28] PDIR29 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [29:29] PDIR30 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [30:30] PDIR31 Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output. [31:31] 6 0x20 0-5 MASK%s Mask register for Port. 0x010 read-write 0 0xFFFFFFFF PMASK0 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [0:0] PMASK1 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [1:1] PMASK2 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [2:2] PMASK3 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [3:3] PMASK4 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [4:4] PMASK5 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [5:5] PMASK6 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [6:6] PMASK7 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [7:7] PMASK8 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [8:8] PMASK9 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [9:9] PMASK10 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [10:10] PMASK11 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [11:11] PMASK12 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [12:12] PMASK13 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [13:13] PMASK14 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [14:14] PMASK15 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [15:15] PMASK16 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [16:16] PMASK17 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [17:17] PMASK18 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [18:18] PMASK19 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [19:19] PMASK20 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [20:20] PMASK21 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [21:21] PMASK22 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [22:22] PMASK23 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [23:23] PMASK24 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [24:24] PMASK25 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [25:25] PMASK26 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [26:26] PMASK27 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [27:27] PMASK28 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [28:28] PMASK29 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [29:29] PMASK30 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [30:30] PMASK31 Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin. [31:31] 6 0x20 0-5 PIN%s PIN[%s] Port Pin value register using MASK. 0x014 read-write 0 0xFFFFFFFF VAL0 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [0:0] VAL1 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [1:1] VAL2 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [2:2] VAL3 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [3:3] VAL4 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [4:4] VAL5 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [5:5] VAL6 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [6:6] VAL7 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [7:7] VAL8 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [8:8] VAL9 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [9:9] VAL10 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [10:10] VAL11 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [11:11] VAL12 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [12:12] VAL13 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [13:13] VAL14 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [14:14] VAL15 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [15:15] VAL16 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [16:16] VAL17 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [17:17] VAL18 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [18:18] VAL19 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [19:19] VAL20 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [20:20] VAL21 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [21:21] VAL22 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [22:22] VAL23 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [23:23] VAL24 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [24:24] VAL25 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [25:25] VAL26 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [26:26] VAL27 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [27:27] VAL28 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [28:28] VAL29 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [29:29] VAL30 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [30:30] VAL31 Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH. [31:31] 6 0x20 0-5 SET%s Port Output Set register using MASK. 0x018 read-write 0 0xFFFFFFFF PSET0 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [0:0] PSET1 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [1:1] PSET2 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [2:2] PSET3 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [3:3] PSET4 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [4:4] PSET5 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [5:5] PSET6 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [6:6] PSET7 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [7:7] PSET8 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [8:8] PSET9 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [9:9] PSET10 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [10:10] PSET11 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [11:11] PSET12 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [12:12] PSET13 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [13:13] PSET14 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [14:14] PSET15 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [15:15] PSET16 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [16:16] PSET17 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [17:17] PSET18 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [18:18] PSET19 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [19:19] PSET20 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [20:20] PSET21 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [21:21] PSET22 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [22:22] PSET23 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [23:23] PSET24 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [24:24] PSET25 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [25:25] PSET26 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [26:26] PSET27 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [27:27] PSET28 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [28:28] PSET29 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [29:29] PSET30 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [30:30] PSET31 Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH. [31:31] 6 0x20 0-5 CLR%s Port Output Clear register using MASK. 0x01C write-only 0 0xFFFFFFFF PCLR0 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [0:0] PCLR1 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [1:1] PCLR2 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [2:2] PCLR3 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [3:3] PCLR4 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [4:4] PCLR5 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [5:5] PCLR6 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [6:6] PCLR7 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [7:7] PCLR8 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [8:8] PCLR9 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [9:9] PCLR10 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [10:10] PCLR11 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [11:11] PCLR12 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [12:12] PCLR13 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [13:13] PCLR14 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [14:14] PCLR15 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [15:15] PCLR16 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [16:16] PCLR17 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [17:17] PCLR18 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [18:18] PCLR19 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [19:19] PCLR20 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [20:20] PCLR21 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [21:21] PCLR22 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [22:22] PCLR23 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [23:23] PCLR24 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [24:24] PCLR25 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [25:25] PCLR26 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [26:26] PCLR27 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [27:27] PCLR28 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [28:28] PCLR29 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [29:29] PCLR30 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [30:30] PCLR31 Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW. [31:31] EMC External Memory Controller (EMC) EMC 0X2009C000 0x0 0xFFF registers CONTROL Controls operation of the memory controller. 0x000 read-write 0x3 0xFFFFFFFF E EMC Enable. Indicates if the EMC is enabled or disabled: [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled (POR and warm reset value). 1 M Address mirror. Indicates normal or reset memory map: [1:1] ENUM NORMAL Normal memory map. 0 RESET Reset memory map. Static memory EMC_CS1 is mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value). 1 L Low-power mode. Indicates normal, or low-power mode: [2:2] ENUM WARMRESET Normal mode (warm reset value). 0 LOWPOWER Low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1] 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] STATUS Provides EMC status information. 0x004 read-only 0x5 0xFFFFFFFF B Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not. [0:0] ENUM IDLE EMC is idle (warm reset value). 0 BUSY EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value). 1 S Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly. [1:1] ENUM EMPTY Write buffers empty (POR reset value) 0 DATA Write buffers contain data. 1 SA Self-refresh acknowledge. This bit indicates the operating mode of the EMC. [2:2] ENUM NORMAL Normal mode 0 SELFREFRESH Self-refresh mode (POR reset value). 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:3] CONFIG Configures operation of the memory controller 0x008 read-write 0x0 0xFFFFFFFF EM Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes. [0:0] ENUM LITTLEENDIAN Little-endian mode (POR reset value). 0 BIGENDIAN Big-endian mode. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:1] CLKR CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC. [8:8] ENUM PORRESET 1:1(POR reset value) 0 DONOTUSE 1:2 (this option is not available on the LPC178x/177x) 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] DYNAMICCONTROL Controls dynamic memory operation. 0x020 read-write 0x006 0xFFFFFFFF CE Dynamic memory clock enable. [0:0] ENUM POWERSAVE Clock enable of idle devices are deasserted to save power (POR reset value). 0 HIGH All clock enables are driven HIGH continuously.[1] 1 CS Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode. [1:1] ENUM STOP CLKOUT stops when all SDRAMs are idle and during self-refresh mode. 0 RUN CLKOUT runs continuously (POR reset value). 1 SR Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2] [2:2] ENUM NORMAL_MODE_ Normal mode. 0 ENTER_SELF_REFRESH_M Enter self-refresh mode (POR reset value). 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:3] MMC Memory clock control. [5:5] ENUM CLKOUT_ENABLED_POR_ CLKOUT enabled (POR reset value). 0 CLKOUT_DISABLED CLKOUT disabled.[3] 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:6] I SDRAM initialization. [8:7] ENUM NORMAL Issue SDRAM NORMAL operation command (POR reset value). 0x0 MODE Issue SDRAM MODE command. 0x1 PALL Issue SDRAM PALL (precharge all) command. 0x2 NOP Issue SDRAM NOP (no operation) command) 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [13:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:14] DYNAMICREFRESH Configures dynamic memory refresh. 0x024 read-write 0x0 0xFFFFFFFF REFRESH Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles [10:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:11] DYNAMICREADCONFIG Configures dynamic memory read strategy. 0x028 read-write 0x0 0xFFFFFFFF RD Read data strategy [1:0] ENUM CLOCK_OUT_DELAYED_ST Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value. 0x0 COMMAND_DELAYED_STRA Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed). 0x1 COMMAND_DELAYED_STRA Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed). 0x2 COMMAND_DELAYED_STRA Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed). 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] DYNAMICRP Precharge command period. 0x030 read-write 0x0F 0xFFFFFFFF TRP Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICRAS Active to precharge command period. 0x034 read-write 0xF 0xFFFFFFFF TRAS Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICSREX Self-refresh exit time. 0x038 read-write 0xF 0xFFFFFFFF TSREX Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICAPR Last-data-out to active command time. 0x03C read-write 0xF 0xFFFFFFFF TAPR Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICDAL Data-in to active command time. 0x040 read-write 0xF 0xFFFFFFFF TDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICWR Write recovery time. 0x044 read-write 0xF 0xFFFFFFFF TWR Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICRC Selects the active to active command period. 0x048 read-write 0x1F 0xFFFFFFFF TRC Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICRFC Selects the auto-refresh period. 0x04C read-write 0x1F 0xFFFFFFFF TRFC Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICXSR Time for exit self-refresh to active command. 0x050 read-write 0x1F 0xFFFFFFFF TXSR Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICRRD Latency for active bank A to active bank B. 0x054 read-write 0xF 0xFFFFFFFF TRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICMRD Time for load mode register to active command. 0x058 read-write 0xF 0xFFFFFFFF TMRD Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] STATICEXTENDEDWAIT Time for long static memory read and write transfers. 0x080 read-write 0x0 0xFFFFFFFF EXTENDEDWAIT Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] 4 0x20 0-3 DYNAMICCONFIG%s Configuration information for EMC_DYCS0. 0x100 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [2:0] MD Memory device. [4:3] ENUM SDRAM_POR_RESET_VAL SDRAM (POR reset value). 0x0 LOW_POWER_SDRAM_ Low-power SDRAM. 0x1 RESERVED_ Reserved. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [6:5] AM0 See Table 133. 000000 = reset value.[1] [12:7] RESERVED Reserved. Read value is undefined, only zero should be written. [13:13] AM1 See Table 133. 0 = reset value. [14:14] RESERVED Reserved. Read value is undefined, only zero should be written. [18:15] B Buffer enable. [19:19] ENUM BUFFER_DISABLED_FOR_ Buffer disabled for accesses to this chip select (POR reset value). 0 BUFFER_ENABLED_FOR_A Buffer enabled for accesses to this chip select.[2] 1 P Write protect. [20:20] ENUM WRITES_NOT_PROTECTED Writes not protected (POR reset value). 0 WRITES_PROTECTED_ Writes protected. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:21] 4 0x20 0-3 DYNAMICRASCAS%s RAS and CAS latencies for EMC_DYCS0. 0x104 read-write 0x303 0xFFFFFFFF RAS RAS latency (active to read/write delay). [1:0] ENUM RESERVED_ Reserved. 0x0 ONE_CCLK_CYCLE_ One CCLK cycle. 0x1 TWO_CCLK_CYCLES_ Two CCLK cycles. 0x2 THREE_CCLK_CYCLES_P Three CCLK cycles (POR reset value). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:2] CAS CAS latency. [9:8] ENUM RESERVED_ Reserved. 0x0 ONE_CCLK_CYCLE_ One CCLK cycle. 0x1 TWO_CCLK_CYCLES_ Two CCLK cycles. 0x2 THREE_CCLK_CYCLES_P Three CCLK cycles (POR reset value). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] 4 0x20 0-3 STATICCONFIG%s Configuration for EMC_CS0. 0x200 read-write 0x0 0xFFFFFFFF MW Memory width. [1:0] ENUM 8_BIT_POR_RESET_VAL 8 bit (POR reset value). 0x0 16_BIT_ 16 bit. 0x1 32_BIT_ 32 bit. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [2:2] PM Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally. [3:3] ENUM DISABLED_POR_RESET_ Disabled (POR reset value). 0 ASYNCHRONOUS_PAGE_MO Asynchronous page mode enabled (page length four). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:4] PC Chip select polarity. The value of the chip select polarity on power-on reset is 0. [6:6] ENUM ACTIVE_LOW_CHIP_SELE Active LOW chip select. 0 ACTIVE_HIGH_CHIP_SEL Active HIGH chip select. 1 PB Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. [7:7] ENUM BLSHIGH For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value). 0 BLSLOW For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW. 1 EW Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1] [8:8] ENUM EXTENDED_WAIT_DISABL Extended wait disabled (POR reset value). 0 EXTENDED_WAIT_ENABLE Extended wait enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [18:9] B Buffer enable [2] [19:19] ENUM BUFFER_DISABLED_POR Buffer disabled (POR reset value). 0 BUFFER_ENABLED_ Buffer enabled. 1 P Write protect [20:20] ENUM WRITES_NOT_PROTECTED Writes not protected (POR reset value). 0 WRITE_PROTECTED_ Write protected. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:21] 4 0x20 0-3 STATICWAITWEN%s Delay from EMC_CS0 to write enable. 0x204 read-write 0x0 0xFFFFFFFF WAITWEN Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] 4 0x20 0-3 STATICWAITOEN%s Delay from EMC_CS0 or address change, whichever is later, to output enable. 0x208 read-write 0x0 0xFFFFFFFF WAITOEN Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] 4 0x20 0-3 STATICWAITRD%s Delay from EMC_CS0 to a read access. 0x20C read-write 0x1F 0xFFFFFFFF WAITRD Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITPAGE%s Delay for asynchronous page mode sequential accesses for EMC_CS0. 0x210 read-write 0x1F 0xFFFFFFFF WAITPAGE Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITWR%s Delay from EMC_CS0 to a write access. 0x214 read-write 0x1F 0xFFFFFFFF WAITWR Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITTURN%s Number of bus turnaround cycles EMC_CS0. 0x218 read-write 0xF 0xFFFFFFFF WAITTURN Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] WWDT Windowed Watchdog Timer (WWDT) WWDT 0x40000000 0x0 0xFFF registers WWDT 0 MOD Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. This bit is Set Only. See Table 652. [0:0] ENUM STOP The watchdog timer is stopped. 0 RUN The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. This bit is Set Only. See Table 652. [1:1] ENUM NORESET A watchdog timeout will not cause a chip reset. 0 RESET A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section WDTOF. [2:2] WDINT Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section WDINT. [3:3] WDPROTECT Watchdog update mode. This bit is Set Only. See Section WDPROTECT. [4:4] ENUM CHANGE The watchdog reload value (WDTC) can be changed at any time. 0 CHANGE_W_CNT The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:5] TC Watchdog timer constant register. The value in this register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF Count Watchdog time-out interval. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 Feed Feed value should be 0xAA followed by 0x55. [7:0] TV Watchdog timer value register. This register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF Count Counter timer value. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] TIMER0 Timer0/1/2/3 TIMER0 0x40004000 0x0 0xFFF registers TIMER0 1 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. [0:0] CRST When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. [1:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] TC Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PM Prescale counter maximum value. [31:0] PC Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0 [0:0] ENUM INTERRUPT_IS_GENERAT Interrupt is generated when MR0 matches the value in the TC. 1 INTERRUPT_IS_DISABLE Interrupt is disabled 0 MR0R Reset on MR0 [1:1] ENUM TC_WILL_BE_RESET_IF_ TC will be reset if MR0 matches it. 1 FEATURE_DISABLED_ Feature disabled. 0 MR0S Stop on MR0 [2:2] ENUM TC_AND_PC_WILL_BE_ST TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 1 FEATURE_DISABLED_ Feature disabled. 0 MR1I Interrupt on MR1 [3:3] ENUM INTERRUPT_IS_GENERAT Interrupt is generated when MR1 matches the value in the TC. 1 INTERRUPT_IS_DISABLE Interrupt is disabled. 0 MR1R Reset on MR1 [4:4] ENUM TC_WILL_BE_RESET_IF_ TC will be reset if MR1 matches it. 1 FEATURE_DISABLED_ Feature disabled. 0 MR1S Stop on MR1 [5:5] ENUM TC_AND_PC_WILL_BE_ST TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 1 FEATURE_DISABLED_ Feature disabled. 0 MR2I Interrupt on MR2 [6:6] ENUM INTERRUPT_IS_GENERAT Interrupt is generated when MR2 matches the value in the TC. 1 INTERRUPT_IS_DISABLE Interrupt is disabled 0 MR2R Reset on MR2 [7:7] ENUM TC_WILL_BE_RESET_IF_ TC will be reset if MR2 matches it. 1 FEATURE_DISABLED_ Feature disabled. 0 MR2S Stop on MR2. [8:8] ENUM TC_AND_PC_WILL_BE_ST TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC 1 FEATURE_DISABLED_ Feature disabled. 0 MR3I Interrupt on MR3 [9:9] ENUM INTERRUPT_IS_GENERAT Interrupt is generated when MR3 matches the value in the TC. 1 THIS_INTERRUPT_IS_DI This interrupt is disabled 0 MR3R Reset on MR3 [10:10] ENUM TC_WILL_BE_RESET_IF_ TC will be reset if MR3 matches it. 1 FEATURE_DISABLED_ Feature disabled. 0 MR3S Stop on MR3 [11:11] ENUM TC_AND_PC_WILL_BE_ST TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 1 FEATURE_DISABLED_ Feature disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR[%s] MR[%s] Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CAPn.0 rising edge [0:0] ENUM ENABLE A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. 1 DISABLE This feature is disabled. 0 CAP0FE Capture on CAPn.0 falling edge [1:1] ENUM ENABLE A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. 1 DISABLE This feature is disabled. 0 CAP0I Interrupt on CAPn.0 event [2:2] ENUM ENABLE A CR0 load due to a CAPn.0 event will generate an interrupt. 1 DISABLE This feature is disabled. 0 CAP1RE Capture on CAPn.1 rising edge [3:3] ENUM ENABLE A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. 1 DISABLE This feature is disabled. 0 CAP1FE Capture on CAPn.1 falling edge [4:4] ENUM ENABLE A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. 1 DISABLE This feature is disabled. 0 CAP1I Interrupt on CAPn.1 event [5:5] ENUM ENABLE A CR1 load due to a CAPn.1 event will generate an interrupt. 1 DISABLE This feature is disabled. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] 2 0x4 0-1 CR[%s] CR[%s] Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the external match pins. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [0:0] EM1 External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). [1:1] EM2 External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [2:2] EM3 External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTMODE Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 DUALEDGE Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. [3:2] ENUM CAPN_0_FOR_TIMERN CAPn.0 for TIMERn 0x0 CAPN_1_FOR_TIMERN CAPn.1 for TIMERn 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] TIMER1 0x40008000 0 0xFFF registers TIMER1 2 UART0 UART0/2/3 UART0 0x4000C000 0x0 0xFFF registers UART0 5 RBR Receiver Buffer Register. Contains the next received character to be read (DLAB =0). 0x000 read-only 0 0x00000000 modify RBR The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO. [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] THR Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). RBR 0x000 write-only 0 0x00000000 THR Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). 0x004 read-write 0 0xFFFFFFFF DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). DLM 0x004 read-write 0 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupts. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupts. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupts. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupts. 1 RXIE RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. [2:2] ENUM DISABLE_THE_RX_LINE_ Disable the RX line status interrupts. 0 ENABLE_THE_RX_LINE_S Enable the RX line status interrupts. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:3] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. [0:0] ENUM AT_LEAST_ONE_INTERRU At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). [3:1] ENUM 1_RECEIVE_LINE_S 1 - Receive Line Status (RLS). 0x3 2A__RECEIVE_DATA_AV 2a - Receive Data Available (RDA). 0x2 2B__CHARACTER_TIME_ 2b - Character Time-out Indicator (CTI). 0x6 3_THRE_INTERRUPT 3 - THRE Interrupt 0x1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:4] FIFOENABLE Copies of UnFCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] FCR FIFO Control Register. Controls UART FIFO usage and modes. IIR 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO Enable. [0:0] ENUM UARTN_FIFOS_ARE_DISA UARTn FIFOs are disabled. Must not be used in the application. 0 ACTIVE_HIGH_ENABLE_F Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. 1 RXFIFORES RX FIFO Reset. [1:1] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UARTn FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset. [2:2] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UARTn FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. 1 DMAMODE DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [5:4] RXTRIGLVL RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select. [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length 0x0 6_BIT_CHARACTER_LENG 6-bit character length 0x1 7_BIT_CHARACTER_LENG 7-bit character length 0x2 8_BIT_CHARACTER_LENG 8-bit character length 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if UnLCR[1:0]=00). 1 PE Parity Enable. [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. [0:0] ENUM EMPTY The UARTn receiver FIFO is empty. 0 NOTEMPTY The UARTn receiver FIFO is not empty. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. [5:5] ENUM VALIDDATA UnTHR contains valid data. 0 EMPTY UnTHR is empty. 1 TEMT Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. [6:6] ENUM VALIDDATA UnTHR and/or the UnTSR contains valid data. 0 EMPTY UnTHR and the UnTSR are empty. 1 RXFE Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. [7:7] ENUM NOERROR UnRBR contains no UARTn RX errors or UnFCR[0]=0. 0 ERRORS UARTn RBR contains at least one UARTn RX error. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. 8-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF PAD A readable, writable byte. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START Start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Restart bit. [2:2] ENUM NO_RESTART_ No restart. 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. [8:8] ENUM NO_IMPACT_ No impact. 0 CLEAR_THE_CORRESPOND Clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. [9:9] ENUM NO_IMPACT_ No impact. 0 CLEAR_THE_CORRESPOND Clear the corresponding interrupt in the IIR. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. [3:0] MULVAL Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. [7:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation. 1 RXDIS Receiver enable. [1:1] ENUM ENABLED The receiver is enabled. 0 DISABLED The receiver is disabled. 1 AADEN AAD enable. [2:2] ENUM DISABLED Auto Address Detect (AAD) is disabled. 0 ENABLED Auto Address Detect (AAD) is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [3:3] DCTRL Direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin. [5:5] ENUM DIRLOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 DIRHIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] UART1 UART1 UART1 0x40010000 0x0 0xFFF registers UART1 6 RBR DLAB =0 Receiver Buffer Register. Contains the next received character to be read. 0x000 read-only 0 0x00000000 modify RBR The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] THR DLAB =0. Transmit Holding Register. The next character to be transmitted is written here. RBR 0x000 write-only 0 0x00000000 THR Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLL DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLM DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. 0x004 read-write 0 0xFFFFFFFF DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] IER DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. DLM 0x004 read-write 0 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupts. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupts. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupts. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupts. 1 RXIE RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE_THE_RX_LINE_ Disable the RX line status interrupts. 0 ENABLE_THE_RX_LINE_S Enable the RX line status interrupts. 1 MSIE Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. [3:3] ENUM DISABLE_THE_MODEM_IN Disable the modem interrupt. 0 ENABLE_THE_MODEM_INT Enable the modem interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:4] CTSIE CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. [7:7] ENUM DISABLE_THE_CTS_INTE Disable the CTS interrupt. 0 ENABLE_THE_CTS_INTER Enable the CTS interrupt. 1 ABEOIE Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOIE Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM AT_LEAST_ONE_INTERRU At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). [3:1] ENUM RLS 1 - Receive Line Status (RLS). 0x3 RDA 2a - Receive Data Available (RDA). 0x2 CTI 2b - Character Time-out Indicator (CTI). 0x6 THRE 3 - THRE Interrupt. 0x1 MODEM 4 - Modem Interrupt. 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOENABLE Copies of FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, the value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls UART1 FIFO usage and modes. IIR 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO enable. [0:0] ENUM MUST_NOT_BE_USED_IN_ Must not be used in the application. 0 ACTIVE_HIGH_ENABLE_F Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. 1 RXFIFORES RX FIFO Reset. [1:1] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UART1 FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset. [2:2] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UART1 FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. 1 DMAMODE DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTRIGLVL RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select. [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select. [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable. [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select. [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED1STICK_PAR Forced 1 stick parity. 0x2 FORCED0STICK_PAR Forced 0 stick parity. 0x3 BC Break Control. [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit (DLAB) [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] MCR Modem Control Register. Contains controls for flow control handshaking and loopback mode. 0x010 read-write 0 0xFFFFFFFF DTRCTRL DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. [0:0] RTSCTRL RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:2] LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. [4:4] ENUM DISABLE_MODEM_LOOPBA Disable modem loopback mode. 0 ENABLE_MODEM_LOOPBAC Enable modem loopback mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:5] RTSEN RTS enable. [6:6] ENUM DISABLE_AUTO_RTS_FLO Disable auto-rts flow control. 0 ENABLE_AUTO_RTS_FLOW Enable auto-rts flow control. 1 CTSEN CTS enable. [7:7] ENUM DISABLE_AUTO_CTS_FLO Disable auto-cts flow control. 0 ENABLE_AUTO_CTS_FLOW Enable auto-cts flow control. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. [0:0] ENUM EMPTY The UART1 receiver FIFO is empty. 0 NOTEMPTY The UART1 receiver FIFO is not empty. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. [5:5] ENUM VALID THR contains valid data. 0 THR_IS_EMPTY_ THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM VALID THR and/or the TSR contains valid data. 0 EMPTY THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. [7:7] ENUM NOERROR RBR contains no UART1 RX errors or FCR[0]=0. 0 ERRORS UART1 RBR contains at least one UART1 RX error. 1 RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] MSR Modem Status Register. Contains handshake signal status flags. 0x018 read-only 0 0xFFFFFFFF modify DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. [0:0] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, CTS. 0 STATE_CHANGE_DETECTE State change detected on modem input, CTS. 1 DDSR Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. [1:1] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DSR. 0 STATE_CHANGE_DETECTE State change detected on modem input, DSR. 1 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. [2:2] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, RI. 0 LOW_TO_HIGH_TRANSITI Low-to-high transition detected on RI. 1 DDCD Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. [3:3] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DCD. 0 STATE_CHANGE_DETECTE State change detected on modem input, DCD. 1 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. [4:4] DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. [5:5] RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. [6:6] DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. [7:7] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. 8-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF Pad A readable, writable byte. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START Auto-baud start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM STOP Auto-baud stop (auto-baud is not running). 0 START Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Auto-baud restart bit. [2:2] ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write-only). [8:8] ENUM WRITING_A_0_HAS_NO_I Writing a 0 has no impact. 0 WRITING_A_1_WILL_CLE Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write-only). [9:9] ENUM WRITING_A_0_HAS_NO_I Writing a 0 has no impact. 0 WRITING_A_1_WILL_CLE Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select. [0:0] ENUM DISABLED_ Disabled. 0 ENABLED_IN_THIS_MOD Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. 1 RXDIS Receive enable. [1:1] ENUM ENABLED_ Enabled. 0 DISABLED_ Disabled. 1 AADEN Auto Address Detect (AAD) enable. [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 SEL Direction control. [3:3] ENUM RTS_IF_DIRECTION_CO RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR_IF_DIRECTION_CO DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW_THE_DIRECTION_C LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH_THE_DIRECTION_ HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] PWM0 Pulse Width Modulators (PWM0/1) PWM 0x40014000 0x0 0xFFF registers PWM0 39 IR Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF PWMMR0INT Interrupt flag for PWM match channel 0. [0:0] PWMMR1INT Interrupt flag for PWM match channel 1. [1:1] PWMMR2INT Interrupt flag for PWM match channel 2. [2:2] PWMMR3INT Interrupt flag for PWM match channel 3. [3:3] PWMCAP0INT Interrupt flag for capture input 0 [4:4] PWMCAP1INT Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR). [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [7:6] PWMMR4INT Interrupt flag for PWM match channel 4. [8:8] PWMMR5INT Interrupt flag for PWM match channel 5. [9:9] PWMMR6INT Interrupt flag for PWM match channel 6. [10:10] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. 0x004 read-write 0 0xFFFFFFFF CE Counter Enable [0:0] ENUM THE_PWM_TIMER_COUNTE The PWM Timer Counter and PWM Prescale Counter are enabled for counting. 1 THE_COUNTERS_ARE_DIS The counters are disabled. 0 CR Counter Reset [1:1] ENUM THE_PWM_TIMER_COUNTE The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. 1 CLEAR_RESET_ Clear reset. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [2:2] PWMEN PWM Enable [3:3] ENUM PWM_MODE_IS_ENABLED_ PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. 1 TIMER_MODE_IS_ENABLE Timer mode is enabled (counter resets to 0). 0 MDIS Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). [4:4] ENUM MASTER_USE_PWM0_IS_ Master use. PWM0 is the master, and both PWMs are enabled for counting. 1 INDIVIDUAL_USE_THE_ Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] TC Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. Determines how often the PWM counter is incremented. 0x00C read-write 0 0xFFFFFFFF PM Prescale counter maximum value. [31:0] PC Prescale Counter. Prescaler for the main PWM counter. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF PWMMR0I Interrupt PWM0 [0:0] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR0 Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC. 1 PWMMR0R Reset PWM0 [1:1] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR0_THE Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. 1 PWMMR0S Stop PWM0 [2:2] ENUM DISABLED Disabled 0 STOP_ON_PWMMR0_THE_ Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. 1 PWMMR1I Interrupt PWM1 [3:3] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. 1 PWMMR1R Reset PWM1 [4:4] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR1_THE Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. 1 PWMMR1S Stop PWM1 [5:5] ENUM DISABLED Disabled 0 STOP_ON_PWMMR1_THE_ Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC. 1 PWMMR2I Interrupt PWM0 [6:6] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR2 Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC. 1 PWMMR2R Reset PWM0 [7:7] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR2_THE Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. 1 PWMMR2S Stop PWM0 [8:8] ENUM DISABLED Disabled 0 STOP_ON_PWMMR2_THE_ Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. 1 PWMMR3I Interrupt PWM3 [9:9] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR3 Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC. 1 PWMMR3R Reset PWM3 [10:10] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR3_THE Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. 1 PWMMR3S Stop PWM0 [11:11] ENUM DISABLED Disabled 0 STOP_ON_PWMMR3_THE_ Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. 1 PWMMR4I Interrupt PWM4 [12:12] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR4 Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC. 1 PWMMR4R Reset PWM4 [13:13] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR4_THE Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. 1 PWMMR4S Stop PWM4 [14:14] ENUM DISABLED Disabled 0 STOP_ON_PWMMR4_THE_ Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC. 1 PWMMR5I Interrupt PWM5 [15:15] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR5 Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC. 1 PWMMR5R Reset PWM5 [16:16] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR5_THE Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. 1 PWMMR5S Stop PWM5 [17:17] ENUM DISABLED Disabled 0 STOP_ON_PWMMR5_THE_ Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC. 1 PWMMR6I Interrupt PWM6 [18:18] ENUM DISABLED_ Disabled. 0 INTERRUPT_ON_PWMMR6 Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC. 1 PWMMR6R Reset PWM6 [19:19] ENUM DISABLED_ Disabled. 0 RESET_ON_PWMMR6_THE Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. 1 PWMMR6S Stop PWM6 [20:20] ENUM DISABLED Disabled 0 STOP_ON_PWMMR6_THE_ Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:21] 4 0x4 0-3 MR%s Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event. 0x028 read-write 0 0xFFFFFFFF CAP0_R Capture on PWMn_CAP0 rising edge [0:0] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 RISING_EDGE_A_SYNCH Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC. 1 CAP0_F Capture on PWMn_CAP0 falling edge [1:1] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 FALLING_EDGE_A_SYNC Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 CAP0_I Interrupt on PWMn_CAP0 event [2:2] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 INTERRUPT_A_CR0_LOA Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt. 1 CAP1_R Capture on PWMn_CAP1 rising edge. Reserved for PWM0. [3:3] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 RISING_EDGE_A_SYNCH Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC. 1 CAP1_F Capture on PWMn_CAP1 falling edge. Reserved for PWM0. [4:4] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 FALLING_EDGE_A_SYNC Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC. 1 CAP1_I Interrupt on PWMn_CAP1 event. Reserved for PWM0. [5:5] ENUM DISABLED_THIS_FEATU Disabled. This feature is disabled. 0 INTERRUPT_A_CR1_LOA Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] 2 0x4 0-1 CR[%s] CR[%s] PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. 0x02C read-write 0 0xFFFFFFFF RESERVED Reserved. [1:0] PWMSEL2 PWM[2] output single/double edge mode control. [2:2] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL3 PWM[3] output edge control. [3:3] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL4 PWM[4] output edge control. [4:4] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL5 PWM[5] output edge control. [5:5] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL6 PWM[6] output edge control. [6:6] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [8:7] PWMENA1 PWM[1] output enable control. [9:9] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA2 PWM[2] output enable control. [10:10] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA3 PWM[3] output enable control. [11:11] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA4 PWM[4] output enable control. [12:12] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA5 PWM[5] output enable control. [13:13] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA6 PWM[6] output enable control. See PWMENA1 for details. [14:14] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 RESERVED Unused, always zero. [31:15] MR4 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. 0x040 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] MR5 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. 0x044 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] MR6 Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges. 0x048 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] PCR PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs. 0x04C read-write 0 0xFFFFFFFF RESERVED Reserved. [1:0] PWMSEL2 PWM[2] output single/double edge mode control. [2:2] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL3 PWM[3] output edge control. [3:3] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL4 PWM[4] output edge control. [4:4] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL5 PWM[5] output edge control. [5:5] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 PWMSEL6 PWM[6] output edge control. [6:6] ENUM SINGLE_EDGE_CONTROLL Single edge controlled mode is selected. 0 DOUBLE_EDGE_CONTROLL Double edge controlled mode is selected. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [8:7] PWMENA1 PWM[1] output enable control. [9:9] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA2 PWM[2] output enable control. [10:10] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA3 PWM[3] output enable control. [11:11] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA4 PWM[4] output enable control. [12:12] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA5 PWM[5] output enable control. [13:13] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 PWMENA6 PWM[6] output enable control. See PWMENA1 for details. [14:14] ENUM THE_PWM_OUTPUT_IS_DI The PWM output is disabled. 0 THE_PWM_OUTPUT_IS_EN The PWM output is enabled. 1 RESERVED Unused, always zero. [31:15] LER Load Enable Register. Enables use of updated PWM match values. 0x050 read-write 0 0xFFFFFFFF MAT0LATCHEN Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7. [0:0] MAT1LATCHEN Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details. [1:1] MAT2LATCHEN Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details. [2:2] MAT3LATCHEN Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details. [3:3] MAT4LATCHEN Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details. [4:4] MAT5LATCHEN Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details. [5:5] MAT6LATCHEN Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF MOD Counter/ Timer Mode [1:0] ENUM TIMER_MODE_THE_TC_I Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register. 0x0 RISING_EDGE_COUNTER_ Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2. 0x1 FALLING_EDGE_COUNTER Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2. 0x2 DUAL_EDGE_COUNTER_MO Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2. 0x3 CIS Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved. [3:2] ENUM FOR_PWM0_00_EQ_PWM0_ For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved) 0x0 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] PWM1 0x40018000 0 0xFFF registers PWM1 9 I2C0 I2C bus interface I2C 0x4001C000 0 0xFFF registers I2C0 10 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AA Assert acknowledge flag. [2:2] SI I2C interrupt flag. [3:3] STO STOP flag. [4:4] STA START flag. [5:5] I2EN I2C interface enable. [6:6] RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x004 read-only 0xF8 0xFFFFFFFF RESERVED These bits are unused and are always 0. [2:0] Status These bits give the actual status information about the I 2C interface. [7:3] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x008 read-write 0x00 0xFFFFFFFF Data This register holds data values that have been received or are to be transmitted. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x00C read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x010 read-write 0x04 0xFFFFFFFF SCLH Count for SCL HIGH time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x014 read-write 0x04 0xFFFFFFFF SCLL Count for SCL low time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x018 write-only 0 0x00000000 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AAC Assert acknowledge Clear bit. [2:2] SIC I2C interrupt Clear bit. [3:3] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:4] STAC START flag Clear bit. [5:5] I2ENC I2C interface Disable bit. [6:6] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] MMCTRL Monitor mode control register. 0x01C read-write 0x00 0xFFFFFFFF MM_ENA Monitor mode enable. [0:0] ENUM MONITOR_MODE_DISABLE Monitor mode disabled. 0 THE_I_2C_MODULE_WILL The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. [1:1] ENUM WHEN_THIS_BIT_IS_CLE When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 WHEN_THIS_BIT_IS_SET When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. [2:2] ENUM WHEN_THIS_BIT_IS_CLE When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 WHEN_THIS_BIT_IS_SET When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 RESERVED Reserved. The value read from reserved bits is not defined. [31:3] 3 0x4 1-3 ADR%s I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x020 read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x02C read-only 0x00 0xFFFFFFFF Data This register holds contents of the 8 MSBs of the DAT shift register. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] 4 0x4 0-3 MASK[%s] MASK[%s] I2C Slave address mask register 0x030 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. [0:0] MASK Mask bits. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] COMPARATOR Comparators COMPARATOR 0x40020000 0x0 0xFFF registers CMP0 41 CMP1 42 CTRL Comparator block control register 0x000 read-write 0 0xFFFFFFFF CMP_PD_IREF Controls the current source used by the comparators. These bits must be set when either comparator is used. [1:0] ENUM DISABLED The comparator current source is disabled. 0x0 DIS_DEEPSLP_PWRDWN The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes. 0x1 DIS_PWRDWN The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down. 0x2 ENABLED The comparator current source is powered up. 0x3 CMP_PD_VBG Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used. [3:2] ENUM DISABLED The comparator bandgap reference is disabled. 0x0 DIS_DEEPSLP_PWRDWN The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes. 0x1 DIS_PWRDWN The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down. 0x2 ENABLED The comparator bandgap reference is powered up. 0x3 CMP_VTEMP Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used. [5:4] ENUM DISABLED The temperature sensor voltage reference is disabled. 0x0 DIS_DEEPSLP_PWRDWN The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes. 0x1 DIS_PWRDWN The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down. 0x2 ENABLED The temperature sensor voltage reference is powered up. 0x3 CMP_TEMPSEN Enables the temperature sensor. These bits must be set when the temperature sensor is used. [7:6] ENUM DISABLED Temperature sensor is disabled. 0x0 DIS_DEEPSLP_PWRDWN The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes. 0x1 DIS_PWRDWN The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down. 0x2 ENABLED Temperature sensor is enabled. 0x3 CMP_ROSCCTL Selects the inputs for the flip/flops that provide the CMP_ROSC output. [8:8] ENUM CMP1 The CMP_ROSC output is set by CMP1 and reset by CMP0. 0 CMP0 The CMP_ROSC output is set by CMP0 and reset by CMP1. 1 CMP_EXT_RESET Selects the reset source for the CMP_ROSC output. [9:9] ENUM INTRESET The CMP_ROSC output is reset by the internal chip reset. 0 CMP_RESETIN The CMP_ROSC output is reset by the CMP_RESET input. 1 RESERVED Reserved. [11:10] CMP_T0CAP2 Selects the input for Timer 0 capture input 2. [12:12] ENUM COMP0 T0CAP2 is connected to comparator 0 level output. 0 COMP1 T0CAP2 is connected to comparator 1 level output. 1 CMP_T0CAP3 Selects the input for Timer 0 capture input 3. [13:13] ENUM COMP0 T0CAP3 is connected to comparator 0 edge output. 0 COMP1 T0CAP3 is connected to comparator 1 edge output. 1 CMP_T1CAP2 Selects the input for Timer 1 capture input 2. [14:14] ENUM COMP1 T1CAP2 is connected to comparator 1 edge output. 0 COMP0 T1CAP2 is connected to comparator 0 level output. 1 CMP_T1CAP3 Selects the input for Timer 1 capture input 3. [15:15] ENUM COMP1 T1CAP3 is connected to comparator 1 level output. 0 COMP0 T1CAP3 is connected to comparator 0 edge output. 1 RESERVED Reserved. [31:16] CTRL0 Comparator 0 control register 0x004 read-write 0 0xFFFFFFFF CMP0_EN Comparator 0 enable control. [1:0] ENUM DISABLED Comparator 0 disabled. 0x0 DIS_DEEPSLP_PWRDWN Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes. 0x1 DIS_PWRDWN Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down. 0x2 ENABLED Comparator 0 is enabled. 0x3 CMP0_OE Comparator 0 output enable. [2:2] ENUM DISABLED Comparator 0 output is disabled. 0 ENABLED Comparator 0 output is enabled. 1 CMP0_STAT Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE. [3:3] CMP0_VM Comparator 0 VM input select. [6:4] ENUM VREF_DIVIDER_0_ Vref divider 0. 0x0 CMP0_IN0 CMP0_IN[0]. 0x1 CMP0_IN1 CMP0_IN[1]. 0x2 CMP0_IN2 CMP0_IN[2]. 0x3 CMP0_IN3 CMP0_IN[3]. 0x4 CMP1_IN0 CMP1_IN[0]. 0x5 INTERNAL_0_9_V_BAND_ internal 0.9 V band gap reference. 0x6 TEMPERATURE_SENSOR_ temperature sensor. 0x7 RESERVED Reserved. [7:7] CMP0_VP Comparator 0 VP input select. [10:8] ENUM VREF_DIVIDER_0_ Vref divider 0. 0x0 CMP0_IN0 CMP0_IN[0]. 0x1 CMP0_IN1 CMP0_IN[1]. 0x2 CMP0_IN2 CMP0_IN[2]. 0x3 CMP0_IN3 CMP0_IN[3]. 0x4 CMP1_IN0 CMP1_IN[0]. 0x5 INTERNAL_0_9_V_BAND_ internal 0.9 V band gap reference. 0x6 TEMPERATURE_SENSOR_ temperature sensor. 0x7 RESERVED Reserved. [11:11] CMP0_SYNC Comparator 0 output synchronization control. [12:12] ENUM DIRECT The comparator 0 output is used directly. 0 SYNCH The comparator 0 output is synchronized with the internal bus clock for output to other peripherals. 1 CMP0_HYS Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESISOFF Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV_ Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV_ Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV_ Hysteresis = 15 mV. 0x3 CMP0_INTPOL Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412. [15:15] ENUM NOTINVERTED The CMP0 output is used as-is for generating interrupts. 0 INVERTED The CMP0 output is used inverted for generating interrupts. 1 CMP0_INTTYPE Select comparator 0 interrupt type. See Table 412. [16:16] ENUM EDGE Comparator 0 interrupt is edge triggered. 0 LEVEL Comparator 0 interrupt is level triggered. 1 CMP0_INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412. [18:17] ENUM FALLING Comparator 0 interrupt is active on falling edges. 0x0 RISING Comparator 0 interrupt is active on rising edges. 0x1 DUALEDGE Comparator 0 Interrupt is active on both edges. 0x2 RESERVED_ reserved. 0x3 CMP0_INTFLAG Comparator 0 interrupt flag. [19:19] ENUM NOTPENDING The Comparator 0 interrupt is not pending. 0 PENDING The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag. 1 CMP0_VLADEN Voltage ladder enable for comparator 0. [21:20] ENUM DISABLED The Comparator 0 voltage ladder is disabled. 0x0 DIS_DEEPSLP_PWRDWN The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes. 0x1 DIS_PWRDWN The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down. 0x2 ENABLED The Comparator 0 voltage ladder is enabled. 0x3 CMP0_VLADREF Voltage reference select for comparator 0 voltage ladder. [22:22] ENUM VREF_CMP_PIN_ VREF_CMP pin. 0 VDDA_PIN_ VDDA pin. 1 RESERVED Reserved. [23:23] CMP0_VSEL Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0 [28:24] RESERVED Reserved. [31:29] CTRL1 Comparator 1 control register 0x008 read-write 0 0xFFFFFFFF CMP1_EN Comparator 1 enable control. [1:0] ENUM DISABLED Comparator 1 disabled. 0x0 DIS_DEEPSLP_PWRDWN Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes. 0x1 DIS_PWRDWN Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down. 0x2 ENABLED Comparator 1 is enabled. 0x3 CMP1_OE Comparator 1 output enable. [2:2] ENUM DISABLED Comparator 1 output is disabled. 0 ENABLED Comparator 1 output is enabled. 1 CMP1_STAT Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE. [3:3] CMP1_VM Comparator 1 VM input select. [6:4] ENUM VREF_DIVIDER_1_ Vref divider 1. 0x0 CMP1_IN0 CMP1_IN[0]. 0x1 CMP1_IN1 CMP1_IN[1]. 0x2 CMP1_IN2 CMP1_IN[2]. 0x3 CMP1_IN3 CMP1_IN[3]. 0x4 CMP0_IN0 CMP0_IN[0]. 0x5 INTERNAL_0_9_V_BAND_ internal 0.9 V band gap reference. 0x6 TEMPERATURE_SENSOR_ temperature sensor. 0x7 RESERVED Reserved. [7:7] CMP1_VP Comparator 1 VP input select. [10:8] ENUM VREF_DIVIDER_0_ Vref divider 0. 0x0 CMP1_IN0 CMP1_IN[0]. 0x1 CMP1_IN1 CMP1_IN[1]. 0x2 CMP1_IN2 CMP1_IN[2]. 0x3 CMP1_IN3 CMP1_IN[3]. 0x4 CMP0_IN0 CMP0_IN[0]. 0x5 INTERNAL_0_9_V_BAND_ internal 0.9 V band gap reference. 0x6 TEMPERATURE_SENSOR_ temperature sensor. 0x7 RESERVED Reserved. [11:11] CMP1_SYNC Comparator 1 output synchronization control. [12:12] ENUM DIRECT The comparator 1 output is used directly. 0 SYNCH The comparator 1 output is synchronized with the internal bus clock for output to other peripherals. 1 CMP1_HYS Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output. [14:13] ENUM HYSTERESISOFF Hysteresis is turned off, comparator output will change as the input voltages cross. 0x0 HYSTERESIS_EQ_5_MV_ Hysteresis = 5 mV. 0x1 HYSTERESIS_EQ_10_MV_ Hysteresis = 10 mV. 0x2 HYSTERESIS_EQ_15_MV_ Hysteresis = 15 mV. 0x3 CMP1_INTPOL Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412. [15:15] ENUM NOTINVERTED The CMP1 output is used as-is for generating interrupts. 0 INVERTED The CMP1 output is used inverted for generating interrupts. 1 CMP1_INTTYPE Select comparator 1 interrupt type. See Table 412. [16:16] ENUM EDGE Comparator 1 interrupt is edge triggered. 0 LEVEL Comparator 1 interrupt is level triggered. 1 CMP1_INTEDGE Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412. [18:17] ENUM FALLING Comparator 1 interrupt is active on falling edges. 0x0 RISING Comparator 1 interrupt is active on rising edges. 0x1 DUALEDGE Comparator 1 Interrupt is active on both edges. 0x2 RESERVED_ reserved. 0x3 CMP1_INTFLAG Comparator 1 interrupt flag. [19:19] ENUM NOTPENDING The Comparator 1 interrupt is not pending. 0 PENDING The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag. 1 CMP1_VLADEN Voltage ladder enable for comparator 1. [21:20] ENUM DISABLED The Comparator 1 voltage ladder is disabled. 0x0 DIS_DEEPSLP_PWRDWN The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes. 0x1 DIS_PWRDWN The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down. 0x2 ENABLED The Comparator 1 voltage ladder is enabled. 0x3 CMP1_VLADREF Voltage reference select for comparator 1 voltage ladder. [22:22] ENUM VREF_CMP_PIN_ VREF_CMP pin. 0 VDDA_PIN_ VDDA pin. 1 RESERVED Reserved. [23:23] CMP1_VSel Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1. [28:24] RESERVED Reserved. [31:29] RTC Real Time Clock (RTC) RTC 0x40024000 0x0 0xFFF registers RTC 17 ILR Interrupt Location Register 0x000 read-write 0 0xFFFFFFFF RTCCIF When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. [0:0] RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. [1:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:21] CCR Clock Control Register 0x008 read-write 0 0x00000000 CLKEN Clock Enable. [0:0] ENUM THE_TIME_COUNTERS_AR The time counters are enabled. 1 THE_TIME_COUNTERS_AR The time counters are disabled so that they may be initialized. 0 CTCRST CTC Reset. [1:1] ENUM RESET When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. 1 NO_EFFECT_ No effect. 0 RESERVED Internal test mode controls. These bits must be 0 for normal RTC operation. [3:2] CCALEN Calibration counter enable. [4:4] ENUM THE_CALIBRATION_COUN The calibration counter is disabled and reset to zero. 1 THE_CALIBRATION_COUN The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] CIIR Counter Increment Interrupt Register 0x00C read-write 0 0xFFFFFFFF IMSEC When 1, an increment of the Second value generates an interrupt. [0:0] IMMIN When 1, an increment of the Minute value generates an interrupt. [1:1] IMHOUR When 1, an increment of the Hour value generates an interrupt. [2:2] IMDOM When 1, an increment of the Day of Month value generates an interrupt. [3:3] IMDOW When 1, an increment of the Day of Week value generates an interrupt. [4:4] IMDOY When 1, an increment of the Day of Year value generates an interrupt. [5:5] IMMON When 1, an increment of the Month value generates an interrupt. [6:6] IMYEAR When 1, an increment of the Year value generates an interrupt. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] AMR Alarm Mask Register 0x010 read-write 0 0xFFFFFFFF AMRSEC When 1, the Second value is not compared for the alarm. [0:0] AMRMIN When 1, the Minutes value is not compared for the alarm. [1:1] AMRHOUR When 1, the Hour value is not compared for the alarm. [2:2] AMRDOM When 1, the Day of Month value is not compared for the alarm. [3:3] AMRDOW When 1, the Day of Week value is not compared for the alarm. [4:4] AMRDOY When 1, the Day of Year value is not compared for the alarm. [5:5] AMRMON When 1, the Month value is not compared for the alarm. [6:6] AMRYEAR When 1, the Year value is not compared for the alarm. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] CTIME0 Consolidated Time Register 0 0x014 read-only 0 0x00000000 SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved. The value read from a reserved bit is not defined. [7:6] MINUTES Minutes value in the range of 0 to 59 [13:8] RESERVED Reserved. The value read from a reserved bit is not defined. [15:14] HOURS Hours value in the range of 0 to 23 [20:16] RESERVED Reserved. The value read from a reserved bit is not defined. [23:21] DOW Day of week value in the range of 0 to 6 [26:24] RESERVED Reserved. The value read from a reserved bit is not defined. [31:27] CTIME1 Consolidated Time Register 1 0x018 read-only 0 0x00000000 DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved. The value read from a reserved bit is not defined. [7:5] MONTH Month value in the range of 1 to 12. [11:8] RESERVED Reserved. The value read from a reserved bit is not defined. [15:12] YEAR Year value in the range of 0 to 4095. [27:16] RESERVED Reserved. The value read from a reserved bit is not defined. [31:28] CTIME2 Consolidated Time Register 2 0x01C read-only 0 0x00000000 DOY Day of year value in the range of 1 to 365 (366 for leap years). [11:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:12] SEC Seconds Counter 0x020 read-write 0 0x00000000 SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] MIN Minutes Register 0x024 read-write 0 0x00000000 MINUTES Minutes value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] HRS Hours Register 0x028 read-write 0 0x00000000 HOURS Hours value in the range of 0 to 23 [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DOM Day of Month Register 0x02C read-write 0 0x00000000 DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DOW Day of Week Register 0x030 read-write 0 0x00000000 DOW Day of week value in the range of 0 to 6. [2:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] DOY Day of Year Register 0x034 read-write 0 0x00000000 DOY Day of year value in the range of 1 to 365 (366 for leap years). [8:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] MONTH Months Register 0x038 read-write 0 0x00000000 MONTH Month value in the range of 1 to 12. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] YEAR Years Register 0x03C read-write 0 0x00000000 YEAR Year value in the range of 0 to 4095. [11:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CALIBRATION Calibration Value Register 0x040 read-write 0 0x00000000 CALVAL If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. [16:0] CALDIR Calibration direction [17:17] ENUM BACKWARD_CALIBRATION Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. 1 FORWARD_CALIBRATION_ Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. 0 5 0x4 0-4 GPREG%s General Purpose Register 0 0x044 read-write 0 0x00000000 GP General purpose storage. [31:0] RTC_AUX RTC Auxiliary control register 0x05C read-write 0x10 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [3:0] RTC_OSCF RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] RTC_PDOUT When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] RTC_AUXEN RTC Auxiliary Enable register 0x058 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [3:0] RTC_OSCFEN Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] ASEC Alarm value for Seconds 0x060 read-write 0 0x00000000 SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] AMIN Alarm value for Minutes 0x64 read-write 0 0x00000000 MINUTES Minutes value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] AHRS Alarm value for Hours 0x068 read-write 0 0x00000000 HOURS Hours value in the range of 0 to 23 [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] ADOM Alarm value for Day of Month 0x06C read-write 0 0x00000000 DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] ADOW Alarm value for Day of Week 0x070 read-write 0 0x00000000 DOW Day of week value in the range of 0 to 6. [2:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] ADOY Alarm value for Day of Year 0x074 read-write 0 0x00000000 DOY Day of year value in the range of 1 to 365 (366 for leap years). [8:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] AMON Alarm value for Months 0x078 read-write 0 0x00000000 MONTH Month value in the range of 1 to 12. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] AYRS Alarm value for Year 0x07C read-write 0 0x00000000 YEAR Year value in the range of 0 to 4095. [11:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] ERCONTROL Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup. 0x084 read-write 0 0xFFFFFFFF INTWAKE_EN0 Interrupt and wakeup enable for channel 0. [0:0] ENUM NO_INTERRUPT_OR_WAKE No interrupt or wakeup will be generated by event channel 0. 0 AN_EVENT_IN_CHANNEL_ An event in channel 0 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN0 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0. [1:1] ENUM NOGPREG Channel 0 has no influence on the general purpose registers. 0 CLRGPREG An event in channel 0 will clear the general purpose registers asynchronously. 1 POL0 Selects the polarity of an event on input pin RTC_EV0. [2:2] ENUM NEG A channel 0 event is defined as a negative edge on RTC_EV0. 0 POS A channel 0 event is defined as a positive edge on RTC_EV0. 1 EV0_INPUT_EN Event enable control for channel 0.[1] [3:3] ENUM DISABLED Event 0 input is disabled and forced high internally. 0 ENABLED Event 0 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [9:4] INTWAKE_EN1 Interrupt and wakeup enable for channel 1. [10:10] ENUM NO_INTERRUPT_OR_WAKE No interrupt or wakeup will be generated by event channel 1. 0 WAKEUP An event in channel 1 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN1 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1. [11:11] ENUM NOGPREG Channel 1 has no influence on the general purpose registers. 0 CLRGPREG A n event in channel 1 will clear the general purpose registers asynchronously. 1 POL1 Selects the polarity of an event on input pin RTC_EV1. [12:12] ENUM NEG A channel 1 event is defined as a negative edge on RTC_EV1. 0 POS A channel 1 event is defined as a positive edge on RTC_EV1. 1 EV1_INPUT_EN Event enable control for channel 1.[1] [13:13] ENUM DISABLED Event 1 input is disabled and forced high internally. 0 ENABLED Event 1 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [19:14] INTWAKE_EN2 Interrupt and wakeup enable for channel 2. [20:20] ENUM NO_INTERRUPT_OR_WAKE No interrupt or wakeup will be generated by event channel 2. 0 WAKEUP An event in channel 2 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN2 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2. [21:21] ENUM NOGPREG Channel 2 has no influence on the general purpose registers. 0 CLRGPREG An event in channel 2 will clear the general purpose registers asynchronously. 1 POL2 Selects the polarity of an event on input pin RTC_EV2. [22:22] ENUM NEG A channel 2 event is defined as a negative edge on RTC_EV2. 0 POS A channel 2 event is defined as a positive edge on RTC_EV2. 1 EV2_INPUT_EN Event enable control for channel 2.[1] [23:23] ENUM DISABLED Event 2 input is disabled and forced high internally. 0 ENABLED Event 2 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [29:24] ERMODE Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2] [31:30] ENUM DISABLED Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected. 0x0 ENABLE_EVENT_MONITOR16HZ Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out. 0x1 ENABLE_EVENT_MONITOR64HZ Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out. 0x2 ENABLE_EVENT_MONITOR1KHZ Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out. 0x3 ERSTATUS Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions. 0x080 read-write 0 0xFFFFFFFF EV0 Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [0:0] ENUM NO_EVENT_CHANGE_ON_C No event change on channel 0. 0 AT_LEAST_ONE_EVENT_H At least one event has occurred on channel 0. 1 EV1 Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [1:1] ENUM NO_EVENT_CHANGE_ON_C No event change on channel 1. 0 AT_LEAST_ONE_EVENT_H At least one event has occurred on channel 1. 1 EV2 Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [2:2] ENUM NO_EVENT_CHANGE_ON_C No event change on channel 2. 0 AT_LEAST_ONE_EVENT_H At least one event has occurred on channel 2. 1 GP_CLEARED General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [3:3] ENUM NOGPCLR General purpose registers have not been asynchronous cleared. 0 GPCLR General purpose registers have been asynchronous cleared. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [30:4] WAKEUP Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect. [31:31] ENUM NO_INTERRUPTWAKEUP_ No interrupt/wakeup request is pending 0 INTWAKEUP_PEND An interrupt/wakeup request is pending. 1 ERCOUNTERS Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels. 0x088 read-only 0 0xFFFFFFFF COUNTER0 Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software. [2:0] RESERVED Reserved. The value read from a reserved bit is not defined. [7:3] COUNTER1 Value of the counter for event 1. See description for COUNTER0. [10:8] RESERVED Reserved. The value read from a reserved bit is not defined. [15:11] COUNTER2 Value of the counter for event 2. See description for COUNTER0. [18:16] RESERVED Reserved. The value read from a reserved bit is not defined. [31:19] 3 0x4 0-2 ERFIRSTSTAMP%s Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0. 0x090 read-only 0 0x00000000 SEC Seconds value in the range of 0 to 59. [5:0] MIN Minutes value in the range of 0 to 59. [11:6] HOUR Hours value in the range of 0 to 23. [16:12] DOY Day of Year value in the range of 1 to 366. [25:17] RESERVED Reserved. The value read from a reserved bit is not defined. [31:26] 3 0x4 0-2 ERLASTSTAMP%s Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0. 0x0A0 read-only 0 0x00000000 SEC Seconds value in the range of 0 to 59. [5:0] MIN Minutes value in the range of 0 to 59. [11:6] HOUR Hours value in the range of 0 to 23. [16:12] DOY Day of Year value in the range of 1 to 366. [25:17] RESERVED Reserved. The value read from a reserved bit is not defined. [31:26] GPIOINT GPIO GPIOINT 0x40028080 0x0 0xFFF registers GPIOINT 38 STATUS GPIO overall Interrupt Status. 0x000 read-only 0 0xFFFFFFFF P0Int Port 0 GPIO interrupt pending. [0:0] ENUM NO_PENDING_INTERRUPT No pending interrupts on Port 0. 0 AT_LEAST_ONE_PENDING At least one pending interrupt on Port 0. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [1:1] P2Int Port 2 GPIO interrupt pending. [2:2] ENUM NO_PENDING_INTERRUPT No pending interrupts on Port 2. 0 AT_LEAST_ONE_PENDING At least one pending interrupt on Port 2. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:2] STATR0 GPIO Interrupt Status for Rising edge for Port 0. 0x004 read-only 0 0xFFFFFFFF P0_0REI Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [0:0] P0_1REI Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [1:1] P0_2REI Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [2:2] P0_3REI Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [3:3] P0_4REI Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [4:4] P0_5REI Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [5:5] P0_6REI Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [6:6] P0_7REI Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [7:7] P0_8REI Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [8:8] P0_9REI Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [9:9] P0_10REI Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [10:10] P0_11REI Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [11:11] P0_12REI Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [12:12] P0_13REI Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [13:13] P0_14REI Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [14:14] P0_15REI Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [15:15] P0_16REI Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [16:16] P0_17REI Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [17:17] P0_18REI Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [18:18] P0_19REI Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [19:19] P0_20REI Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [20:20] P0_21REI Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [21:21] P0_22REI Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [22:22] P0_23REI Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [23:23] P0_24REI Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [24:24] P0_25REI Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [25:25] P0_26REI Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [26:26] P0_27REI Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [27:27] P0_28REI Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [28:28] P0_29REI Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [29:29] P0_30REI Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [30:30] P0_31REI Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [31:31] STATF0 GPIO Interrupt Status for Falling edge for Port 0. 0x008 read-only 0 0xFFFFFFFF P0_0FEI Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [0:0] P0_1FEI Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [1:1] P0_2FEI Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [2:2] P0_3FEI Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [3:3] P0_4FEI Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [4:4] P0_5FEI Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [5:5] P0_6FEI Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [6:6] P0_7FEI Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [7:7] P0_8FEI Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [8:8] P0_9FEI Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [9:9] P0_10FEI Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [10:10] P0_11FEI Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [11:11] P0_12FEI Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [12:12] P0_13FEI Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [13:13] P0_14FEI Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [14:14] P0_15FEI Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [15:15] P0_16FEI Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [16:16] P0_17FEI Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [17:17] P0_18FEI Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [18:18] P0_19FEI Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [19:19] P0_20FEI Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [20:20] P0_21FEI Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [21:21] P0_22FEI Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [22:22] P0_23FEI Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [23:23] P0_24FEI Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [24:24] P0_25FEI Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [25:25] P0_26FEI Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [26:26] P0_27FEI Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [27:27] P0_28FEI Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [28:28] P0_29FEI Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [29:29] P0_30FEI Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [30:30] P0_31FEI Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [31:31] CLR0 GPIO Interrupt Clear. 0x00C write-only 0 0xFFFFFFFF P0_0CI Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [0:0] P0_1CI Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [1:1] P0_2CI Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [2:2] P0_3CI Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [3:3] P0_4CI Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [4:4] P0_5CI Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [5:5] P0_6CI Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [6:6] P0_7CI Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [7:7] P0_8CI Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [8:8] P0_9CI Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [9:9] P0_10CI Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [10:10] P0_11CI Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [11:11] P0_12CI Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [12:12] P0_13CI Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [13:13] P0_14CI Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [14:14] P0_15CI Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [15:15] P0_16CI Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [16:16] P0_17CI Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [17:17] P0_18CI Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [18:18] P0_19CI Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [19:19] P0_20CI Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [20:20] P0_21CI Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [21:21] P0_22CI Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [22:22] P0_23CI Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [23:23] P0_24CI Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [24:24] P0_25CI Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [25:25] P0_26CI Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [26:26] P0_27CI Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [27:27] P0_28CI Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [28:28] P0_29CI Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [29:29] P0_30CI Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [30:30] P0_31CI Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [31:31] ENR0 GPIO Interrupt Enable for Rising edge for Port 0. 0x010 read-write 0 0xFFFFFFFF P0_0ER Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [0:0] P0_1ER Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [1:1] P0_2ER Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [2:2] P0_3ER Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [3:3] P0_4ER Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [4:4] P0_5ER Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [5:5] P0_6ER Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [6:6] P0_7ER Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [7:7] P0_8ER Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [8:8] P0_9ER Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [9:9] P0_10ER Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [10:10] P0_11ER Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [11:11] P0_12ER Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [12:12] P0_13ER Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [13:13] P0_14ER Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [14:14] P0_15ER Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [15:15] P0_16ER Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [16:16] P0_17ER Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [17:17] P0_18ER Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [18:18] P0_19ER Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [19:19] P0_20ER Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [20:20] P0_21ER Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [21:21] P0_22ER Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [22:22] P0_23ER Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [23:23] P0_24ER Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [24:24] P0_25ER Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [25:25] P0_26ER Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [26:26] P0_27ER Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [27:27] P0_28ER Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [28:28] P0_29ER Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [29:29] P0_30ER Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [30:30] P0_31ER Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [31:31] ENF0 GPIO Interrupt Enable for Falling edge for Port 0. 0x014 read-write 0 0xFFFFFFFF P0_0EF Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [0:0] P0_1EF Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [1:1] P0_2EF Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [2:2] P0_3EF Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [3:3] P0_4EF Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [4:4] P0_5EF Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [5:5] P0_6EF Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [6:6] P0_7EF Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [7:7] P0_8EF Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [8:8] P0_9EF Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [9:9] P0_10EF Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [10:10] P0_11EF Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [11:11] P0_12EF Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [12:12] P0_13EF Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [13:13] P0_14EF Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [14:14] P0_15EF Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [15:15] P0_16EF Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [16:16] P0_17EF Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [17:17] P0_18EF Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [18:18] P0_19EF Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [19:19] P0_20EF Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [20:20] P0_21EF Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [21:21] P0_22EF Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [22:22] P0_23EF Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [23:23] P0_24EF Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [24:24] P0_25EF Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [25:25] P0_26EF Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [26:26] P0_27EF Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [27:27] P0_28EF Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [28:28] P0_29EF Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [29:29] P0_30EF Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [30:30] P0_31EF Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [31:31] STATR2 GPIO Interrupt Status for Rising edge for Port 0. 0x024 read-only 0 0xFFFFFFFF P2_0REI Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [0:0] P2_1REI Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [1:1] P2_2REI Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [2:2] P2_3REI Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [3:3] P2_4REI Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [4:4] P2_5REI Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [5:5] P2_6REI Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [6:6] P2_7REI Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [7:7] P2_8REI Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [8:8] P2_9REI Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [9:9] P2_10REI Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [10:10] P2_11REI Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [11:11] P2_12REI Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [12:12] P2_13REI Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [13:13] P2_14REI Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [14:14] P2_15REI Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [15:15] P2_16REI Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [16:16] P2_17REI Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [17:17] P2_18REI Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [18:18] P2_19REI Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [19:19] P2_20REI Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [20:20] P2_21REI Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [21:21] P2_22REI Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [22:22] P2_23REI Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [23:23] P2_24REI Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [24:24] P2_25REI Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [25:25] P2_26REI Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [26:26] P2_27REI Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [27:27] P2_28REI Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [28:28] P2_29REI Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [29:29] P2_30REI Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [30:30] P2_31REI Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated. [31:31] STATF2 GPIO Interrupt Status for Falling edge for Port 0. 0x028 read-only 0 0xFFFFFFFF P2_0FEI Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [0:0] P2_1FEI Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [1:1] P2_2FEI Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [2:2] P2_3FEI Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [3:3] P2_4FEI Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [4:4] P2_5FEI Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [5:5] P2_6FEI Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [6:6] P2_7FEI Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [7:7] P2_8FEI Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [8:8] P2_9FEI Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [9:9] P2_10FEI Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [10:10] P2_11FEI Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [11:11] P2_12FEI Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [12:12] P2_13FEI Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [13:13] P2_14FEI Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [14:14] P2_15FEI Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [15:15] P2_16FEI Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [16:16] P2_17FEI Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [17:17] P2_18FEI Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [18:18] P2_19FEI Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [19:19] P2_20FEI Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [20:20] P2_21FEI Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [21:21] P2_22FEI Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [22:22] P2_23FEI Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [23:23] P2_24FEI Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [24:24] P2_25FEI Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [25:25] P2_26FEI Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [26:26] P2_27FEI Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [27:27] P2_28FEI Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [28:28] P2_29FEI Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [29:29] P2_30FEI Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [30:30] P2_31FEI Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated. [31:31] CLR2 GPIO Interrupt Clear. 0x02C write-only 0 0xFFFFFFFF P2_0CI Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [0:0] P2_1CI Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [1:1] P2_2CI Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [2:2] P2_3CI Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [3:3] P2_4CI Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [4:4] P2_5CI Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [5:5] P2_6CI Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [6:6] P2_7CI Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [7:7] P2_8CI Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [8:8] P2_9CI Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [9:9] P2_10CI Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [10:10] P2_11CI Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [11:11] P2_12CI Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [12:12] P2_13CI Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [13:13] P2_14CI Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [14:14] P2_15CI Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [15:15] P2_16CI Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [16:16] P2_17CI Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [17:17] P2_18CI Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [18:18] P2_19CI Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [19:19] P2_20CI Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [20:20] P2_21CI Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [21:21] P2_22CI Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [22:22] P2_23CI Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [23:23] P2_24CI Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [24:24] P2_25CI Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [25:25] P2_26CI Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [26:26] P2_27CI Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [27:27] P2_28CI Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [28:28] P2_29CI Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [29:29] P2_30CI Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [30:30] P2_31CI Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF. [31:31] ENR2 GPIO Interrupt Enable for Rising edge for Port 0. 0x030 read-write 0 0xFFFFFFFF P2_0ER Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [0:0] P2_1ER Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [1:1] P2_2ER Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [2:2] P2_3ER Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [3:3] P2_4ER Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [4:4] P2_5ER Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [5:5] P2_6ER Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [6:6] P2_7ER Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [7:7] P2_8ER Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [8:8] P2_9ER Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [9:9] P2_10ER Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [10:10] P2_11ER Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [11:11] P2_12ER Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [12:12] P2_13ER Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [13:13] P2_14ER Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [14:14] P2_15ER Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [15:15] P2_16ER Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [16:16] P2_17ER Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [17:17] P2_18ER Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [18:18] P2_19ER Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [19:19] P2_20ER Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [20:20] P2_21ER Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [21:21] P2_22ER Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [22:22] P2_23ER Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [23:23] P2_24ER Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [24:24] P2_25ER Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [25:25] P2_26ER Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [26:26] P2_27ER Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [27:27] P2_28ER Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [28:28] P2_29ER Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [29:29] P2_30ER Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [30:30] P2_31ER Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt. [31:31] ENF2 GPIO Interrupt Enable for Falling edge for Port 0. 0x034 read-write 0 0xFFFFFFFF P2_0EF Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [0:0] P2_1EF Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [1:1] P2_2EF Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [2:2] P2_3EF Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [3:3] P2_4EF Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [4:4] P2_5EF Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [5:5] P2_6EF Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [6:6] P2_7EF Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [7:7] P2_8EF Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [8:8] P2_9EF Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [9:9] P2_10EF Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [10:10] P2_11EF Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [11:11] P2_12EF Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [12:12] P2_13EF Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [13:13] P2_14EF Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [14:14] P2_15EF Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [15:15] P2_16EF Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [16:16] P2_17EF Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [17:17] P2_18EF Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [18:18] P2_19EF Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [19:19] P2_20EF Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [20:20] P2_21EF Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [21:21] P2_22EF Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [22:22] P2_23EF Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [23:23] P2_24EF Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [24:24] P2_25EF Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [25:25] P2_26EF Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [26:26] P2_27EF Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [27:27] P2_28EF Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [28:28] P2_29EF Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [29:29] P2_30EF Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [30:30] P2_31EF Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt. [31:31] IOCON IOCON pin configuration 0x4002C000 0x0 0xFFF registers P0_0 I/O configuration register for pin P0[0] 0x0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[0] [2:0] ENUM P0_0 General purpose digital input/output pin. 0x0 CAN_RD1 CAN1 receiver input. 0x1 U3_TXD Transmitter output for UART3. 0x2 I2C1_SDA I2C1 data input/output (this pin does not use a specialized I2C pad). 0x3 U0_TXD Transmitter output for UART0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_1 I/O configuration register for pin P0[1] 0x4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[1] [2:0] ENUM P0_1 General purpose digital input/output pin. 0x0 CAN_TD1 CAN1 transmitter output. 0x1 U3_RXD Receiver input for UART3. 0x2 I2C1_SCL I2C1 clock input/output (this pin does not use a specialized I2C pad). 0x3 U0_RXD Receiver input for UART0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_2 I/O configuration register for pin P0[2] 0x8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[2] [2:0] ENUM P0_2 General purpose digital input/output pin. 0x0 U0_TXD Transmitter output for UART0. 0x1 U3_TXD Transmitter output for UART3. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_3 I/O configuration register for pin P0[3] 0xC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[3] [2:0] ENUM P0_3 General purpose digital input/output pin. 0x0 U0_RXD Receiver input for UART0. 0x1 U3_RXD Receiver input for UART3. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_4 I/O configuration register for pin P0[4] 0x10 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[4] [2:0] ENUM P0_4 General purpose digital input/output pin. 0x0 I2S_RX_SCK I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. 0x1 CAN_RD2 CAN2 receiver input. 0x2 T2_CAP0 Capture input for Timer 2, channel 0. 0x3 CMP_ROSC Comparator relaxation oscillator for 555 timer applications. 0x5 LCD_VD_0 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_5 I/O configuration register for pin P0[5] 0x14 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[5] [2:0] ENUM P0_5 General purpose digital input/output pin. 0x0 I2S_RX_WS I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. 0x1 CAN_TD2 CAN2 transmitter output. 0x2 T2_CAP1 Capture input for Timer 2, channel 1. 0x3 CMP_RESET Comparator reset. 0x5 LCD_VD_1 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_6 I/O configuration register for pin P0[6] 0x18 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[6] [2:0] ENUM P0_6 General purpose digital input/output pin. 0x0 I2S_RX_SDA I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. 0x1 SSP1_SSEL Slave Select for SSP1. 0x2 T2_MAT0 Match output for Timer 2, channel 0. 0x3 U1_RTS Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x4 CMP_ROSC Comparator relaxation oscillator for 555 timer applications. 0x5 LCD_VD_8 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_7 I/O configuration register for pin P0[7] 0x1C read-write 0x000000A0 0xFFFFFFFF FUNC Selects pin function for pin P0[7] [2:0] ENUM P0_7 General purpose digital input/output pin. 0x0 I2S_TX_SCK I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. 0x1 SSP1_SCK Serial Clock for SSP1. 0x2 T2_MAT1 Match output for Timer 2, channel 1. 0x3 RTC_EV0 Event input 0 to Event Monitor/Recorder. 0x4 CMP_VREF Comparator reference voltage. 0x5 LCD_VD_9 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTER Glitch filter control [8:8] ENUM ENABLED Noise pulses below approximately 10 ns are filtered out. 0 DISABLED No input filtering is done. 1 SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_8 I/O configuration register for pin P0[8] 0x20 read-write 0x000000A0 0xFFFFFFFF FUNC Selects pin function for pin P0[8] [2:0] ENUM P0_8 General purpose digital input/output pin. 0x0 I2S_TX_WS I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. 0x1 SSP1_MISO Master In Slave Out for SSP1. 0x2 T2_MAT2 Match output for Timer 2, channel 2. 0x3 RTC_EV1 Event input 1 to Event Monitor/Recorder. 0x4 CMP1_IN_3 Comparator 1, input 3. 0x5 LCD_VD_16 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTER Glitch filter control [8:8] ENUM ENABLED Noise pulses below approximately 10 ns are filtered out. 0 DISABLED No input filtering is done. 1 SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_9 I/O configuration register for pin P0[9] 0x24 read-write 0x000000A0 0xFFFFFFFF FUNC Selects pin function for pin P0[9] [2:0] ENUM P0_9 General purpose digital input/output pin. 0x0 I2S_TX_SDA I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. 0x1 SSP1_MOSI Master Out Slave In for SSP1. 0x2 T2_MAT3 Match output for Timer 2, channel 3. 0x3 RTC_EV2 Event input 2 to Event Monitor/Recorder. 0x4 CMP1_IN_2 Comparator 1, input 2. 0x5 LCD_VD_17 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] FILTER Glitch filter control [8:8] ENUM ENABLED Noise pulses below approximately 10 ns are filtered out. 0 DISABLED No input filtering is done. 1 SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_10 I/O configuration register for pin P0[10] 0x28 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[10] [2:0] ENUM P0_10 General purpose digital input/output pin. 0x0 U2_TXD Transmitter output for UART2. 0x1 I2C2_SDA I2C2 data input/output (this pin does not use a specialized I2C pad). 0x2 T3_MAT0 Match output for Timer 3, channel 0. 0x3 LCD_VD_5 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_11 I/O configuration register for pin P0[11] 0x2C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[11] [2:0] ENUM P0_11 General purpose digital input/output pin. 0x0 U2_RXD Receiver input for UART2. 0x1 I2C2_SCL I2C2 clock input/output (this pin does not use a specialized I2C pad). 0x2 T3_MAT1 Match output for Timer 3, channel 1. 0x3 LCD_VD_10 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_12 I/O configuration register for pin P0[12] 0x30 read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[12] [2:0] ENUM P0_12 General purpose digital input/output pin. 0x0 USB_PPWR2 Port Power enable signal for USB port 2. 0x1 SSP1_MISO Master In Slave Out for SSP1. 0x2 ADC0_IN_6 A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled. 0x3 P0_13 I/O configuration register for pin P0[13] 0x34 read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[13] [2:0] ENUM P0_13 General purpose digital input/output pin. 0x0 USB_UP_LED2 USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. 0x1 SSP1_MOSI Master Out Slave In for SSP1. 0x2 ADC0_IN_7 A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled. 0x3 P0_14 I/O configuration register for pin P0[14] 0x38 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[14] [2:0] ENUM P0_14 General purpose digital input/output pin. 0x0 USB_HSTEN2 Host Enabled status for USB port 2. 0x1 SSP1_SSEL Slave Select for SSP1. 0x2 USB_CONNECT2 SoftConnect control for USB port 2. Signal used to switch an external 1.5 kW resistor under software control. Used with the SoftConnect USB feature. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_15 I/O configuration register for pin P0[15] 0x3C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[15] [2:0] ENUM P0_15 General purpose digital input/output pin. 0x0 U1_TXD Transmitter output for UART1. 0x1 SSP0_SCK Serial clock for SSP0. 0x2 SPIFI_IO_2 Data bit 0 for SPIFI. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_16 I/O configuration register for pin P0[16] 0x40 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[16] [2:0] ENUM P0_16 General purpose digital input/output pin. 0x0 U1_RXD Receiver input for UART1. 0x1 SSP0_SSEL Slave Select for SSP0. 0x2 SPIFI_IO_3 Data bit 0 for SPIFI. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_17 I/O configuration register for pin P0[17] 0x44 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[17] [2:0] ENUM P0_17 General purpose digital input/output pin. 0x0 U1_CTS Clear to Send input for UART1. 0x1 SSP0_MISO Master In Slave Out for SSP0. 0x2 SPIFI_IO_1 Data bit 0 for SPIFI. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_18 I/O configuration register for pin P0[18] 0x48 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[18] [2:0] ENUM P0_18 General purpose digital input/output pin. 0x0 U1_DCD Data Carrier Detect input for UART1. 0x1 SSP0_MOSI Master Out Slave In for SSP0. 0x2 SPIFI_IO_0 Data bit 0 for SPIFI. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_19 I/O configuration register for pin P0[19] 0x4C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[19] [2:0] ENUM P0_19 General purpose digital input/output pin. 0x0 U1_DSR Data Set Ready input for UART1. 0x1 SD_CLK Clock output line for SD card interface. 0x2 I2C1_SDA I2C1 data input/output (this pin does not use a specialized I2C pad). 0x3 LCD_VD_13 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_20 I/O configuration register for pin P0[20] 0x50 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[20] [2:0] ENUM P0_20 General purpose digital input/output pin. 0x0 U1_DTR Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x1 SD_CMD Command line for SD card interface. 0x2 I2C1_SCL I2C1 clock input/output (this pin does not use a specialized I2C pad). 0x3 LCD_VD_14 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_21 I/O configuration register for pin P0[21] 0x54 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P0[21] [2:0] ENUM P0_21 General purpose digital input/output pin. 0x0 U1_RI Ring Indicator input for UART1. 0x1 SD_PWR Power Supply Enable for external SD card power supply. 0x2 U4_OE RS-485/EIA-485 output enable signal for UART4. 0x3 CAN_RD1 CAN1 receiver input. 0x4 U4_SCLK USART 4 clock input or output in synchronous mode. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P0_22 I/O configuration register for pin P0[22] 0x58 read-write 0x000001B0 0xFFFFFFFF FUNC Selects pin function for pin P0[22] [2:0] ENUM P0_22 General purpose digital input/output pin. 0x0 U1_RTS Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x1 SD_DAT_0 Data line 0 for SD card interface. 0x2 U4_TXD Transmitter output for USART4 (input/output in smart card mode). 0x3 CAN_TD1 CAN1 transmitter output. 0x4 SPIFI_CLK Clock output for SPIFI. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] P0_23 I/O configuration register for pin P0[23] 0x5C read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[23] [2:0] ENUM P0_23 General purpose digital input/output pin. 0x0 ADC0_IN_0 A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled. 0x1 I2S_RX_SCK Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. 0x2 T3_CAP0 Capture input for Timer 3, channel 0. 0x3 P0_24 I/O configuration register for pin P0[24] 0x60 read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[24] [2:0] ENUM P0_24 General purpose digital input/output pin. 0x0 ADC0_IN_1 A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled. 0x1 I2S_RX_WS Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. 0x2 T3_CAP1 Capture input for Timer 3, channel 1. 0x3 P0_25 I/O configuration register for pin P0[25] 0x64 read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[25] [2:0] ENUM P0_25 General purpose digital input/output pin. 0x0 ADC0_IN_2 A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. 0x1 I2S_RX_SDA Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. 0x2 U3_TXD Transmitter output for UART3. 0x3 P0_26 I/O configuration register for pin P0[26] 0x68 read-write 0xFFFFFFFF FUNC Selects pin function for pin P0[26] [2:0] ENUM P0_26 General purpose digital input/output pin. 0x0 ADC0_IN_3 A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled. 0x1 DAC_OUT D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled. 0x2 U3_RXD Receiver input for UART3. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [15:11] DACEN DAC output enable. [16:16] ENUM DISABLE DAC disable. 0 ENABLE DAC enable. 1 RESERVED Reserved. [31:17] P0_27 I/O configuration register for pin P0[27] 0x6C read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin P0[27] [2:0] ENUM P0_27 General purpose digital input/output pin. 0x0 I2C0_SDA I2C0 data input/output. (This pin uses a specialized I2C pad). 0x1 USB_SDA1 I2C serial data for communication with an external USB transceiver. 0x2 RESERVED Reserved. [5:3] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] HS Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. [8:8] ENUM ENABLED I2C 50ns glitch filter and slew rate control enabled. 0 DISABLED I2C 50ns glitch filter and slew rate control disabled. 1 HIDRIVE Controls sink current capability of the pin, only for P5[2] and P5[3]. [9:9] ENUM LOWDRIVE Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGHDRIVE Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the appropriate specific device data sheet for details. 1 RESERVED Reserved. [31:10] P0_28 I/O configuration register for pin P0[28] 0x70 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin P0[28] [2:0] ENUM P0_28 General purpose digital input/output pin. 0x0 I2C0_SCL I2C0 clock input/output (this pin uses a specialized I2C pad. 0x1 USB_SCL1 I2C serial clock for communication with an external USB transceiver. 0x2 RESERVED Reserved. [5:3] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] HS Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. [8:8] ENUM ENABLED I2C 50ns glitch filter and slew rate control enabled. 0 DISABLED I2C 50ns glitch filter and slew rate control disabled. 1 HIDRIVE Controls sink current capability of the pin, only for P5[2] and P5[3]. [9:9] ENUM LOWDRIVE Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGHDRIVE Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the appropriate specific device data sheet for details. 1 RESERVED Reserved. [31:10] P0_29 I/O configuration register for pin P0[29] 0x74 read-write 0x00000000 0xFFFFFFFF FUNC Selects pin function for pin P0[29] [2:0] ENUM P0_29 General purpose digital input/output pin. 0x0 USB_DP1 USB port 1 bidirectional D+ line. 0x1 EINT0 External interrupt 0 input. 0x2 RESERVED Reserved. [31:3] P0_30 I/O configuration register for pin P0[30] 0x78 read-write 0x00000000 0xFFFFFFFF FUNC Selects pin function for pin P0[30] [2:0] ENUM P0_30 General purpose digital input/output pin. 0x0 USB_DM1 USB port 1 bidirectional D- line. 0x1 EINT1 External interrupt 1 input. 0x2 RESERVED Reserved. [31:3] P0_31 I/O configuration register for pin P0[31] 0x7C read-write 0x00000000 0xFFFFFFFF FUNC Selects pin function for pin P0[31] [2:0] ENUM P0_31 General purpose digital input/output pin. 0x0 USB_DP2 USB port 2 bidirectional D+ line. 0x1 RESERVED Reserved. [31:3] P1_0 I/O configuration register for pin P1[0] 0x80 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[0] [2:0] ENUM P1_0 General purpose digital input/output pin. 0x0 ENET_TXD0 Ethernet transmit data 0 (RMII/MII interface). 0x1 T3_CAP1 Capture input for Timer 3, channel 1. 0x3 SSP2_SCK Serial clock for SSP2. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_1 I/O configuration register for pin P1[1] 0x84 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[1] [2:0] ENUM P1_1 General purpose digital input/output pin. 0x0 ENET_TXD1 Ethernet transmit data 1 (RMII/MII interface). 0x1 T3_MAT3 Match output for Timer 3, channel 3. 0x3 SSP2_MOSI Master Out Slave In for SSP2. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_2 I/O configuration register for pin P1[2] 0x88 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[2] [2:0] ENUM P1_2 General purpose digital input/output pin. 0x0 ENET_TXD2 Ethernet transmit data 2 (MII interface). 0x1 SD_CLK Clock output line for SD card interface. 0x2 PWM0_1 Pulse Width Modulator 0, output 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_3 I/O configuration register for pin P1[3] 0x8C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[3] [2:0] ENUM P1_3 General purpose digital input/output pin. 0x0 ENET_TXD3 Ethernet transmit data 3 (MII interface). 0x1 SD_CMD Command line for SD card interface. 0x2 PWM0_2 Pulse Width Modulator 0, output 2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_4 I/O configuration register for pin P1[4] 0x90 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[4] [2:0] ENUM P1_4 General purpose digital input/output pin. 0x0 ENET_TX_EN Ethernet transmit data enable (RMII/MII interface). 0x1 T3_MAT2 Match output for Timer 3, channel 2. 0x3 SSP2_MISO Master In Slave Out for SSP2. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_5 I/O configuration register for pin P1[5] 0x94 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[5] [2:0] ENUM P1_5 General purpose digital input/output pin. 0x0 ENET_TX_ER Ethernet Transmit Error (MII interface). 0x1 SD_PWR Power Supply Enable for external SD card power supply. 0x2 PWM0_3 Pulse Width Modulator 0, output 3. 0x3 CMP1_IN_1 Comparator 1, input 1. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_6 I/O configuration register for pin P1[6] 0x98 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[6] [2:0] ENUM P1_6 General purpose digital input/output pin. 0x0 ENET_TX_CLK Ethernet Transmit Clock (MII interface). 0x1 SD_DAT_0 Data line 0 for SD card interface. 0x2 PWM0_4 Pulse Width Modulator 0, output 4. 0x3 CMP0_IN_3 Comparator 0, input 3. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_7 I/O configuration register for pin P1[7] 0x9C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[7] [2:0] ENUM P1_7 General purpose digital input/output pin. 0x0 ENET_COL Ethernet Collision detect (MII interface). 0x1 SD_DAT_1 Data line 1 for SD card interface. 0x2 PWM0_5 Pulse Width Modulator 0, output 5. 0x3 CMP1_IN_0 Comparator 1, input 0. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_8 I/O configuration register for pin P1[8] 0xA0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[8] [2:0] ENUM P1_8 General purpose digital input/output pin. 0x0 ENET_CRS_CRS_DV Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). 0x1 T3_MAT1 Match output for Timer 3, channel 1. 0x3 SSP2_SSEL Slave Select for SSP2. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_9 I/O configuration register for pin P1[9] 0xA4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[9] [2:0] ENUM P1_9 General purpose digital input/output pin. 0x0 ENET_RXD0 Ethernet receive data 0 (RMII/MII interface). 0x1 T3_MAT0 Match output for Timer 3, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_10 I/O configuration register for pin P1[10] 0xA8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[10] [2:0] ENUM P1_10 General purpose digital input/output pin. 0x0 ENET_RXD1 Ethernet receive data 1 (RMII/MII interface). 0x1 T3_CAP0 Capture input for Timer 3, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_11 I/O configuration register for pin P1[11] 0xAC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[11] [2:0] ENUM P1_11 General purpose digital input/output pin. 0x0 ENET_RXD2 Ethernet Receive Data 2 (MII interface). 0x1 SD_DAT_2 Data line 2 for SD card interface. 0x2 PWM0_6 Pulse Width Modulator 0, output 6. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_12 I/O configuration register for pin P1[12] 0xB0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[12] [2:0] ENUM P1_12 General purpose digital input/output pin. 0x0 ENET_RXD3 Ethernet Receive Data (MII interface). 0x1 SD_DAT_3 Data line 3 for SD card interface. 0x2 PWM0_CAP0 Capture input for PWM0, channel 0. 0x3 CMP1_OUT Comparator 1, output. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_13 I/O configuration register for pin P1[13] 0xB4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[13] [2:0] ENUM P1_13 General purpose digital input/output pin. 0x0 ENET_RX_DV Ethernet Receive Data Valid (MII interface). 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_14 I/O configuration register for pin P1[14] 0xB8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[14] [2:0] ENUM P1_14 General purpose digital input/output pin. 0x0 ENET_RX_ER Ethernet receive error (RMII/MII interface). 0x1 T2_CAP0 Capture input for Timer 2, channel 0. 0x3 CMP0_IN_0 Comparator 0, input 0. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_15 I/O configuration register for pin P1[15] 0xBC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[15] [2:0] ENUM P1_15 General purpose digital input/output pin. 0x0 ENET_RX_CLK_REF_CLK Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). 0x1 I2C2_SDA I2C2 data input/output (this pin does not use a specialized I2C pad). 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_16 I/O configuration register for pin P1[16] 0xC0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[16] [2:0] ENUM P1_16 General purpose digital input/output pin. 0x0 ENET_MDC Ethernet MIIM clock. 0x1 I2S_TX_MCLK I2S transmit master clock. 0x2 CMP0_IN_1 Comparator 0, input 1. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_17 I/O configuration register for pin P1[17] 0xC4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[17] [2:0] ENUM P1_17 General purpose digital input/output pin. 0x0 ENET_MDIO Ethernet MIIM data input and output. 0x1 I2S_RX_MCLK I2S receive master clock. 0x2 CMP0_IN_2 Comparator 0, input 2. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_18 I/O configuration register for pin P1[18] 0xC8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[18] [2:0] ENUM P1_18 General purpose digital input/output pin. 0x0 USB_UP_LED1 It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. 0x1 PWM1_1 Pulse Width Modulator 1, channel 1 output. 0x2 T1_CAP0 Capture input for Timer 1, channel 0. 0x3 SSP1_MISO Master In Slave Out for SSP1. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_19 I/O configuration register for pin P1[19] 0xCC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[19] [2:0] ENUM P1_19 General purpose digital input/output pin. 0x0 USB_TX_E1 Transmit Enable signal for USB port 1 (OTG transceiver). 0x1 USB_PPWR1 Port Power enable signal for USB port 1. 0x2 T1_CAP1 Capture input for Timer 1, channel 1. 0x3 MC_0A Motor control PWM channel 0, output A. 0x4 SSP1_SCK Serial clock for SSP1. 0x5 U2_OE RS-485/EIA-485 output enable signal for UART2. 0x6 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_20 I/O configuration register for pin P1[20] 0xD0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[20] [2:0] ENUM P1_20 General purpose digital input/output pin. 0x0 USB_TX_DP1 D+ transmit data for USB port 1 (OTG transceiver). 0x1 PWM1_2 Pulse Width Modulator 1, channel 2 output. 0x2 QEI_PHA Quadrature Encoder Interface PHA input. 0x3 MC_FB0 Motor control PWM channel 0 feedback input. 0x4 SSP0_SCK Serial clock for SSP0. 0x5 LCD_VD_6 LCD data. 0x6 LCD_VD_10 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_21 I/O configuration register for pin P1[21] 0xD4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[21] [2:0] ENUM P1_21 General purpose digital input/output pin. 0x0 USB_TX_DM1 D- transmit data for USB port 1 (OTG transceiver). 0x1 PWM1_3 Pulse Width Modulator 1, channel 3 output. 0x2 SSP0_SSEL Slave Select for SSP0. 0x3 MC_ABORT Motor control PWM, active low fast abort. 0x4 LCD_VD_7 LCD data. 0x6 LCD_VD_11 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_22 I/O configuration register for pin P1[22] 0xD8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[22] [2:0] ENUM P1_22 General purpose digital input/output pin. 0x0 USB_RCV1 Differential receive data for USB port 1 (OTG transceiver). 0x1 USB_PWRD1 Power Status for USB port 1 (host power switch). 0x2 T1_MAT0 Match output for Timer 1, channel 0. 0x3 MC_0B Motor control PWM channel 0, output B. 0x4 SSP1_MOSI Master Out Slave In for SSP1. 0x5 LCD_VD_8 LCD data. 0x6 LCD_VD_12 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_23 I/O configuration register for pin P1[23] 0xDC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[23] [2:0] ENUM P1_23 General purpose digital input/output pin. 0x0 USB_RX_DP1 D+ receive data for USB port 1 (OTG transceiver). 0x1 PWM1_4 Pulse Width Modulator 1, channel 4 output. 0x2 QEI_PHB Quadrature Encoder Interface PHB input. 0x3 MC_FB1 Motor control PWM channel 1 feedback input. 0x4 SSP0_MISO Master In Slave Out for SSP0. 0x5 LCD_VD_9 LCD data. 0x6 LCD_VD_13 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_24 I/O configuration register for pin P1[24] 0xE0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[24] [2:0] ENUM P1_24 General purpose digital input/output pin. 0x0 USB_RX_DM1 D- receive data for USB port 1 (OTG transceiver). 0x1 PWM1_5 Pulse Width Modulator 1, channel 5 output. 0x2 QEI_IDX Quadrature Encoder Interface INDEX input. 0x3 MC_FB2 Motor control PWM channel 2 feedback input. 0x4 SSP0_MOSI Master Out Slave in for SSP0. 0x5 LCD_VD_10 LCD data. 0x6 LCD_VD_14 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_25 I/O configuration register for pin P1[25] 0xE4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[25] [2:0] ENUM P1_25 General purpose digital input/output pin. 0x0 USB_LS1 Low Speed status for USB port 1 (OTG transceiver). 0x1 USB_HSTEN1 Host Enabled status for USB port 1. 0x2 T1_MAT1 Match output for Timer 1, channel 1. 0x3 MC_1A Motor control PWM channel 1, output A. 0x4 CLKOUT Selectable clock output. 0x5 LCD_VD_11 LCD data. 0x6 LCD_VD_15 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_26 I/O configuration register for pin P1[26] 0xE8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[26] [2:0] ENUM P1_26 General purpose digital input/output pin. 0x0 USB_SSPND1 USB port 1 Bus Suspend status (OTG transceiver). 0x1 PWM1_6 Pulse Width Modulator 1, channel 6 output. 0x2 T0_CAP0 Capture input for Timer 0, channel 0. 0x3 MC_1B Motor control PWM channel 1, output B. 0x4 SSP1_SSEL Slave Select for SSP1. 0x5 LCD_VD_12 LCD data. 0x6 LCD_VD_20 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_27 I/O configuration register for pin P1[27] 0xEC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[27] [2:0] ENUM P1_27 General purpose digital input/output pin. 0x0 USB_INT1 USB port 1 OTG transceiver interrupt (OTG transceiver). 0x1 USB_OVRCR1 USB port 1 Over-Current status. 0x2 T0_CAP1 Capture input for Timer 0, channel 1. 0x3 CLKOUT Selectable clock output. 0x4 LCD_VD_13 LCD data. 0x6 LCD_VD_21 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_28 I/O configuration register for pin P1[28] 0xF0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[28] [2:0] ENUM P1_28 General purpose digital input/output pin. 0x0 USB_SCL1 USB port 1 I2C serial clock (OTG transceiver). 0x1 PWM1_CAP0 Capture input for PWM1, channel 0. 0x2 T0_MAT0 Match output for Timer 0, channel 0. 0x3 MC_2A Motor control PWM channel 2, output A. 0x4 SSP0_SSEL Slave Select for SSP0. 0x5 LCD_VD_14 LCD data. 0x6 LCD_VD_22 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_29 I/O configuration register for pin P1[29] 0xF4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P1[29] [2:0] ENUM P1_29 General purpose digital input/output pin. 0x0 USB_SDA1 USB port 1 I2C serial data (OTG transceiver). 0x1 PWM1_CAP1 Capture input for PWM1, channel 1. 0x2 T0_MAT1 Match output for Timer 0, channel 1. 0x3 MC_2B Motor control PWM channel 2, output B. 0x4 U4_TXD Transmitter output for USART4 (input/output in smart card mode). 0x5 LCD_VD_15 LCD data. 0x6 LCD_VD_23 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P1_30 I/O configuration register for pin P1[30] 0xF8 read-write 0xFFFFFFFF FUNC Selects pin function for pin P1[30] [2:0] ENUM P1_30 General purpose digital input/output pin. 0x0 USB_PWRD2 Power Status for USB port 2. 0x1 USB_VBUS Monitors the presence of USB bus power.This signal must be HIGH for USB reset to occur. 0x2 ADC0_IN_4 A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled. 0x3 I2C0_SDA I2C0 data input/output (this pin does not use a specialized I2C pad. 0x4 U3_OE RS-485/EIA-485 output enable signal for UART3. 0x5 P1_31 I/O configuration register for pin P1[31] 0xFC read-write 0xFFFFFFFF FUNC Selects pin function for pin P1[31] [2:0] ENUM P1_31 General purpose digital input/output pin. 0x0 USB_OVRCR2 Over-Current status for USB port 2. 0x1 SSP1_SCK Serial Clock for SSP1. 0x2 ADC0_IN_5 A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled. 0x3 I2C0_SCL I2C0 clock input/output (this pin does not use a specialized I2C pad. 0x4 P2_0 I/O configuration register for pin P2[0] 0x100 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[0] [2:0] ENUM P2_0 General purpose digital input/output pin. 0x0 PWM1_1 Pulse Width Modulator 1, channel 1 output. 0x1 U1_TXD Transmitter output for UART1. 0x2 LCD_PWR LCD panel power enable. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_1 I/O configuration register for pin P2[1] 0x104 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[1] [2:0] ENUM P2_1 General purpose digital input/output pin. 0x0 PWM1_2 Pulse Width Modulator 1, channel 2 output. 0x1 U1_RXD Receiver input for UART1. 0x2 LCD_LE Line end signal. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_2 I/O configuration register for pin P2[2] 0x108 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[2] [2:0] ENUM P2_2 General purpose digital input/output pin. 0x0 PWM1_3 Pulse Width Modulator 1, channel 3 output. 0x1 U1_CTS Clear to Send input for UART1. 0x2 T2_MAT3 Match output for Timer 2, channel 3. 0x3 TRACEDATA_3 Trace data, bit 3. 0x5 LCD_DCLK LCD panel clock. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_3 I/O configuration register for pin P2[3] 0x10C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[3] [2:0] ENUM P2_3 General purpose digital input/output pin. 0x0 PWM1_4 Pulse Width Modulator 1, channel 4 output. 0x1 U1_DCD Data Carrier Detect input for UART1. 0x2 T2_MAT2 Match output for Timer 2, channel 2. 0x3 TRACEDATA_2 Trace data, bit 2. 0x5 LCD_FP Frame pulse (STN). Vertical synchronization pulse (TFT). 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_4 I/O configuration register for pin P2[4] 0x110 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[4] [2:0] ENUM P2_4 General purpose digital input/output pin. 0x0 PWM1_5 Pulse Width Modulator 1, channel 5 output. 0x1 U1_DSR Data Set Ready input for UART1. 0x2 T2_MAT1 Match output for Timer 2, channel 1. 0x3 TRACEDATA_1 Trace data, bit 1. 0x5 LCD_ENAB_M STN AC bias drive or TFT data enable output. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_5 I/O configuration register for pin P2[5] 0x114 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[5] [2:0] ENUM P2_5 General purpose digital input/output pin. 0x0 PWM1_6 Pulse Width Modulator 1, channel 6 output. 0x1 U1_DTR Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x2 T2_MAT0 Match output for Timer 2, channel 0. 0x3 TRACEDATA_0 Trace data, bit 0. 0x5 LCD_LP Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_6 I/O configuration register for pin P2[6] 0x118 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[6] [2:0] ENUM P2_6 General purpose digital input/output pin. 0x0 PWM1_CAP0 Capture input for PWM1, channel 0. 0x1 U1_RI Ring Indicator input for UART1. 0x2 T2_CAP0 Capture input for Timer 2, channel 0. 0x3 U2_OE RS-485/EIA-485 output enable signal for UART2. 0x4 TRACECLK Trace clock. 0x5 LCD_VD_0 LCD data. 0x6 LCD_VD_4 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_7 I/O configuration register for pin P2[7] 0x11C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[7] [2:0] ENUM P2_7 General purpose digital input/output pin. 0x0 CAN_RD2 CAN2 receiver input. 0x1 U1_RTS Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x2 SPIFI_CS Chip select output for SPIFI. 0x5 LCD_VD_1 LCD data. 0x6 LCD_VD_5 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_8 I/O configuration register for pin P2[8] 0x120 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[8] [2:0] ENUM P2_8 General purpose digital input/output pin. 0x0 CAN_TD2 CAN2 transmitter output. 0x1 U2_TXD Transmitter output for UART2. 0x2 U1_CTS Clear to Send input for UART1. 0x3 ENET_MDC Ethernet MIIM clock. 0x4 LCD_VD_2 LCD data. 0x6 LCD_VD_6 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_9 I/O configuration register for pin P2[9] 0x124 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[9] [2:0] ENUM P2_9 General purpose digital input/output pin. 0x0 USB_CONNECT1 USB1 SoftConnect control. Signal used to switch an external 1.5 kW resistor under the software control. Used with the SoftConnect USB feature. 0x1 U2_RXD Receiver input for UART2. 0x2 U4_RXD Receiver input for USART4. 0x3 ENET_MDIO Ethernet MIIM data input and output. 0x4 LCD_VD_3 LCD data. 0x6 LCD_VD_7 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_10 I/O configuration register for pin P2[10] 0x128 read-write 0xFFFFFFFF FUNC Selects pin function for pin P2[10] [2:0] ENUM P2_10 General purpose digital input/output pin. This pin includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip boot loader to take over control of the part after a reset and go into ISP mode. 0x0 EINT0 External interrupt 0 input. 0x1 NMI Non-maskable interrupt input. 0x2 P2_11 I/O configuration register for pin P2[11] 0x12C read-write 0xFFFFFFFF FUNC Selects pin function for pin P2[11] [2:0] ENUM P2_11 General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. 0x0 EINT1 External interrupt 1 input. 0x1 SD_DAT_1 Data line 1 for SD card interface. 0x2 I2S_TX_SCK Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. 0x3 LCD_CLKIN LCD clock. 0x7 P2_12 I/O configuration register for pin P2[12] 0x130 read-write 0xFFFFFFFF FUNC Selects pin function for pin P2[12] [2:0] ENUM P2_12 General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. 0x0 EINT2 External interrupt 2 input. 0x1 SD_DAT_2 Data line 2 for SD card interface. 0x2 I2S_TX_WS Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. 0x3 LCD_VD_4 LCD data. 0x4 LCD_VD_3 LCD data. 0x5 LCD_VD_8 LCD data. 0x6 LCD_VD_18 LCD data. 0x7 P2_13 I/O configuration register for pin P2[13] 0x134 read-write 0xFFFFFFFF FUNC Selects pin function for pin P2[13] [2:0] ENUM P2_13 General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. 0x0 EINT3 External interrupt 3 input. 0x1 SD_DAT_3 Data line 3 for SD card interface. 0x2 I2S_TX_SDA Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. 0x3 LCD_VD_5 LCD data. 0x5 LCD_VD_9 LCD data. 0x6 LCD_VD_19 LCD data. 0x7 P2_14 I/O configuration register for pin P2[14] 0x138 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[14] [2:0] ENUM P2_14 General purpose digital input/output pin. 0x0 EMC_CS2 LOW active Chip Select 2 signal. 0x1 I2C1_SDA I2C1 data input/output (this pin does not use a specialized I2C pad). 0x2 T2_CAP0 Capture input for Timer 2, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_15 I/O configuration register for pin P2[15] 0x13C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[15] [2:0] ENUM P2_15 General purpose digital input/output pin. 0x0 EMC_CS3 LOW active Chip Select 3 signal. 0x1 I2C1_SCL I2C1 clock input/output (this pin does not use a specialized I2C pad). 0x2 T2_CAP1 Capture input for Timer 2, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_16 I/O configuration register for pin P2[16] 0x140 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[16] [2:0] ENUM P2_16 General purpose digital input/output pin. 0x0 EMC_CAS LOW active SDRAM Column Address Strobe. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_17 I/O configuration register for pin P2[17] 0x144 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[17] [2:0] ENUM P2_17 General purpose digital input/output pin. 0x0 EMC_RAS LOW active SDRAM Row Address Strobe. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_18 I/O configuration register for pin P2[18] 0x148 read-write 0x000001B0 0xFFFFFFFF FUNC Selects pin function for pin P2[18] [2:0] ENUM P2_18 General purpose digital input/output pin. 0x0 EMC_CLK_0 SDRAM clock 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] P2_19 I/O configuration register for pin P2[19] 0x14C read-write 0x000001B0 0xFFFFFFFF FUNC Selects pin function for pin P2[19] [2:0] ENUM P2_19 General purpose digital input/output pin. 0x0 EMC_CLK_1 SDRAM clock 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] P2_20 I/O configuration register for pin P2[20] 0x150 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[20] [2:0] ENUM P2_20 General purpose digital input/output pin. 0x0 EMC_DYCS0 SDRAM chip select 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_21 I/O configuration register for pin P2[21] 0x154 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[21] [2:0] ENUM P2_21 General purpose digital input/output pin. 0x0 EMC_DYCS1 SDRAM chip select 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_22 I/O configuration register for pin P2[22] 0x158 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[22] [2:0] ENUM P2_22 General purpose digital input/output pin. 0x0 EMC_DYCS2 SDRAM chip select 2. 0x1 SSP0_SCK Serial clock for SSP0. 0x2 T3_CAP0 Capture input for Timer 3, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_23 I/O configuration register for pin P2[23] 0x15C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[23] [2:0] ENUM P2_23 General purpose digital input/output pin. 0x0 EMC_DYCS3 SDRAM chip select 3. 0x1 SSP0_SSEL Slave Select for SSP0. 0x2 T3_CAP1 Capture input for Timer 3, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_24 I/O configuration register for pin P2[24] 0x160 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[24] [2:0] ENUM P2_24 General purpose digital input/output pin. 0x0 EMC_CKE0 SDRAM clock enable 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_25 I/O configuration register for pin P2[25] 0x164 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[25] [2:0] ENUM P2_25 General purpose digital input/output pin. 0x0 EMC_CKE1 SDRAM clock enable 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_26 I/O configuration register for pin P2[26] 0x168 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[26] [2:0] ENUM P2_26 General purpose digital input/output pin. 0x0 EMC_CKE2 SDRAM clock enable 2. 0x1 SSP0_MISO Master In Slave Out for SSP0. 0x2 T3_MAT0 Match output for Timer 3, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_27 I/O configuration register for pin P2[27] 0x16C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[27] [2:0] ENUM P2_27 General purpose digital input/output pin. 0x0 EMC_CKE3 SDRAM clock enable 3. 0x1 SSP0_MOSI Master Out Slave In for SSP0. 0x2 T3_MAT1 Match output for Timer 3, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_28 I/O configuration register for pin P2[28] 0x170 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[28] [2:0] ENUM P2_28 General purpose digital input/output pin. 0x0 EMC_DQM0 Data mask 0 used with SDRAM and static devices. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_29 I/O configuration register for pin P2[29] 0x174 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[29] [2:0] ENUM P2_29 General purpose digital input/output pin. 0x0 EMC_DQM1 Data mask 1 used with SDRAM and static devices. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_30 I/O configuration register for pin P2[30] 0x178 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[30] [2:0] ENUM P2_30 General purpose digital input/output pin. 0x0 EMC_DQM2 Data mask 2 used with SDRAM and static devices. 0x1 I2C2_SDA I2C2 data input/output (this pin does not use a specialized I2C pad). 0x2 T3_MAT2 Match output for Timer 3, channel 2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P2_31 I/O configuration register for pin P2[31] 0x17C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P2[31] [2:0] ENUM P2_31 General purpose digital input/output pin. 0x0 EMC_DQM3 Data mask 3 used with SDRAM and static devices. 0x1 I2C2_SCL I2C2 clock input/output (this pin does not use a specialized I2C pad). 0x2 T3_MAT3 Match output for Timer 3, channel 3. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_0 I/O configuration register for pin P3[0] 0x180 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[0] [2:0] ENUM P3_0 General purpose digital input/output pin. 0x0 EMC_D_0 External memory data line 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_1 I/O configuration register for pin P3[1] 0x184 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[1] [2:0] ENUM P3_1 General purpose digital input/output pin. 0x0 EMC_D_1 External memory data line 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_2 I/O configuration register for pin P3[2] 0x188 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[2] [2:0] ENUM P3_2 General purpose digital input/output pin. 0x0 EMC_D_2 External memory data line 2. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_3 I/O configuration register for pin P3[3] 0x18C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[3] [2:0] ENUM P3_3 General purpose digital input/output pin. 0x0 EMC_D_3 External memory data line 3. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_4 I/O configuration register for pin P3[4] 0x190 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[4] [2:0] ENUM P3_4 General purpose digital input/output pin. 0x0 EMC_D_4 External memory data line 4. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_5 I/O configuration register for pin P3[5] 0x194 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[5] [2:0] ENUM P3_5 General purpose digital input/output pin. 0x0 EMC_D_5 External memory data line 5. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_6 I/O configuration register for pin P3[6] 0x198 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[6] [2:0] ENUM P3_6 General purpose digital input/output pin. 0x0 EMC_D_6 External memory data line 6. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_7 I/O configuration register for pin P3[7] 0x19C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[7] [2:0] ENUM P3_7 General purpose digital input/output pin. 0x0 EMC_D_7 External memory data line 7. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_8 I/O configuration register for pin P3[8] 0x1A0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[8] [2:0] ENUM P3_8 General purpose digital input/output pin. 0x0 EMC_D_8 External memory data line 8. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_9 I/O configuration register for pin P3[9] 0x1A4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[9] [2:0] ENUM P3_9 General purpose digital input/output pin. 0x0 EMC_D_9 External memory data line 9. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_10 I/O configuration register for pin P3[10] 0x1A8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[10] [2:0] ENUM P3_10 General purpose digital input/output pin. 0x0 EMC_D_10 External memory data line 10. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_11 I/O configuration register for pin P3[11] 0x1AC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[11] [2:0] ENUM P3_11 General purpose digital input/output pin. 0x0 EMC_D_11 External memory data line 11. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_12 I/O configuration register for pin P3[12] 0x1B0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[12] [2:0] ENUM P3_12 General purpose digital input/output pin. 0x0 EMC_D_12 External memory data line 12. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_13 I/O configuration register for pin P3[13] 0x1B4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[13] [2:0] ENUM P3_13 General purpose digital input/output pin. 0x0 EMC_D_13 External memory data line 13. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_14 I/O configuration register for pin P3[14] 0x1B8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[14] [2:0] ENUM P3_14 General purpose digital input/output pin. 0x0 EMC_D_14 External memory data line 14. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_15 I/O configuration register for pin P3[15] 0x1BC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[15] [2:0] ENUM P3_15 General purpose digital input/output pin. 0x0 EMC_D_15 External memory data line 15. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_16 I/O configuration register for pin P3[16] 0x1C0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[16] [2:0] ENUM P3_16 General purpose digital input/output pin. 0x0 EMC_D_16 External memory data line 16. 0x1 PWM0_1 Pulse Width Modulator 0, output 1. 0x2 U1_TXD Transmitter output for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_17 I/O configuration register for pin P3[17] 0x1C4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[17] [2:0] ENUM P3_17 General purpose digital input/output pin. 0x0 EMC_D_17 External memory data line 17. 0x1 PWM0_2 Pulse Width Modulator 0, output 2. 0x2 U1_RXD Receiver input for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_18 I/O configuration register for pin P3[18] 0x1C8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[18] [2:0] ENUM P3_18 General purpose digital input/output pin. 0x0 EMC_D_18 External memory data line 18. 0x1 PWM0_3 Pulse Width Modulator 0, output 3. 0x2 U1_CTS Clear to Send input for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_19 I/O configuration register for pin P3[19] 0x1CC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[19] [2:0] ENUM P3_19 General purpose digital input/output pin. 0x0 EMC_D_19 External memory data line 19. 0x1 PWM0_4 Pulse Width Modulator 0, output 4. 0x2 U1_DCD Data Carrier Detect input for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_20 I/O configuration register for pin P3[20] 0x1D0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[20] [2:0] ENUM P3_20 General purpose digital input/output pin. 0x0 EMC_D_20 External memory data line 20. 0x1 PWM0_5 Pulse Width Modulator 0, output 5. 0x2 U1_DSR Data Set Ready input for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_21 I/O configuration register for pin P3[21] 0x1D4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[21] [2:0] ENUM P3_21 General purpose digital input/output pin. 0x0 EMC_D_21 External memory data line 21. 0x1 PWM0_6 Pulse Width Modulator 0, output 6. 0x2 U1_DTR Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_22 I/O configuration register for pin P3[22] 0x1D8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[22] [2:0] ENUM P3_22 General purpose digital input/output pin. 0x0 EMC_D_22 External memory data line 22. 0x1 PWM0_CAP0 Capture input for PWM0, channel 0. 0x2 U1_RI Ring Indicator input for UART1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_23 I/O configuration register for pin P3[23] 0x1DC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[23] [2:0] ENUM P3_23 General purpose digital input/output pin. 0x0 EMC_D_23 External memory data line 23. 0x1 PWM1_CAP0 Capture input for PWM1, channel 0. 0x2 T0_CAP0 Capture input for Timer 0, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_24 I/O configuration register for pin P3[24] 0x1E0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[24] [2:0] ENUM P3_24 General purpose digital input/output pin. 0x0 EMC_D_24 External memory data line 24. 0x1 PWM1_1 Pulse Width Modulator 1, output 1. 0x2 T0_CAP1 Capture input for Timer 0, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_25 I/O configuration register for pin P3[25] 0x1E4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[25] [2:0] ENUM P3_25 General purpose digital input/output pin. 0x0 EMC_D_25 External memory data line 25. 0x1 PWM1_2 Pulse Width Modulator 1, output 2. 0x2 T0_MAT0 Match output for Timer 0, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_26 I/O configuration register for pin P3[26] 0x1E8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[26] [2:0] ENUM P3_26 General purpose digital input/output pin. 0x0 EMC_D_26 External memory data line 26. 0x1 PWM1_3 Pulse Width Modulator 1, output 3. 0x2 T0_MAT1 Match output for Timer 0, channel 1. 0x3 STCLK System tick timer clock input. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_27 I/O configuration register for pin P3[27] 0x1EC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[27] [2:0] ENUM P3_27 General purpose digital input/output pin. 0x0 EMC_D_27 External memory data line 27. 0x1 PWM1_4 Pulse Width Modulator 1, output 4. 0x2 T1_CAP0 Capture input for Timer 1, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_28 I/O configuration register for pin P3[28] 0x1F0 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[28] [2:0] ENUM P3_28 General purpose digital input/output pin. 0x0 EMC_D_28 External memory data line 28. 0x1 PWM1_5 Pulse Width Modulator 1, output 5. 0x2 T1_CAP1 Capture input for Timer 1, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_29 I/O configuration register for pin P3[29] 0x1F4 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[29] [2:0] ENUM P3_29 General purpose digital input/output pin. 0x0 EMC_D_29 External memory data line 29. 0x1 PWM1_6 Pulse Width Modulator 1, output 6. 0x2 T1_MAT0 Match output for Timer 1, channel 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_30 I/O configuration register for pin P3[30] 0x1F8 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[30] [2:0] ENUM P3_30 General purpose digital input/output pin. 0x0 EMC_D_30 External memory data line 30. 0x1 U1_RTS Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. 0x2 T1_MAT1 Match output for Timer 1, channel 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P3_31 I/O configuration register for pin P3[31] 0x1FC read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P3[31] [2:0] ENUM P3_31 General purpose digital input/output pin. 0x0 EMC_D_31 External memory data line 31. 0x1 T1_MAT2 Match output for Timer 1, channel 2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_0 I/O configuration register for pin P4[0] 0x200 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[0] [2:0] ENUM P4_0 General purpose digital input/output pin. 0x0 EMC_A_0 External memory address line 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_1 I/O configuration register for pin P4[1] 0x204 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[1] [2:0] ENUM P4_1 General purpose digital input/output pin. 0x0 EMC_A_1 External memory address line 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_2 I/O configuration register for pin P4[2] 0x208 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[2] [2:0] ENUM P4_2 General purpose digital input/output pin. 0x0 EMC_A_2 External memory address line 2. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_3 I/O configuration register for pin P4[3] 0x20C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[3] [2:0] ENUM P4_3 General purpose digital input/output pin. 0x0 EMC_A_3 External memory address line 3. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_4 I/O configuration register for pin P4[4] 0x210 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[4] [2:0] ENUM P4_4 General purpose digital input/output pin. 0x0 EMC_A_4 External memory address line 4. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_5 I/O configuration register for pin P4[5] 0x214 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[5] [2:0] ENUM P4_5 General purpose digital input/output pin. 0x0 EMC_A_5 External memory address line 5. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_6 I/O configuration register for pin P4[6] 0x218 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[6] [2:0] ENUM P4_6 General purpose digital input/output pin. 0x0 EMC_A_6 External memory address line 6. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_7 I/O configuration register for pin P4[7] 0x21C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[7] [2:0] ENUM P4_7 General purpose digital input/output pin. 0x0 EMC_A_7 External memory address line 7. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_8 I/O configuration register for pin P4[8] 0x220 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[8] [2:0] ENUM P4_8 General purpose digital input/output pin. 0x0 EMC_A_8 External memory address line 8. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_9 I/O configuration register for pin P4[9] 0x224 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[9] [2:0] ENUM P4_9 General purpose digital input/output pin. 0x0 EMC_A_9 External memory address line 9. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_10 I/O configuration register for pin P4[10] 0x228 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[10] [2:0] ENUM P4_10 General purpose digital input/output pin. 0x0 EMC_A_10 External memory address line 10. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_11 I/O configuration register for pin P4[11] 0x22C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[11] [2:0] ENUM P4_11 General purpose digital input/output pin. 0x0 EMC_A_11 External memory address line 11. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_12 I/O configuration register for pin P4[12] 0x230 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[12] [2:0] ENUM P4_12 General purpose digital input/output pin. 0x0 EMC_A_12 External memory address line 12. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_13 I/O configuration register for pin P4[13] 0x234 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[13] [2:0] ENUM P4_13 General purpose digital input/output pin. 0x0 EMC_A_13 External memory address line 13. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_14 I/O configuration register for pin P4[14] 0x238 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[14] [2:0] ENUM P4_14 General purpose digital input/output pin. 0x0 EMC_A_14 External memory address line 14. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_15 I/O configuration register for pin P4[15] 0x23C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[15] [2:0] ENUM P4_15 General purpose digital input/output pin. 0x0 EMC_A_15 External memory address line 15. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_16 I/O configuration register for pin P4[16] 0x240 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[16] [2:0] ENUM P4_16 General purpose digital input/output pin. 0x0 EMC_A_16 External memory address line 16. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_17 I/O configuration register for pin P4[17] 0x244 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[17] [2:0] ENUM P4_17 General purpose digital input/output pin. 0x0 EMC_A_17 External memory address line 17. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_18 I/O configuration register for pin P4[18] 0x248 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[18] [2:0] ENUM P4_18 General purpose digital input/output pin. 0x0 EMC_A_18 External memory address line 18. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_19 I/O configuration register for pin P4[19] 0x24C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[19] [2:0] ENUM P4_19 General purpose digital input/output pin. 0x0 EMC_A_19 External memory address line 19. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_20 I/O configuration register for pin P4[20] 0x250 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[20] [2:0] ENUM P4_20 General purpose digital input/output pin. 0x0 EMC_A_20 External memory address line 20. 0x1 I2C2_SDA I2C2 data input/output (this pin does not use a specialized I2C pad). 0x2 SSP1_SCK Serial Clock for SSP1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_21 I/O configuration register for pin P4[21] 0x254 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[21] [2:0] ENUM P4_21 General purpose digital input/output pin. 0x0 EMC_A_21 External memory address line 21. 0x1 I2C2_SCL I2C2 clock input/output (this pin does not use a specialized I2C pad). 0x2 SSP1_SSEL Slave Select for SSP1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_22 I/O configuration register for pin P4[22] 0x258 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[22] [2:0] ENUM P4_22 General purpose digital input/output pin. 0x0 EMC_A_22 External memory address line 22. 0x1 U2_TXD Transmitter output for UART2. 0x2 SSP1_MISO Master In Slave Out for SSP1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_23 I/O configuration register for pin P4[23] 0x25C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[23] [2:0] ENUM P4_23 General purpose digital input/output pin. 0x0 EMC_A_23 External memory address line 23. 0x1 U2_RXD Receiver input for UART2. 0x2 SSP1_MOSI Master Out Slave In for SSP1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_24 I/O configuration register for pin P4[24] 0x260 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[24] [2:0] ENUM P4_24 General purpose digital input/output pin. 0x0 EMC_OE LOW active Output Enable signal. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_25 I/O configuration register for pin P4[25] 0x264 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[25] [2:0] ENUM P4_25 General purpose digital input/output pin. 0x0 EMC_WE LOW active Write Enable signal. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_26 I/O configuration register for pin P4[26] 0x268 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[26] [2:0] ENUM P4_26 General purpose digital input/output pin. 0x0 EMC_BLS0 LOW active Byte Lane select signal 0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_27 I/O configuration register for pin P4[27] 0x26C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[27] [2:0] ENUM P4_27 General purpose digital input/output pin. 0x0 EMC_BLS1 LOW active Byte Lane select signal 1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_28 I/O configuration register for pin P4[28] 0x270 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[28] [2:0] ENUM P4_28 General purpose digital input/output pin. 0x0 EMC_BLS2 LOW active Byte Lane select signal 2. 0x1 U3_TXD Transmitter output for UART3. 0x2 T2_MAT0 Match output for Timer 2, channel 0. 0x3 LCD_VD_6 LCD data. 0x5 LCD_VD_10 LCD data. 0x6 LCD_VD_2 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_29 I/O configuration register for pin P4[29] 0x274 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[29] [2:0] ENUM P4_29 General purpose digital input/output pin. 0x0 EMC_BLS3 LOW active Byte Lane select signal 3. 0x1 U3_RXD Receiver input for UART3. 0x2 T2_MAT1 Match output for Timer 2, channel 1. 0x3 I2C2_SCL I2C2 clock input/output (this pin does not use a specialized I2C pad). 0x4 LCD_VD_7 LCD data. 0x5 LCD_VD_11 LCD data. 0x6 LCD_VD_3 LCD data. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_30 I/O configuration register for pin P4[30] 0x278 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[30] [2:0] ENUM P4_30 General purpose digital input/output pin. 0x0 EMC_CS0 LOW active Chip Select 0 signal. 0x1 CMP0_OUT Comparator 0, output. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P4_31 I/O configuration register for pin P4[31] 0x27C read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P4[31] [2:0] ENUM P4_31 General purpose digital input/output pin. 0x0 EMC_CS1 LOW active Chip Select 1 signal. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P5_0 I/O configuration register for pin P5[0] 0x280 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P5[0] [2:0] ENUM P5_0 General purpose digital input/output pin. 0x0 EMC_A_24 External memory address line 24. 0x1 SSP2_MOSI Master Out Slave In for SSP2. 0x2 T2_MAT2 Match output for Timer 2, channel 2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P5_1 I/O configuration register for pin P5[1] 0x284 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P5[1] [2:0] ENUM P5_1 General purpose digital input/output pin. 0x0 EMC_A_25 External memory address line 25. 0x1 SSP2_MISO Master In Slave Out for SSP2. 0x2 T2_MAT3 Match output for Timer 2, channel 3. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] P5_2 I/O configuration register for pin P5[2] 0x288 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin P5[2] [2:0] ENUM P5_2 General purpose digital input/output pin. 0x0 T3_MAT2 Match output for Timer 3, channel 2. 0x3 I2C0_SDA I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus). 0x5 RESERVED Reserved. [5:3] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] HS Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. [8:8] ENUM ENABLED I2C 50ns glitch filter and slew rate control enabled. 0 DISABLED I2C 50ns glitch filter and slew rate control disabled. 1 HIDRIVE Controls sink current capability of the pin, only for P5[2] and P5[3]. [9:9] ENUM LOWDRIVE Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGHDRIVE Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the appropriate specific device data sheet for details. 1 RESERVED Reserved. [31:10] P5_3 I/O configuration register for pin P5[3] 0x28C read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin P5[3] [2:0] ENUM P5_3 General purpose digital input/output pin. 0x0 U4_RXD Receiver input for USART4. 0x4 I2C0_SCL I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus. 0x5 RESERVED Reserved. [5:3] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] HS Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. [8:8] ENUM ENABLED I2C 50ns glitch filter and slew rate control enabled. 0 DISABLED I2C 50ns glitch filter and slew rate control disabled. 1 HIDRIVE Controls sink current capability of the pin, only for P5[2] and P5[3]. [9:9] ENUM LOWDRIVE Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. 0 HIGHDRIVE Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the appropriate specific device data sheet for details. 1 RESERVED Reserved. [31:10] P5_4 I/O configuration register for pin P5[4] 0x290 read-write 0x00000030 0xFFFFFFFF FUNC Selects pin function for pin P5[4] [2:0] ENUM P5_4 General purpose digital input/output pin. 0x0 U0_OE RS-485/EIA-485 output enable signal for UART0. 0x1 T3_MAT3 Match output for Timer 3, channel 3. 0x3 U4_TXD Transmitter output for USART4 (input/output in smart card mode). 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM STANDARD Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. 0 FAST Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] SSP1 SSP1 controller 0x40030000 0 0xFFF registers SSP1 15 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 THIS_COMBINATION_IS_ This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM BUS_LOW SSP controller maintains the bus clock low between frames. 0 BUS_HIGH SSP controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRST_CLOCK SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECOND_CLOCK SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] ENUM NORMAL During normal operation. 0 OUPTU Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SSP Enable. [1:1] ENUM DISABLED The SSP controller is disabled. 0 ENABLED The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] ENUM MASTER The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] DMACR SSP0 DMA control register 0x024 read-write 0 0xFFFFFFFF RXDMAE Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. [0:0] TXDMAE Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] ADC Analog-to-Digital Converter (ADC) ADC 0x40034000 0x0 0xFFF registers ADC 22 CR A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. 0x000 read-write 0 0x00000000 SEL Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. [7:0] CLKDIV The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [15:8] BURST Burst mode [16:16] ENUM BURST The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start. 1 SW Conversions are software controlled and require 31 clocks. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [20:17] PDN Power down mode [21:21] ENUM POWERED The A/D converter is operational. 1 POWERDOWN The A/D converter is in power-down mode. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [23:22] START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: [26:24] ENUM NO_START_THIS_VALUE No start (this value should be used when clearing PDN to 0). 0x0 START_CONVERSION_NOW Start conversion now. 0x1 P2_10 Start conversion when the edge selected by bit 27 occurs on the P2[10] pin. 0x2 P1_27 Start conversion when the edge selected by bit 27 occurs on the P1[27] pin. 0x3 MAT0_1 Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. 0x4 MAT0_3 Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. 0x5 MAT1_0 Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. 0x6 MAT1_1 Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. 0x7 EDGE This bit is significant only when the START field contains 010-111. In these cases: [27:27] ENUM FALLLING Start conversion on a falling edge on the selected CAP/MAT signal. 1 RISING Start conversion on a rising edge on the selected CAP/MAT signal. 0 RESERVED Reserved. Read value is undefined, only zero should be written. [31:28] GDR A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion. 0x004 read-write 0 0x00000000 RESERVED Reserved. Read value is undefined, only zero should be written. [3:0] RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. [15:4] RESERVED Reserved. Read value is undefined, only zero should be written. [23:16] CHN These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). [26:24] RESERVED Reserved. Read value is undefined, only zero should be written. [29:27] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. [31:31] INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0x00C read-write 0x100 0xFFFFFFFF ADINTEN0 Interrupt enable [0:0] ENUM DISABLE Completion of a conversion on ADC channel 0 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 0 will generate an interrupt. 1 ADINTEN1 Interrupt enable [1:1] ENUM DISABLE Completion of a conversion on ADC channel 1 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 1 will generate an interrupt. 1 ADINTEN2 Interrupt enable [2:2] ENUM DISABLE Completion of a conversion on ADC channel 2 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 2 will generate an interrupt. 1 ADINTEN3 Interrupt enable [3:3] ENUM DISABLE Completion of a conversion on ADC channel 3 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 3 will generate an interrupt. 1 ADINTEN4 Interrupt enable [4:4] ENUM DISABLE Completion of a conversion on ADC channel 4 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 4 will generate an interrupt. 1 ADINTEN5 Interrupt enable [5:5] ENUM DISABLE Completion of a conversion on ADC channel 5 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 5 will generate an interrupt. 1 ADINTEN6 Interrupt enable [6:6] ENUM DISABLE Completion of a conversion on ADC channel 6 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 6 will generate an interrupt. 1 ADINTEN7 Interrupt enable [7:7] ENUM DISABLE Completion of a conversion on ADC channel 7 will not generate an interrupt. 0 ENABLE Completion of a conversion on ADC channel 7 will generate an interrupt. 1 ADGINTEN Interrupt enable [8:8] ENUM CHANNELS Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts. 0 GLOBAL The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] 8 0x4 0-7 DR[%s] DR[%s] A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0. 0x010 read-only 0 0x00000000 RESERVED Reserved. Read value is undefined, only zero should be written. [3:0] RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. [15:4] RESERVED Reserved. Read value is undefined, only zero should be written. [29:16] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. [31:31] STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag. 0x030 read-only 0 0xFFFFFFFF DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0. [0:0] DONE1 This bit mirrors the DONE status flag from the result register for A/D channel 1. [1:1] DONE2 This bit mirrors the DONE status flag from the result register for A/D channel 2. [2:2] DONE3 This bit mirrors the DONE status flag from the result register for A/D channel 3. [3:3] DONE4 This bit mirrors the DONE status flag from the result register for A/D channel 4. [4:4] DONE5 This bit mirrors the DONE status flag from the result register for A/D channel 5. [5:5] DONE6 This bit mirrors the DONE status flag from the result register for A/D channel 6. [6:6] DONE7 This bit mirrors the DONE status flag from the result register for A/D channel 7. [7:7] OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. [8:8] OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. [9:9] OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. [10:10] OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. [11:11] OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. [12:12] OVERRUN5 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. [13:13] OVERRUN6 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. [14:14] OVERRUN7 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. [15:15] ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] TRM ADC trim register. 0x034 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [3:0] ADCOFFS Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. [7:4] TRIM written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. [11:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] CANAFRAM CAN acceptance filter RAM 0x40038000 0x0 0xFFF registers 512 0x4 0-511 MASK[%s] MASK[%s] CAN AF ram access register 0x000 read-write 0 0x00000000 MASK CAN AF RAM mask [31:0] CANAF CAN controller CANAF 0x4003C000 0x0 0xFFF registers AFMR Acceptance Filter Register 0x000 read-write 0 0x00000000 ACCOFF if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. [0:0] ACCBP All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. [1:1] EFCAN FullCAN mode [2:2] ENUM SOFTWARE_MUST_READ_A Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers. 0 THE_ACCEPTANCE_FILTE The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] SFF_SA Standard Frame Individual Start Address Register 0x004 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] SFF_SA The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. [10:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] SFF_GRP_SA Standard Frame Group Start Address Register 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] SFF_GRP_SA The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. [11:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] EFF_SA Extended Frame Start Address Register 0x00C read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] EFF_SA The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. [10:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] EFF_GRP_SA Extended Frame Group Start Address Register 0x010 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] EFF_GRP_SA The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. [11:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] ENDOFTABLE End of AF Tables register 0x014 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] ENDOFTABLE The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. [11:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] LUTERRAD LUT Error Address register 0x018 read-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] LUTERRAD It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. [10:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] LUTERR LUT Error Register 0x01C read-only 0 0xFFFFFFFF LUTERR This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC. [0:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:1] FCANIE FullCAN interrupt enable register 0x020 read-write 0 0xFFFFFFFF FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] FCANIC0 FullCAN interrupt and capture register0 0x024 read-write 0 0xFFFFFFFF INTPND FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31. [31:0] FCANIC1 FullCAN interrupt and capture register1 0x028 read-write 0 0xFFFFFFFF IntPnd32 FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63. [31:0] CCAN CAN controller CCAN 0x40040000 0x0 0xFFF registers TXSR CAN Central Transmit Status Register 0x000 read-only 0x00030300 0xFFFFFFFF TS1 When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). [0:0] TS2 When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) [1:1] RESERVED Reserved, the value read from a reserved bit is not defined. [7:2] TBS1 When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). [8:8] TBS2 When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). [9:9] RESERVED Reserved, the value read from a reserved bit is not defined. [15:10] TCS1 When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). [16:16] TCS2 When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). [17:17] RESERVED Reserved, the value read from a reserved bit is not defined. [31:18] RXSR CAN Central Receive Status Register 0x004 read-only 0 0xFFFFFFFF RS1 When 1, CAN1 is receiving a message (same as RS in CAN1GSR). [0:0] RS2 When 1, CAN2 is receiving a message (same as RS in CAN2GSR). [1:1] RESERVED Reserved, the value read from a reserved bit is not defined. [7:2] RB1 When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). [8:8] RB2 When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). [9:9] RESERVED Reserved, the value read from a reserved bit is not defined. [15:10] DOS1 When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). [16:16] DOS2 When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). [17:17] RESERVED Reserved, the value read from a reserved bit is not defined. [31:18] MSR CAN Central Miscellaneous Register 0x008 read-only 0 0xFFFFFFFF E1 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR) [0:0] E2 When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR) [1:1] RESERVED Reserved, the value read from a reserved bit is not defined. [7:2] BS1 When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). [8:8] BS2 When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). [9:9] RESERVED Reserved, the value read from a reserved bit is not defined. [31:10] CAN1 CAN controller CAN 0x40044000 0x0 0xFFF registers CAN 25 MOD Controls the operating mode of the CAN Controller. 0x000 read-write 0 0x00000000 RM Reset Mode. [0:0] ENUM NORMAL_THE_CAN_CONTR Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written. 0 RESET_CAN_OPERATION Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. 1 LOM Listen Only Mode. [1:1] ENUM NORMAL_THE_CAN_CONT Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. 0 LISTEN_ONLY_THE_CON Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging. 1 STM Self Test Mode. [2:2] ENUM NORMAL_A_TRANSMITTE Normal. A transmitted message must be acknowledged to be considered successful. 0 SELF_TEST_THE_CONTR Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. 1 TPM Transmit Priority Mode. [3:3] ENUM CAN_ID_THE_TRANSMIT CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. 0 LOCAL_PRIORITY_THE_ Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. 1 SM Sleep Mode. [4:4] ENUM WAKE_UP_NORMAL_OPER Wake-up. Normal operation. 0 SLEEP_THE_CAN_CONTR Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565. 1 RPM Receive Polarity Mode. [5:5] ENUM LOW_ACTIVE_RD_INPUT Low active. RD input is active Low (dominant bit = 0). 0 HIGH_ACTIVE_RD_INPU High active. RD input is active High (dominant bit = 1) -- reverse polarity. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [6:6] TM Test Mode. [7:7] ENUM DISABLED_NORMAL_OPE Disabled. Normal operation. 0 ENABLED_THE_TD_PIN_ Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] CMR Command bits that affect the state of the CAN Controller 0x004 write-only 0 0xFFFFFFFF TR Transmission Request. [0:0] ENUM ABSENT_NO_TRANSMISSI Absent.No transmission request. 0 PRESENT_THE_MESSAGE Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB)) 1 AT Abort Transmission. [1:1] ENUM NO_ACTION_DO_NOT_AB No action. Do not abort the transmission. 0 PRESENT_IF_NOT_ALRE Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. 1 RRB Release Receive Buffer. [2:2] ENUM NO_ACTION_DO_NOT_RE No action. Do not release the receive buffer. 0 RELEASED_THE_INFORM Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). 1 CDO Clear Data Overrun. [3:3] ENUM NO_ACTION_DO_NOT_CL No action. Do not clear the data overrun bit. 0 CLEAR_THE_DATA_OVER Clear. The Data Overrun bit in Status Register(s) is cleared. 1 SRR Self Reception Request. [4:4] ENUM ABSENT_NO_SELF_RECE Absent. No self reception request. 0 PRESENT_THE_MESSAGE Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. 1 STB1 Select Tx Buffer 1. [5:5] ENUM NOT_SELECTED_TX_BUF Not selected. Tx Buffer 1 is not selected for transmission. 0 SELECTED_TX_BUFFER_ Selected. Tx Buffer 1 is selected for transmission. 1 STB2 Select Tx Buffer 2. [6:6] ENUM NOT_SELECTED_TX_BUF Not selected. Tx Buffer 2 is not selected for transmission. 0 SELECTED_TX_BUFFER_ Selected. Tx Buffer 2 is selected for transmission. 1 STB3 Select Tx Buffer 3. [7:7] ENUM NOT_SELECTED_TX_BUF Not selected. Tx Buffer 3 is not selected for transmission. 0 SELECTED_TX_BUFFER_ Selected. Tx Buffer 3 is selected for transmission. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] GSR Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1. 0x008 read-only 0x3C 0xFFFFFFFF RBS Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. [0:0] ENUM EMPTY_NO_MESSAGE_IS Empty. No message is available. 0 FULL_AT_LEAST_ONE_C Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. 1 DOS Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. [1:1] ENUM ABSENT_NO_DATA_OVER Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). 0 OVERRUN_A_MESSAGE_W Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). 1 TBS Transmit Buffer Status. [2:2] ENUM LOCKED_AT_LEAST_ONE Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). 0 RELEASED_ALL_THREE_ Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 1 TCS Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. [3:3] ENUM INCOMPLETE_AT_LEAST Incomplete. At least one requested transmission has not been successfully completed yet. 0 COMPLETE_ALL_REQUES Complete. All requested transmission(s) has (have) been successfully completed. 1 RS Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. [4:4] ENUM IDLE_THE_CAN_CONTRO Idle. The CAN controller is idle. 0 RECEIVE_THE_CAN_CON Receive. The CAN controller is receiving a message. 1 TS Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. [5:5] ENUM IDLE_THE_CAN_CONTRO Idle. The CAN controller is idle. 0 TRANSMIT_THE_CAN_CO Transmit. The CAN controller is sending a message. 1 ES Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018). [6:6] ENUM OK_BOTH_ERROR_COUNT OK. Both error counters are below the Error Warning Limit. 0 ERROR_ONE_OR_BOTH_O Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. 1 BS Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. [7:7] ENUM BUS_ON_THE_CAN_CONT Bus-on. The CAN Controller is involved in bus activities 0 BUS_OFF_THE_CAN_CON Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [15:8] RXERR The current value of the Rx Error Counter (an 8-bit value). [23:16] TXERR The current value of the Tx Error Counter (an 8-bit value). [31:24] ICR Interrupt status, Arbitration Lost Capture, Error Code Capture 0x00C read-only 0 0xFFFFFFFF RI Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. [0:0] ENUM RESET Reset 0 SET Set 1 TI1 Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. [1:1] ENUM RESET Reset 0 SET Set 1 EI Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. [2:2] ENUM RESET Reset 0 SET Set 1 DOI Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1. [3:3] ENUM RESET Reset 0 SET Set 1 WUI Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. [4:4] ENUM RESET Reset 0 SET Set 1 EPI Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. [5:5] ENUM RESET Reset 0 SET Set 1 ALI Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. [6:6] ENUM RESET Reset 0 SET Set 1 BEI Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. [7:7] ENUM RESET Reset 0 SET Set 1 IDI ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. [8:8] ENUM RESET Reset 0 SET Set 1 TI2 Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. [9:9] ENUM RESET Reset 0 SET Set 1 TI3 Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. [10:10] ENUM RESET Reset 0 SET Set 1 RESERVED Reserved. The value read from a reserved bit is not defined. [15:11] ERRBIT4_0 Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. [20:16] ERRDIR When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. [21:21] ENUM ERROR_OCCURRED_DURIN Error occurred during transmitting. 0 ERROR_OCCURRED_DURIN Error occurred during receiving. 1 ERRC1_0 When the CAN controller detects a bus error, the type of error is captured in this field: [23:22] ENUM BIT_ERROR Bit error 0x0 FORM_ERROR Form error 0x1 STUFF_ERROR Stuff error 0x2 OTHER_ERROR Other error 0x3 ALCBIT Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. [31:24] IER Interrupt Enable 0x010 read-write 0 0xFFFFFFFF RIE Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. [0:0] TIE1 Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. [1:1] EIE Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. [2:2] DOIE Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. [3:3] WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. [4:4] EPIE Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. [5:5] ALIE Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. [6:6] BEIE Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. [7:7] IDIE ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. [8:8] TIE2 Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. [9:9] TIE3 Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. [10:10] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] BTR Bus Timing. Can only be written when RM in CANMOD is 1. 0x014 read-write 0x1C0000 0xFFFFFFFF BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. [9:0] RESERVED Reserved. Read value is undefined, only zero should be written. [13:10] SJW The Synchronization Jump Width is (this value plus one) CAN clocks. [15:14] TESG1 The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. [19:16] TESG2 The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. [22:20] SAM Sampling [23:23] ENUM THE_BUS_IS_SAMPLED_O The bus is sampled once (recommended for high speed buses) 0 THE_BUS_IS_SAMPLED_3 The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:24] EWL Error Warning Limit. Can only be written when RM in CANMOD is 1. 0x018 read-write 0x60 0xFFFFFFFF EWL During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SR Status Register 0x01C read-only 0x3C3C3C 0xFFFFFFFF RBS_1 Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. [0:0] DOS_1 Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. [1:1] TBS1_1 Transmit Buffer Status 1. [2:2] ENUM LOCKED_SOFTWARE_CAN Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 0 RELEASED_SOFTWARE_M Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 1 TCS1_1 Transmission Complete Status. [3:3] ENUM INCOMPLETE_THE_PREV Incomplete. The previously requested transmission for Tx Buffer 1 is not complete. 0 COMPLETE_THE_PREVIO Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. 1 RS_1 Receive Status. This bit is identical to the RS bit in the GSR. [4:4] TS1_1 Transmit Status 1. [5:5] ENUM IDLE_THERE_IS_NO_TR Idle. There is no transmission from Tx Buffer 1. 0 TRANSMIT_THE_CAN_CO Transmit. The CAN Controller is transmitting a message from Tx Buffer 1. 1 ES_1 Error Status. This bit is identical to the ES bit in the CANxGSR. [6:6] BS_1 Bus Status. This bit is identical to the BS bit in the CANxGSR. [7:7] RBS_2 Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. [8:8] DOS_2 Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. [9:9] TBS2_2 Transmit Buffer Status 2. [10:10] ENUM LOCKED_SOFTWARE_CAN Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 0 RELEASED_SOFTWARE_M Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 1 TCS2_2 Transmission Complete Status. [11:11] ENUM INCOMPLETE_THE_PREV Incomplete. The previously requested transmission for Tx Buffer 2 is not complete. 0 COMPLETE_THE_PREVIO Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. 1 RS_2 Receive Status. This bit is identical to the RS bit in the GSR. [12:12] TS2_2 Transmit Status 2. [13:13] ENUM IDLE_THERE_IS_NO_TR Idle. There is no transmission from Tx Buffer 2. 0 TRANSMIT_THE_CAN_CO Transmit. The CAN Controller is transmitting a message from Tx Buffer 2. 1 ES_2 Error Status. This bit is identical to the ES bit in the CANxGSR. [14:14] BS_2 Bus Status. This bit is identical to the BS bit in the CANxGSR. [15:15] RBS_3 Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. [16:16] DOS_3 Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. [17:17] TBS3_3 Transmit Buffer Status 3. [18:18] ENUM LOCKED_SOFTWARE_CAN Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. 0 RELEASED_SOFTWARE_M Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 1 TCS3_3 Transmission Complete Status. [19:19] ENUM INCOMPLETE_THE_PREV Incomplete. The previously requested transmission for Tx Buffer 3 is not complete. 0 COMPLETE_THE_PREVIO Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. 1 RS_3 Receive Status. This bit is identical to the RS bit in the GSR. [20:20] TS3_3 Transmit Status 3. [21:21] ENUM IDLE_THERE_IS_NO_TR Idle. There is no transmission from Tx Buffer 3. 0 TRANSMIT_THE_CAN_CO Transmit. The CAN Controller is transmitting a message from Tx Buffer 3. 1 ES_3 Error Status. This bit is identical to the ES bit in the CANxGSR. [22:22] BS_3 Bus Status. This bit is identical to the BS bit in the CANxGSR. [23:23] RESERVED Reserved, the value read from a reserved bit is not defined. [31:24] RFS Receive frame status. Can only be written when RM in CANMOD is 1. 0x020 read-write 0 0xFFFFFFFF IDINDEX ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values. [9:0] BP If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. [10:10] RESERVED Reserved. The value read from a reserved bit is not defined. [15:11] DLC The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. [19:16] RESERVED Reserved. Read value is undefined, only zero should be written. [29:20] RTR This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. [30:30] FF A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. [31:31] RID Received Identifier. Can only be written when RM in CANMOD is 1. 0x024 read-write 0 0xFFFFFFFF ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18. [10:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:11] RDA Received data bytes 1-4. Can only be written when RM in CANMOD is 1. 0x028 read-write 0 0xFFFFFFFF DATA1 Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message. [7:0] DATA2 Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message. [15:8] DATA3 Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message. [23:16] DATA4 Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message. [31:24] RDB Received data bytes 5-8. Can only be written when RM in CANMOD is 1. 0x02C read-write 0 0xFFFFFFFF DATA5 Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message. [7:0] DATA6 Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message. [15:8] DATA7 Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message. [23:16] DATA8 Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message. [31:24] 3 0x10 1-3 TFI%s Transmit frame info (Tx Buffer ) 0x030 read-write 0 0xFFFFFFFF PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [15:8] DLC Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes [19:16] RESERVED Reserved. Read value is undefined, only zero should be written. [29:20] RTR This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. [30:30] FF If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format). [31:31] 3 0x10 1-3 TID%s Transmit Identifier (Tx Buffer) 0x034 read-write 0 0xFFFFFFFF ID The 11-bit Identifier to be sent in the next transmit message. [10:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] 3 0x10 1-3 TDA%s Transmit data bytes 1-4 (Tx Buffer) 0x038 read-write 0 0x00000000 DATA1 Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. [7:0] DATA2 Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. [15:8] DATA3 Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. [23:16] DATA4 Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. [31:24] 3 0x10 1-3 TDB%s Transmit data bytes 5-8 (Tx Buffer ) 0x03C read-write 0 0x00000000 DATA5 Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message. [7:0] DATA6 Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message. [15:8] DATA7 Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message. [23:16] DATA8 Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message. [31:24] CAN2 0x40048000 0 0xFFF registers I2C1 0x4005C000 I2C1 11 SSP0 SSP controller SSP 0x40088000 0 0x300 registers SSP0 14 DAC Digital-to-Analog Converter (DAC) Modification DAC 0x4008C000 0x0 0xFFF registers CR D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [5:0] VALUE After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN. [15:6] BIAS Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet. [16:16] ENUM FAST The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. 0 SLOW The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] CTRL DAC Control register. This register controls DMA and timer operation. 0x004 read-write 0 0xFFFFFFFF INT_DMA_REQ DMA interrupt request [0:0] ENUM CLEAR_ON_ANY_WRITE_T Clear on any write to the DACR register. 0 SET_BY_HARDWARE_WHEN Set by hardware when the timer times out. 1 DBLBUF_ENA Double buffering [1:1] ENUM DISABLE Disable 0 ENABLE_WHEN_THIS_BI Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. 1 CNT_ENA Time-out counter operation [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 DMA_ENA DMA access [3:3] ENUM DISABLE Disable 0 ENABLE_DMA_BURST_RE Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] CNTVAL DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. 0x008 read-write 0 0xFFFFFFFF VALUE 16-bit reload value for the DAC interrupt/DMA timer. [15:0] RESERVED Reserved [31:16] TIMER2 0x40090000 0 0xFFF registers TIMER2 3 TIMER3 0x40094000 0 0xFFF registers TIMER3 4 UART2 0x40098000 0 0xFFF registers UART2 7 UART3 0x4009C000 0 0xFFF registers UART3 8 I2C2 0x400A0000 I2C2 12 UART4 UART4 UART4 0x400A4000 0x0 0xFFF registers UART4 35 RBR Receiver Buffer Register. Contains the next received character to be read (DLAB =0). 0x000 read-only 0 0x00000000 modify RBR The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO. [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] THR Transmit Holding Register. The next character to be transmitted is written here (DLAB =0). RBR 0x000 write-only 0 0x00000000 THR Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). 0x004 read-write 0x01 0xFFFFFFFF DLMSB The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). DLM 0x004 read-write 0 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupts. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupts. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupts. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupts. 1 RXIE RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. [2:2] ENUM DISABLE_THE_RX_LINE_ Disable the RX line status interrupts. 0 ENABLE_THE_RX_LINE_S Enable the RX line status interrupts. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:3] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1]. [0:0] ENUM AT_LEAST_ONE_INTERRU At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111). [3:1] ENUM 1_RECEIVE_LINE_S 1 - Receive Line Status (RLS). 0x3 2A__RECEIVE_DATA_AV 2a - Receive Data Available (RDA). 0x2 2B__CHARACTER_TIME_ 2b - Character Time-out Indicator (CTI). 0x6 3_THRE_INTERRUPT 3 - THRE Interrupt 0x1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:4] FIFOENABLE Copies of U4FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] FCR FIFO Control Register. Controls UART FIFO usage and modes. IIR 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO Enable. [0:0] ENUM UARTN_FIFOS_ARE_DISA UARTn FIFOs are disabled. Must not be used in the application. 0 ACTIVE_HIGH_ENABLE_F Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. 1 RXFIFORES RX FIFO Reset. [1:1] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UARTn FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset. [2:2] ENUM NO_IMPACT_ON_EITHER_ No impact on either of UARTn FIFOs. 0 WRITING_A_LOGIC_1_TO Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing. 1 DMAMODE DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [5:4] RXTRIGLVL RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select. [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length 0x0 6_BIT_CHARACTER_LENG 6-bit character length 0x1 7_BIT_CHARACTER_LENG 7-bit character length 0x2 8_BIT_CHARACTER_LENG 8-bit character length 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if UnLCR[1:0]=00). 1 PE Parity Enable. [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. [0:0] ENUM THE_UARTN_RECEIVER_F The UARTn receiver FIFO is empty. 0 THE_UARTN_RECEIVER_F The UARTn receiver FIFO is not empty. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. [1:1] ENUM OVERRUN_ERROR_STATUS Overrun error status is inactive. 0 OVERRUN_ERROR_STATUS Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. [2:2] ENUM PARITY_ERROR_STATUS_ Parity error status is inactive. 0 PARITY_ERROR_STATUS_ Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. [3:3] ENUM FRAMING_ERROR_STATUS Framing error status is inactive. 0 FRAMING_ERROR_STATUS Framing error status is active. 1 BI Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. [4:4] ENUM BREAK_INTERRUPT_STAT Break interrupt status is inactive. 0 BREAK_INTERRUPT_STAT Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. [5:5] ENUM UNTHR_CONTAINS_VALID UnTHR contains valid data. 0 UNTHR_IS_EMPTY_ UnTHR is empty. 1 TEMT Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. [6:6] ENUM VALID_DATA UnTHR and/or the UnTSR contains valid data. 0 EMPTY UnTHR and the UnTSR are empty. 1 RXFE Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. [7:7] ENUM UNRBR_CONTAINS_NO_UA UnRBR contains no UARTn RX errors or UnFCR[0]=0. 0 UARTN_RBR_CONTAINS_A UARTn RBR contains at least one UARTn RX error. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. 8-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF Pad A readable, writable byte. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START Start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Restart bit. [2:2] ENUM NO_RESTART_ No restart. 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. [8:8] ENUM NO_IMPACT_ No impact. 0 CLEAR_THE_CORRESPOND Clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. [9:9] ENUM NO_IMPACT_ No impact. 0 CLEAR_THE_CORRESPOND Clear the corresponding interrupt in the IIR. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] ICR IrDA Control Register. Enables and configures the IrDA mode. 0x024 read-write 0 0xFFFFFFFF IRDAEN IrDA mode [0:0] ENUM DISABLED_IRDA_MODE_ Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART. 0 ENABLED_IRDA_MODE_O Enabled. IrDA mode on UART4 is enabled. 1 IRDAINV Serial input direction. [1:1] ENUM NOT_INVERTED_ Not inverted. 0 INVERTED_THIS_HAS_N Inverted. This has no effect on the serial output. 1 FIXPULSEEN IrDA fixed pulse width mode. [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 PULSEDIV Configures the pulse when FixPulseEn = 1. [5:3] ENUM 2XTPCLK 2xTPCLK 0x0 4XTPCLK 4xTPCLK 0x1 8XTPCLK 8xTPCLK 0x2 16XTPCLK 16xTPCLK 0x3 32XTPCLK 32xTPCLK 0x4 64XTPCLK 64xTPCLK 0x5 128XTPCLK 128xTPCLK 0x6 256XTPCLK 256xTPCLK 0x7 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate. [3:0] MULVAL Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] OSR Oversampling register. Controls the degree of oversampling during each bit time. 0x02C read-write 0xF0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875) [3:1] OSINT Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time. [7:4] FDINT In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. [14:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:15] SCICTRL Smart Card Interface control register. Enables and configures the smartcard Interface feature. 0x048 read-write 0 0xFFFFFFFF SCIEN Smart Card Interface Enable. [0:0] ENUM SMART_CARD_INTERFACE Smart card interface disabled. 0 ASYNCHRONOUS_HALF_DU Asynchronous half duplex smart card interface is enabled. 1 NACKDIS NACK response disable. Only applicable in T=0. [1:1] ENUM A_NACK_RESPONSE_IS_E A NACK response is enabled. 0 A_NACK_RESPONSE_IS_I A NACK response is inhibited. 1 PROTSEL Protocol selection as defined in the ISO7816-3 standard. [2:2] ENUM T_EQ_0 T = 0 0 T_EQ_1 T = 1 1 TXRETRY Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled. [7:5] GUARDTIME Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation. 1 RXDIS Receiver enable. [1:1] ENUM ENABLED_ Enabled. 0 DISABLED_ Disabled. 1 AADEN AAD enable [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 RESERVED Reserved. [3:3] DCTRL Direction control for DIR pin. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin. [5:5] ENUM LOW_THE_DIRECTION_C Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH_THE_DIRECTION_ High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SYNCCTRL Synchronous mode control register. 0x058 read-write 0 0xFFFFFFFF SYNC Enables synchronous mode. [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 CSRC Clock source select. [1:1] ENUM SYNCHRONOUS_SLAVE_MO Synchronous slave mode (SCLK in) 0 SYNCHRONOUS_MASTER_M Synchronous master mode (SCLK out) 1 FES Falling edge sampling. [2:2] ENUM RXD_IS_SAMPLED_ON_TH RxD is sampled on the rising edge of SCLK 0 RXD_IS_SAMPLED_ON_TH RxD is sampled on the falling edge of SCLK 1 TSBYPASS Transmit synchronization bypass in synchronous slave mode. [3:3] ENUM THE_INPUT_CLOCK_IS_S The input clock is synchronized prior to being used in clock edge detection logic. 0 THE_INPUT_CLOCK_IS_N The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. 1 CSCEN Continuous master clock enable (used only when CSRC is 1) [4:4] ENUM SCLK_CYCLES_ONLY_WHE SCLK cycles only when characters are being sent on TxD 0 SCLK_RUNS_CONTINUOUS SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) 1 SSSDIS Start/stop bits [5:5] ENUM SEND_START_AND_STOP_ Send start and stop bits as in other modes. 0 NOSTARTSTOPBIT Do not send start/stop bits. 1 CCCLR Continuous clock clear [6:6] ENUM CSCEN_IS_UNDER_SOFTW CSCEN is under software control. 0 HARDWARE_CLEARS_CSCE Hardware clears CSCEN after each character is received. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:6] I2S I2S interface I2S 0x400A8000 0 0xFFF registers I2S 27 DAO I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. 0x000 read-write 0x87E1 0xFFFFFFFF WORDWIDTH Selects the number of bytes in data as follows: [1:0] ENUM 8_BIT_DATA 8-bit data 0x0 16_BIT_DATA 16-bit data 0x1 32_BIT_DATA 32-bit data 0x3 MONO When 1, data is of monaural format. When 0, the data is in stereo format. [2:2] STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode. [3:3] RESET When 1, asynchronously resets the transmit channel and FIFO. [4:4] WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. [5:5] WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. [14:6] MUTE When 1, the transmit channel sends only zeroes. [15:15] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] DAI I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. 0x004 read-write 0x07E1 0xFFFFFFFF WORDWIDTH Selects the number of bytes in data as follows: [1:0] ENUM 8_BIT_DATA 8-bit data 0x0 16_BIT_DATA 16-bit data 0x1 32_BIT_DATA 32-bit data 0x3 MONO When 1, data is of monaural format. When 0, the data is in stereo format. [2:2] STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode. [3:3] RESET When 1, asynchronously reset the transmit channel and FIFO. [4:4] WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. [5:5] WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. [14:6] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] TXFIFO I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. 0x008 write-only 0 0xFFFFFFFF I2STXFIFO 8 x 32-bit transmit FIFO. [31:0] RXFIFO I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. 0x00C read-only 0 0xFFFFFFFF modify I2SRXFIFO 8 x 32-bit transmit FIFO. [31:0] STATE I2S Status Feedback Register. Contains status information about the I2S interface. 0x010 read-only 0x7 0xFFFFFFFF IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. [0:0] DMAREQ1 This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. [1:1] DMAREQ2 This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. [2:2] RESERVED Reserved. [7:3] RX_LEVEL Reflects the current level of the Receive FIFO. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_LEVEL Reflects the current level of the Transmit FIFO. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] DMA1 I2S DMA Configuration Register 1. Contains control information for DMA request 1. 0x014 read-write 0 0xFFFFFFFF RX_DMA1_ENABLE When 1, enables DMA1 for I2S receive. [0:0] TX_DMA1_ENABLE When 1, enables DMA1 for I2S transmit. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:2] RX_DEPTH_DMA1 Set the FIFO level that triggers a receive DMA request on DMA1. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_DMA1 Set the FIFO level that triggers a transmit DMA request on DMA1. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] DMA2 I2S DMA Configuration Register 2. Contains control information for DMA request 2. 0x018 read-write 0 0xFFFFFFFF RX_DMA2_ENABLE When 1, enables DMA1 for I2S receive. [0:0] TX_DMA2_ENABLE When 1, enables DMA1 for I2S transmit. [1:1] RESERVED Reserved. [7:2] RX_DEPTH_DMA2 Set the FIFO level that triggers a receive DMA request on DMA2. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_DMA2 Set the FIFO level that triggers a transmit DMA request on DMA2. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] IRQ I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. 0x01C read-write 0 0xFFFFFFFF RX_IRQ_ENABLE When 1, enables I2S receive interrupt. [0:0] TX_IRQ_ENABLE When 1, enables I2S transmit interrupt. [1:1] RESERVED Reserved. [7:2] RX_DEPTH_IRQ Set the FIFO level on which to create an irq request. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_IRQ Set the FIFO level on which to create an irq request. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] TXRATE I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. 0x020 read-write 0 0xFFFFFFFF Y_DIVIDER I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. [7:0] X_DIVIDER I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RXRATE I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. 0x024 read-write 0 0xFFFFFFFF Y_DIVIDER I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. [7:0] X_DIVIDER I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] TXBITRATE I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. 0x028 read-write 0 0xFFFFFFFF TX_BITRATE I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RXBITRATE I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. 0x02C read-write 0 0xFFFFFFFF RX_BITRATE I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TXMODE I2S Transmit mode control. 0x030 read-write 0 0xFFFFFFFF TXCLKSEL Clock source selection for the transmit bit clock divider. [1:0] ENUM SELECT_THE_TX_FRACTI Select the TX fractional rate divider clock output as the source 0x0 RESERVED Reserved 0x1 SELECT_THE_RX_MCLK_S Select the RX_MCLK signal as the TX_MCLK clock source 0x2 RESERVED Reserved 0x3 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode. [2:2] TXMCENA Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RXMODE I2S Receive mode control. 0x034 read-write 0 0xFFFFFFFF RXCLKSEL Clock source selection for the receive bit clock divider. [1:0] ENUM SELECT_THE_RX_FRACTI Select the RX fractional rate divider clock output as the source 0x0 RESERVED Reserved 0x1 SELECT_THE_TX_MCLK_S Select the TX_MCLK signal as the RX_MCLK clock source 0x2 RESERVED Reserved 0x3 RX4PIN Receive 4-pin mode selection. When 1, enables 4-pin mode. [2:2] RXMCENA Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] SSP2 0x400AC000 SSP2 36 MCPWM Motor Control PWM MCPWM 0x400B8000 0 0xFFF registers MCPWM 30 CON PWM Control read address 0x000 read-only 0 0xFFFFFFFF RUN0 Stops/starts timer channel 0. [0:0] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER0 Edge/center aligned operation for channel 0. [1:1] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA0 Selects polarity of the MCOA0 and MCOB0 pins. [2:2] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE0 Controls the dead-time feature for channel 0. [3:3] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP0 Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). [4:4] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [7:5] RUN1 Stops/starts timer channel 1. [8:8] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER1 Edge/center aligned operation for channel 1. [9:9] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA1 Selects polarity of the MCOA1 and MCOB1 pins. [10:10] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE1 Controls the dead-time feature for channel 1. [11:11] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP1 Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). [12:12] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [15:13] RUN2 Stops/starts timer channel 2. [16:16] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER2 Edge/center aligned operation for channel 2. [17:17] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA2 Selects polarity of the MCOA2 and MCOB2 pins. [18:18] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE2 Controls the dead-time feature for channel 1. [19:19] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP2 Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). [20:20] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [28:21] INVBDC Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. [29:29] ENUM OPPOSITE The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). 0 SAME The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6) 1 ACMODE 3-phase AC mode select (see Section 24.8.7). [30:30] ENUM 3_PHASE_AC_MODE_OFF 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. 0 3_PHASE_AC_MODE_ON_ 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. 1 DCMODE 3-phase DC mode select (see Section 24.8.6). [31:31] ENUM 3_PHASE_DC_MODE_OFF 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) 0 3_PHASE_DC_MODE_ON_ 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. 1 CON_SET PWM Control set address 0x004 write-only 0 0x00000000 RUN0_SET Writing a one sets the corresponding bit in the CON register. [0:0] CENTER0_SET Writing a one sets the corresponding bit in the CON register. [1:1] POLA0_SET Writing a one sets the corresponding bit in the CON register. [2:2] DTE0_SET Writing a one sets the corresponding bit in the CON register. [3:3] DISUP0_SET Writing a one sets the corresponding bit in the CON register. [4:4] RESERVED Writing a one sets the corresponding bit in the CON register. [7:5] RUN1_SET Writing a one sets the corresponding bit in the CON register. [8:8] CENTER1_SET Writing a one sets the corresponding bit in the CON register. [9:9] POLA1_SET Writing a one sets the corresponding bit in the CON register. [10:10] DTE1_SET Writing a one sets the corresponding bit in the CON register. [11:11] DISUP1_SET Writing a one sets the corresponding bit in the CON register. [12:12] RESERVED Writing a one sets the corresponding bit in the CON register. [15:13] RUN2_SET Writing a one sets the corresponding bit in the CON register. [16:16] CENTER2_SET Writing a one sets the corresponding bit in the CON register. [17:17] POLA2_SET Writing a one sets the corresponding bit in the CON register. [18:18] DTE2_SET Writing a one sets the corresponding bit in the CON register. [19:19] DISUP2_SET Writing a one sets the corresponding bit in the CON register. [20:20] RESERVED Writing a one sets the corresponding bit in the CON register. [28:21] INVBDC_SET Writing a one sets the corresponding bit in the CON register. [29:29] ACMODE_SET Writing a one sets the corresponding bit in the CON register. [30:30] DCMODE_SET Writing a one sets the corresponding bit in the CON register. [31:31] CON_CLR PWM Control clear address 0x008 write-only 0 0x00000000 RUN0_CLR Writing a one clears the corresponding bit in the CON register. [0:0] CENTER0_CLR Writing a one clears the corresponding bit in the CON register. [1:1] POLA0_CLR Writing a one clears the corresponding bit in the CON register. [2:2] DTE0_CLR Writing a one clears the corresponding bit in the CON register. [3:3] DISUP0_CLR Writing a one clears the corresponding bit in the CON register. [4:4] RESERVED Writing a one clears the corresponding bit in the CON register. [7:5] RUN1_CLR Writing a one clears the corresponding bit in the CON register. [8:8] CENTER1_CLR Writing a one clears the corresponding bit in the CON register. [9:9] POLA1_CLR Writing a one clears the corresponding bit in the CON register. [10:10] DTE1_CLR Writing a one clears the corresponding bit in the CON register. [11:11] DISUP1_CLR Writing a one clears the corresponding bit in the CON register. [12:12] RESERVED Writing a one clears the corresponding bit in the CON register. [15:13] RUN2_CLR Writing a one clears the corresponding bit in the CON register. [16:16] CENTER2_CLR Writing a one clears the corresponding bit in the CON register. [17:17] POLA2_CLR Writing a one clears the corresponding bit in the CON register. [18:18] DTE2_CLR Writing a one clears the corresponding bit in the CON register. [19:19] DISUP2_CLR Writing a one clears the corresponding bit in the CON register. [20:20] RESERVED Writing a one clears the corresponding bit in the CON register. [28:21] INVBDC_CLR Writing a one clears the corresponding bit in the CON register. [29:29] ACMOD_CLR Writing a one clears the corresponding bit in the CON register. [30:30] DCMODE_CLR Writing a one clears the corresponding bit in the CON register. [31:31] CAPCON Capture Control read address 0x00C read-only 0 0xFFFFFFFF CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. [0:0] CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. [1:1] CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. [2:2] CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. [3:3] CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. [4:4] CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. [5:5] CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. [6:6] CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. [7:7] CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. [8:8] CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. [9:9] CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. [10:10] CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. [11:11] CAP2MCI0_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. [12:12] CAP2MCI0_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. [13:13] CAP2MCI1_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. [14:14] CAP2MCI1_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. [15:15] CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. [16:16] CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. [17:17] RT0 If this bit is 1, TC0 is reset by a channel 0 capture event. [18:18] RT1 If this bit is 1, TC1 is reset by a channel 1 capture event. [19:19] RT2 If this bit is 1, TC2 is reset by a channel 2 capture event. [20:20] RESERVED Reserved. [31:21] CAPCON_SET Capture Control set address 0x010 write-only 0 0x00000000 CAP0MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [0:0] CAP0MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [1:1] CAP0MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [2:2] CAP0MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [3:3] CAP0MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [4:4] CAP0MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [5:5] CAP1MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [6:6] CAP1MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [7:7] CAP1MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [8:8] CAP1MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [9:9] CAP1MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [10:10] CAP1MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [11:11] CAP2MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [12:12] CAP2MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [13:13] CAP2MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [14:14] CAP2MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [15:15] CAP2MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [16:16] CAP2MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [17:17] RT0_SET Writing a one sets the corresponding bits in the CAPCON register. [18:18] RT1_SET Writing a one sets the corresponding bits in the CAPCON register. [19:19] RT2_SET Writing a one sets the corresponding bits in the CAPCON register. [20:20] RESERVED Reserved. [31:21] CAPCON_CLR Event Control clear address 0x014 write-only 0 0x00000000 CAP0MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [0:0] CAP0MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [1:1] CAP0MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [2:2] CAP0MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [3:3] CAP0MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [4:4] CAP0MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [5:5] CAP1MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [6:6] CAP1MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [7:7] CAP1MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [8:8] CAP1MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [9:9] CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [10:10] CAP1MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [11:11] CAP2MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [12:12] CAP2MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [13:13] CAP2MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [14:14] CAP2MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [15:15] CAP2MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [16:16] CAP2MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [17:17] RT0_CLR Writing a one clears the corresponding bits in the CAPCON register. [18:18] RT1_CLR Writing a one clears the corresponding bits in the CAPCON register. [19:19] RT2_CLR Writing a one clears the corresponding bits in the CAPCON register. [20:20] RESERVED Reserved. [31:21] 3 0x4 0-2 TC[%s] TC[%s] Timer Counter register 0x018 read-write 0 0xFFFFFFFF MCTC Timer/Counter value. [31:0] 3 0x4 0-2 LIM[%s] LIM[%s] Limit register 0x024 read-write 0 0xFFFFFFFF MCLIM Limit value. [31:0] 3 0x4 0-2 MAT[%s] MAT[%s] Match register 0x030 read-write 0 0xFFFFFFFF MCMAT Match value. [31:0] DT Dead time register 0x03C read-write 0x3FFFFFFF 0xFFFFFFFF DT0 Dead time for channel 0.[1] [9:0] DT1 Dead time for channel 1.[2] [19:10] DT2 Dead time for channel 2.[2] [29:20] RESERVED reserved [31:30] CCP Communication Pattern register 0x040 read-write 0 0xFFFFFFFF CCPA0 Communication pattern output A, channel 0. [0:0] ENUM MCOA0_PASSIVE_ MCOA0 passive. 0 INTERNAL_MCOA0_ internal MCOA0. 1 CCPB0 Communication pattern output B, channel 0. [1:1] ENUM MCOB0_PASSIVE_ MCOB0 passive. 0 MCOB0_TRACKS_INTERNA MCOB0 tracks internal MCOA0. 1 CCPA1 Communication pattern output A, channel 1. [2:2] ENUM MCOA1_PASSIVE_ MCOA1 passive. 0 MCOA1_TRACKS_INTERNA MCOA1 tracks internal MCOA0. 1 CCPB1 Communication pattern output B, channel 1. [3:3] ENUM MCOB1_PASSIVE_ MCOB1 passive. 0 MCOB1_TRACKS_INTERNA MCOB1 tracks internal MCOA0. 1 CCPA2 Communication pattern output A, channel 2. [4:4] ENUM MCOA2_PASSIVE_ MCOA2 passive. 0 MCOA2_TRACKS_INTERNA MCOA2 tracks internal MCOA0. 1 CCPB2 Communication pattern output B, channel 2. [5:5] ENUM MCOB2_PASSIVE_ MCOB2 passive. 0 MCOB2_TRACKS_INTERNA MCOB2 tracks internal MCOA0. 1 RESERVED Reserved. [31:6] 3 0x4 0-2 CAP[%s] CAP[%s] Capture register 0x044 read-only 0 0xFFFFFFFF CAP Current TC value at a capture event. [31:0] INTEN Interrupt Enable read address 0x050 read-only 0 0xFFFFFFFF ILIM0 Limit interrupt for channel 0. [0:0] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT0 Match interrupt for channel 0. [1:1] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP0 Capture interrupt for channel 0. [2:2] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [3:3] ILIM1 Limit interrupt for channel 1. [4:4] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT1 Match interrupt for channel 1. [5:5] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP1 Capture interrupt for channel 1. [6:6] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [7:7] ILIM2 Limit interrupt for channel 2. [8:8] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT2 Match interrupt for channel 2. [9:9] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP2 Capture interrupt for channel 2. [10:10] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [14:11] ABORT Fast abort interrupt. [15:15] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [31:16] INTEN_SET Interrupt Enable set address 0x054 write-only 0 0x00000000 ILIM0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [0:0] IMAT0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [1:1] ICAP0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [4:4] IMAT1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [5:5] ICAP1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [9:9] IMAT2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [10:10] ICAP2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [11:11] RESERVED Reserved. [14:12] ABORT_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [15:15] RESERVED Reserved. [31:16] INTEN_CLR Interrupt Enable clear address 0x058 write-only 0 0x00000000 ILIM0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [0:0] IMAT0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [1:1] ICAP0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [4:4] IMAT1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [5:5] ICAP1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [8:8] IMAT2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [9:9] ICAP2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [10:10] RESERVED Reserved. [14:11] ABORT_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [15:15] RESERVED Reserved. [31:16] INTF Interrupt flags read address 0x068 read-only 0 0xFFFFFFFF ILIM0_F Limit interrupt flag for channel 0. [0:0] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT0_F Match interrupt flag for channel 0. [1:1] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP0_F Capture interrupt flag for channel 0. [2:2] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [3:3] ILIM1_F Limit interrupt flag for channel 1. [4:4] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT1_F Match interrupt flag for channel 1. [5:5] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP1_F Capture interrupt flag for channel 1. [6:6] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [7:7] ILIM2_F Limit interrupt flag for channel 2. [8:8] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT2_F Match interrupt flag for channel 2. [9:9] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP2_F Capture interrupt flag for channel 2. [10:10] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [14:11] ABORT_F Fast abort interrupt flag. [15:15] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [31:16] INTF_SET Interrupt flags set address 0x06C write-only 0 0x00000000 ILIM0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [0:0] IMAT0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [1:1] ICAP0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [4:4] IMAT1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [5:5] ICAP1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [8:8] IMAT2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [9:9] ICAP2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [10:10] RESERVED Reserved. [14:11] ABORT_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [15:15] RESERVED Reserved. [31:16] INTF_CLR Interrupt flags clear address 0x070 write-only 0 0x00000000 ILIM0_F_CLR Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. [0:0] IMAT0_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [1:1] ICAP0_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [4:4] IMAT1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [5:5] ICAP1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [8:8] IMAT2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [9:9] ICAP2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [10:10] RESERVED Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [14:11] ABORT_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [15:15] RESERVED Reserved. [31:16] CNTCON Count Control read address 0x05C read-only 0 0xFFFFFFFF TC0MCI0_RE Counter 0 rising edge mode, channel 0. [0:0] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI0 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI0. 1 TC0MCI0_FE Counter 0 falling edge mode, channel 0. [1:1] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI0 does not affect counter 0. 0 FALLING If MODE0 is 1, counter 0 advances on a falling edge on MCI0. 1 TC0MCI1_RE Counter 0 rising edge mode, channel 1. [2:2] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI1 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI1. 1 TC0MCI1_FE Counter 0 falling edge mode, channel 1. [3:3] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI1 does not affect counter 0. 0 FALLING If MODE0 is 1, counter 0 advances on a falling edge on MCI1. 1 TC0MCI2_RE Counter 0 rising edge mode, channel 2. [4:4] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI0 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI2. 1 TC0MCI2_FE Counter 0 falling edge mode, channel 2. [5:5] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI0 does not affect counter 0. 0 FALLLING If MODE0 is 1, counter 0 advances on a falling edge on MCI2. 1 TC1MCI0_RE Counter 1 rising edge mode, channel 0. [6:6] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI0 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI0. 1 TC1MCI0_FE Counter 1 falling edge mode, channel 0. [7:7] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI0 does not affect counter 1. 0 FALLING If MODE1 is 1, counter 1 advances on a falling edge on MCI0. 1 TC1MCI1_RE Counter 1 rising edge mode, channel 1. [8:8] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI1 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI1. 1 TC1MCI1_FE Counter 1 falling edge mode, channel 1. [9:9] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI0 does not affect counter 1. 0 FALLING If MODE1 is 1, counter 1 advances on a falling edge on MCI1. 1 TC1MCI2_RE Counter 1 rising edge mode, channel 2. [10:10] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI2 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI2. 1 TC1MCI2_FE Counter 1 falling edge mode, channel 2. [11:11] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI2 does not affect counter 1. 0 FALLING If MODE1 is 1, counter 1 advances on a falling edge on MCI2. 1 TC2MCI0_RE Counter 2 rising edge mode, channel 0. [12:12] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI0 does not affect counter 2. 0 RISING If MODE2 is 1, counter 2 advances on a rising edge on MCI0. 1 TC2MCI0_FE Counter 2 falling edge mode, channel 0. [13:13] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI0 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI0. 1 TC2MCI1_RE Counter 2 rising edge mode, channel 1. [14:14] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI1 does not affect counter 2. 0 RISING If MODE2 is 1, counter 2 advances on a rising edge on MCI1. 1 TC2MCI1_FE Counter 2 falling edge mode, channel 1. [15:15] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI1 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI1. 1 TC2MCI2_RE Counter 2 rising edge mode, channel 2. [16:16] ENUM A_RISING_EDGE_ON_MCI A rising edge on MCI2 does not affect counter 2. 0 RISIING If MODE2 is 1, counter 2 advances on a rising edge on MCI2. 1 TC2MCI2_FE Counter 2 falling edge mode, channel 2. [17:17] ENUM A_FALLING_EDGE_ON_MC A falling edge on MCI2 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI2. 1 RESERVED Reserved. [28:18] CNTR0 Channel 0 counter/timer mode. [29:29] ENUM CHANNEL_0_IS_IN_TIME Channel 0 is in timer mode. 0 CHANNEL_0_IS_IN_COUN Channel 0 is in counter mode. 1 CNTR1 Channel 1 counter/timer mode. [30:30] ENUM CHANNEL_1_IS_IN_TIME Channel 1 is in timer mode. 0 CHANNEL_1_IS_IN_COUN Channel 1 is in counter mode. 1 CNTR2 Channel 2 counter/timer mode. [31:31] ENUM CHANNEL_2_IS_IN_TIME Channel 2 is in timer mode. 0 CHANNEL_2_IS_IN_COUN Channel 2 is in counter mode. 1 CNTCON_SET Count Control set address 0x060 write-only 0 0x00000000 TC0MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [0:0] TC0MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [1:1] TC0MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [2:2] TC0MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [3:3] TC0MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [4:4] TC0MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [5:5] TC1MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [6:6] TC1MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [7:7] TC1MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [8:8] TC1MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [9:9] TC1MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [10:10] TC1MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [11:11] TC2MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [12:12] TC2MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [13:13] TC2MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [14:14] TC2MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [15:15] TC2MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [16:16] TC2MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [17:17] RESERVED Reserved. [28:18] CNTR0_SET Writing a one sets the corresponding bit in the CNTCON register. [29:29] CNTR1_SET Writing a one sets the corresponding bit in the CNTCON register. [30:30] CNTR2_SET Writing a one sets the corresponding bit in the CNTCON register. [31:31] CNTCON_CLR Count Control clear address 0x064 write-only 0 0x00000000 TC0MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [0:0] TC0MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [1:1] TC0MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [2:2] TC0MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [3:3] TC0MCI2_RE Writing a one clears the corresponding bit in the CNTCON register. [4:4] TC0MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [5:5] TC1MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [6:6] TC1MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [7:7] TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [8:8] TC1MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [9:9] TC1MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [10:10] TC1MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [11:11] TC2MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [12:12] TC2MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [13:13] TC2MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [14:14] TC2MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [15:15] TC2MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [16:16] TC2MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [17:17] RESERVED Reserved. [28:18] CNTR0_CLR Writing a one clears the corresponding bit in the CNTCON register. [29:29] CNTR1_CLR Writing a one clears the corresponding bit in the CNTCON register. [30:30] CNTR2_CLR Writing a one clears the corresponding bit in the CNTCON register. [31:31] CAP_CLR Capture clear address 0x074 write-only 0 0x00000000 CAP_CLR0 Writing a 1 to this bit clears the CAP0 register. [0:0] CAP_CLR1 Writing a 1 to this bit clears the CAP1 register. [1:1] CAP_CLR2 Writing a 1 to this bit clears the CAP2 register. [2:2] RESERVED Reserved [31:3] QEI Quadrature Encoder Interface (QEI) QEI 0x400BC000 0x0 0xFFF registers QEI 31 CON Control register 0x000 write-only 0 0x00000000 RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. [0:0] RESPI Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared. [1:1] RESV Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared. [2:2] RESI Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] CONF Configuration register 0x008 read-write 0 0xFFFFFFFF DIRINV Direction invert. When 1, complements the DIR bit. [0:0] SIGMODE Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal. [1:1] CAPMODE Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. [2:2] INVINX Invert Index. When 1, inverts the sense of the index input. [3:3] CRESPI Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [15:5] INXGATE Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index. [19:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:20] STAT Status register 0x004 read-only 0 0xFFFFFFFF DIR Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] POS Position register 0x00C read-only 0 0xFFFFFFFF POS Current position value. [31:0] MAXPOS Maximum position register 0x010 read-write 0 0xFFFFFFFF MAXPOS Current maximum position value. [31:0] CMPOS0 Position compare register 0 0x014 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP0 Position compare value 0. [31:0] CMPOS1 Position compare register 1 0x018 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP1 Position compare value 1. [31:0] CMPOS2 Position compare register 2 0x01C read-write 0xFFFFFFFF 0xFFFFFFFF PCMP2 Position compare value 2. [31:0] INXCNT Index count register 0 0x020 read-only 0 0xFFFFFFFF ENCPOS Current index counter value. [31:0] INXCMP0 Index compare register 0 0x024 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP0 Index compare value 0. [31:0] LOAD Velocity timer reload register 0x028 read-write 0 0xFFFFFFFF VELLOAD Current velocity timer load value. [31:0] TIME Velocity timer register 0x02C read-only 0 0xFFFFFFFF VELVAL Current velocity timer value. [31:0] VEL Velocity counter register 0x030 read-only 0 0xFFFFFFFF VELPC Current velocity pulse count. [31:0] CAP Velocity capture register 0x034 read-only 0xFFFFFFFF 0xFFFFFFFF VELCAP Last velocity capture. [31:0] VELCOMP Velocity compare register 0x038 read-write 0 0xFFFFFFFF VELPC Compare velocity pulse count. [31:0] FILTERPHA Digital filter register on PHA 0x03C read-write 0 0xFFFFFFFF FILTA Digital filter sampling delay for PhA. [31:0] FILTERPHB Digital filter register on PHB 0x040 read-write 0 0xFFFFFFFF FILTB Digital filter sampling delay for PhB. [31:0] FILTERINX Digital filter register on IDX 0x044 read-write 0 0xFFFFFFFF FITLINX Digital filter sampling delay for the index. [31:0] WINDOW Index acceptance window register 0x048 read-write 0xF 0xFFFFFFFF WINDOW Index acceptance window width. [31:0] INXCMP1 Index compare register 1 0x04C read-write 0xFFFFFFFF 0xFFFFFFFF ICMP1 Index compare value 1. [31:0] INXCMP2 Index compare register 2 0x050 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP2 Index compare value 2. [31:0] INTSTAT Interrupt status register 0xFE0 read-only 0 0xFFFFFFFF INX_INT Indicates that an index pulse was detected. [0:0] TIM_INT Indicates that a velocity timer overflow occurred [1:1] VELC_INT Indicates that captured velocity is less than compare velocity. [2:2] DIR_INT Indicates that a change of direction was detected. [3:3] ERR_INT Indicates that an encoder phase error was detected. [4:4] ENCLK_INT Indicates that and encoder clock pulse was detected. [5:5] POS0_INT Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_INT Indicates that the position 1compare value is equal to the current position. [7:7] POS2_INT Indicates that the position 2 compare value is equal to the current position. [8:8] REV0_INT Indicates that the index compare 0 value is equal to the current index count. [9:9] POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set. [10:10] POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set. [11:11] POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set. [12:12] REV1_INT Indicates that the index compare 1value is equal to the current index count. [13:13] REV2_INT Indicates that the index compare 2 value is equal to the current index count. [14:14] MAXPOS_INT Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] SET Interrupt status set register 0xFEC write-only 0 0x00000000 INX_INT Writing a 1 sets the INX_Int bit in QEIINTSTAT. [0:0] TIM_INT Writing a 1 sets the TIN_Int bit in QEIINTSTAT. [1:1] VELC_INT Writing a 1 sets the VELC_Int bit in QEIINTSTAT. [2:2] DIR_INT Writing a 1 sets the DIR_Int bit in QEIINTSTAT. [3:3] ERR_INT Writing a 1 sets the ERR_Int bit in QEIINTSTAT. [4:4] ENCLK_INT Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT. [5:5] POS0_INT Writing a 1 sets the POS0_Int bit in QEIINTSTAT. [6:6] POS1_INT Writing a 1 sets the POS1_Int bit in QEIINTSTAT. [7:7] POS2_INT Writing a 1 sets the POS2_Int bit in QEIINTSTAT. [8:8] REV0_INT Writing a 1 sets the REV0_Int bit in QEIINTSTAT. [9:9] POS0REV_INT Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT. [10:10] POS1REV_INT Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT. [11:11] POS2REV_INT Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT. [12:12] REV1_INT Writing a 1 sets the REV1_Int bit in QEIINTSTAT. [13:13] REV2_INT Writing a 1 sets the REV2_Int bit in QEIINTSTAT. [14:14] MAXPOS_INT Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] CLR Interrupt status clear register 0xFE8 write-only 0 0x00000000 INX_INT Writing a 1 clears the INX_Int bit in QEIINTSTAT. [0:0] TIM_INT Writing a 1 clears the TIN_Int bit in QEIINTSTAT. [1:1] VELC_INT Writing a 1 clears the VELC_Int bit in QEIINTSTAT. [2:2] DIR_INT Writing a 1 clears the DIR_Int bit in QEIINTSTAT. [3:3] ERR_INT Writing a 1 clears the ERR_Int bit in QEIINTSTAT. [4:4] ENCLK_INT Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT. [5:5] POS0_INT Writing a 1 clears the POS0_Int bit in QEIINTSTAT. [6:6] POS1_INT Writing a 1 clears the POS1_Int bit in QEIINTSTAT. [7:7] POS2_INT Writing a 1 clears the POS2_Int bit in QEIINTSTAT. [8:8] REV0_INT Writing a 1 clears the REV0_Int bit in QEIINTSTAT. [9:9] POS0REV_INT Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT. [10:10] POS1REV_INT Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT. [11:11] POS2REV_INT Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT. [12:12] REV1_INT Writing a 1 clears the REV1_Int bit in QEIINTSTAT. [13:13] REV2_INT Writing a 1 clears the REV2_Int bit in QEIINTSTAT. [14:14] MAXPOS_INT Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] IE Interrupt enable register 0xFE4 read-only 0 0xFFFFFFFF INX_INT When 1, the INX_Int interrupt is enabled. [0:0] TIM_INT When 1, the TIN_Int interrupt is enabled. [1:1] VELC_INT When 1, the VELC_Int interrupt is enabled. [2:2] DIR_INT When 1, the DIR_Int interrupt is enabled. [3:3] ERR_INT When 1, the ERR_Int interrupt is enabled. [4:4] ENCLK_INT When 1, the ENCLK_Int interrupt is enabled. [5:5] POS0_INT When 1, the POS0_Int interrupt is enabled. [6:6] POS1_INT When 1, the POS1_Int interrupt is enabled. [7:7] POS2_INT When 1, the POS2_Int interrupt is enabled. [8:8] REV0_INT When 1, the REV0_Int interrupt is enabled. [9:9] POS0REV_INT When 1, the POS0REV_Int interrupt is enabled. [10:10] POS1REV_INT When 1, the POS1REV_Int interrupt is enabled. [11:11] POS2REV_INT When 1, the POS2REV_Int interrupt is enabled. [12:12] REV1_INT When 1, the REV1_Int interrupt is enabled. [13:13] REV2_INT When 1, the REV2_Int interrupt is enabled. [14:14] MAXPOS_INT When 1, the MAXPOS_Int interrupt is enabled. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] IES Interrupt enable set register 0xFDC write-only 0 0x00000000 INX_INT Writing a 1 enables the INX_Int interrupt in the QEIIE register. [0:0] TIM_INT Writing a 1 enables the TIN_Int interrupt in the QEIIE register. [1:1] VELC_INT Writing a 1 enables the VELC_Int interrupt in the QEIIE register. [2:2] DIR_INT Writing a 1 enables the DIR_Int interrupt in the QEIIE register. [3:3] ERR_INT Writing a 1 enables the ERR_Int interrupt in the QEIIE register. [4:4] ENCLK_INT Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. [5:5] POS0_INT Writing a 1 enables the POS0_Int interrupt in the QEIIE register. [6:6] POS1_INT Writing a 1 enables the POS1_Int interrupt in the QEIIE register. [7:7] POS2_INT Writing a 1 enables the POS2_Int interrupt in the QEIIE register. [8:8] REV0_INT Writing a 1 enables the REV0_Int interrupt in the QEIIE register. [9:9] POS0REV_INT Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. [10:10] POS1REV_INT Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. [11:11] POS2REV_INT Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. [12:12] REV1_INT Writing a 1 enables the REV1_Int interrupt in the QEIIE register. [13:13] REV2_INT Writing a 1 enables the REV2_Int interrupt in the QEIIE register. [14:14] MAXPOS_INT Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] IEC Interrupt enable clear register 0xFD8 write-only 0 0x00000000 INX_INT Writing a 1 disables the INX_Int interrupt in the QEIIE register. [0:0] TIM_INT Writing a 1 disables the TIN_Int interrupt in the QEIIE register. [1:1] VELC_INT Writing a 1 disables the VELC_Int interrupt in the QEIIE register. [2:2] DIR_INT Writing a 1 disables the DIR_Int interrupt in the QEIIE register. [3:3] ERR_INT Writing a 1 disables the ERR_Int interrupt in the QEIIE register. [4:4] ENCLK_INT Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register. [5:5] POS0_INT Writing a 1 disables the POS0_Int interrupt in the QEIIE register. [6:6] POS1_INT Writing a 1 disables the POS1_Int interrupt in the QEIIE register. [7:7] POS2_INT Writing a 1 disables the POS2_Int interrupt in the QEIIE register. [8:8] REV0_INT Writing a 1 disables the REV0_Int interrupt in the QEIIE register. [9:9] POS0REV_INT Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register. [10:10] POS1REV_INT Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register. [11:11] POS2REV_INT Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register. [12:12] REV1_INT Writing a 1 disables the REV1_Int interrupt in the QEIIE register. [13:13] REV2_INT Writing a 1 disables the REV2_Int interrupt in the QEIIE register. [14:14] MAXPOS_INT Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] SDMMC SD card SDMMC 0x400C0000 0x0 0xFFFF registers SDMMC 29 PWR Power control register. 0x000 read-write 0 0xFFFFFFFF CTRL Power control [1:0] ENUM POWER_OFF Power-off 0x0 RESERVED Reserved 0x1 POWER_UP Power-up 0x2 POWER_ON Power-on 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [5:2] OPENDRAIN SD_CMD output control. [6:6] ROD Rod control. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] CLOCK Clock control register. 0x004 read-write 0 0xFFFFFFFF CLKDIV Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]. [7:0] ENABLE Enable SD card bus clock: [8:8] ENUM CLOCK_DISABLED_ Clock disabled. 0 CLOCK_ENABLED_ Clock enabled. 1 PWRSAVE Disable SD_CLK output when bus is idle: [9:9] ENUM ALWAYS_ENABLED_ Always enabled. 0 CLOCK_ENABLED_WHEN_B Clock enabled when bus is active. 1 BYPASS Enable bypass of clock divide logic: [10:10] ENUM DISABLE_BYPASS_ Disable bypass. 0 ENABLE_BYPASS_MCLK_ Enable bypass. MCLK driven to card bus output (SD_CLK). 1 WIDEBUS Enable wide bus mode. [11:11] ENUM STANDARD_BUS_MODE_O Standard bus mode (only SD_DAT[0] used). 0 WIDE_BUS_MODE_SD_DA Wide bus mode (SD_DAT[3:0] used) 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] ARGUMENT Argument register. 0x008 read-write 0 0xFFFFFFFF CmdArg Command argument [31:0] COMMAND Command register. 0x00C read-write 0 0xFFFFFFFF CmdIndex Command index. [5:0] Response If set, CPSM waits for a response. [6:6] LongRsp If set, CPSM receives a 136 bit long response. [7:7] Interrupt If set, CPSM disables command timer and waits for interrupt request. [8:8] Pending If set, CPSM waits for CmdPend before it starts sending a command. [9:9] Enable If set, CPSM is enabled. [10:10] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] RESPCMD Response command register. 0x010 read-only 0 0xFFFFFFFF RESPCMD Response command index [5:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] 4 0x4 0-3 RESPONSE%s Response register. 0x014 read-only 0 0xFFFFFFFF STATUS Card status [31:0] DATATIMER Data Timer. 0x024 read-write 0 0xFFFFFFFF DATATIME Data timeout period. [31:0] DATALENGTH Data length register. 0x028 read-write 0 0xFFFFFFFF DATALENGTH Data length value [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] DATACTRL Data control register. 0x02C read-write 0 0xFFFFFFFF ENABLE Data transfer enable. [0:0] DIRECTION Data transfer direction [1:1] ENUM FROM_CONTROLLER_TO_C From controller to card. 0 FROM_CARD_TO_CONTROL From card to controller. 1 MODE Data transfer mode [2:2] ENUM BLOCK_DATA_TRANSFER_ Block data transfer. 0 STREAM_DATA_TRANSFER Stream data transfer. 1 DMAENABLE Enable DMA [3:3] ENUM DMA_DISABLED_ DMA disabled. 0 DMA_ENABLED_ DMA enabled. 1 BLOCKSIZE Data block length [7:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] DATACNT Data counter. 0x030 read-only 0 0xFFFFFFFF DATACOUNT Remaining data [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] STATUS Status register. 0x034 read-only 0 0xFFFFFFFF CMDCRCFAIL Command response received (CRC check failed). [0:0] DATACRCFAIL Data block sent/received (CRC check failed). [1:1] CMDTIMEOUT Command response timeout. [2:2] DATATIMEOUT Data timeout. [3:3] TXUNDERRUN Transmit FIFO underrun error. [4:4] RXOVERRUN Receive FIFO overrun error. [5:5] CMDRESPEND Command response received (CRC check passed). [6:6] CMDSENT Command sent (no response required). [7:7] DATAEND Data end (data counter is zero). [8:8] STARTBITERR Start bit not detected on all data signals in wide bus mode. [9:9] DATABLOCKEND Data block sent/received (CRC check passed). [10:10] CMDACTIVE Command transfer in progress. [11:11] TXACTIVE Data transmit in progress. [12:12] RXACTIVE Data receive in progress. [13:13] TXFIFOHALFEMPTY Transmit FIFO half empty. [14:14] RXFIFOHALFFULL Receive FIFO half full. [15:15] TXFIFOFULL Transmit FIFO full. [16:16] RXFIFOFULL Receive FIFO full. [17:17] TXFIFOEMPTY Transmit FIFO empty. [18:18] RXFIFOEMPTY Receive FIFO empty. [19:19] TXDATAAVLBL Data available in transmit FIFO. [20:20] RXDATAAVLBL Data available in receive FIFO. [21:21] RESERVED Reserved. The value read from a reserved bit is not defined. [31:22] CLEAR Clear register. 0x038 write-only 0 0x00000000 CMDCRCFAILCLR Clears CmdCrcFail flag. [0:0] DATACRCFAILCLR Clears DataCrcFail flag. [1:1] CMDTIMEOUTCLR Clears CmdTimeOut flag. [2:2] DATATIMEOUTCLR Clears DataTimeOut flag. [3:3] TXUNDERRUNCLR Clears TxUnderrun flag. [4:4] RXOVERRUNCLR Clears RxOverrun flag. [5:5] CMDRESPENDCLR Clears CmdRespEnd flag. [6:6] CMDSENTCLR Clears CmdSent flag. [7:7] DATAENDCLR Clears DataEnd flag. [8:8] STARTBITERRCLR Clears StartBitErr flag. [9:9] DATABLOCKENDCLR Clears DataBlockEnd flag. [10:10] RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] MASK0 Interrupt 0 mask register. 0x03C read-write 0 0xFFFFFFFF MASK0 Mask CmdCrcFail flag. [0:0] MASK1 Mask DataCrcFail flag. [1:1] MASK2 Mask CmdTimeOut flag. [2:2] MASK3 Mask DataTimeOut flag. [3:3] MASK4 Mask TxUnderrun flag. [4:4] MASK5 Mask RxOverrun flag. [5:5] MASK6 Mask CmdRespEnd flag. [6:6] MASK7 Mask CmdSent flag. [7:7] MASK8 Mask DataEnd flag. [8:8] MASK9 Mask StartBitErr flag. [9:9] MASK10 Mask DataBlockEnd flag. [10:10] MASK11 Mask CmdActive flag. [11:11] MASK12 Mask TxActive flag. [12:12] MASK13 Mask RxActive flag. [13:13] MASK14 Mask TxFifoHalfEmpty flag. [14:14] MASK15 Mask RxFifoHalfFull flag. [15:15] MASK16 Mask TxFifoFull flag. [16:16] MASK17 Mask RxFifoFull flag. [17:17] MASK18 Mask TxFifoEmpty flag. [18:18] MASK19 Mask RxFifoEmpty flag. [19:19] MASK20 Mask TxDataAvlbl flag. [20:20] MASK21 Mask RxDataAvlbl flag. [21:21] RESERVED Reserved. Read value is undefined, only zero should be written. [31:22] FIFOCNT FIFO Counter. 0x048 read-only 0 0xFFFFFFFF DATACOUNT Remaining data [14:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:15] 16 0x4 0-15 FIFO%s Data FIFO Register. 0x080 read-write 0 0xFFFFFFFF DATA FIFO data. [31:0] SYSCON System and clock control SYSCON 0x400FC000 0x0 0xFFF registers EINT0 18 EINT1 19 EINT2 20 EINT3 21 BOD 23 FLASHCFG Flash Accelerator Configuration Register. Controls flash access timing. 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved, user software should not change these bits from the reset value. [11:0] FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved. [15:12] ENUM FLASH_ACCESSES_USE_1 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off. 0x0 FLASH_ACCESSES_USE_2 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off. 0x1 FLASH_ACCESSES_USE_3 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off. 0x2 FLASH_ACCESSES_USE_4 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on. 0x3 FLASH_ACCESSES_USE_5 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off. 0x4 FLASH_ACCESSES_USE_6 Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions. 0x5 RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] 2 0x20 0-1 PLLCON%s PLL0 Control register 0x080 read-write 0 0xFFFFFFFF PLLE PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] 2 0x20 0-1 PLLCFG%s PLL0 Configuration register 0x084 read-write 0 0xFFFFFFFF MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4. [4:0] PSEL PLL Divider value. Supplies the value "P" in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4. [6:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] 2 0x20 0-1 PLLSTAT%s PLL0 Status register 0x088 read-only 0 0xFFFFFFFF MSEL Read-back for the PLL Multiplier value. This is the value currently used by the related PLL. [4:0] PSEL Read-back for the PLL Divider value. This is the value currently used by the related PLL. [6:5] RESERVED Reserved. The value read from a reserved bit is not defined. [7:7] PLLE_STAT Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated. [8:8] RESERVED Reserved. The value read from a reserved bit is not defined. [9:9] PLOCK Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency. [10:10] RESERVED Reserved. The value read from a reserved bit is not defined. [31:11] 2 0x20 0-1 PLLFEED%s PLL0 Feed register 0x08C write-only 0 0x00000000 PLLFEED The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] PCON Power Control register 0x0C0 read-write 0 0xFFFFFFFF PM0 Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details. [0:0] PM1 Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details. [1:1] BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. [2:2] BOGD Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. [3:3] BORD Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [7:3] SMFLAG Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. [8:8] DSFLAG Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit. [9:9] PDFLAG Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. [10:10] DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [31:12] PCONP0 Power Control for Peripherals 0x0C4 read-write 0x0408829E 0xFFFFFFFF PCLCD LCD controller power/clock control bit. [0:0] PCTIM0 Timer/Counter 0 power/clock control bit. [1:1] PCTIM1 Timer/Counter 1 power/clock control bit. [2:2] PCUART0 UART0 power/clock control bit. [3:3] PCUART1 UART1 power/clock control bit. [4:4] PCPWM0 PWM0 power/clock control bit. [5:5] PCPWM1 PWM1 power/clock control bit. [6:6] PCI2C0 I2C0 interface power/clock control bit. [7:7] PCUART4 UART4 power/clock control bit. [8:8] PCRTC RTC and Event Monitor/Recorder power/clock control bit. [9:9] PCSSP1 SSP 1 interface power/clock control bit. [10:10] PCEMC External Memory Controller power/clock control bit. [11:11] PCADC A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN. [12:12] PCCAN1 CAN Controller 1 power/clock control bit. [13:13] PCCAN2 CAN Controller 2 power/clock control bit. [14:14] PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. [15:15] PCSPIFI SPI Flash Interface power/clock control bit. [16:16] PCMCPWM Motor Control PWM power/clock control bit. [17:17] PCQEI Quadrature Encoder Interface power/clock control bit. [18:18] PCI2C1 I2C1 interface power/clock control bit. [19:19] PCSSP2 SSP2 interface power/clock control bit. [20:20] PCSSP0 SSP0 interface power/clock control bit. [21:21] PCTIM2 Timer 2 power/clock control bit. [22:22] PCTIM3 Timer 3 power/clock control bit. [23:23] PCUART2 UART 2 power/clock control bit. [24:24] PCUART3 UART 3 power/clock control bit. [25:25] PCI2C2 I2C interface 2 power/clock control bit. [26:26] PCI2S I2S interface power/clock control bit. [27:27] PCSDC SD Card interface power/clock control bit. [28:28] PCGPDMA GPDMA function power/clock control bit. [29:29] PCENET Ethernet block power/clock control bit. [30:30] PCUSB USB interface power/clock control bit. [31:31] PCONP1 Power Control for Peripherals 0x0C8 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved. [2:0] PCCMP comparator 0/1 power/clock control bit. [3:3] RESERVED Reserved. [31:4] EMCCLKSEL External Memory Controller Clock Selection register 0x100 read-write 0 0xFFFFFFFF EMCDIV Selects the EMC clock rate relative to the CPU clock. [0:0] ENUM THE_EMC_USES_THE_SAM The EMC uses the same clock as the CPU. 0 THE_EMC_USES_A_CLOCK The EMC uses a clock at half the rate of the CPU. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] CCLKSEL CPU Clock Selection register 0x104 read-write 0 0x00000000 CCLKDIV Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock. [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:5] CCLKSEL Selects the input clock for the CPU clock divider. [8:8] ENUM SYSCLK_IS_USED_AS_TH Sysclk is used as the input to the CPU clock divider. 0 THE_OUTPUT_OF_THE_MA The output of the Main PLL is used as the input to the CPU clock divider. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] USBCLKSEL USB Clock Selection register 0x108 read-write 0 0xFFFFFFFF USBDIV Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation. [4:0] ENUM THE_DIVIDER_IS_TURNE The divider is turned off, no clock will be provided to the USB subsystem. 0x0 PLL0_OUTPUT_IS_DIVID PLL0 output is divided by 4. PLL0 output must be 192 MHz. 0x4 PLL0_OUTPUT_IS_DIVID PLL0 output is divided by 6. PLL0 output must be 288 MHz. 0x6 RESERVED Reserved. Read value is undefined, only zero should be written. [7:5] USBSEL Selects the input clock for the USB clock divider. [9:8] ENUM SYSCLK Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions. 0x0 MAINPLLOUT The output of the Main PLL is used as the input to the USB clock divider. 0x1 ALTPLLOOUT The output of the Alt PLL is used as the input to the USB clock divider. 0x2 RESERVED Reserved, this setting should not be used. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] CLKSRCSEL Clock Source Select Register 0x10C read-write 0 0xFFFFFFFF CLKSRC Selects the clock source for sysclk and PLL0 as follows: [0:0] ENUM SELECTS_THE_INTERNAL Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default). 0 SELECTS_THE_MAIN_OSC Selects the main oscillator as the sysclk and PLL0 clock source. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] CANSLEEPCLR Allows clearing the current CAN channel sleep state as well as reading that state. 0x110 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] CAN1SLEEP Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. [1:1] CAN2SLEEP Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] CANWAKEFLAGS Allows reading the wake-up state of the CAN channels. 0x114 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] CAN1WAKE Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. [1:1] CAN2WAKE Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] EXTINT External Interrupt Flag Register 0x140 read-write 0 0xFFFFFFFF EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] [0:0] EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] [1:1] EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] [2:2] EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] EXTMODE External Interrupt Mode register 0x148 read-write 0 0xFFFFFFFF EXTMODE0 Level or edge sensitivity select for EINT0. [0:0] ENUM LEVEL_SENSITIVE_ Level sensitive. 0 EDGE_SENSITIVE_ Edge sensitive. 1 EXTMODE1 Level or edge sensitivity select for EINT1. [1:1] ENUM LEVEL_SENSITIVE_ Level sensitive. 0 EDGE_SENSITIVE_ Edge sensitive. 1 EXTMODE2 Level or edge sensitivity select for EINT2. [2:2] ENUM LEVEL_SENSITIVE_ Level sensitive. 0 EDGE_SENSITIVE_ Edge sensitive. 1 EXTMODE3 Level or edge sensitivity select for EINT3. [3:3] ENUM LEVEL_SENSITIVE_ Level sensitive. 0 EDGE_SENSITIVE_ Edge sensitive. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] EXTPOLAR External Interrupt Polarity Register 0x14C read-write 0 0xFFFFFFFF EXTPOLAR0 External interrupt polarity for EINT0. [0:0] ENUM LOW_ACTIVE_OR_FALLIN Low-active or falling-edge sensitive (depending on EXTMODE0). 0 HIGH_ACTIVE_OR_RISIN High-active or rising-edge sensitive (depending on EXTMODE0). 1 EXTPOLAR1 External interrupt polarity for EINT1. [1:1] ENUM LOW_ACTIVE_OR_FALLIN Low-active or falling-edge sensitive (depending on EXTMODE1). 0 HIGH_ACTIVE_OR_RISIN High-active or rising-edge sensitive (depending on EXTMODE1). 1 EXTPOLAR2 External interrupt polarity for EINT2. [2:2] ENUM LOW_ACTIVE_OR_FALLIN Low-active or falling-edge sensitive (depending on EXTMODE2). 0 HIGH_ACTIVE_OR_RISIN High-active or rising-edge sensitive (depending on EXTMODE2). 1 EXTPOLAR3 External interrupt polarity for EINT3. [3:3] ENUM LOW_ACTIVE_OR_FALLIN Low-active or falling-edge sensitive (depending on EXTMODE3). 0 HIGH_ACTIVE_OR_RISIN High-active or rising-edge sensitive (depending on EXTMODE3). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] RSID Reset Source Identification Register 0x180 read-write 0 0x00000000 POR Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. [0:0] EXTR Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR. [1:1] WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR. [2:2] BODR This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. [3:3] SYSRESET This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR. [4:4] LOCKUP This bit is set if the processor has been reset due to a "lockup". The lockup state causes a chip reset. This bit is cleared only by software or POR. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] MATRIXARB Matrix arbitration register 0x188 read-write 0 0x00000000 PRI_ICODE I-Code bus priority. Should be lower than PRI_DCODE for proper operation. [1:0] PRI_DCODE D-Code bus priority. [3:2] PRI_SYS System bus priority. [5:4] PRI_GPDMA General Purpose DMA controller priority. [7:6] PRI_ETH Ethernet DMA priority. [9:8] PRI_LCD LCD DMA priority. [11:10] PRI_USB USB DMA priority. [13:12] RESERVED Reserved. Read value is undefined, only zero should be written. [15:14] ROM_LAT ROM latency select. Should always be 0. [16:16] RESERVED Reserved. Read value is undefined, only zero should be written. [31:17] SCS System Control and Status 0x1A0 read-write 0 0xFFFFFFFF EMCSC EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter. [0:0] ENUM STATIC_MEMORY_ADDRES Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift. 0 STATIC_MEMORY_ADDRES Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices. 1 EMCRD EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter. [1:1] ENUM BOTH_EMC_RESETS_ARE_ Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition. 0 MANY_PORTIONS_OF_THE Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset. 1 EMCBC External Memory Controller burst control. Also see Section 9.10 in the EMC chapter. [2:2] ENUM BURST_ENABLED_ Burst enabled. 0 BURST_DISABLED_THIS Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices. 1 MCIPWRAL MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR. [3:3] ENUM SD_PWR_IS_ACTIVE_LOW SD_PWR is active low (inverted output of the SD Card interface block). 0 SD_PWR_IS_ACTIVE_HIG SD_PWR is active high (follows the output of the SD Card interface block). 1 OSCRS Main oscillator range select. [4:4] ENUM THE_FREQUENCY_RANGE_ The frequency range of the main oscillator is 1 MHz to 20 MHz. 0 THE_FREQUENCY_RANGE_ The frequency range of the main oscillator is 15 MHz to 25 MHz. 1 OSCEN Main oscillator enable. [5:5] ENUM THE_MAIN_OSCILLATOR_ The main oscillator is disabled. 0 THE_MAIN_OSCILLATOR_ The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. 1 OSCSTAT Main oscillator status. [6:6] ENUM THE_MAIN_OSCILLATOR_ The main oscillator is not ready to be used as a clock source. 0 THE_MAIN_OSCILLATOR_ The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] PCLKSEL Peripheral Clock Selection register 0x1A8 read-write 0x10 0xFFFFFFFF PCLKDIV Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock. [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] PBOOST Power boost register 0x1B0 read-write 0 0x00000000 Boost Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed. [1:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] SPIFICLKSEL SPIFI Clock Selection register 0x1B4 read-write 0 0xFFFFFFFF SPIFIDIV Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock. [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:5] SPIFISEL Selects the input clock for the USB clock divider. [9:8] ENUM SYSCLK Sysclk is used as the input to the SPIFI clock divider. 0x0 MAINPLLOUT The output of the Main PLL is used as the input to the SPIFI clock divider. 0x1 ALTPLLOUT The output of the Alt PLL is used as the input to the SPIFI clock divider. 0x2 RESERVED Reserved, this setting should not be used. 0x3 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] LCD_CFG LCD Clock configuration register 0x1B8 read-write 0 0xFFFFFFFF CLKDIV LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock. [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] USBINTST USB Interrupt Status 0x1C0 read-write 0x80000000 0xFFFFFFFF USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. [0:0] USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. [1:1] USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. [2:2] USB_HOST_INT USB host interrupt line status. This bit is read-only. [3:3] USB_ATX_INT External ATX interrupt line status. This bit is read-only. [4:4] USB_OTG_INT OTG interrupt line status. This bit is read-only. [5:5] USB_I2C_INT I2C module interrupt line status. This bit is read-only. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] USB_NEED_CLK USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 "Wake-up from Reduced Power Modes" for details). Also see Section 3.10.3 "PLLs and Power-down mode" and Section 3.3.7 "Power Control for Peripherals registers" for considerations about the PLL and invoking the Power-down mode. This bit is read-only. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [30:9] EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines. [31:31] DMACREQSEL Selects between alternative requests on DMA channels 0 through 7 and 10 through 15 0x1C4 read-write 0 0xFFFFFFFF DMASEL00 Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected. [0:0] DMASEL01 Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected. [1:1] DMASEL02 Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected. [2:2] DMASEL03 Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected. [3:3] DMASEL04 Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected. [4:4] DMASEL05 Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected. [5:5] DMASEL06 Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected. [6:6] DMASEL07 Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [9:8] DMASEL10 Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected. [10:10] DMASEL11 Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected. [11:11] DMASEL12 Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected. [12:12] DMASEL13 Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected. [13:13] DMASEL14 Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected. [14:14] DMASEL15 Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] CLKOUTCFG Clock Output Configuration register 0x1C8 read-write 0 0xFFFFFFFF CLKOUTSEL Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use. [3:0] CLKOUTDIV Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16. [7:4] CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. [8:8] CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. [9:9] RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] RSTCON0 Individual peripheral reset control bits 0x1CC read-write 0 0xFFFFFFFF RSTLCD LCD controller reset control bit. [0:0] RSTTIM0 Timer/Counter 0 reset control bit. [1:1] RSTTIM1 Timer/Counter 1 reset control bit. [2:2] RSTUART0 UART0 reset control bit. [3:3] RSTUART1 UART1 reset control bit. [4:4] RSTPWM0 PWM0 reset control bit. [5:5] RSTPWM1 PWM1 reset control bit. [6:6] RSTI2C0 The I2C0 interface reset control bit. [7:7] RSTUART4 UART4 reset control bit. [8:8] RSTRTC RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 "Register overview: Real-Time Clock (base address 0x4002 4000)" for details. [9:9] RSTSSP1 The SSP 1 interface reset control bit. [10:10] RSTEMC External Memory Controller reset control bit. [11:11] RSTADC A/D converter (ADC) reset control bit. [12:12] RSTCAN1 CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register. [13:13] RSTCAN2 CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register. [14:14] RSTGPIO Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register. [15:15] RSTSPIFI SPI Flash Interface reset control bit. [16:16] RSTMCPWM Motor Control PWM reset control bit. [17:17] RSTQEI Quadrature Encoder Interface reset control bit. [18:18] RSTI2C1 The I2C1 interface reset control bit. [19:19] RSTSSP2 The SSP2 interface reset control bit. [20:20] RSTSSP0 The SSP0 interface reset control bit. [21:21] RSTTIM2 Timer 2 reset control bit. [22:22] RSTTIM3 Timer 3 reset control bit. [23:23] RSTUART2 UART 2 reset control bit. [24:24] RSTUART3 UART 3 reset control bit. [25:25] RSTI2C2 I2C interface 2 reset control bit. [26:26] RSTI2S I2S interface reset control bit. [27:27] RSTSDC SD Card interface reset control bit. [28:28] RSTGPDMA GPDMA function reset control bit. [29:29] RSTENET Ethernet block reset control bit. [30:30] RSTUSB USB interface reset control bit. [31:31] RSTCON1 Individual peripheral reset control bits 0x1D0 read-write 0 0xFFFFFFFF RSTIOCON Reset control bit for the IOCON registers. [0:0] RSTDAC D/A converter (DAC) reset control bit. [1:1] RSTCANACC CAN acceptance filter reset control bit. [2:2] RSTCMP Comparator 0/1 reset control bit. [3:3] RESERVED Reserved. Read value is undefined, only zero should be written. [31:4] EMCDLYCTL Values for the 4 programmable delays associated with SDRAM operation. 0x1DC read-write 0x210 0xFFFFFFFF CMDDLY Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet. [4:0] RESERVED Reserved. Read value is undefined, only zero should be written. [7:5] FBCLKDLY Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds. [12:8] RESERVED Reserved. Read value is undefined, only zero should be written. [15:13] CLKOUT0DLY Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet. [20:16] RESERVED Reserved. Read value is undefined, only zero should be written. [23:21] CLKOUT1DLY Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds. [28:24] RESERVED Reserved. Read value is undefined, only zero should be written. [31:29] EMCCAL Controls the calibration counter for programmable delays and returns the result value. 0x1E0 read-write 0x1F00 0xFFFFFFFF CALVALUE Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [13:8] START Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete. [14:14] DONE Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16]