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RMUL2025/lib/cmsis_svd/data/NXP/LPC11Axxv0.6.svd

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>LPC11Axx</name>
<version>0.6</version>
<description>LPC11Axx</description>
<cpu>
<name>CM0</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>0</mpuPresent>
<fpuPresent>0</fpuPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>0</vendorSystickConfig>
</cpu>
<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<!--
Software that is described herein is for illustrative purposes only
which provides customers with programming information regarding the
products. This software is supplied "AS IS" without any warranties.
NXP Semiconductors assumes no responsibility or liability for the
use of the software, conveys no license or title under any patent,
copyright, or mask work right to the product. NXP Semiconductors
reserves the right to make changes in the software without
notification. NXP Semiconductors also make no representation or
warranty that such application will be suitable for the specified
use without further testing or modification.
-->
<!--
updates:
v02: - add PINTSEL registers in syscon block
- add PIOPORCAP1 registers added
- DACR register renamed to CR
- ACMP prefix removed
- BOD bit 3 in PDRUNCFG register changed to reserved
v03: remove UM number from peripheral description
- ADC SEL register bits updated
v04: - fix iocon function bits
- update syscon
v05: - add SYSOSCCTRL register
v06: - add adc single-burst mode
-->
<peripherals>
<peripheral>
<name>I2C</name>
<description>I2C-bus controller</description>
<groupName>I2C</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C</name>
<value>15</value>
</interrupt>
<registers>
<register>
<name>CONSET</name>
<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>AA</name>
<description>Assert acknowledge flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SI</name>
<description>I2C interrupt flag.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>STO</name>
<description>STOP flag.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>STA</name>
<description>START flag.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2EN</name>
<description>I2C interface enable.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<resetValue>0xF8</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>These bits are unused and are always 0.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>Status</name>
<description>These bits give the actual status information about the I2C interface.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DAT</name>
<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Data</name>
<description>This register holds data values that have been received or are to be transmitted.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>ADR0</name>
<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call enable bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>Address</name>
<description>The I2C device address for slave mode.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCLH</name>
<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x04</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCLH</name>
<description>Count for SCL HIGH time period selection.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCLL</name>
<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x04</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCLL</name>
<description>Count for SCL low time period selection.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CONCLR</name>
<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>AAC</name>
<description>Assert acknowledge Clear bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SIC</name>
<description>I2C interrupt Clear bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>STAC</name>
<description>START flag Clear bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>I2ENC</name>
<description>I2C interface Disable bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MMCTRL</name>
<description>Monitor mode control register.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MM_ENA</name>
<description>Monitor mode enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MONITOR_MODE_DISABLE</name>
<description>Monitor mode disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_I2C_MODULE_WILL_</name>
<description>The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENA_SCL</name>
<description>SCL output enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>HIGH</name>
<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NORMAL</name>
<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATCH_ALL</name>
<description>Select interrupt register match.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MATCH</name>
<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ANYADDRESS</name>
<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from reserved bits is not defined.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>3</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1-3</dimIndex>
<name>ADR%s</name>
<description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call enable bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>Address</name>
<description>The I2C device address for slave mode.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DATA_BUFFER</name>
<description>Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>Data</name>
<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MASK%s</name>
<description>I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0x00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MASK</name>
<description>Mask bits.</description>
<bitRange>[7:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from reserved bits is undefined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDT</name>
<description>Windowed Watchdog Timer (WWDT)</description>
<groupName>WWDT</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDT</name>
<value>25</value>
</interrupt>
<registers>
<register>
<name>MOD</name>
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDEN</name>
<description>Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STOPPED</name>
<description>The watchdog timer is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUNNING</name>
<description>The watchdog timer is running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRESET</name>
<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INTERRUPT</name>
<description>A watchdog timeout will not cause a chip reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>A watchdog timeout will cause a chip reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOF</name>
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>WDINT</name>
<description>Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>WDPROTECT</name>
<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOT_LOCKED</name>
<description>The watchdog time-out value (TC) can be changed at any time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7).</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Watchdog time-out value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>FEED</name>
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>FEED</name>
<description>Feed value should be 0xAA followed by 0x55.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>TV</name>
<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter timer value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKSEL</name>
<description>Watchdog clock select register.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKSEL</name>
<description>Selects source of WDT clock</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC</name>
<description>IRC</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WATCHDOG_OSCILLATOR_</name>
<description>Watchdog oscillator (WDOSC)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[30:1]</bitRange>
</field>
<field>
<name>LOCK</name>
<description>If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>WARNINT</name>
<description>Watchdog Warning Interrupt compare value.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WARNINT</name>
<description>Watchdog warning interrupt compare value.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>WINDOW</name>
<description>Watchdog Window compare value.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WINDOW</name>
<description>Watchdog window value.</description>
<bitRange>[23:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART</name>
<description>USART</description>
<groupName>USART</groupName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>RBR</name>
<description>Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)</description>
<addressOffset>0x000</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RBR</name>
<description>The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>THR</name>
<description>Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)</description>
<alternateRegister>RBR</alternateRegister>
<addressOffset>0x000</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>THR</name>
<description>Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DLL</name>
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
<alternateRegister>RBR</alternateRegister>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x01</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLLSB</name>
<description>The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>DLM</name>
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLMSB</name>
<description>The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IER</name>
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)</description>
<alternateRegister>DLM</alternateRegister>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RBRINTEN</name>
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_RDA_INTE</name>
<description>Disable the RDA interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_RDA_INTER</name>
<description>Enable the RDA interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THREINTEN</name>
<description>THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_THRE_INT</name>
<description>Disable the THRE interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_THRE_INTE</name>
<description>Enable the THRE interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RLSINTEN</name>
<description>Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_RLS_INTE</name>
<description>Disable the RLS interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_RLS_INTER</name>
<description>Enable the RLS interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSINTEN</name>
<description>Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_THE_MS_INTER</name>
<description>Disable the MS interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_THE_MS_INTERR</name>
<description>Enable the MS interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>ABEOINTEN</name>
<description>Enables the end of auto-baud interrupt.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_END_OF_AUTO_</name>
<description>Disable end of auto-baud Interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_END_OF_AUTO_B</name>
<description>Enable end of auto-baud Interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABTOINTEN</name>
<description>Enables the auto-baud time-out interrupt.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_BAUD_TI</name>
<description>Disable auto-baud time-out Interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_BAUD_TIM</name>
<description>Enable auto-baud time-out Interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>IIR</name>
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
<addressOffset>0x008</addressOffset>
<access>read-only</access>
<resetValue>0x01</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTSTATUS</name>
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AT_LEAST_ONE_INTERRU</name>
<description>At least one interrupt is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_INTERRUPT_IS_PEND</name>
<description>No interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTID</name>
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.</description>
<bitRange>[3:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_RECEIVE_LINE_S</name>
<description>1 - Receive Line Status (RLS).</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>2A__RECEIVE_DATA_AV</name>
<description>2a - Receive Data Available (RDA).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>2B__CHARACTER_TIME_</name>
<description>2b - Character Time-out Indicator (CTI).</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>3_THRE_INTERRUPT</name>
<description>3 - THRE Interrupt.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_MODEM_STATUS</name>
<description>4 - Modem status</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>FIFOEN</name>
<description>These bits are equivalent to FCR[0].</description>
<bitRange>[7:6]</bitRange>
</field>
<field>
<name>ABEOINT</name>
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ABTOINT</name>
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<description>FIFO Control Register. Controls USART FIFO usage and modes.</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FIFOEN</name>
<description>FIFO enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>USART FIFOs are disabled. Must not be used in the application.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFIFORES</name>
<description>RX FIFO Reset</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>No impact on either of USART FIFOs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFORES</name>
<description>TX FIFO Reset</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>No impact on either of USART FIFOs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:4]</bitRange>
</field>
<field>
<name>RXTL</name>
<description>RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TRIGGER_LEVEL_0_1_C</name>
<description>Trigger level 0 (1 character or 0x01).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_1_4_C</name>
<description>Trigger level 1 (4 characters or 0x04).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_2_8_C</name>
<description>Trigger level 2 (8 characters or 0x08).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRIGGER_LEVEL_3_14_</name>
<description>Trigger level 3 (14 characters or 0x0E).</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>LCR</name>
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WLS</name>
<description>Word Length Select</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>5_BIT_CHARACTER_LENG</name>
<description>5-bit character length.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BIT_CHARACTER_LENG</name>
<description>6-bit character length.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BIT_CHARACTER_LENG</name>
<description>7-bit character length.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_CHARACTER_LENG</name>
<description>8-bit character length.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBS</name>
<description>Stop Bit Select</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_STOP_BIT_</name>
<description>1 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP_BITS_1_5_IF_</name>
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_PARITY_GENER</name>
<description>Disable parity generation and checking.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_PARITY_GENERA</name>
<description>Enable parity generation and checking.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PS</name>
<description>Parity Select</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ODD_PARITY_NUMBER_O</name>
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN_PARITY_NUMBER_</name>
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_1_STICK_PARIT</name>
<description>Forced 1 stick parity.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCED_0_STICK_PARIT</name>
<description>Forced 0 stick parity.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BC</name>
<description>Break Control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_BREAK_TRANSM</name>
<description>Disable break transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_BREAK_TRANSMI</name>
<description>Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLAB</name>
<description>Divisor Latch Access Bit</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_ACCESS_TO_DI</name>
<description>Disable access to Divisor Latches.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_ACCESS_TO_DIV</name>
<description>Enable access to Divisor Latches.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Modem Control Register.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRCTRL</name>
<description>Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTSCTRL</name>
<description>Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[3:2]</bitRange>
</field>
<field>
<name>LMS</name>
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_MODEM_LOOPBA</name>
<description>Disable modem loopback mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_MODEM_LOOPBAC</name>
<description>Enable modem loopback mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RTSEN</name>
<description>RTS enable</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_RTS_FLO</name>
<description>Disable auto-rts flow control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_RTS_FLOW</name>
<description>Enable auto-rts flow control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS enable</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_CTS_FLO</name>
<description>Disable auto-cts flow control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_CTS_FLOW</name>
<description>Enable auto-cts flow control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>LSR</name>
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
<addressOffset>0x014</addressOffset>
<access>read-only</access>
<resetValue>0x60</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDR</name>
<description>Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RBR_IS_EMPTY_</name>
<description>RBR is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RBR_CONTAINS_VALID_D</name>
<description>RBR contains valid data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OE</name>
<description>Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Overrun error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Overrun error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Parity error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Parity error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Framing error status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Framing error status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BI</name>
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE</name>
<description>Break interrupt status is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Break interrupt status is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>THRE</name>
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THR_CONTAINS_VALID_D</name>
<description>THR contains valid data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THR_IS_EMPTY_</name>
<description>THR is empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEMT</name>
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>VALID_D</name>
<description>THR and/or the TSR contains valid data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>THR and the TSR are empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_ERROR</name>
<description>RBR contains no USART RX errors or FCR[0]=0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ERRO</name>
<description>USART RBR contains at least one USART RX error.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXERR</name>
<description>Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>MSR</name>
<description>Modem Status Register.</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCTS</name>
<description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, CTS.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, CTS.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDSR</name>
<description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, DSR.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, DSR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TERI</name>
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, RI.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_TO_HIGH_TRANSITI</name>
<description>Low-to-high transition detected on RI.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDCD</name>
<description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE_DETECTED_O</name>
<description>No change detected on modem input, DCD.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STATE_CHANGE_DETECTE</name>
<description>State change detected on modem input, DCD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTS</name>
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DSR</name>
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RI</name>
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>DCD</name>
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, the value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>Scratch Pad Register. Eight-bit temporary storage for software.</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PAD</name>
<description>A readable, writable byte.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>ACR</name>
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>START</name>
<description>This bit is automatically cleared after auto-baud completion.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AUTO_BAUD_STOP_AUTO</name>
<description>Auto-baud stop (auto-baud is not running).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_BAUD_START_AUT</name>
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Auto-baud mode select bit.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MODE_0_</name>
<description>Mode 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE_1_</name>
<description>Mode 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTORESTART</name>
<description>Start mode</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_RESTART</name>
<description>No restart</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESTART_IN_CASE_OF_T</name>
<description>Restart in case of time-out (counter restarts at next USART Rx falling edge)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>ABEOINTCLR</name>
<description>End of auto-baud interrupt clear bit (write only accessible).</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>Writing a 0 has no impact.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABTOINTCLR</name>
<description>Auto-baud time-out interrupt clear bit (write only accessible).</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_IMPACT</name>
<description>Writing a 0 has no impact.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>IrDA Control Register. Enables and configures the IrDA (remote control) mode.</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRDAEN</name>
<description>IrDA mode enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRDA_MODE_IS_DISABLE</name>
<description>IrDA mode is disabled, USARTn acts as a standard USART.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IRDA_MODE_IS_ENABLED</name>
<description>IrDA mode is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRDAINV</name>
<description>Serial input inverter</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INVERTED</name>
<description>The serial input is not inverted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOT_INVERTED</name>
<description>The serial input is inverted. This has no effect on the serial output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIXPULSEEN</name>
<description>IrDA fixed pulse width mode.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>IrDA fixed pulse width mode disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>IrDA fixed pulse width mode enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PULSEDIV</name>
<description>Configures the pulse width when FixPulseEn = 1.</description>
<bitRange>[5:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>3_DIV_16_X_BAUD_RATE</name>
<description>3 / (16 x baud rate)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_X_TPCLK</name>
<description>2 x TPCLK</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_X_TPCLK</name>
<description>4 x TPCLK</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_X_TPCLK</name>
<description>8 x TPCLK</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>16_X_TPCLK</name>
<description>16 x TPCLK</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>32_X_TPCLK</name>
<description>32 x TPCLK</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>64_X_TPCLK</name>
<description>64 x TPCLK</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>128_X_TPCLK</name>
<description>128 x TPCLK</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>FDR</name>
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVADDVAL</name>
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate.</description>
<bitRange>[3:0]</bitRange>
</field>
<field>
<name>MULVAL</name>
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>OSR</name>
<description>Oversampling Register. Controls the degree of oversampling during each bit time.</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0xF0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>OSFRAC</name>
<description>Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)</description>
<bitRange>[3:1]</bitRange>
</field>
<field>
<name>OSINT</name>
<description>Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.</description>
<bitRange>[7:4]</bitRange>
</field>
<field>
<name>FDINT</name>
<description>In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.</description>
<bitRange>[14:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:15]</bitRange>
</field>
</fields>
</register>
<register>
<name>TER</name>
<description>Transmit Enable Register. Turns off USART transmitter for use with software flow control.</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[6:0]</bitRange>
</field>
<field>
<name>TXEN</name>
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>HDEN</name>
<description>Half duplex enable register.</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HDEN</name>
<description>Half-duplex mode enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_HALF_DUPLEX_</name>
<description>Disable half-duplex mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_HALF_DUPLEX_M</name>
<description>Enable half-duplex mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SCICTRL</name>
<description>Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.</description>
<addressOffset>0x048</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCIEN</name>
<description>Smart Card Interface Enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SMART_CARD_INTERFACE</name>
<description>Smart card interface disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ASYNCHRONOUS_HALF_DU</name>
<description>Asynchronous half duplex smart card interface is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NACKDIS</name>
<description>NACK response disable. Only applicable in T=0.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>A NACK response is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>A NACK response is inhibited.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PROTSEL</name>
<description>Protocol selection as defined in the ISO7816-3 standard.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>T_EQ_0</name>
<description>T = 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>T_EQ_1</name>
<description>T = 1</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[4:3]</bitRange>
</field>
<field>
<name>TXRETRY</name>
<description>When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared.</description>
<bitRange>[7:5]</bitRange>
</field>
<field>
<name>XTRAGUARD</name>
<description>When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485CTRL</name>
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
<addressOffset>0x04C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMMEN</name>
<description>NMM enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXDIS</name>
<description>Receiver enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_RECEIVER_IS_ENAB</name>
<description>The receiver is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_RECEIVER_IS_DISA</name>
<description>The receiver is disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AADEN</name>
<description>AAD enable.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AUTO_ADDRESS_DETECT_</name>
<description>Auto Address Detect (AAD) is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO_ADDRESS_DETECT_</name>
<description>Auto Address Detect (AAD) is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEL</name>
<description>Select direction control pin</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RTS</name>
<description>If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTR</name>
<description>If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCTRL</name>
<description>Auto direction control enable.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_AUTO_DIRECTI</name>
<description>Disable Auto Direction Control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_AUTO_DIRECTIO</name>
<description>Enable Auto Direction Control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OINV</name>
<description>Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485ADRMATCH</name>
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
<addressOffset>0x050</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADRMATCH</name>
<description>Contains the address match value.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RS485DLY</name>
<description>RS-485/EIA-485 direction control delay.</description>
<addressOffset>0x054</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYNCCTRL</name>
<description>Synchronous mode control register.</description>
<addressOffset>0x058</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYNC</name>
<description>Enables synchronous mode.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSRC</name>
<description>Clock source select.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYNCHRONOUS_SLAVE_MO</name>
<description>Synchronous slave mode (SCLK in)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCHRONOUS_MASTER_M</name>
<description>Synchronous master mode (SCLK out)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FES</name>
<description>Falling edge sampling.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RISING</name>
<description>RxD is sampled on the rising edge of SCLK </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>RxD is sampled on the falling edge of SCLK</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSBYPASS</name>
<description>Transmit synchronization bypass in synchronous slave mode.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SYNC</name>
<description>The input clock is synchronized prior to being used in clock edge detection logic</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NOSYNC</name>
<description>The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSCEN</name>
<description>Continuous master clock enable (used only when CSRC is 1)</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SCLK_CYCLES_ONLY_WHE</name>
<description>SCLK cycles only when characters are being sent on TxD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCLK_RUNS_CONTINUOUS</name>
<description>SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSDIS</name>
<description>Start/stop bits</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SEND</name>
<description>Send start and stop bits as in other modes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DO_NOT_SEND</name>
<description>Do not send start/stop bits.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCCLR</name>
<description>Continuous clock clear</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CSCEN_IS_UNDER_SOFTW</name>
<description>CSCEN is under software control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HARDWARE_CLEARS_CSCE</name>
<description>Hardware clears CSCEN after each character is received.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. The value read from a reserved bit is not defined.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CT16B0</name>
<description>16-bit counter/timers CT16B0/1</description>
<groupName>CT16B0</groupName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT16B0</name>
<value>16</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CR3INT</name>
<description>Interrupt flag for capture channel 3 event.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_COUNTERS_ARE_DIS</name>
<description>The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_TIMER_COUNTER_AN</name>
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_TIMER_COUNTER_AN</name>
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TC</name>
<description>Timer counter value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescale value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PC</name>
<description>Prescale counter value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MR%s</name>
<description>Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0FE</name>
<description>Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0I</name>
<description>Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CR%s</name>
<description>Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and the external match pins </description>
<addressOffset>0x03C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of External Match 0. Table 238 shows the encoding of these bits.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT0 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT16Bi_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT1 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT16Bi_MAT1 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT2 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT16Bi_MAT2 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of External Match 3. Table 238 shows the encoding of these bits.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT3 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT16Bi_MAT3 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTM</name>
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_MODE_EVERY_RI</name>
<description>Timer Mode: every rising PCLK edge</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIS</name>
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 to 0x3 are reserved.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CT16BN_CAP0</name>
<description>CT16Bn_CAP0</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SELCC</name>
<description>When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x7 are reserved.</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RISING_EDGE_OF_CAP0_</name>
<description>Rising Edge of CAP0 clears the timer (if bit 4 is set)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE_OF_CAP0</name>
<description>Falling Edge of CAP0 clears the timer (if bit 4 is set)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM0</name>
<description>CT16Bi_MAT0 is controlled by EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT16Bi_MAT0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM1</name>
<description>CT16Bi_MAT01 is controlled by EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT16Bi_MAT1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM2</name>
<description>CT16Bi_MAT2 is controlled by EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT16Bi_MAT2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM3</name>
<description>CT16Bi_MAT3 is controlled by EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT16Bi_MAT3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CT16B0">
<name>CT16B1</name>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT16B1</name>
<value>17</value>
</interrupt>
</peripheral>
<peripheral>
<name>CT32B0</name>
<description>32-bit counter/timers CT32B0/1</description>
<groupName>CT32B0</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B0</name>
<value>18</value>
</interrupt>
<registers>
<register>
<name>IR</name>
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0INT</name>
<description>Interrupt flag for match channel 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MR1INT</name>
<description>Interrupt flag for match channel 1.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MR2INT</name>
<description>Interrupt flag for match channel 2.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MR3INT</name>
<description>Interrupt flag for match channel 3.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CR0INT</name>
<description>Interrupt flag for capture channel 0 event.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CR1INT</name>
<description>Interrupt flag for capture channel 1 event.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CR2INT</name>
<description>Interrupt flag for capture channel 2 event.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CR3INT</name>
<description>Interrupt flag for capture channel 3 event.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CEN</name>
<description>Counter enable.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>THE_COUNTERS_ARE_DIS</name>
<description>The counters are disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_TIMER_COUNTER_AN</name>
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRST</name>
<description>Counter reset.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do nothing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THE_TIMER_COUNTER_AN</name>
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TC</name>
<description>Timer counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PR</name>
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCVAL</name>
<description>Prescaler value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PC</name>
<description>Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PC</name>
<description>Prescale counter value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MR0I</name>
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0R</name>
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR0S</name>
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1I</name>
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1R</name>
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR1S</name>
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2I</name>
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2R</name>
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR2S</name>
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3I</name>
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3R</name>
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MR3S</name>
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>MR%s</name>
<description>Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Timer counter match value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RE</name>
<description>Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0FE</name>
<description>Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP0I</name>
<description>Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1RE</name>
<description>Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1FE</name>
<description>Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAP1I</name>
<description>Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED_</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED_</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>CR%s</name>
<description>Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input.</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP</name>
<description>Timer counter capture value.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<description>External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0].</description>
<addressOffset>0x03C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EM0</name>
<description>External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>EM1</name>
<description>External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>EM2</name>
<description>External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>EM3</name>
<description>External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>EMC0</name>
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC1</name>
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
<bitRange>[7:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC2</name>
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMC3</name>
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DO_NOTHING_</name>
<description>Do Nothing.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_CORRESPOND</name>
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_THE_CORRESPONDIN</name>
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out).</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE_THE_CORRESPON</name>
<description>Toggle the corresponding External Match bit/output.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>CTCR</name>
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CTM</name>
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TIMER_MODE_EVERY_RI</name>
<description>Timer Mode: every rising PCLK edge</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTHEDGES</name>
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIS</name>
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved.</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CT32BN_CAP0</name>
<description>CT32Bn_CAP0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32BN_CAP1</name>
<description>CT32Bn_CAP1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCC</name>
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SElCC</name>
<description>When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved.</description>
<bitRange>[7:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RISING_EDGE_OF_CAP0_</name>
<description>Rising Edge of CAP0 clears the timer (if bit 4 is set)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE_OF_CAP0</name>
<description>Falling Edge of CAP0 clears the timer (if bit 4 is set)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE_OF_CAP1_</name>
<description>Rising Edge of CAP1 clears the timer (if bit 4 is set)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE_OF_CAP1</name>
<description>Falling Edge of CAP1 clears the timer (if bit 4 is set)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PWMC</name>
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMEN0</name>
<description>PWM mode enable for channel0.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM0</name>
<description>CT32Bi_MAT0 is controlled by EM0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT32Bi_MAT0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN1</name>
<description>PWM mode enable for channel1.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM1</name>
<description>CT32Bi_MAT01 is controlled by EM1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT32Bi_MAT1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN2</name>
<description>PWM mode enable for channel2.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM2</name>
<description>CT32Bi_MAT2 is controlled by EM2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT32Bi_MAT2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMEN3</name>
<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EM3</name>
<description>CT32Bi_MAT3 is controlled by EM3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_MODE_IS_ENABLED_</name>
<description>PWM mode is enabled for CT132Bi_MAT3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CT32B0">
<name>CT32B1</name>
<baseAddress>0x40018000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CT32B1</name>
<value>19</value>
</interrupt>
</peripheral>
<peripheral>
<name>ADC</name>
<description>ADC </description>
<groupName>ADC</groupName>
<baseAddress>0x4001C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are 0 (as after Reset) channel 0 is selected automatically.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>CLKDIV</name>
<description>The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>BURST</name>
<description>Burst mode</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SOFTWARE_CONTROLLED_</name>
<description>Software-controlled mode: Conversions are software-controlled and require 11 clocks.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HARDWARE_SCAN_MODE_</name>
<description>Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. If bit 20 in this register is set (single-burst mode), hardware clears this bit automatically after one set of conversions on all of the selected channels.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>11_CLOCKS</name>
<description>11 clocks / 10 bits</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>10_CLOCKS</name>
<description>10 clocks / 9 bits</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>9_CLOCKS</name>
<description>9 clocks / 8 bits</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_CLOCKS</name>
<description>8 clocks / 7 bits</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>7_CLOCKS</name>
<description>7 clocks / 6 bits</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>6_CLOCK</name>
<description>6 clocks / 5 bits</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>5_CLOCKS</name>
<description>5 clocks / 4 bits</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>4_CLOCKS</name>
<description>4 clocks / 3 bits</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SINGLEBURST</name>
<description>Single-burst mode</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>CONTINUOUS_BURST</name>
<description>Continuous. Burst mode can only be terminated via a software write to clear bit 16 in this register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SINGLE_BURST</name>
<description>Single-burst. When the burst mode is selected by writing a 1 to bit 16 in this register, the ADC cycles through a single set of conversions on the selection of channels specified in the SEL field. Once the conversion has been completed on each selected channel, bit 16 is automatically cleared and the conversions stop until a new trigger event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[22:21]</bitRange>
</field>
<field>
<name>START</name>
<description>When the BURST bit is 0, these bits control whether/when an A/D conversion is started. All other values are reserved.</description>
<bitRange>[26:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_START_THIS_VALUE</name>
<description>No start (this value should be used when clearing PDN to 0).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_NOW</name>
<description>Start conversion now.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on ATRG0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on the analog comparator output.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on ATRG1.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_WHE</name>
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].</description>
<value>0xE</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGE</name>
<description>This bit is significant only when the START field contains 0100-1110. In these cases:</description>
<bitRange>[27:27]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>START_CONVERSION_ON_</name>
<description>Start conversion on a rising edge on the selected signal.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START_CONVERSION_ON_</name>
<description>Start conversion on a falling edge on the selected signal.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>GDR</name>
<description>A/D Global Data Register. Contains the result of the most recent A/D conversion.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. These bits always read as zeroes.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>V_VREF</name>
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking, for at least 256 values without overflow into the CHN field.</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>CHN</name>
<description>These bits contain the channel from which the LS bits were converted.</description>
<bitRange>[26:24]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. These bits always read as zeroes.</description>
<bitRange>[29:27]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits. In non-FIFO operation, this bit is cleared by reading this register.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DONE</name>
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>SEL</name>
<description>A/D Select Register. Selects between external pins and internal sources.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Always write zeroes to these bits.</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>AD5SEL</name>
<description>This field selects the source signal for channel 5.</description>
<bitRange>[11:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AD5_PIN</name>
<description>AD5 pin</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CONNECTION_OR_LOA</name>
<description>No connection or load</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CORE_VOLTAGE_REGULAT</name>
<description>Core voltage regulator output (1.2 to 1.8V)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED_DO_NOT_PRO</name>
<description>Reserved. Do not program this value.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AD6SEL</name>
<description>This field selects the source signal for channel 6.</description>
<bitRange>[13:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AD6_PIN</name>
<description>AD6 pin</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CONNECTION_OR_LOA</name>
<description>No connection or load</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERNAL_VOLTAGE_REF</name>
<description>Internal voltage reference</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED_DO_NOT_PRO</name>
<description>Reserved. Do not program this value.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AD7SEL</name>
<description>This field selects the source signal for channel 7.</description>
<bitRange>[15:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>AD7_PIN</name>
<description>AD7 pin</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CONNECTION_OR_LOA</name>
<description>No connection or load</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>TEMPERATURE_SENSOR</name>
<description>Temperature sensor</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED_DO_NOT_PRO</name>
<description>Reserved. Do not program this value.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always write zeroes to these bits.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.</description>
<addressOffset>0x030</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DONE</name>
<description>These bits mirror the DONE status flags that appear in the result register for each A/D channel.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>These bits mirror the OVERRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>ADINT</name>
<description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always 0.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>INTEN</name>
<description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
<addressOffset>0x00C</addressOffset>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADINTEN</name>
<description>These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>ADGINTEN</name>
<description>When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Always 0.</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>DR%s</name>
<description>A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0</description>
<addressOffset>0x010</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. These bits always read as zeroes.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>V_VREF</name>
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field.</description>
<bitRange>[29:16]</bitRange>
</field>
<field>
<name>OVERRUN</name>
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DONE</name>
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC</name>
<description>DAC</description>
<groupName>DAC</groupName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DAC</name>
<value>11</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>D/A control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[5:0]</bitRange>
</field>
<field>
<name>VALUE</name>
<description>After the selected settling time after a conversion begins, the voltage on the AOUT pin (with respect to VSS) is VALUE x (V DD/1024).</description>
<bitRange>[15:6]</bitRange>
</field>
<field>
<name>BIAS</name>
<description>Settling time</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FAST</name>
<description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLOW</name>
<description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG</name>
<description>The value written to this field determines whether conversion begins immediately after this register is written, or whether conversion is delayed until a selected event occurs.</description>
<bitRange>[19:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IMMEDIATE</name>
<description>Conversion begins when this register is written, and AOUT begins to change to the new voltage immediately. For all other values in this field, AOUT remains at its previous voltage until the selected event has occurred.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>COMPLEVELOUT</name>
<description>Conversion is triggered by the selected edge(s) on the analog comparator (level) output</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ATRG0EDGE</name>
<description>Conversion is triggered by the selected edge(s) on ATRG0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ATRG1EDGE</name>
<description>Conversion is triggered by the selected edge(s) on ATRG1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT0EDGE</name>
<description>Conversion is triggered by the selected edge(s) on CT32B1_MAT0 [2].</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT1EDGE</name>
<description>Conversion is triggered by the selected edge(s) on CT32B1_MAT1[2].</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT0EDGE</name>
<description>Conversion is triggered by the selected edge(s) on CT16B1_MAT0[2].</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT1EDGE</name>
<description>Conversion is triggered by the selected edge(s) on CT16B1_MAT1[2].</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>EDGESEL</name>
<description>For non-zero values of TRIG, this field selects when the conversion is triggered:</description>
<bitRange>[22:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edges</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISINGs</name>
<description>Rising edges</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUALEDGE</name>
<description>Both edges</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DUALEDGE</name>
<description>Both edges</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGERD</name>
<description>If the TRIG field (above) is non-zero, this bit is set when a conversion is triggered, and is cleared by any write to this register.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:24]</bitRange>
</field>
</fields>
</register>
<register>
<name>RESERVED</name>
<description>Reserved</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP</name>
<description>Comparator</description>
<groupName>Comparator</groupName>
<baseAddress>0x40028000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP</name>
<value>10</value>
</interrupt>
<registers>
<register>
<name>CTL</name>
<description>Comparator control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>EDGESEL</name>
<description>This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edges</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edges</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUALEDGE</name>
<description>Both edges</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>DUALEDGE</name>
<description>Both edges</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>COMPSA</name>
<description>Comarator output control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DIRECT</name>
<description>Uses the comparator output directly.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYNCH</name>
<description>Synchronizes the comparator output to the bus clock for output to other modules.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>COMP_VP_SEL</name>
<description>Selects positive voltage input</description>
<bitRange>[10:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>VLADOUT</name>
<description>voltage ladder output</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI1</name>
<description>ACMPI1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI2</name>
<description>ACMPI2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI3</name>
<description>ACMPI3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI4</name>
<description>ACMPI4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI5</name>
<description>ACMPI5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INTVOLTAGEREF</name>
<description>internal reference voltage</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>TEMPSENSOR</name>
<description>temperature sensor</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP_VM_SEL</name>
<description>Selects negative voltage input</description>
<bitRange>[13:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>VLADDOUT</name>
<description>voltage ladder output</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI1</name>
<description>ACMPI1</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI2</name>
<description>ACMPI2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI3</name>
<description>ACMPI3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI4</name>
<description>ACMPI4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMPI5</name>
<description>ACMPI5</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>INTVOLTAGEREF</name>
<description>internal reference voltage</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[19:14]</bitRange>
</field>
<field>
<name>EDGECLR</name>
<description>Interrupt clear bit. Writing a 1 to this bit clears the COMPEDGE bit (bit 23 below) and thus negates the interrupt request.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>COMPSTAT</name>
<description>Comparator status. This bit reflects the state of the comparator output.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>COMPEDGE</name>
<description>Comparator edge-detect status.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Write as 0.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>HYS</name>
<description>Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.</description>
<bitRange>[26:25]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NOHYSTERESIS</name>
<description>None (the output will switch as the voltages cross)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HYS5MV</name>
<description>5 mV</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>HSY10MV</name>
<description>10 mV</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>HSY20MV</name>
<description>20 mV</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:27]</bitRange>
</field>
</fields>
</register>
<register>
<name>LAD</name>
<description>Voltage ladder register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LADEN</name>
<description>Voltage ladder enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>LADSEL</name>
<description>Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 Vref/31 00010 = 2 Vref/31 ... 11111 = Vref</description>
<bitRange>[5:1]</bitRange>
</field>
<field>
<name>LADREF</name>
<description>Selects the reference voltage for the voltage ladder</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>VDDPIN</name>
<description>VDD pin</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDCMPPIN</name>
<description>VDDCMP pin</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Unused</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FMC</name>
<description>Flash controller</description>
<groupName>FLASHCTRL</groupName>
<baseAddress>0x4003C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FMC</name>
<value>27</value>
</interrupt>
<registers>
<register>
<name>EEMSSTART</name>
<description>EEPROM BIST start address register</description>
<addressOffset>0x09C</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STARTA</name>
<description>BIST start address: Bit 0 is fixed zero since only even addresses are allowed.</description>
<bitRange>[13:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:14]</bitRange>
</field>
</fields>
</register>
<register>
<name>EEMSSTOP</name>
<description>EEPROM BIST stop address register</description>
<addressOffset>0x0A0</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STOPA</name>
<description>BIST stop address: Bit 0 is fixed zero since only even addresses are allowed.</description>
<bitRange>[13:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[29:14]</bitRange>
</field>
<field>
<name>DEVSEL</name>
<description>BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>STRTBIST</name>
<description>BIST start bit Setting this bit will start the BIST. This bit is self-clearing.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<name>EEMSSIG</name>
<description>EEPROM 24-bit BIST signature register</description>
<addressOffset>0x0A4</addressOffset>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA_SIG</name>
<description>BIST 16-bit signature calculated from only the data bytes</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>PARITY_SIG</name>
<description>BIST 16-bit signature calculated from only the parity bits of the data bytes</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>FLASHCFG</name>
<description>Flash memory access time configuration register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>FLASHTIM</name>
<description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1_SYSTEM_CLOCK_FLASH</name>
<description>1 system clock flash access time (for system clock frequencies of up to 20 MHz).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_SYSTEM_CLOCKS_FLAS</name>
<description>2 system clocks flash access time (for system clock frequencies of up to 40 MHz).</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>3_SYSTEM_CLOCKS_FLAS</name>
<description>3 system clocks flash access time (for system clock frequencies of up to 50 MHz).</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSSTART</name>
<description>Signature start address register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>START</name>
<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
<bitRange>[16:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSSTOP</name>
<description>Signature stop-address register</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STOP</name>
<description>BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).</description>
<bitRange>[16:0]</bitRange>
</field>
<field>
<name>SIG_START</name>
<description>Start control bit for signature generation.</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SIGNATURE_GENERATION</name>
<description>Signature generation is stopped</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INITIATE_SIGNATURE_G</name>
<description>Initiate signature generation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:18]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSW0</name>
<description>Word 0 [31:0]</description>
<addressOffset>0x02C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SW0_31_0</name>
<description>Word 0 of 128-bit signature (bits 31 to 0).</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSW1</name>
<description>Word 1 [63:32]</description>
<addressOffset>0x030</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SW1_63_32</name>
<description>Word 1 of 128-bit signature (bits 63 to 32).</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSW2</name>
<description>Word 2 [95:64]</description>
<addressOffset>0x034</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SW2_95_64</name>
<description>Word 2 of 128-bit signature (bits 95 to 64).</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSW3</name>
<description>Word 3 [127:96]</description>
<addressOffset>0x038</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SW3_127_96</name>
<description>Word 3 of 128-bit signature (bits 127 to 96).</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSTAT</name>
<description>Signature generation status register</description>
<addressOffset>0xFE0</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>SIG_DONE</name>
<description>When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<name>FMSTATCLR</name>
<description>Signature generation status clear register</description>
<addressOffset>0xFE8</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>SIG_DONE_CLR</name>
<description>Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SSP0</name>
<description> SSP/SPI </description>
<groupName>SSP0</groupName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SSP0</name>
<value>20</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DSS</name>
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
<bitRange>[3:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>4_BIT_TRANSFER</name>
<description>4-bit transfer</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>5_BIT_TRANSFER</name>
<description>5-bit transfer</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BIT_TRANSFER</name>
<description>6-bit transfer</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BIT_TRANSFER</name>
<description>7-bit transfer</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BIT_TRANSFER</name>
<description>8-bit transfer</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BIT_TRANSFER</name>
<description>9-bit transfer</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>10_BIT_TRANSFER</name>
<description>10-bit transfer</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>11_BIT_TRANSFER</name>
<description>11-bit transfer</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>12_BIT_TRANSFER</name>
<description>12-bit transfer</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>13_BIT_TRANSFER</name>
<description>13-bit transfer</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>14_BIT_TRANSFER</name>
<description>14-bit transfer</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>15_BIT_TRANSFER</name>
<description>15-bit transfer</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>16_BIT_TRANSFER</name>
<description>16-bit transfer</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRF</name>
<description>Frame Format.</description>
<bitRange>[5:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SPI</name>
<description>SPI</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TI</name>
<description>TI</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MICROWIRE</name>
<description>Microwire</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>This combination is not supported and should not be used.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LOW</name>
<description>SPI controller maintains the bus clock low between frames.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>SPI controller maintains the bus clock high between frames.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FIRSTCLOCK</name>
<description>SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SECONDCLOCK</name>
<description>SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCR</name>
<description>Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>Control Register 1. Selects master/slave and other modes.</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LBM</name>
<description>Loop Back Mode.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DURING_NORMAL_OPERAT</name>
<description>During normal operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SERIAL_INPUT_IS_TAKE</name>
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSE</name>
<description>SPI Enable.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>The SPI controller is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MS</name>
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>MASTER</name>
<description>The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLAVE</name>
<description>The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOD</name>
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>DR</name>
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.</description>
<bitRange>[15:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0x00000003</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TFE</name>
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>TNF</name>
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RNE</name>
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RFF</name>
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>BSY</name>
<description>Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>CPSR</name>
<description>Clock Prescale Register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPSDVSR</name>
<description>This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IMSC</name>
<description>Interrupt Mask Set and Clear Register</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORIM</name>
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTIM</name>
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXIM</name>
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXIM</name>
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>RIS</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORRIS</name>
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTRIS</name>
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXRIS</name>
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXRIS</name>
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>MIS</name>
<description>Masked Interrupt Status Register</description>
<addressOffset>0x01C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RORMIS</name>
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTMIS</name>
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RXMIS</name>
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>TXMIS</name>
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:4]</bitRange>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>SSPICR Interrupt Clear Register</description>
<addressOffset>0x020</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RORIC</name>
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RTIC</name>
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IOCON</name>
<description>IOCON block</description>
<groupName>IOCON</groupName>
<baseAddress>0x40044000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>RESET_PIO0_0</name>
<description>I/O configuration register for pin RESET/PIO0_0</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin RESET/PIO0_0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESET</name>
<description>External reset input with fixed 20 ns glitch filter: A
LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states and processor
execution to begin at address 0. </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_0</name>
<description>General purpose digital input/output pin.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_1</name>
<description>I/O configuration register for pin PIO0_1/RXD/CLKOUT/ CT32B0_MAT2/SSEL0/ CLKIN</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_1/RXD/CLKOUT/ CT32B0_MAT2/SSEL0/ CLKIN</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_1</name>
<description>General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command
handler.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXD</name>
<description>Receiver data input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKOUT</name>
<description>Clock output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT2</name>
<description>Match output 2 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL0</name>
<description>Slave Select for SSP0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>External clock input.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_2</name>
<description>I/O configuration register for pin PIO0_2/SCL/ACMP_O/ TCK/SWCLK/ CT16B0_CAP0</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_2/SCL/ACMP_O/ TCK/SWCLK/ CT16B0_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_2</name>
<description>General purpose digital input/output pin. High-current
sink (20 mA) or standard-current sink (4 mA) programmable; true
open-drain for all pin functions. Input glitch filter (50 ns)
capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCL</name>
<description>I2C-bus clock (true open-drain) input/output. Input glitch filter (50 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_O</name>
<description>Analog comparator output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>TCK_SWCLK</name>
<description>Serial Wire Debug Clock (secondary for LQFP and HVQFN packages). Input glitch filter (50 ns) capable. For the WLCSP20 package only, this pin is configured to the SWCLK function by the boot loader after reset.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP0</name>
<description>Capture input 0 for 16-bit timer 0.Input glitch filter (50 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>HS</name>
<description>Controls glitch filter and slew rate.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HIDRIVE</name>
<description>Controls sink current.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard; 4 mA sink current.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High; 20 mA sink current.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_3</name>
<description>I/O configuration register for pin PIO0_3/SDA/ACMP_O/ SWDIO/CT16B1_CAP0</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_3/SDA/ACMP_O/ SWDIO/CT16B1_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_3</name>
<description>General purpose digital input/output pin. High-current
sink (20 mA) or standard-current sink (4 mA) programmable; true
open-drain for all pin functions. Input glitch filter (50 ns)
capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SDA</name>
<description>I2C-bus data (true open-drain) input/output. Input glitch filter (50 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_O</name>
<description>Analog comparator output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>SWDIO</name>
<description>Serial Wire Debug I/O (secondary for LQFP and HVQFN packages). Input glitch filter (50 ns) capable. For the WLCSP20 package only, this pin is configured to the SWDIO function by the boot loader after reset.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP0</name>
<description>Capture input 0 for 16-bit timer 1. Input glitch filter (50 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>HS</name>
<description>Controls glitch filter and slew rate.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HIDRIVE</name>
<description>Controls sink current.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD</name>
<description>Standard; 4 mA sink current.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High; 20 mA sink current.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_4</name>
<description>I/O configuration register for pin PIO0_4/R/AOUT/ CT16B0_MAT1/MOSI0</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_4/R/AOUT/ CT16B0_MAT1/MOSI0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_4</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>R</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AOUT</name>
<description>D/A converter output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT1</name>
<description>Match output 1 for 16-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI0</name>
<description>Master Out Slave In for SSP0. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>TCK_SWCLK_PIO0_5</name>
<description>I/O configuration register for pin TCK/SWCLK/PIO0_5/ R/CT16B0_MAT2/ SCK0 </description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin TCK/SWCLK/PIO0_5/ R/CT16B0_MAT2/ SCK0 </description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TCK_SWCLK</name>
<description>Test clock TCK for JTAG interface and primary (default)
Serial Wire Debug Clock. Input glitch filter (10 ns)
capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_5</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>R</name>
<description>Reserved.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT2</name>
<description>Match output 2 for 16-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK0</name>
<description>Serial clock for SSP0. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>TDI_PIO0_6</name>
<description>I/O configuration register for pin TDI/PIO0_6/AD0/ CT32B0_MAT3/MISO0</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin TDI/PIO0_6/AD0/ CT32B0_MAT3/MISO0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TDI</name>
<description>Test Data In for JTAG interface. Input glitch filter (10
ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_6</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD0</name>
<description>A/D converter input 0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT3</name>
<description>Match output 3 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO0</name>
<description>Master In Slave Out for SSP0. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>TMS_PIO0_7</name>
<description>I/O configuration register for pin TMS/PIO0_7/AD1/ CT32B1_CAP0/ CT16B0_MAT0</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin TMS/PIO0_7/AD1/ CT32B1_CAP0/ CT16B0_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TMS</name>
<description>Test Mode Select for JTAG interface. Input glitch filter
(10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_7</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD1</name>
<description>A/D converter input 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP0</name>
<description>Capture input 0 for 32-bit timer 1. Input glitch filter (10 ns) capable.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT0</name>
<description>Match output 2 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>TDO_PIO0_8</name>
<description>I/O configuration register for pin TDO/PIO0_8/AD2/ CT32B1_MAT0/SCK1</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin TDO/PIO0_8/AD2/ CT32B1_MAT0/SCK1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TDO</name>
<description>Test Data Out for JTAG interface.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_8</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD2</name>
<description>A/D converter input 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT0</name>
<description>Match output 0 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK1</name>
<description>Serial clock for SSP1. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>TRST_PIO0_9</name>
<description>I/O configuration register for pin TRST/PIO0_9/AD3/CT32B1_MAT1/CT16B0_MAT1/CTS</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin TRST/PIO0_9/AD3/CT32B1_MAT1/CT16B0_MAT1/CTS</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>TRST</name>
<description>Test Reset for JTAG interface. Input glitch filter (10
ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_9</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD3</name>
<description>A/D converter, input 3.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT1</name>
<description>Match output 1 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT1</name>
<description>Match output 1 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CTS</name>
<description>Clear To Send input for USART. Input glitch filter (10 ns) capable.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>SWDIO_PIO0_10</name>
<description>I/O configuration register for pin SWDIO/PIO0_10/AD4/ CT32B1_MAT2/ CT16B0_MAT2/RTS</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin SWDIO/PIO0_10/AD4/ CT32B1_MAT2/ CT16B0_MAT2/RTS</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SWDIO</name>
<description>Primary (default) Serial Wire Debug I/O for the LQFP48
and HVQFN33 packages. For the WLCSP20 package, use PIO0_3. Input
glitch filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PIO0_10</name>
<description>General purpose digital input/output pin. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD4</name>
<description>A/D converter, input 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT2</name>
<description>Match output 2 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT2</name>
<description>Match output 2 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>RTS</name>
<description>Request To Send output for USART.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_11</name>
<description>I/O configuration register for pin PIO0_11/SCLK/ AD5/CT32B1_MAT3/ CT32B0_CAP0</description>
<addressOffset>0x2C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_11/SCLK/ AD5/CT32B1_MAT3/ CT32B0_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_11</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCLK</name>
<description>Serial clock for USART. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD5</name>
<description>A/D converter, input 5.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT3</name>
<description>Match output 3 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP0</name>
<description>Capture input 0 for 32-bit timer 0. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_12</name>
<description>I/O configuration register for pin PIO0_12/RXD/ ACMP_O/ CT32B0_MAT0/SCL/ CLKIN</description>
<addressOffset>0x30</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_12/RXD/ ACMP_O/ CT32B0_MAT0/SCL/ CLKIN</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_12</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXD</name>
<description>Receiver data input for USART. This pin is used for ISP communication.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_O</name>
<description>Analog comparator output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT0</name>
<description>Match output 0 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCL</name>
<description>I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. </description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>External clock input.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_13</name>
<description>I/O configuration register for pin PIO0_13/TXD/ ACMP_I2/ CT32B0_MAT1/SDA</description>
<addressOffset>0x34</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_13/TXD/ ACMP_I2/ CT32B0_MAT1/SDA</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_13</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXD</name>
<description>Transmitter data output for USART. This pin is used for ISP communication.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I2</name>
<description>Analog comparator input 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT1</name>
<description>Match output 1 for 32-bit timer 0. </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SDA</name>
<description>I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_14</name>
<description>I/O configuration register for pin PIO0_14/MISO1/AD6/CT32B0_CAP1/CT16B1_MAT1/VDDCMP</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_14/MISO1/AD6/CT32B0_CAP1/CT16B1_MAT1/xxxCMP</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_14</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO1</name>
<description>Master In Slave Out for SSP1. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD6</name>
<description>A/D converter, input 6.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP1</name>
<description>Capture input 1 for 32-bit timer 0. Input glitch filter (10 ns) capable.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT1</name>
<description>Match output 1 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDCMP</name>
<description>Analog comparator alternate reference voltage. </description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_15</name>
<description>I/O configuration register for pin PIO0_15/TXD/AD7/ CT32B0_CAP2/SDA</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_15/TXD/AD7/ CT32B0_CAP2/SDA</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_15</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXD</name>
<description>Transmitter data output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>AD7</name>
<description>A/D converter, input 7.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP2</name>
<description>Capture input 2 for 32-bit timer 0. Input glitch filter (10 ns) capable.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SDA</name>
<description>I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_16</name>
<description>I/O configuration register for pin PIO0_16/ ATRG0/ACMP_I3/ CT16B0_CAP1/SCL</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_16/ ATRG0/ACMP_I3/ CT16B0_CAP1/SCL</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_16</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ATRG0</name>
<description>Conversion trigger 0 for ADC or DAC. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I3</name>
<description>Analog comparator input 3.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP1</name>
<description>Capture input 1 for 16-bit timer 0. Input glitch filter (10 ns) capable.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCL</name>
<description>I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_17</name>
<description>I/O configuration register for pin PIO0_17/ ATRG1/ACMP_I4/ CT16B0_CAP2/ CT16B0_MAT0</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_17/ ATRG1/ACMP_I4/ CT16B0_CAP2/ CT16B0_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_17</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>ATRG1</name>
<description>Conversion trigger 1 for ADC or DAC. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I4</name>
<description>Analog comparator input 4.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP2</name>
<description>Capture input 2 for 16-bit timer 0. Input glitch filter (10 ns) capable.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT0</name>
<description>Match output 0 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_18</name>
<description>I/O configuration register for pin PIO0_18/R/SSEL0/ CT16B0_CAP0/ CT16B1_CAP1</description>
<addressOffset>0x48</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_18/R/SSEL0/ CT16B0_CAP0/ CT16B1_CAP1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_18</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>R</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL0</name>
<description>Slave Select for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP0</name>
<description>Capture input 0 for 16-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP1</name>
<description>Capture input 1 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_19</name>
<description>I/O configuration register for pin PIO0_19/CLKIN/ CLKOUT/ MOSI0/CT16B1_MAT0</description>
<addressOffset>0x4C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_19/CLKIN/ CLKOUT/ MOSI0/CT16B1_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_19</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>External clock input.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKOUT</name>
<description>Clock output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI0</name>
<description>Master Out Slave In for SSP0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT0</name>
<description>Match output 0 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_20</name>
<description>I/O configuration register for pin PIO0_20/R/SCK0/ CT32B1_CAP0/ CT16B1_MAT2</description>
<addressOffset>0x50</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_20/R/SCK0/ CT32B1_CAP0/ CT16B1_MAT2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_20</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>R</name>
<description>Reserved.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK0</name>
<description>Serial clock for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP0</name>
<description>Capture input 0 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT2</name>
<description>Match output 2 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_21</name>
<description>I/O configuration register for pin PIO0_21/CTS/ ACMP_O/ CT32B1_CAP1/SCLK</description>
<addressOffset>0x54</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_21/CTS/ ACMP_O/ CT32B1_CAP1/SCLK</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_21</name>
<description>General purpose digital input/output pin. If configured
as output, this pin is a high-current source output driver (20
mA).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CTS</name>
<description>Clear To Send input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_O</name>
<description>Analog comparator output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP1</name>
<description>Capture input 1 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCLK</name>
<description>Serial clock for USART.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_22</name>
<description>I/O configuration register for pin PIO0_22/MISO0/ ACMP_I5/ CT32B1_MAT2/ CT32B1_CAP2</description>
<addressOffset>0x58</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_22/MISO0/ ACMP_I5/ CT32B1_MAT2/ CT32B1_CAP2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_22</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO0</name>
<description>Master In Slave Out for SSP0. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I5</name>
<description>Analog comparator input 5.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT2</name>
<description>Match output 2 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP2</name>
<description>Capture input 2 for 32-bit timer 1. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_23</name>
<description>I/O configuration register for pin PIO0_23/RTS/ ACMP_O/ CT32B0_CAP0/SCLK</description>
<addressOffset>0x5C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_23/RTS/ ACMP_O/ CT32B0_CAP0/SCLK</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_23</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RTS</name>
<description>Request To Send output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_O</name>
<description>Analog comparator output.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP0</name>
<description>Capture input 0 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>SCLK</name>
<description>Serial clock for USART.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_24</name>
<description>I/O configuration register for pin PIO0_24/SCL/CLKIN/ CT16B1_CAP0</description>
<addressOffset>0x60</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_24/SCL/CLKIN/ CT16B1_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_24</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCL</name>
<description>I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. </description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN</name>
<description>External clock input.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP0</name>
<description>Capture input 0 for 16-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_25</name>
<description>I/O configuration register for pin PIO0_25/SDA/SSEL1/ CT16B1_MAT0</description>
<addressOffset>0x64</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_25/SDA/SSEL1/ CT16B1_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_25</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>SDA</name>
<description>I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. </description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL1</name>
<description>Slave Select for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT0</name>
<description>Match output 0 for 16-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_26</name>
<description>I/O configuration register for pin PIO0_26/TXD/MISO1/ CT16B1_CAP1/ CT32B0_CAP2</description>
<addressOffset>0x68</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_26/TXD/MISO1/ CT16B1_CAP1/ CT32B0_CAP2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_26</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXD</name>
<description>Transmitter data output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO1</name>
<description>Master In Slave Out for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP1</name>
<description>Capture input 1 for 16-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP2</name>
<description>Capture input 2 for 32-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_27</name>
<description>I/O configuration register for pin PIO0_27/MOSI1/ ACMP_I1/ CT32B1_MAT1/ CT16B1_CAP2</description>
<addressOffset>0x6C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_27/MOSI1/ ACMP_I1/ CT32B1_MAT1/ CT16B1_CAP2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_27</name>
<description>General purpose digital input/output pin. Input glitch
filter (10 ns) capable.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI1</name>
<description>Master Out Slave In for SSP1. Input glitch filter (10 ns) capable.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACMP_I1</name>
<description>Analog comparator input 1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT1</name>
<description>Match output 1 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP2</name>
<description>Capture input 2 for 16-bit timer 1. Input glitch filter (10 ns) capable.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADMODE</name>
<description>Selects Analog/Digital mode.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>ANALOG_INPUT_MODE_</name>
<description>Analog input mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIGITAL_FUNCTIONAL_M</name>
<description>Digital functional mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTR</name>
<description>Selects 10 ns input glitch filter.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>FILTER_DISABLED_</name>
<description>Filter disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FILTER_ENABLED_</name>
<description>Filter enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_28</name>
<description>I/O configuration register for pin PIO0_28/DTR/SSEL1/ CT32B0_CAP0</description>
<addressOffset>0x70</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_28/DTR/SSEL1/ CT32B0_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_28</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTR</name>
<description>Data Terminal Ready output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL1</name>
<description>Slave Select for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP0</name>
<description>Capture input 0 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_29</name>
<description>I/O configuration register for pin PIO0_29/DSR/SCK1/ CT32B0_CAP1</description>
<addressOffset>0x74</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_29/DSR/SCK1/ CT32B0_CAP1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_29</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DSR</name>
<description>Data Set Ready input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK1</name>
<description>Serial clock for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_CAP1</name>
<description>Capture input 1 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_30</name>
<description>I/O configuration register for pin PIO0_30/RI/MOSI1/ CT32B0_MAT0/ CT16B0_CAP0</description>
<addressOffset>0x78</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_30/RI/MOSI1/ CT32B0_MAT0/ CT16B0_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_30</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RI</name>
<description>Ring Indicator input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI1</name>
<description>Master Out Slave In for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT0</name>
<description>Match output 0 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP0</name>
<description>Capture input 0 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_31</name>
<description>I/O configuration register for pin PIO0_31/RI/MOSI1/ CT32B1_MAT0/ CT16B1_CAP1</description>
<addressOffset>0x7C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO0_31/RI/MOSI1/ CT32B1_MAT0/ CT16B1_CAP1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO0_31</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RI</name>
<description>Ring Indicator input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI1</name>
<description>Master Out Slave In for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT0</name>
<description>Match output 0 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP1</name>
<description>Capture input 1 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_0</name>
<description>I/O configuration register for pin PIO1_0/DCD/SCK0/ CT32B1_MAT3/ CT16B0_MAT1</description>
<addressOffset>0x80</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_0/DCD/SCK0/ CT32B1_MAT3/ CT16B0_MAT1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_0</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCD</name>
<description>Data Carrier Detect input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK0</name>
<description>Serial clock for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT3</name>
<description>Match output 3 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT1</name>
<description>Match output 1 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_1</name>
<description>I/O configuration register for pin PIO1_1/DTR/SSEL0/ CT32B1_MAT3/ CT16B1_MAT0</description>
<addressOffset>0x84</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_1/DTR/SSEL0/ CT32B1_MAT3/ CT16B1_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_1</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTR</name>
<description>Data Terminal Ready output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL0</name>
<description>Slave Select for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT3</name>
<description>Match output 3 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT0</name>
<description>Match output 0 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_2</name>
<description>I/O configuration register for pin PIO1_2/DSR/MISO0/ CT16B1_MAT2/ CT16B1_MAT1</description>
<addressOffset>0x88</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_2/DSR/MISO0/ CT16B1_MAT2/ CT16B1_MAT1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_2</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DSR</name>
<description>Data Set Ready input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO0</name>
<description>Master In Slave Out for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT2</name>
<description>Match output 2 for 16-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT1</name>
<description>Match output 1 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_3</name>
<description>I/O configuration register for pin PIO1_3/RI/MOSI0/ CT16B1_CAP0</description>
<addressOffset>0x8C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_3/RI/MOSI0/ CT16B1_CAP0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_3</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RI</name>
<description>Ring Indicator input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI0</name>
<description>Master Out Slave In for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP0</name>
<description>Capture input 0 for 16-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_4</name>
<description>I/O configuration register for pin PIO1_4/RXD/SSEL1/ CT32B0_MAT1/ CT32B1_CAP0/ CT16B0_CAP1</description>
<addressOffset>0x90</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_4/RXD/SSEL1/ CT32B0_MAT1/ CT32B1_CAP0/ CT16B0_CAP1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_4</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXD</name>
<description>Receiver data input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SSEL1</name>
<description>Slave Select for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT1</name>
<description>Match output 1 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP0</name>
<description>Capture input 0 for 32-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP1</name>
<description>Capture input 1 for 16-bit timer 0.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_5</name>
<description>I/O configuration register for pin PIO1_5/TXD/SCK1/ CT32B0_MAT2/ CT32B1_CAP1/ CT16B0_CAP2</description>
<addressOffset>0x94</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_5/TXD/SCK1/ CT32B0_MAT2/ CT32B1_CAP1/ CT16B0_CAP2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_5</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>TXD</name>
<description>Transmitter data output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>SCK1</name>
<description>Serial clock for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT2</name>
<description>Match output 2 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP1</name>
<description>Capture input 1 for 32-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_CAP2</name>
<description>Capture input 2 for 16-bit timer 0.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_6</name>
<description>I/O configuration register for pin PIO1_6/RTS/MOSI1/ CT32B0_MAT3/ CT32B1_CAP2/ CT16B0_MAT0</description>
<addressOffset>0x98</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_6/RTS/MOSI1/ CT32B0_MAT3/ CT32B1_CAP2/ CT16B0_MAT0</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_6</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RTS</name>
<description>Request To Send output for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI1</name>
<description>Master Out Slave In for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_MAT3</name>
<description>Match output 3 for 32-bit timer 0.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_CAP2</name>
<description>Capture input 2 for 32-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT0</name>
<description>Match output 0 for 16-bit timer 0.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_7</name>
<description>I/O configuration register for pin PIO1_7/CTS/MOSI0/ CT32B1_MAT1/ CT16B0_MAT2/ CT16B1_CAP2</description>
<addressOffset>0x9C</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_7/CTS/MOSI0/ CT32B1_MAT1/ CT16B0_MAT2/ CT16B1_CAP2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_7</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CTS</name>
<description>Clear To Send input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MOSI0</name>
<description>Master Out Slave In for SSP0.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT1</name>
<description>Match output 1 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_MAT2</name>
<description>Match output 2 for 16-bit timer 0.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_CAP2</name>
<description>Capture input 2 for 16-bit timer 1.</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_8</name>
<description>I/O configuration register for pin PIO1_8/RXD / MISO1/ CT32B1_MAT0/ CT16B1_MAT1</description>
<addressOffset>0xA0</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_8/RXD / MISO1/ CT32B1_MAT0/ CT16B1_MAT1</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_8</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXD</name>
<description>Receiver data input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>MISO1</name>
<description>Master In Slave Out for SSP1.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT0</name>
<description>Match output 0 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT1</name>
<description>Match output 1 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO1_9</name>
<description>I/O configuration register for pin PIO1_9/DCD/R/ CT32B1_MAT2 / CT16B1_MAT2</description>
<addressOffset>0xA4</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function for pin PIO1_9/DCD/R/ CT32B1_MAT2 / CT16B1_MAT2</description>
<bitRange>[2:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PIO1_9</name>
<description>General purpose digital input/output pin.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCD</name>
<description>Data Carrier Detect input for USART.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>R</name>
<description>Reserved.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_MAT2</name>
<description>Match output 2 for 32-bit timer 1.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_MAT2</name>
<description>Match output 2 for 16-bit timer 1.</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE_</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE_</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED_</name>
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[8:7]</bitRange>
</field>
<field>
<name>SLEW</name>
<description>Driver slew rate</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>SLOW</name>
<description>Slow. More outputs can be switched simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Fast.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE_</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OPEN_DRAIN_MODE_ENAB</name>
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:11]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCON</name>
<description>System configuration </description>
<groupName>SYSCON</groupName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>BOD</name>
<value>26</value>
</interrupt>
<interrupt>
<name>RESERVED0</name>
<value>12</value>
</interrupt>
<interrupt>
<name>RESERVED1</name>
<value>13</value>
</interrupt>
<interrupt>
<name>RESERVED2</name>
<value>22</value>
</interrupt>
<interrupt>
<name>RESERVED3</name>
<value>23</value>
</interrupt>
<interrupt>
<name>RESERVED4</name>
<value>28</value>
</interrupt>
<interrupt>
<name>RESERVED5</name>
<value>29</value>
</interrupt>
<interrupt>
<name>RESERVED6</name>
<value>30</value>
</interrupt>
<interrupt>
<name>RESERVED7</name>
<value>31</value>
</interrupt>
<registers>
<register>
<name>SYSMEMREMAP</name>
<description>System memory remap</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x02</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAP</name>
<description>System memory remap</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BOOT_LOADER_MODE_IN</name>
<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_RAM_MODE_INTER</name>
<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>USER_FLASH_MODE_INT</name>
<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>PRESETCTRL</name>
<description>Peripheral reset control</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSP0_RST_N</name>
<description>SSP0 reset control</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_SSP0_PERI</name>
<description>Resets the SSP0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSP0_RESET_DE_ASSERT</name>
<description>SSP0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C_RST_N</name>
<description>I2C reset control</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_I2C_PERIP</name>
<description>Resets the I2C peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C_RESET_DE_ASSERTE</name>
<description>I2C reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSP1_RST_N</name>
<description>SSP1 reset control</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_SSP1_PERI</name>
<description>Resets the SSP1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SSP1_RESET_DE_ASSERT</name>
<description>SSP1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>UART_RST_N</name>
<description>UART reset control</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_UART_PERI</name>
<description>Resets the UART peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UART_RESET_DE_ASSERT</name>
<description>UART reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B0_RST_N</name>
<description>CT16B0 reset control</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_CT16B0_PE</name>
<description>Resets the CT16B0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B0_RESET_DE_ASSE</name>
<description>CT16B0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B1_RST_N</name>
<description>CT16B1 reset control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_CT16B1_PE</name>
<description>Resets the CT16B1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CT16B1_RESET_DE_ASSE</name>
<description>CT16B1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B0_RST_N</name>
<description>CT32B0 reset control</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_CT32B0_PE</name>
<description>Resets the CT32B0 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B0_RESET_DE_ASSE</name>
<description>CT32B0 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B1_RST_N</name>
<description>CT32B1 reset control</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_CT32B1_PE</name>
<description>Resets the CT32B1 peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CT32B1_RESET_DE_ASSE</name>
<description>CT32B1 reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACOMP_RST_N</name>
<description>Analog comparator reset control</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_ANALOG_CO</name>
<description>Resets the Analog comparator peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ANALOG_COMPARATOR_RE</name>
<description>Analog comparator reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC_RST_N</name>
<description>DAC reset control</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_DAC_PERIP</name>
<description>Resets the DAC peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DAC_RESET_DE_ASSERTE</name>
<description>DAC reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC_RST_N</name>
<description>ADC reset control</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESETS_THE_ADC_PERIP</name>
<description>Resets the ADC peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADC_RESET_DE_ASSERTE</name>
<description>ADC reset de-asserted.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:12]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCTRL</name>
<description>System PLL control</description>
<addressOffset>0x008</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>PSEL</name>
<description>Post divider ratio P. The division ratio is 2 x P.</description>
<bitRange>[6:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>P_EQ_1</name>
<description>P = 1</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_2</name>
<description>P = 2</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_4</name>
<description>P = 4</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>P_EQ_8</name>
<description>P = 8</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. Do not write ones to reserved bits.</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLSTAT</name>
<description>System PLL status</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOCK</name>
<description>PLL lock status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>PLL_NOT_LOCKED</name>
<description>PLL not locked</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_LOCKED</name>
<description>PLL locked</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSOSCCTRL</name>
<description>System oscillator control</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0x000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BYPASS</name>
<description>Bypass system oscillator</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OSCILLATOR_IS_NOT_BY</name>
<description>Oscillator is not bypassed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BYPASS_ENABLED_PLL_</name>
<description>Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FREQRANGE</name>
<description>Determines frequency range for Low-power oscillator.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>1__20_MHZ_FREQUENCY</name>
<description>1 - 20 MHz frequency range.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>15__25_MHZ_FREQUENC</name>
<description>15 - 25 MHz frequency range</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>WDTOSCCTRL</name>
<description>Watchdog oscillator control</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0x0A0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVSEL</name>
<description>Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>FREQSEL</name>
<description>Select watchdog oscillator analog output frequency (Fclkana).</description>
<bitRange>[8:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OPERATION_IS_UNDEFIN</name>
<description>Operation is undefined for this value. Startup code should program a non-zero value in this field as soon after reset as possible.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>0_6_MHZ</name>
<description>0.6 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>1_05_MHZ</name>
<description>1.05 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>1_4_MHZ</name>
<description>1.4 MHz</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>1_75_MHZ</name>
<description>1.75 MHz</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>2_1_MHZ</name>
<description>2.1 MHz</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>2_4_MHZ</name>
<description>2.4 MHz</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>2_7_MHZ</name>
<description>2.7 MHz</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>3_0_MHZ</name>
<description>3.0 MHz</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>3_25_MHZ</name>
<description>3.25 MHz</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>3_5_MHZ</name>
<description>3.5 MHz</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>3_75_MHZ</name>
<description>3.75 MHz</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>4_0_MHZ</name>
<description>4.0 MHz</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>4_2_MHZ</name>
<description>4.2 MHz</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>4_4_MHZ</name>
<description>4.4 MHz</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>4_6_MHZ</name>
<description>4.6 MHz</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>IRCCTRL</name>
<description>IRC oscillator control</description>
<addressOffset>0x028</addressOffset>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>Trim value</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>LFOSCCTRL</name>
<description>LF oscillator control</description>
<addressOffset>0x02C</addressOffset>
<access>read-write</access>
<resetValue>0x0A0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVSEL</name>
<description>Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>FREQSEL</name>
<description>Select watchdog oscillator analog output frequency (Fclkana).</description>
<bitRange>[8:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OPERATION_IS_UNDEFIN</name>
<description>Operation is undefined for this value. Startup code should program a non-zero value in this field as soon after reset as possible.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>0_6_MHZ</name>
<description>0.6 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>1_05_MHZ</name>
<description>1.05 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>1_4_MHZ</name>
<description>1.4 MHz</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>1_75_MHZ</name>
<description>1.75 MHz</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>2_1_MHZ</name>
<description>2.1 MHz</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>2_4_MHZ</name>
<description>2.4 MHz</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>2_7_MHZ</name>
<description>2.7 MHz</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>3_0_MHZ</name>
<description>3.0 MHz</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>3_25_MHZ</name>
<description>3.25 MHz</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>3_5_MHZ</name>
<description>3.5 MHz</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>3_75_MHZ</name>
<description>3.75 MHz</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>4_0_MHZ</name>
<description>4.0 MHz</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>4_2_MHZ</name>
<description>4.2 MHz</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>4_4_MHZ</name>
<description>4.4 MHz</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>4_6_MHZ</name>
<description>4.6 MHz</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:9]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSRSTSTAT</name>
<description>System reset status register</description>
<addressOffset>0x030</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POR</name>
<description>POR reset status</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_POR_DETECTED</name>
<description>No POR detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POR_DETECTED</name>
<description>POR detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTRST</name>
<description>External reset status</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_RESET_EVENT_DETEC</name>
<description>No RESET event detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_DETECTED</name>
<description>RESET detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT</name>
<description>Status of the Watchdog reset</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_WDT_RESET_DETECTE</name>
<description>No WDT reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WDT_RESET_DETECTED</name>
<description>WDT reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOD</name>
<description>Status of the Brown-out detect reset</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_BOD_RESET_DETECTE</name>
<description>No BOD reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BOD_RESET_DETECTED</name>
<description>BOD reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSRST</name>
<description>Status of the software system reset</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_SYSTEM_RESET_DETE</name>
<description>No System reset detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SYSTEM_RESET_DETECTE</name>
<description>System reset detected</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCLKSEL</name>
<description>System PLL clock source select</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>System PLL clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC</name>
<description>IRC</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRYSTAL_OSCILLATOR_</name>
<description>Crystal Oscillator (XTAL)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLKIN_PIN</name>
<description>CLKIN pin</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSPLLCLKUEN</name>
<description>System PLL clock source update enable</description>
<addressOffset>0x044</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable system PLL clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKSEL</name>
<description>Main clock source select</description>
<addressOffset>0x070</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>Clock source for main clock</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC Oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_INPUT</name>
<description>PLL input</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LF_OSCILLATOR</name>
<description>LF Oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_OUTPUT</name>
<description>PLL output</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>MAINCLKUEN</name>
<description>Main clock source update enable</description>
<addressOffset>0x074</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable main clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKDIV</name>
<description>System clock divider</description>
<addressOffset>0x078</addressOffset>
<access>read-write</access>
<resetValue>0x001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSAHBCLKCTRL</name>
<description>System clock control</description>
<addressOffset>0x080</addressOffset>
<access>read-write</access>
<resetValue>0x01F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYS</name>
<description>Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROM</name>
<description>Enables clock for ROM.</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Enables clock for RAM.</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHREG</name>
<description>Enables clock for flash/EEPROM register interface.</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHARRAY</name>
<description>Enables clock for flash/EEPROM array access.</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C</name>
<description>Enables clock for I2C.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIO</name>
<description>Enables clock for GPIO.</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B0</name>
<description>Enables clock for 16-bit counter/timer 0.</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT16B1</name>
<description>Enables clock for 16-bit counter/timer 1.</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B0</name>
<description>Enables clock for 32-bit counter/timer 0.</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CT32B1</name>
<description>Enables clock for 32-bit counter/timer 1.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSP0</name>
<description>Enables clock for SSP0.</description>
<bitRange>[11:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART</name>
<description>Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled.</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC</name>
<description>Enables clock for ADC.</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>WDT</name>
<description>Enables clock for WDT.</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IOCON</name>
<description>Enables clock for I/O configuration block.</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SSP1</name>
<description>Enables clock for SSP1.</description>
<bitRange>[18:18]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINT</name>
<description>GPIO Pin interrupts</description>
<bitRange>[19:19]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACOMP</name>
<description>Enables clock for ACOMP.</description>
<bitRange>[20:20]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC</name>
<description>Enables clock for DAC.</description>
<bitRange>[21:21]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>P0INT</name>
<description>GPIO Port 0 interrupt</description>
<bitRange>[23:23]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>P1INT</name>
<description>GPIO Port 1interrupt</description>
<bitRange>[24:24]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:25]</bitRange>
</field>
</fields>
</register>
<register>
<name>SSP0CLKDIV</name>
<description>SSP0 clock divider</description>
<addressOffset>0x094</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>SSP0_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>UARTCLKDIV</name>
<description>UART clock divider</description>
<addressOffset>0x098</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SSP1CLKDIV</name>
<description>SSP1 clock divider</description>
<addressOffset>0x09C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTSEL</name>
<description>CLKOUT clock source select</description>
<addressOffset>0x0E0</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEL</name>
<description>CLKOUT clock source</description>
<bitRange>[1:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IRC_OSCILLATOR</name>
<description>IRC oscillator</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRYSTAL_OSCILLATOR_</name>
<description>Crystal oscillator (XTAL)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>LF_OSCILLATOR</name>
<description>LF oscillator</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>MAIN_CLOCK</name>
<description>Main clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:2]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTUEN</name>
<description>CLKOUT clock source update enable</description>
<addressOffset>0x0E4</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA</name>
<description>Enable CLKOUT clock source update</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No change</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATE_CLOCK_SOURCE</name>
<description>Update clock source</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:1]</bitRange>
</field>
</fields>
</register>
<register>
<name>CLKOUTDIV</name>
<description>CLKOUT clock divider</description>
<addressOffset>0x0E8</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIV</name>
<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP0</name>
<description>POR captured PIO status 0</description>
<addressOffset>0x100</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO0_31 through PIO0_0 at power-on reset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIOPORCAP1</name>
<description>POR captured PIO status 1</description>
<addressOffset>0x104</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>PIOSTAT</name>
<description>State of PIO1_9 through PIO1_0 at power-on reset</description>
<bitRange>[9:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>BODR</name>
<description>Brown-Out Detect</description>
<addressOffset>0x150</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>BODINTVAL</name>
<description>BOD interrupt threshold</description>
<bitRange>[3:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>LEVEL_2_THE_INTERRU</name>
<description>Level 2: the interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_3_THE_INTERRU</name>
<description>Level 3: the interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>BODINT</name>
<description>This bit is 1 if the BOD is requesting an interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYSTCKCAL</name>
<description>System tick counter calibration</description>
<addressOffset>0x158</addressOffset>
<access>read-write</access>
<resetValue>0x004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAL</name>
<description>System tick timer calibration value</description>
<bitRange>[25:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:26]</bitRange>
</field>
</fields>
</register>
<register>
<name>NMISRC</name>
<description>NMI Source Control</description>
<addressOffset>0x174</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRQNO</name>
<description>The IRQ number of the interrupt that is to act as the Non-Maskable interrupt (NMI) if bit 31 is 1. See Section 4.3 for the list of interrupt sources and their IRQ numbers.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[30:5]</bitRange>
</field>
<field>
<name>NMIEN</name>
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-7</dimIndex>
<name>PINTSEL%s</name>
<description>GPIO Pin Interrupt Select register 0</description>
<addressOffset>0x178</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTPIN</name>
<description>The pin number within the port identified by the INTPORT field.</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>INTPORT</name>
<description>Select the port: 0 = P0 pin. 1 = P1 pin.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:6]</bitRange>
</field>
</fields>
</register>
<register>
<name>PDRUNCFG</name>
<description>Power configuration register</description>
<addressOffset>0x238</addressOffset>
<access>read-write</access>
<resetValue>0x0000EDF0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IRCOUT_PD</name>
<description>IRC oscillator output power-down</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRC_PD</name>
<description>IRC oscillator power-down</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASH_PD</name>
<description>Flash power-down</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ADC_PD</name>
<description>ADC power-down</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XTAL_PD</name>
<description>Crystal oscillator power-down</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOSC_PD</name>
<description>Watchdog oscillator power-down</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYSPLL_PD</name>
<description>System PLL power-down</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. This bit must be set to zero during normal operation in Run mode.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved. This bit must be set to one in Run mode.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>LFOSC_PD</name>
<description>Low frequency oscillator power-down</description>
<bitRange>[13:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC_PD</name>
<description>DAC power-down</description>
<bitRange>[14:14]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS_PD</name>
<description>Temperature Sensor power-down</description>
<bitRange>[15:15]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACOMP_PD</name>
<description>Analog Comparator power-down</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>POWERED_DOWN</name>
<description>Powered down</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POWERED</name>
<description>Powered</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:17]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVICE_ID</name>
<description>Device ID</description>
<addressOffset>0x3F4</addressOffset>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>DEVICEID</name>
<description>Part ID number for LPC11Axx LPC11A11FBD48/001 = 0x455E C02B LPC11A11FHN33/001 = 0x455E C02B LPC11A12FBD48/101 = 0x4574 802B LPC11A12FHN33/101 = 0x4574 802B LPC11A13FBD48/201 = 0x4582 402B LPC11A13FHI33/201 = 0x4582 402B LPC11A14FBD48/301 = 0x35A0 002B; 0x45A0 002B LPC11A14FHN33/301 = 0x35A0 002B; 0x45A0 002B LPC11A02UK = 0x4D5C C02B LPC11A04UK = 0x4D80 002B</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIO_PIN_INT</name>
<description>GPIO Modification </description>
<groupName>GPIO_PIN_INT</groupName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIN_INT0</name>
<value>0</value>
</interrupt>
<interrupt>
<name>PIN_INT1</name>
<value>1</value>
</interrupt>
<interrupt>
<name>PIN_INT2</name>
<value>2</value>
</interrupt>
<interrupt>
<name>PIN_INT3</name>
<value>3</value>
</interrupt>
<interrupt>
<name>PIN_INT4</name>
<value>4</value>
</interrupt>
<interrupt>
<name>PIN_INT5</name>
<value>5</value>
</interrupt>
<interrupt>
<name>PIN_INT6</name>
<value>6</value>
</interrupt>
<interrupt>
<name>PIN_INT7</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>ISEL</name>
<description>Pin Interrupt Mode register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMODE0</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PMODE1</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PMODE2</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PMODE3</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PMODE4</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PMODE5</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PMODE6</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PMODE7</name>
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENR</name>
<description>Pin Interrupt Enable (Rising) register</description>
<addressOffset>0x004</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENRL0</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENRL1</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENRL2</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENRL3</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENRL4</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENRL5</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENRL6</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENRL7</name>
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENR</name>
<description>Set Pin Interrupt Enable (Rising) register</description>
<addressOffset>0x008</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENRL0</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETENRL1</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETENRL2</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETENRL3</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETENRL4</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETENRL5</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETENRL6</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETENRL7</name>
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENR</name>
<description>Clear Pin Interrupt Enable (Rising) register</description>
<addressOffset>0x00C</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENRL0</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CENRL1</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CENRL2</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CENRL3</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CENRL4</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CENRL5</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CENRL6</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CENRL7</name>
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IENF</name>
<description>Pin Interrupt Enable Falling Edge / Active Level register</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENAF0</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENAF1</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENAF2</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENAF3</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENAF4</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENAF5</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENAF6</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENAF7</name>
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>SIENF</name>
<description>Set Pin Interrupt Enable Falling Edge / Active Level register</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>SETENAF0</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETENAF1</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETENAF2</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETENAF3</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETENAF4</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETENAF5</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETENAF6</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETENAF7</name>
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>CIENF</name>
<description>Clear Pin Interrupt Enable Falling Edge / Active Level address</description>
<addressOffset>0x018</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CENAF0</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CENAF1</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CENAF2</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CENAF3</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CENAF4</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CENAF5</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CENAF6</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CENAF7</name>
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>RISE</name>
<description>Pin Interrupt Rising Edge register</description>
<addressOffset>0x01C</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDET0</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RDET1</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>RDET2</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>RDET3</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>RDET4</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>RDET5</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>RDET6</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>RDET7</name>
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>FALL</name>
<description>Pin Interrupt Falling Edge register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FDET0</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>FDET1</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>FDET2</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>FDET3</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>FDET4</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>FDET5</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>FDET6</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>FDET7</name>
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
<register>
<name>IST</name>
<description>Pin Interrupt Status register</description>
<addressOffset>0x024</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PSTAT0</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PSTAT1</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PSTAT2</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PSTAT3</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PSTAT4</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PSTAT5</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PSTAT6</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PSTAT7</name>
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:8]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SSP0">
<name>SSP1</name>
<baseAddress>0x40058000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SSP1</name>
<value>14</value>
</interrupt>
</peripheral>
<peripheral>
<name>GPIO_GROUP_INT0</name>
<description>GPIO group interrupt </description>
<groupName>GPIO_GROUP_INT0</groupName>
<baseAddress>0x4005C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT0</name>
<value>8</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>GPIO grouped interrupt control register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT</name>
<description>Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>NO_INTERRUPT_REQUEST</name>
<description>No interrupt request is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERRUPT_REQUEST_IS</name>
<description>Interrupt request is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMB</name>
<description>Combine enabled inputs for group interrupt</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>OR_FUNCTIONALITY_A_</name>
<description>OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AND_FUNCTIONALITY_A</name>
<description>AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG</name>
<description>Group interrupt trigger</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>EDGE_TRIGGERED</name>
<description>Edge-triggered</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEVEL_TRIGGERED</name>
<description>Level-triggered</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved</description>
<bitRange>[31:3]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PORT_POL%s</name>
<description>GPIO grouped interrupt port 0 polarity register</description>
<addressOffset>0x020</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL_0</name>
<description>Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>POL_1</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>POL_2</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>POL_3</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>POL_4</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>POL_5</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>POL_6</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>POL_7</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>POL_8</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>POL_9</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>POL_10</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>POL_11</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>POL_12</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>POL_13</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>POL_14</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>POL_15</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>POL_16</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>POL_17</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>POL_18</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>POL_19</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>POL_20</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>POL_21</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>POL_22</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>POL_23</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>POL_24</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>POL_25</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>POL_26</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>POL_27</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>POL_28</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>POL_29</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>POL_30</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>POL_31</name>
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PORT_ENA%s</name>
<description>GPIO grouped interrupt port 0/1 enable register</description>
<addressOffset>0x040</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENA_0</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ENA_1</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENA_2</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ENA_3</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ENA_4</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ENA_5</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ENA_6</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ENA_7</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>ENA_8</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ENA_9</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>ENA_10</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>ENA_11</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>ENA_12</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>ENA_13</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>ENA_14</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>ENA_15</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>ENA_16</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>ENA_17</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>ENA_18</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>ENA_19</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>ENA_20</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>ENA_21</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>ENA_22</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>ENA_23</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>ENA_24</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>ENA_25</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>ENA_26</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>ENA_27</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>ENA_28</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>ENA_29</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>ENA_30</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>ENA_31</name>
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIO_GROUP_INT0">
<name>GPIO_GROUP_INT1</name>
<baseAddress>0x40060000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GINT1</name>
<value>9</value>
</interrupt>
</peripheral>
<peripheral>
<name>GPIO_PORT</name>
<description>GPIO port </description>
<groupName>GPIO_PORT</groupName>
<baseAddress>0x50000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFFFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!-- <register> this occupies the same address space as B0 and B1 but causes an error in svdconv
<dim>64</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0-63</dimIndex>
<name>B%s</name>
<description>Byte pin registers port 0; pins PIO0_0 to PIO0_31</description>
<addressOffset>0x0000</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register> -->
<register>
<dim>32</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0-31</dimIndex>
<name>B%s</name>
<description>Byte pin registers port 0; pins PIO0_0 to PIO0_31</description>
<addressOffset>0x0000</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>32-41</dimIndex>
<name>B%s</name>
<description>Byte pin registers port 1</description>
<addressOffset>0x0020</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PBYTE</name>
<description>Read: state of the pin P1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-31</dimIndex>
<name>W%s</name>
<description>Word pin registers port 0</description>
<addressOffset>0x1000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>10</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>32-41</dimIndex>
<name>W%s</name>
<description>Word pin registers port 1</description>
<addressOffset>0x1080</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWORD</name>
<description>Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>DIR%s</name>
<description>Direction registers port 0/1</description>
<addressOffset>0x2000</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIRP0</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>DIRP1</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>DIRP2</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>DIRP3</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>DIRP4</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>DIRP5</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>DIRP6</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>DIRP7</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>DIRP8</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>DIRP9</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>DIRP10</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>DIRP11</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>DIRP12</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>DIRP13</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>DIRP14</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>DIRP15</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>DIRP16</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>DIRP17</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>DIRP18</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>DIRP19</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>DIRP20</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>DIRP21</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>DIRP22</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>DIRP23</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>DIRP24</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>DIRP25</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>DIRP26</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>DIRP27</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>DIRP28</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>DIRP29</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>DIRP30</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>DIRP31</name>
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>MASK%s</name>
<description>Mask register port 0/1</description>
<addressOffset>0x2080</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASKP0</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MASKP1</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MASKP2</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MASKP3</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MASKP4</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>MASKP5</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MASKP6</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>MASKP7</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MASKP8</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>MASKP9</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MASKP10</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>MASKP11</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>MASKP12</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>MASKP13</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>MASKP14</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>MASKP15</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MASKP16</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MASKP17</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>MASKP18</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MASKP19</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MASKP20</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>MASKP21</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>MASKP22</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>MASKP23</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>MASKP24</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>MASKP25</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>MASKP26</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>MASKP27</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>MASKP28</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>MASKP29</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MASKP30</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>MASKP31</name>
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PIN%s</name>
<description>Portpin register port 0</description>
<addressOffset>0x2100</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT0</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>PORT1</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>PORT2</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>PORT3</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>PORT4</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>PORT5</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>PORT6</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>PORT7</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>PORT8</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>PORT9</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>PORT10</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>PORT11</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>PORT12</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>PORT13</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>PORT14</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>PORT15</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>PORT16</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>PORT17</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>PORT18</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>PORT19</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>PORT20</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>PORT21</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>PORT22</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>PORT23</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>PORT24</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>PORT25</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>PORT26</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>PORT27</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>PORT28</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>PORT29</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>PORT30</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>PORT31</name>
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>MPIN%s</name>
<description>Masked port register port 0/1</description>
<addressOffset>0x2180</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MPORTP0</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>MPORTP1</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>MPORTP2</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>MPORTP3</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>MPORTP4</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>MPORTP5</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>MPORTP6</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>MPORTP7</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>MPORTP8</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>MPORTP9</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>MPORTP10</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>MPORTP11</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>MPORTP12</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>MPORTP13</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>MPORTP14</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>MPORTP15</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>MPORTP16</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>MPORTP17</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>MPORTP18</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>MPORTP19</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MPORTP20</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>MPORTP21</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>MPORTP22</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>MPORTP23</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>MPORTP24</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>MPORTP25</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>MPORTP26</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>MPORTP27</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>MPORTP28</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>MPORTP29</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>MPORTP30</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>MPORTP31</name>
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>SET%s</name>
<description>Write: Set register for port 0/1 Read: output bits for port 0/1</description>
<addressOffset>0x2200</addressOffset>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETP0</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SETP1</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SETP2</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SETP3</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SETP4</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SETP5</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>SETP6</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>SETP7</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SETP8</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>SETP9</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>SETP10</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>SETP11</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>SETP12</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>SETP13</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>SETP14</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>SETP15</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>SETP16</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>SETP17</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>SETP18</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>SETP19</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>SETP20</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>SETP21</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>SETP22</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>SETP23</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>SETP24</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>SETP25</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>SETP26</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>SETP27</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>SETP28</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>SETP29</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>SETP30</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>SETP31</name>
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>CLR%s</name>
<description>Clear port 0/1</description>
<addressOffset>0x2280</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CLRP00</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CLRP01</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CLRP02</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CLRP03</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CLRP04</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CLRP05</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CLRP06</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>CLRP07</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>CLRP08</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>CLRP09</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>CLRP010</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>CLRP011</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>CLRP012</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>CLRP013</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>CLRP014</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>CLRP015</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>CLRP016</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>CLRP017</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>CLRP018</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>CLRP019</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>CLRP020</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>CLRP021</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>CLRP022</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>CLRP023</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>CLRP024</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>CLRP025</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>CLRP026</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>CLRP027</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>CLRP028</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>CLRP029</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>CLRP030</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>CLRP031</name>
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>NOT%s</name>
<description>Toggle port 0/1</description>
<addressOffset>0x2300</addressOffset>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>NOTP0</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>NOTP1</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>NOTP2</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>NOTP3</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>NOTP4</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>NOTP5</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>NOTP6</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>NOTP7</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>NOTP8</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>NOTP9</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>NOTP10</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>NOTP11</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>NOTP12</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>NOTP13</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>NOTP14</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>NOTP15</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>NOTP16</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>NOTP17</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>NOTP18</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>NOTP19</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>NOTP20</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>NOTP21</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[21:21]</bitRange>
</field>
<field>
<name>NOTP22</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[22:22]</bitRange>
</field>
<field>
<name>NOTP23</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>NOTP24</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>NOTP25</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>NOTP26</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[26:26]</bitRange>
</field>
<field>
<name>NOTP27</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[27:27]</bitRange>
</field>
<field>
<name>NOTP28</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[28:28]</bitRange>
</field>
<field>
<name>NOTP29</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[29:29]</bitRange>
</field>
<field>
<name>NOTP30</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[30:30]</bitRange>
</field>
<field>
<name>NOTP31</name>
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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