LPC11Axx 0.6 LPC11Axx CM0 r0p0 little 0 0 2 0 LPC_ 8 32 32 I2C I2C-bus controller I2C 0x40000000 0 0xFFF registers I2C 15 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AA Assert acknowledge flag. [2:2] SI I2C interrupt flag. [3:3] STO STOP flag. [4:4] STA START flag. [5:5] I2EN I2C interface enable. [6:6] RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x004 read-only 0xF8 0xFFFFFFFF RESERVED These bits are unused and are always 0. [2:0] Status These bits give the actual status information about the I2C interface. [7:3] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x008 read-write 0x00 0xFFFFFFFF Data This register holds data values that have been received or are to be transmitted. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x00C read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x010 read-write 0x04 0xFFFFFFFF SCLH Count for SCL HIGH time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x014 read-write 0x04 0xFFFFFFFF SCLL Count for SCL low time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x018 write-only 0 0x00000000 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AAC Assert acknowledge Clear bit. [2:2] SIC I2C interrupt Clear bit. [3:3] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:4] STAC START flag Clear bit. [5:5] I2ENC I2C interface Disable bit. [6:6] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] MMCTRL Monitor mode control register. 0x01C read-write 0x00 0xFFFFFFFF MM_ENA Monitor mode enable. [0:0] ENUM MONITOR_MODE_DISABLE Monitor mode disabled. 0 THE_I2C_MODULE_WILL_ The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. [1:1] ENUM HIGH When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 NORMAL When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. [2:2] ENUM MATCH When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 ANYADDRESS When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 RESERVED Reserved. The value read from reserved bits is not defined. [31:3] 3 0x4 1-3 ADR%s I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x020 read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x02C read-only 0x00 0xFFFFFFFF Data This register holds contents of the 8 MSBs of the DAT shift register. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] 4 0x4 0-3 MASK%s I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x030 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. [0:0] MASK Mask bits. [7:1] RESERVED Reserved. The value read from reserved bits is undefined. [31:8] WWDT Windowed Watchdog Timer (WWDT) WWDT 0x40004000 0 0xFFF registers WDT 25 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [0:0] ENUM STOPPED The watchdog timer is stopped. 0 RUNNING The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [1:1] ENUM INTERRUPT A watchdog timeout will not cause a chip reset. 0 RESET A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. [4:4] ENUM NOT_LOCKED The watchdog time-out value (TC) can be changed at any time. 0 LOCKED The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 LOCK A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7). [5:5] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF COUNT Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 FEED Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF COUNT Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] CLKSEL Watchdog clock select register. 0x010 read-write 0 0xFFFFFFFF CLKSEL Selects source of WDT clock [0:0] ENUM IRC IRC 0 WATCHDOG_OSCILLATOR_ Watchdog oscillator (WDOSC) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:1] LOCK If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. [31:31] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] USART USART USART 0x40008000 0 0xFFF registers USART 21 RBR Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) 0x000 read-only 0 0x00000000 RBR The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO. [7:0] RESERVED Reserved [31:8] THR Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) RBR 0x000 write-only 0 0x00000000 THR Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available. [7:0] RESERVED Reserved [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) 0x004 read-write 0 0xFFFFFFFF DLMSB The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) DLM 0x004 read-write 0 0xFFFFFFFF RBRINTEN RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupt. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupt. 1 THREINTEN THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupt. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupt. 1 RLSINTEN Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE_THE_RLS_INTE Disable the RLS interrupt. 0 ENABLE_THE_RLS_INTER Enable the RLS interrupt. 1 MSINTEN Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR. [3:3] ENUM DISABLE_THE_MS_INTER Disable the MS interrupt. 0 ENABLE_THE_MS_INTERR Enable the MS interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:4] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE_END_OF_AUTO_ Disable end of auto-baud Interrupt. 0 ENABLE_END_OF_AUTO_B Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE_AUTO_BAUD_TI Disable auto-baud time-out Interrupt. 0 ENABLE_AUTO_BAUD_TIM Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM AT_LEAST_ONE_INTERRU At least one interrupt is pending. 0 NO_INTERRUPT_IS_PEND No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved. [3:1] ENUM 1_RECEIVE_LINE_S 1 - Receive Line Status (RLS). 0x3 2A__RECEIVE_DATA_AV 2a - Receive Data Available (RDA). 0x2 2B__CHARACTER_TIME_ 2b - Character Time-out Indicator (CTI). 0x6 3_THRE_INTERRUPT 3 - THRE Interrupt. 0x1 4_MODEM_STATUS 4 - Modem status 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOEN These bits are equivalent to FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls USART FIFO usage and modes. 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO enable [0:0] ENUM DISABLED USART FIFOs are disabled. Must not be used in the application. 0 ENABLED Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs. 1 RXFIFORES RX FIFO Reset [1:1] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset [2:2] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTL RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated. [7:6] ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved [31:8] MCR Modem Control Register. 0x010 read-write 0 0xFFFFFFFF DTRCTRL Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active. [0:0] RTSCTRL Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:2] LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR. [4:4] ENUM DISABLE_MODEM_LOOPBA Disable modem loopback mode. 0 ENABLE_MODEM_LOOPBAC Enable modem loopback mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:5] RTSEN RTS enable [6:6] ENUM DISABLE_AUTO_RTS_FLO Disable auto-rts flow control. 0 ENABLE_AUTO_RTS_FLOW Enable auto-rts flow control. 1 CTSEN CTS enable [7:7] ENUM DISABLE_AUTO_CTS_FLO Disable auto-cts flow control. 0 ENABLE_AUTO_CTS_FLOW Enable auto-cts flow control. 1 RESERVED Reserved [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF RDR Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty. [0:0] ENUM RBR_IS_EMPTY_ RBR is empty. 0 RBR_CONTAINS_VALID_D RBR contains valid data. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write. [5:5] ENUM THR_CONTAINS_VALID_D THR contains valid data. 0 THR_IS_EMPTY_ THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM VALID_D THR and/or the TSR contains valid data. 0 EMPTY THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO. [7:7] ENUM NO_ERROR RBR contains no USART RX errors or FCR[0]=0. 0 ERRO USART RBR contains at least one USART RX error. 1 TXERR Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field. [8:8] RESERVED Reserved [31:9] MSR Modem Status Register. 0x018 read-only 0 0xFFFFFFFF DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. [0:0] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, CTS. 0 STATE_CHANGE_DETECTE State change detected on modem input, CTS. 1 DDSR Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. [1:1] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DSR. 0 STATE_CHANGE_DETECTE State change detected on modem input, DSR. 1 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. [2:2] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, RI. 0 LOW_TO_HIGH_TRANSITI Low-to-high transition detected on RI. 1 DDCD Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. [3:3] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DCD. 0 STATE_CHANGE_DETECTE State change detected on modem input, DCD. 1 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. [4:4] DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. [5:5] RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. [6:6] DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. [7:7] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF PAD A readable, writable byte. [7:0] RESERVED Reserved [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START This bit is automatically cleared after auto-baud completion. [0:0] ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 AUTORESTART Start mode [2:2] ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next USART Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write only accessible). [8:8] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write only accessible). [9:9] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] ICR IrDA Control Register. Enables and configures the IrDA (remote control) mode. 0x024 read-write 0 0xFFFFFFFF IRDAEN IrDA mode enable [0:0] ENUM IRDA_MODE_IS_DISABLE IrDA mode is disabled, USARTn acts as a standard USART. 0 IRDA_MODE_IS_ENABLED IrDA mode is enabled. 1 IRDAINV Serial input inverter [1:1] ENUM INVERTED The serial input is not inverted. 0 NOT_INVERTED The serial input is inverted. This has no effect on the serial output. 1 FIXPULSEEN IrDA fixed pulse width mode. [2:2] ENUM DISABLED IrDA fixed pulse width mode disabled. 0 ENABLED IrDA fixed pulse width mode enabled. 1 PULSEDIV Configures the pulse width when FixPulseEn = 1. [5:3] ENUM 3_DIV_16_X_BAUD_RATE 3 / (16 x baud rate) 0x0 2_X_TPCLK 2 x TPCLK 0x1 4_X_TPCLK 4 x TPCLK 0x2 8_X_TPCLK 8 x TPCLK 0x3 16_X_TPCLK 16 x TPCLK 0x4 32_X_TPCLK 32 x TPCLK 0x5 64_X_TPCLK 64 x TPCLK 0x6 128_X_TPCLK 128 x TPCLK 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] OSR Oversampling Register. Controls the degree of oversampling during each bit time. 0x02C read-write 0xF0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875) [3:1] OSINT Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time. [7:4] FDINT In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. [14:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] TER Transmit Enable Register. Turns off USART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. [7:7] RESERVED Reserved [31:8] HDEN Half duplex enable register. 0x040 read-write 0 0xFFFFFFFF HDEN Half-duplex mode enable [0:0] ENUM DISABLE_HALF_DUPLEX_ Disable half-duplex mode. 0 ENABLE_HALF_DUPLEX_M Enable half-duplex mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] SCICTRL Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. 0x048 read-write 0 0xFFFFFFFF SCIEN Smart Card Interface Enable. [0:0] ENUM SMART_CARD_INTERFACE Smart card interface disabled. 0 ASYNCHRONOUS_HALF_DU Asynchronous half duplex smart card interface is enabled. 1 NACKDIS NACK response disable. Only applicable in T=0. [1:1] ENUM ENABLED A NACK response is enabled. 0 DISABLED A NACK response is inhibited. 1 PROTSEL Protocol selection as defined in the ISO7816-3 standard. [2:2] ENUM T_EQ_0 T = 0 0 T_EQ_1 T = 1 1 RESERVED Reserved. [4:3] TXRETRY When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared. [7:5] XTRAGUARD When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. 1 RXDIS Receiver enable. [1:1] ENUM THE_RECEIVER_IS_ENAB The receiver is enabled. 0 THE_RECEIVER_IS_DISA The receiver is disabled. 1 AADEN AAD enable. [2:2] ENUM AUTO_ADDRESS_DETECT_ Auto Address Detect (AAD) is disabled. 0 AUTO_ADDRESS_DETECT_ Auto Address Detect (AAD) is enabled. 1 SEL Select direction control pin [3:3] ENUM RTS If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Auto direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] SYNCCTRL Synchronous mode control register. 0x058 read-write 0 0xFFFFFFFF SYNC Enables synchronous mode. [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 CSRC Clock source select. [1:1] ENUM SYNCHRONOUS_SLAVE_MO Synchronous slave mode (SCLK in) 0 SYNCHRONOUS_MASTER_M Synchronous master mode (SCLK out) 1 FES Falling edge sampling. [2:2] ENUM RISING RxD is sampled on the rising edge of SCLK 0 FALLING RxD is sampled on the falling edge of SCLK 1 TSBYPASS Transmit synchronization bypass in synchronous slave mode. [3:3] ENUM SYNC The input clock is synchronized prior to being used in clock edge detection logic 0 NOSYNC The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. 1 CSCEN Continuous master clock enable (used only when CSRC is 1) [4:4] ENUM SCLK_CYCLES_ONLY_WHE SCLK cycles only when characters are being sent on TxD 0 SCLK_RUNS_CONTINUOUS SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) 1 SSDIS Start/stop bits [5:5] ENUM SEND Send start and stop bits as in other modes. 0 DO_NOT_SEND Do not send start/stop bits. 1 CCCLR Continuous clock clear [6:6] ENUM CSCEN_IS_UNDER_SOFTW CSCEN is under software control. 0 HARDWARE_CLEARS_CSCE Hardware clears CSCEN after each character is received. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] CT16B0 16-bit counter/timers CT16B0/1 CT16B0 0x4000C000 0 0xFFF registers CT16B0 16 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] CR2INT Interrupt flag for capture channel 2 event. [6:6] CR3INT Interrupt flag for capture channel 3 event. [7:7] RESERVED Reserved [31:8] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING_ Do nothing. 0 THE_TIMER_COUNTER_AN The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [15:0] RESERVED Reserved. [31:16] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescale value. [15:0] RESERVED Reserved. [31:16] PC Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [15:0] RESERVED Reserved. [31:16] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [15:0] RESERVED Reserved. [31:16] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] 4 0x4 0-3 CR%s Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] EMR External Match Register. The EMR controls the match function and the external match pins 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. [2:2] EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 238 shows the encoding of these bits. [5:4] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT0 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT1 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bi_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT2 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bi_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. Table 238 shows the encoding of these bits. [11:10] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT3 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bi_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING_EDGE Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING_EDGE Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTH_EDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 to 0x3 are reserved. [3:2] ENUM CT16BN_CAP0 CT16Bn_CAP0 0x0 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SELCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CAP0_ Rising Edge of CAP0 clears the timer (if bit 4 is set) 0x0 FALLING_EDGE_OF_CAP0 Falling Edge of CAP0 clears the timer (if bit 4 is set) 0x1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT16Bi_MAT0 is controlled by EM0. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT16Bi_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT16Bi_MAT01 is controlled by EM1. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT16Bi_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT16Bi_MAT2 is controlled by EM2. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT16Bi_MAT2. 1 PWMEN3 PWM mode enable for channel3. [3:3] ENUM EM3 CT16Bi_MAT3 is controlled by EM3. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT16Bi_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT16B1 0x40010000 0 0xFFF registers CT16B1 17 CT32B0 32-bit counter/timers CT32B0/1 CT32B0 0x40014000 0 0xFFF registers CT32B0 18 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] CR2INT Interrupt flag for capture channel 2 event. [6:6] CR3INT Interrupt flag for capture channel 3 event. [7:7] RESERVED Reserved [31:8] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING_ Do nothing. 0 THE_TIMER_COUNTER_AN The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescaler value. [31:0] PC Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP1RE Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. [3:3] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP1FE Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. [4:4] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 CAP1I Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt. [5:5] ENUM ENABLED_ Enabled. 1 DISABLED_ Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] 4 0x4 0-3 CR%s Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved. [3:2] ENUM CT32BN_CAP0 CT32Bn_CAP0 0x0 CT32BN_CAP1 CT32Bn_CAP1 0x1 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SElCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CAP0_ Rising Edge of CAP0 clears the timer (if bit 4 is set) 0x0 FALLING_EDGE_OF_CAP0 Falling Edge of CAP0 clears the timer (if bit 4 is set) 0x1 RISING_EDGE_OF_CAP1_ Rising Edge of CAP1 clears the timer (if bit 4 is set) 0x2 FALLING_EDGE_OF_CAP1 Falling Edge of CAP1 clears the timer (if bit 4 is set) 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT32Bi_MAT0 is controlled by EM0. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT32Bi_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT32Bi_MAT01 is controlled by EM1. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT32Bi_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT32Bi_MAT2 is controlled by EM2. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT32Bi_MAT2. 1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] ENUM EM3 CT32Bi_MAT3 is controlled by EM3. 0 PWM_MODE_IS_ENABLED_ PWM mode is enabled for CT132Bi_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT32B1 0x40018000 0 0xFFF registers CT32B1 19 ADC ADC ADC 0x4001C000 0 0xFFF registers ADC 24 CR A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. 0x000 read-write 0 0xFFFFFFFF SEL Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are 0 (as after Reset) channel 0 is selected automatically. [7:0] CLKDIV The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [15:8] BURST Burst mode [16:16] ENUM SOFTWARE_CONTROLLED_ Software-controlled mode: Conversions are software-controlled and require 11 clocks. 0 HARDWARE_SCAN_MODE_ Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. If bit 20 in this register is set (single-burst mode), hardware clears this bit automatically after one set of conversions on all of the selected channels. 1 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). [19:17] ENUM 11_CLOCKS 11 clocks / 10 bits 0x0 10_CLOCKS 10 clocks / 9 bits 0x1 9_CLOCKS 9 clocks / 8 bits 0x2 8_CLOCKS 8 clocks / 7 bits 0x3 7_CLOCKS 7 clocks / 6 bits 0x4 6_CLOCK 6 clocks / 5 bits 0x5 5_CLOCKS 5 clocks / 4 bits 0x6 4_CLOCKS 4 clocks / 3 bits 0x7 SINGLEBURST Single-burst mode [20:20] ENUM CONTINUOUS_BURST Continuous. Burst mode can only be terminated via a software write to clear bit 16 in this register. 0 SINGLE_BURST Single-burst. When the burst mode is selected by writing a 1 to bit 16 in this register, the ADC cycles through a single set of conversions on the selection of channels specified in the SEL field. Once the conversion has been completed on each selected channel, bit 16 is automatically cleared and the conversions stop until a new trigger event occurs. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [22:21] START When the BURST bit is 0, these bits control whether/when an A/D conversion is started. All other values are reserved. [26:23] ENUM NO_START_THIS_VALUE No start (this value should be used when clearing PDN to 0). 0x0 START_CONVERSION_NOW Start conversion now. 0x2 START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on ATRG0. 0x4 START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on the analog comparator output. 0x5 START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on ATRG1. 0x6 START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. 0x8 START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. 0xA START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. 0xC START_CONVERSION_WHE Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. 0xE EDGE This bit is significant only when the START field contains 0100-1110. In these cases: [27:27] ENUM START_CONVERSION_ON_ Start conversion on a rising edge on the selected signal. 0 START_CONVERSION_ON_ Start conversion on a falling edge on the selected signal. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:28] GDR A/D Global Data Register. Contains the result of the most recent A/D conversion. 0x004 read-only 0 0x00000000 RESERVED Reserved. These bits always read as zeroes. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF. [15:6] RESERVED Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking, for at least 256 values without overflow into the CHN field. [23:16] CHN These bits contain the channel from which the LS bits were converted. [26:24] RESERVED Reserved. These bits always read as zeroes. [29:27] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits. In non-FIFO operation, this bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. [31:31] SEL A/D Select Register. Selects between external pins and internal sources. 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved. Always write zeroes to these bits. [9:0] AD5SEL This field selects the source signal for channel 5. [11:10] ENUM AD5_PIN AD5 pin 0x0 NO_CONNECTION_OR_LOA No connection or load 0x1 CORE_VOLTAGE_REGULAT Core voltage regulator output (1.2 to 1.8V) 0x2 RESERVED_DO_NOT_PRO Reserved. Do not program this value. 0x3 AD6SEL This field selects the source signal for channel 6. [13:12] ENUM AD6_PIN AD6 pin 0x0 NO_CONNECTION_OR_LOA No connection or load 0x1 INTERNAL_VOLTAGE_REF Internal voltage reference 0x2 RESERVED_DO_NOT_PRO Reserved. Do not program this value. 0x3 AD7SEL This field selects the source signal for channel 7. [15:14] ENUM AD7_PIN AD7 pin 0x0 NO_CONNECTION_OR_LOA No connection or load 0x1 TEMPERATURE_SENSOR Temperature sensor 0x2 RESERVED_DO_NOT_PRO Reserved. Do not program this value. 0x3 RESERVED Reserved. Always write zeroes to these bits. [31:16] STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. 0x030 read-only 0 0xFFFFFFFF DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel. [7:0] OVERRUN These bits mirror the OVERRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. [15:8] ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. [16:16] RESERVED Reserved. Always 0. [31:17] INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0x00C read-write 0x00000100 0xFFFFFFFF ADINTEN These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. [7:0] ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. [8:8] RESERVED Reserved. Always 0. [31:9] 8 0x4 0-7 DR%s A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0 0x010 read-only 0 0x00000000 RESERVED Reserved. These bits always read as zeroes. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. [15:6] RESERVED Reserved. These bits always read as zeroes. They allow accumulation of successive A/D values without AND-masking for at least 256 values without overflow into the CHN field. [29:16] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits.This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. [31:31] DAC DAC DAC 0x40024000 0 0xFFF registers DAC 11 CR D/A control register 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:0] VALUE After the selected settling time after a conversion begins, the voltage on the AOUT pin (with respect to VSS) is VALUE x (V DD/1024). [15:6] BIAS Settling time [16:16] ENUM FAST The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. 0 SLOW The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. 1 TRIG The value written to this field determines whether conversion begins immediately after this register is written, or whether conversion is delayed until a selected event occurs. [19:17] ENUM IMMEDIATE Conversion begins when this register is written, and AOUT begins to change to the new voltage immediately. For all other values in this field, AOUT remains at its previous voltage until the selected event has occurred. 0x0 COMPLEVELOUT Conversion is triggered by the selected edge(s) on the analog comparator (level) output 0x1 ATRG0EDGE Conversion is triggered by the selected edge(s) on ATRG0. 0x2 ATRG1EDGE Conversion is triggered by the selected edge(s) on ATRG1. 0x3 CT32B1_MAT0EDGE Conversion is triggered by the selected edge(s) on CT32B1_MAT0 [2]. 0x4 CT32B1_MAT1EDGE Conversion is triggered by the selected edge(s) on CT32B1_MAT1[2]. 0x5 CT16B1_MAT0EDGE Conversion is triggered by the selected edge(s) on CT16B1_MAT0[2]. 0x6 CT16B1_MAT1EDGE Conversion is triggered by the selected edge(s) on CT16B1_MAT1[2]. 0x7 RESERVED Reserved. [20:20] EDGESEL For non-zero values of TRIG, this field selects when the conversion is triggered: [22:21] ENUM FALLING Falling edges 0x0 RISINGs Rising edges 0x1 DUALEDGE Both edges 0x2 DUALEDGE Both edges 0x3 TRIGERD If the TRIG field (above) is non-zero, this bit is set when a conversion is triggered, and is cleared by any write to this register. [23:23] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] RESERVED Reserved 0x004 read-write 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:0] CMP Comparator Comparator 0x40028000 0x0 0xFFF registers CMP 10 CTL Comparator control register 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved. Write as 0. [2:0] EDGESEL This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges [4:3] ENUM FALLING Falling edges 0x0 RISING Rising edges 0x1 DUALEDGE Both edges 0x2 DUALEDGE Both edges 0x3 RESERVED Reserved. Write as 0. [5:5] COMPSA Comarator output control [6:6] ENUM DIRECT Uses the comparator output directly. 0 SYNCH Synchronizes the comparator output to the bus clock for output to other modules. 1 RESERVED Reserved. Write as 0. [7:7] COMP_VP_SEL Selects positive voltage input [10:8] ENUM VLADOUT voltage ladder output 0x0 ACMPI1 ACMPI1 0x1 ACMPI2 ACMPI2 0x2 ACMPI3 ACMPI3 0x3 ACMPI4 ACMPI4 0x4 ACMPI5 ACMPI5 0x5 INTVOLTAGEREF internal reference voltage 0x6 TEMPSENSOR temperature sensor 0x7 COMP_VM_SEL Selects negative voltage input [13:11] ENUM VLADDOUT voltage ladder output 0x0 ACMPI1 ACMPI1 0x1 ACMPI2 ACMPI2 0x2 ACMPI3 ACMPI3 0x3 ACMPI4 ACMPI4 0x4 ACMPI5 ACMPI5 0x5 INTVOLTAGEREF internal reference voltage 0x6 RESERVED Reserved. Write as 0. [19:14] EDGECLR Interrupt clear bit. Writing a 1 to this bit clears the COMPEDGE bit (bit 23 below) and thus negates the interrupt request. [20:20] COMPSTAT Comparator status. This bit reflects the state of the comparator output. [21:21] RESERVED Reserved. Write as 0. [22:22] COMPEDGE Comparator edge-detect status. [23:23] RESERVED Reserved. Write as 0. [24:24] HYS Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output. [26:25] ENUM NOHYSTERESIS None (the output will switch as the voltages cross) 0x0 HYS5MV 5 mV 0x1 HSY10MV 10 mV 0x2 HSY20MV 20 mV 0x3 RESERVED Reserved [31:27] LAD Voltage ladder register 0x004 read-write 0 0xFFFFFFFF LADEN Voltage ladder enable [0:0] LADSEL Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 Vref/31 00010 = 2 Vref/31 ... 11111 = Vref [5:1] LADREF Selects the reference voltage for the voltage ladder [6:6] ENUM VDDPIN VDD pin 0 VDDCMPPIN VDDCMP pin 1 RESERVED Unused [31:7] FMC Flash controller FLASHCTRL 0x4003C000 0x0 0xFFF registers FMC 27 EEMSSTART EEPROM BIST start address register 0x09C read-write 0x0 0xFFFFFFFF STARTA BIST start address: Bit 0 is fixed zero since only even addresses are allowed. [13:0] RESERVED Reserved [31:14] EEMSSTOP EEPROM BIST stop address register 0x0A0 read-write 0x0 0xFFFFFFFF STOPA BIST stop address: Bit 0 is fixed zero since only even addresses are allowed. [13:0] RESERVED Reserved [29:14] DEVSEL BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same. [30:30] STRTBIST BIST start bit Setting this bit will start the BIST. This bit is self-clearing. [31:31] EEMSSIG EEPROM 24-bit BIST signature register 0x0A4 read-only 0x0 0xFFFFFFFF DATA_SIG BIST 16-bit signature calculated from only the data bytes [15:0] PARITY_SIG BIST 16-bit signature calculated from only the parity bits of the data bytes [31:16] FLASHCFG Flash memory access time configuration register 0x010 read-write 0 0x00000000 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. [1:0] ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x0 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). 0x1 3_SYSTEM_CLOCKS_FLAS 3 system clocks flash access time (for system clock frequencies of up to 50 MHz). 0x2 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. [31:2] FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). [16:0] SIG_START Start control bit for signature generation. [17:17] ENUM SIGNATURE_GENERATION Signature generation is stopped 0 INITIATE_SIGNATURE_G Initiate signature generation 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:18] FMSW0 Word 0 [31:0] 0x02C read-only 0 0x00000000 SW0_31_0 Word 0 of 128-bit signature (bits 31 to 0). [31:0] FMSW1 Word 1 [63:32] 0x030 read-only 0 0x00000000 SW1_63_32 Word 1 of 128-bit signature (bits 63 to 32). [31:0] FMSW2 Word 2 [95:64] 0x034 read-only 0 0x00000000 SW2_95_64 Word 2 of 128-bit signature (bits 95 to 64). [31:0] FMSW3 Word 3 [127:96] 0x038 read-only 0 0x00000000 SW3_127_96 Word 3 of 128-bit signature (bits 127 to 96). [31:0] FMSTAT Signature generation status register 0xFE0 read-only 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] FMSTATCLR Signature generation status clear register 0xFE8 write-only 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] SSP0 SSP/SPI SSP0 0x40040000 0 0xFFF registers SSP0 20 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 RESERVED This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM LOW SPI controller maintains the bus clock low between frames. 0 HIGH SPI controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRSTCLOCK SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOCK SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] ENUM DURING_NORMAL_OPERAT During normal operation. 0 SERIAL_INPUT_IS_TAKE Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SPI Enable. [1:1] ENUM DISABLED The SPI controller is disabled. 0 ENABLED The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] ENUM MASTER The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] IOCON IOCON block IOCON 0x40044000 0x0 0xFFF registers RESET_PIO0_0 I/O configuration register for pin RESET/PIO0_0 0x0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin RESET/PIO0_0 [2:0] ENUM RESET External reset input with fixed 20 ns glitch filter: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. 0x0 PIO0_0 General purpose digital input/output pin. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_1 I/O configuration register for pin PIO0_1/RXD/CLKOUT/ CT32B0_MAT2/SSEL0/ CLKIN 0x4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_1/RXD/CLKOUT/ CT32B0_MAT2/SSEL0/ CLKIN [2:0] ENUM PIO0_1 General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. 0x0 RXD Receiver data input for USART. 0x1 CLKOUT Clock output. 0x2 CT32B0_MAT2 Match output 2 for 32-bit timer 0. 0x3 SSEL0 Slave Select for SSP0. 0x4 CLKIN External clock input. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_2 I/O configuration register for pin PIO0_2/SCL/ACMP_O/ TCK/SWCLK/ CT16B0_CAP0 0x8 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin PIO0_2/SCL/ACMP_O/ TCK/SWCLK/ CT16B0_CAP0 [2:0] ENUM PIO0_2 General purpose digital input/output pin. High-current sink (20 mA) or standard-current sink (4 mA) programmable; true open-drain for all pin functions. Input glitch filter (50 ns) capable. 0x0 SCL I2C-bus clock (true open-drain) input/output. Input glitch filter (50 ns) capable. 0x1 ACMP_O Analog comparator output. 0x2 TCK_SWCLK Serial Wire Debug Clock (secondary for LQFP and HVQFN packages). Input glitch filter (50 ns) capable. For the WLCSP20 package only, this pin is configured to the SWCLK function by the boot loader after reset. 0x3 CT16B0_CAP0 Capture input 0 for 16-bit timer 0.Input glitch filter (50 ns) capable. 0x4 RESERVED Reserved. [7:3] HS Controls glitch filter and slew rate. [8:8] ENUM ENABLED Enabled. 0x0 DISABLED Disabled. 0x1 HIDRIVE Controls sink current. [9:9] ENUM STANDARD Standard; 4 mA sink current. 0x0 HIGH High; 20 mA sink current. 0x1 RESERVED Reserved. [31:10] PIO0_3 I/O configuration register for pin PIO0_3/SDA/ACMP_O/ SWDIO/CT16B1_CAP0 0xC read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function for pin PIO0_3/SDA/ACMP_O/ SWDIO/CT16B1_CAP0 [2:0] ENUM PIO0_3 General purpose digital input/output pin. High-current sink (20 mA) or standard-current sink (4 mA) programmable; true open-drain for all pin functions. Input glitch filter (50 ns) capable. 0x0 SDA I2C-bus data (true open-drain) input/output. Input glitch filter (50 ns) capable. 0x1 ACMP_O Analog comparator output. 0x2 SWDIO Serial Wire Debug I/O (secondary for LQFP and HVQFN packages). Input glitch filter (50 ns) capable. For the WLCSP20 package only, this pin is configured to the SWDIO function by the boot loader after reset. 0x3 CT16B1_CAP0 Capture input 0 for 16-bit timer 1. Input glitch filter (50 ns) capable. 0x4 RESERVED Reserved. [7:3] HS Controls glitch filter and slew rate. [8:8] ENUM ENABLED Enabled. 0x0 DISABLED Disabled. 0x1 HIDRIVE Controls sink current. [9:9] ENUM STANDARD Standard; 4 mA sink current. 0x0 HIGH High; 20 mA sink current. 0x1 RESERVED Reserved. [31:10] PIO0_4 I/O configuration register for pin PIO0_4/R/AOUT/ CT16B0_MAT1/MOSI0 0x10 read-write 0xFFFFFFFF FUNC Selects pin function for pin PIO0_4/R/AOUT/ CT16B0_MAT1/MOSI0 [2:0] ENUM PIO0_4 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 R Reserved. 0x1 AOUT D/A converter output. 0x2 CT16B0_MAT1 Match output 1 for 16-bit timer 0. 0x3 MOSI0 Master Out Slave In for SSP0. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TCK_SWCLK_PIO0_5 I/O configuration register for pin TCK/SWCLK/PIO0_5/ R/CT16B0_MAT2/ SCK0 0x14 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin TCK/SWCLK/PIO0_5/ R/CT16B0_MAT2/ SCK0 [2:0] ENUM TCK_SWCLK Test clock TCK for JTAG interface and primary (default) Serial Wire Debug Clock. Input glitch filter (10 ns) capable. 0x0 PIO0_5 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 R Reserved. 0x2 CT16B0_MAT2 Match output 2 for 16-bit timer 0. 0x3 SCK0 Serial clock for SSP0. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TDI_PIO0_6 I/O configuration register for pin TDI/PIO0_6/AD0/ CT32B0_MAT3/MISO0 0x18 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin TDI/PIO0_6/AD0/ CT32B0_MAT3/MISO0 [2:0] ENUM TDI Test Data In for JTAG interface. Input glitch filter (10 ns) capable. 0x0 PIO0_6 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 AD0 A/D converter input 0. 0x2 CT32B0_MAT3 Match output 3 for 32-bit timer 0. 0x3 MISO0 Master In Slave Out for SSP0. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TMS_PIO0_7 I/O configuration register for pin TMS/PIO0_7/AD1/ CT32B1_CAP0/ CT16B0_MAT0 0x1C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin TMS/PIO0_7/AD1/ CT32B1_CAP0/ CT16B0_MAT0 [2:0] ENUM TMS Test Mode Select for JTAG interface. Input glitch filter (10 ns) capable. 0x0 PIO0_7 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 AD1 A/D converter input 1. 0x2 CT32B1_CAP0 Capture input 0 for 32-bit timer 1. Input glitch filter (10 ns) capable. 0x3 CT16B0_MAT0 Match output 2 for 16-bit timer 0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TDO_PIO0_8 I/O configuration register for pin TDO/PIO0_8/AD2/ CT32B1_MAT0/SCK1 0x20 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin TDO/PIO0_8/AD2/ CT32B1_MAT0/SCK1 [2:0] ENUM TDO Test Data Out for JTAG interface. 0x0 PIO0_8 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 AD2 A/D converter input 2. 0x2 CT32B1_MAT0 Match output 0 for 32-bit timer 1. 0x3 SCK1 Serial clock for SSP1. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TRST_PIO0_9 I/O configuration register for pin TRST/PIO0_9/AD3/CT32B1_MAT1/CT16B0_MAT1/CTS 0x24 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin TRST/PIO0_9/AD3/CT32B1_MAT1/CT16B0_MAT1/CTS [2:0] ENUM TRST Test Reset for JTAG interface. Input glitch filter (10 ns) capable. 0x0 PIO0_9 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 AD3 A/D converter, input 3. 0x2 CT32B1_MAT1 Match output 1 for 32-bit timer 1. 0x3 CT16B0_MAT1 Match output 1 for 16-bit timer 0. 0x4 CTS Clear To Send input for USART. Input glitch filter (10 ns) capable. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] SWDIO_PIO0_10 I/O configuration register for pin SWDIO/PIO0_10/AD4/ CT32B1_MAT2/ CT16B0_MAT2/RTS 0x28 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin SWDIO/PIO0_10/AD4/ CT32B1_MAT2/ CT16B0_MAT2/RTS [2:0] ENUM SWDIO Primary (default) Serial Wire Debug I/O for the LQFP48 and HVQFN33 packages. For the WLCSP20 package, use PIO0_3. Input glitch filter (10 ns) capable. 0x0 PIO0_10 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x1 AD4 A/D converter, input 4. 0x2 CT32B1_MAT2 Match output 2 for 32-bit timer 1. 0x3 CT16B0_MAT2 Match output 2 for 16-bit timer 0. 0x4 RTS Request To Send output for USART. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_11 I/O configuration register for pin PIO0_11/SCLK/ AD5/CT32B1_MAT3/ CT32B0_CAP0 0x2C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_11/SCLK/ AD5/CT32B1_MAT3/ CT32B0_CAP0 [2:0] ENUM PIO0_11 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 SCLK Serial clock for USART. Input glitch filter (10 ns) capable. 0x1 AD5 A/D converter, input 5. 0x2 CT32B1_MAT3 Match output 3 for 32-bit timer 1. 0x3 CT32B0_CAP0 Capture input 0 for 32-bit timer 0. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_12 I/O configuration register for pin PIO0_12/RXD/ ACMP_O/ CT32B0_MAT0/SCL/ CLKIN 0x30 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_12/RXD/ ACMP_O/ CT32B0_MAT0/SCL/ CLKIN [2:0] ENUM PIO0_12 General purpose digital input/output pin. 0x0 RXD Receiver data input for USART. This pin is used for ISP communication. 0x1 ACMP_O Analog comparator output. 0x2 CT32B0_MAT0 Match output 0 for 32-bit timer 0. 0x3 SCL I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. 0x4 CLKIN External clock input. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_13 I/O configuration register for pin PIO0_13/TXD/ ACMP_I2/ CT32B0_MAT1/SDA 0x34 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_13/TXD/ ACMP_I2/ CT32B0_MAT1/SDA [2:0] ENUM PIO0_13 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 TXD Transmitter data output for USART. This pin is used for ISP communication. 0x1 ACMP_I2 Analog comparator input 2. 0x2 CT32B0_MAT1 Match output 1 for 32-bit timer 0. 0x3 SDA I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_14 I/O configuration register for pin PIO0_14/MISO1/AD6/CT32B0_CAP1/CT16B1_MAT1/VDDCMP 0x38 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_14/MISO1/AD6/CT32B0_CAP1/CT16B1_MAT1/xxxCMP [2:0] ENUM PIO0_14 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 MISO1 Master In Slave Out for SSP1. Input glitch filter (10 ns) capable. 0x1 AD6 A/D converter, input 6. 0x2 CT32B0_CAP1 Capture input 1 for 32-bit timer 0. Input glitch filter (10 ns) capable. 0x3 CT16B1_MAT1 Match output 1 for 16-bit timer 1. 0x4 VDDCMP Analog comparator alternate reference voltage. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_15 I/O configuration register for pin PIO0_15/TXD/AD7/ CT32B0_CAP2/SDA 0x3C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_15/TXD/AD7/ CT32B0_CAP2/SDA [2:0] ENUM PIO0_15 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 TXD Transmitter data output for USART. 0x1 AD7 A/D converter, input 7. 0x2 CT32B0_CAP2 Capture input 2 for 32-bit timer 0. Input glitch filter (10 ns) capable. 0x3 SDA I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_16 I/O configuration register for pin PIO0_16/ ATRG0/ACMP_I3/ CT16B0_CAP1/SCL 0x40 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_16/ ATRG0/ACMP_I3/ CT16B0_CAP1/SCL [2:0] ENUM PIO0_16 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 ATRG0 Conversion trigger 0 for ADC or DAC. Input glitch filter (10 ns) capable. 0x1 ACMP_I3 Analog comparator input 3. 0x2 CT16B0_CAP1 Capture input 1 for 16-bit timer 0. Input glitch filter (10 ns) capable. 0x3 SCL I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_17 I/O configuration register for pin PIO0_17/ ATRG1/ACMP_I4/ CT16B0_CAP2/ CT16B0_MAT0 0x44 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_17/ ATRG1/ACMP_I4/ CT16B0_CAP2/ CT16B0_MAT0 [2:0] ENUM PIO0_17 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 ATRG1 Conversion trigger 1 for ADC or DAC. Input glitch filter (10 ns) capable. 0x1 ACMP_I4 Analog comparator input 4. 0x2 CT16B0_CAP2 Capture input 2 for 16-bit timer 0. Input glitch filter (10 ns) capable. 0x3 CT16B0_MAT0 Match output 0 for 16-bit timer 0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_18 I/O configuration register for pin PIO0_18/R/SSEL0/ CT16B0_CAP0/ CT16B1_CAP1 0x48 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_18/R/SSEL0/ CT16B0_CAP0/ CT16B1_CAP1 [2:0] ENUM PIO0_18 General purpose digital input/output pin. 0x0 R Reserved. 0x1 SSEL0 Slave Select for SSP0. 0x2 CT16B0_CAP0 Capture input 0 for 16-bit timer 0. 0x3 CT16B1_CAP1 Capture input 1 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_19 I/O configuration register for pin PIO0_19/CLKIN/ CLKOUT/ MOSI0/CT16B1_MAT0 0x4C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_19/CLKIN/ CLKOUT/ MOSI0/CT16B1_MAT0 [2:0] ENUM PIO0_19 General purpose digital input/output pin. 0x0 CLKIN External clock input. 0x1 CLKOUT Clock output. 0x2 MOSI0 Master Out Slave In for SSP0. 0x3 CT16B1_MAT0 Match output 0 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_20 I/O configuration register for pin PIO0_20/R/SCK0/ CT32B1_CAP0/ CT16B1_MAT2 0x50 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_20/R/SCK0/ CT32B1_CAP0/ CT16B1_MAT2 [2:0] ENUM PIO0_20 General purpose digital input/output pin. 0x0 R Reserved. 0x1 SCK0 Serial clock for SSP0. 0x2 CT32B1_CAP0 Capture input 0 for 32-bit timer 1. 0x3 CT16B1_MAT2 Match output 2 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_21 I/O configuration register for pin PIO0_21/CTS/ ACMP_O/ CT32B1_CAP1/SCLK 0x54 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_21/CTS/ ACMP_O/ CT32B1_CAP1/SCLK [2:0] ENUM PIO0_21 General purpose digital input/output pin. If configured as output, this pin is a high-current source output driver (20 mA). 0x0 CTS Clear To Send input for USART. 0x1 ACMP_O Analog comparator output. 0x2 CT32B1_CAP1 Capture input 1 for 32-bit timer 1. 0x3 SCLK Serial clock for USART. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_22 I/O configuration register for pin PIO0_22/MISO0/ ACMP_I5/ CT32B1_MAT2/ CT32B1_CAP2 0x58 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_22/MISO0/ ACMP_I5/ CT32B1_MAT2/ CT32B1_CAP2 [2:0] ENUM PIO0_22 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 MISO0 Master In Slave Out for SSP0. Input glitch filter (10 ns) capable. 0x1 ACMP_I5 Analog comparator input 5. 0x2 CT32B1_MAT2 Match output 2 for 32-bit timer 1. 0x3 CT32B1_CAP2 Capture input 2 for 32-bit timer 1. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_23 I/O configuration register for pin PIO0_23/RTS/ ACMP_O/ CT32B0_CAP0/SCLK 0x5C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_23/RTS/ ACMP_O/ CT32B0_CAP0/SCLK [2:0] ENUM PIO0_23 General purpose digital input/output pin. 0x0 RTS Request To Send output for USART. 0x1 ACMP_O Analog comparator output. 0x2 CT32B0_CAP0 Capture input 0 for 32-bit timer 0. 0x3 SCLK Serial clock for USART. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_24 I/O configuration register for pin PIO0_24/SCL/CLKIN/ CT16B1_CAP0 0x60 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_24/SCL/CLKIN/ CT16B1_CAP0 [2:0] ENUM PIO0_24 General purpose digital input/output pin. 0x0 SCL I2C-bus clock input/output. This is not an I2C-bus open-drain pin[8]. 0x1 CLKIN External clock input. 0x2 CT16B1_CAP0 Capture input 0 for 16-bit timer 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_25 I/O configuration register for pin PIO0_25/SDA/SSEL1/ CT16B1_MAT0 0x64 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_25/SDA/SSEL1/ CT16B1_MAT0 [2:0] ENUM PIO0_25 General purpose digital input/output pin. 0x0 SDA I2C-bus data input/output. This is not an I2C-bus open-drain pin[8]. 0x1 SSEL1 Slave Select for SSP1. 0x2 CT16B1_MAT0 Match output 0 for 16-bit timer 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_26 I/O configuration register for pin PIO0_26/TXD/MISO1/ CT16B1_CAP1/ CT32B0_CAP2 0x68 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_26/TXD/MISO1/ CT16B1_CAP1/ CT32B0_CAP2 [2:0] ENUM PIO0_26 General purpose digital input/output pin. 0x0 TXD Transmitter data output for USART. 0x1 MISO1 Master In Slave Out for SSP1. 0x2 CT16B1_CAP1 Capture input 1 for 16-bit timer 1. 0x3 CT32B0_CAP2 Capture input 2 for 32-bit timer 0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_27 I/O configuration register for pin PIO0_27/MOSI1/ ACMP_I1/ CT32B1_MAT1/ CT16B1_CAP2 0x6C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_27/MOSI1/ ACMP_I1/ CT32B1_MAT1/ CT16B1_CAP2 [2:0] ENUM PIO0_27 General purpose digital input/output pin. Input glitch filter (10 ns) capable. 0x0 MOSI1 Master Out Slave In for SSP1. Input glitch filter (10 ns) capable. 0x1 ACMP_I1 Analog comparator input 1. 0x2 CT32B1_MAT1 Match output 1 for 32-bit timer 1. 0x3 CT16B1_CAP2 Capture input 2 for 16-bit timer 1. Input glitch filter (10 ns) capable. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG_INPUT_MODE_ Analog input mode. 0 DIGITAL_FUNCTIONAL_M Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM FILTER_DISABLED_ Filter disabled. 0 FILTER_ENABLED_ Filter enabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_28 I/O configuration register for pin PIO0_28/DTR/SSEL1/ CT32B0_CAP0 0x70 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_28/DTR/SSEL1/ CT32B0_CAP0 [2:0] ENUM PIO0_28 General purpose digital input/output pin. 0x0 DTR Data Terminal Ready output for USART. 0x1 SSEL1 Slave Select for SSP1. 0x2 CT32B0_CAP0 Capture input 0 for 32-bit timer 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_29 I/O configuration register for pin PIO0_29/DSR/SCK1/ CT32B0_CAP1 0x74 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_29/DSR/SCK1/ CT32B0_CAP1 [2:0] ENUM PIO0_29 General purpose digital input/output pin. 0x0 DSR Data Set Ready input for USART. 0x1 SCK1 Serial clock for SSP1. 0x2 CT32B0_CAP1 Capture input 1 for 32-bit timer 0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_30 I/O configuration register for pin PIO0_30/RI/MOSI1/ CT32B0_MAT0/ CT16B0_CAP0 0x78 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_30/RI/MOSI1/ CT32B0_MAT0/ CT16B0_CAP0 [2:0] ENUM PIO0_30 General purpose digital input/output pin. 0x0 RI Ring Indicator input for USART. 0x1 MOSI1 Master Out Slave In for SSP1. 0x2 CT32B0_MAT0 Match output 0 for 32-bit timer 0. 0x3 CT16B0_CAP0 Capture input 0 for 16-bit timer 0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO0_31 I/O configuration register for pin PIO0_31/RI/MOSI1/ CT32B1_MAT0/ CT16B1_CAP1 0x7C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO0_31/RI/MOSI1/ CT32B1_MAT0/ CT16B1_CAP1 [2:0] ENUM PIO0_31 General purpose digital input/output pin. 0x0 RI Ring Indicator input for USART. 0x1 MOSI1 Master Out Slave In for SSP1. 0x2 CT32B1_MAT0 Match output 0 for 32-bit timer 1. 0x3 CT16B1_CAP1 Capture input 1 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_0 I/O configuration register for pin PIO1_0/DCD/SCK0/ CT32B1_MAT3/ CT16B0_MAT1 0x80 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_0/DCD/SCK0/ CT32B1_MAT3/ CT16B0_MAT1 [2:0] ENUM PIO1_0 General purpose digital input/output pin. 0x0 DCD Data Carrier Detect input for USART. 0x1 SCK0 Serial clock for SSP0. 0x2 CT32B1_MAT3 Match output 3 for 32-bit timer 1. 0x3 CT16B0_MAT1 Match output 1 for 16-bit timer 0. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_1 I/O configuration register for pin PIO1_1/DTR/SSEL0/ CT32B1_MAT3/ CT16B1_MAT0 0x84 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_1/DTR/SSEL0/ CT32B1_MAT3/ CT16B1_MAT0 [2:0] ENUM PIO1_1 General purpose digital input/output pin. 0x0 DTR Data Terminal Ready output for USART. 0x1 SSEL0 Slave Select for SSP0. 0x2 CT32B1_MAT3 Match output 3 for 32-bit timer 1. 0x3 CT16B1_MAT0 Match output 0 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_2 I/O configuration register for pin PIO1_2/DSR/MISO0/ CT16B1_MAT2/ CT16B1_MAT1 0x88 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_2/DSR/MISO0/ CT16B1_MAT2/ CT16B1_MAT1 [2:0] ENUM PIO1_2 General purpose digital input/output pin. 0x0 DSR Data Set Ready input for USART. 0x1 MISO0 Master In Slave Out for SSP0. 0x2 CT16B1_MAT2 Match output 2 for 16-bit timer 1. 0x3 CT16B1_MAT1 Match output 1 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_3 I/O configuration register for pin PIO1_3/RI/MOSI0/ CT16B1_CAP0 0x8C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_3/RI/MOSI0/ CT16B1_CAP0 [2:0] ENUM PIO1_3 General purpose digital input/output pin. 0x0 RI Ring Indicator input for USART. 0x1 MOSI0 Master Out Slave In for SSP0. 0x2 CT16B1_CAP0 Capture input 0 for 16-bit timer 1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_4 I/O configuration register for pin PIO1_4/RXD/SSEL1/ CT32B0_MAT1/ CT32B1_CAP0/ CT16B0_CAP1 0x90 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_4/RXD/SSEL1/ CT32B0_MAT1/ CT32B1_CAP0/ CT16B0_CAP1 [2:0] ENUM PIO1_4 General purpose digital input/output pin. 0x0 RXD Receiver data input for USART. 0x1 SSEL1 Slave Select for SSP1. 0x2 CT32B0_MAT1 Match output 1 for 32-bit timer 0. 0x3 CT32B1_CAP0 Capture input 0 for 32-bit timer 1. 0x4 CT16B0_CAP1 Capture input 1 for 16-bit timer 0. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_5 I/O configuration register for pin PIO1_5/TXD/SCK1/ CT32B0_MAT2/ CT32B1_CAP1/ CT16B0_CAP2 0x94 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_5/TXD/SCK1/ CT32B0_MAT2/ CT32B1_CAP1/ CT16B0_CAP2 [2:0] ENUM PIO1_5 General purpose digital input/output pin. 0x0 TXD Transmitter data output for USART. 0x1 SCK1 Serial clock for SSP1. 0x2 CT32B0_MAT2 Match output 2 for 32-bit timer 0. 0x3 CT32B1_CAP1 Capture input 1 for 32-bit timer 1. 0x4 CT16B0_CAP2 Capture input 2 for 16-bit timer 0. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_6 I/O configuration register for pin PIO1_6/RTS/MOSI1/ CT32B0_MAT3/ CT32B1_CAP2/ CT16B0_MAT0 0x98 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_6/RTS/MOSI1/ CT32B0_MAT3/ CT32B1_CAP2/ CT16B0_MAT0 [2:0] ENUM PIO1_6 General purpose digital input/output pin. 0x0 RTS Request To Send output for USART. 0x1 MOSI1 Master Out Slave In for SSP1. 0x2 CT32B0_MAT3 Match output 3 for 32-bit timer 0. 0x3 CT32B1_CAP2 Capture input 2 for 32-bit timer 1. 0x4 CT16B0_MAT0 Match output 0 for 16-bit timer 0. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_7 I/O configuration register for pin PIO1_7/CTS/MOSI0/ CT32B1_MAT1/ CT16B0_MAT2/ CT16B1_CAP2 0x9C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_7/CTS/MOSI0/ CT32B1_MAT1/ CT16B0_MAT2/ CT16B1_CAP2 [2:0] ENUM PIO1_7 General purpose digital input/output pin. 0x0 CTS Clear To Send input for USART. 0x1 MOSI0 Master Out Slave In for SSP0. 0x2 CT32B1_MAT1 Match output 1 for 32-bit timer 1. 0x3 CT16B0_MAT2 Match output 2 for 16-bit timer 0. 0x4 CT16B1_CAP2 Capture input 2 for 16-bit timer 1. 0x5 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_8 I/O configuration register for pin PIO1_8/RXD / MISO1/ CT32B1_MAT0/ CT16B1_MAT1 0xA0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_8/RXD / MISO1/ CT32B1_MAT0/ CT16B1_MAT1 [2:0] ENUM PIO1_8 General purpose digital input/output pin. 0x0 RXD Receiver data input for USART. 0x1 MISO1 Master In Slave Out for SSP1. 0x2 CT32B1_MAT0 Match output 0 for 32-bit timer 1. 0x3 CT16B1_MAT1 Match output 1 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_9 I/O configuration register for pin PIO1_9/DCD/R/ CT32B1_MAT2 / CT16B1_MAT2 0xA4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function for pin PIO1_9/DCD/R/ CT32B1_MAT2 / CT16B1_MAT2 [2:0] ENUM PIO1_9 General purpose digital input/output pin. 0x0 DCD Data Carrier Detect input for USART. 0x1 R Reserved. 0x2 CT32B1_MAT2 Match output 2 for 32-bit timer 1. 0x3 CT16B1_MAT2 Match output 2 for 16-bit timer 1. 0x4 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [8:7] SLEW Driver slew rate [9:9] ENUM SLOW Slow. More outputs can be switched simultaneously. 0 FAST Fast. 1 OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] SYSCON System configuration SYSCON 0x40048000 0x0 0xFFF registers BOD 26 RESERVED0 12 RESERVED1 13 RESERVED2 22 RESERVED3 23 RESERVED4 28 RESERVED5 29 RESERVED6 30 RESERVED7 31 SYSMEMREMAP System memory remap 0x0 read-write 0x02 0xFFFFFFFF MAP System memory remap [1:0] ENUM BOOT_LOADER_MODE_IN Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE_INTER User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] PRESETCTRL Peripheral reset control 0x004 read-write 0 0xFFFFFFFF SSP0_RST_N SSP0 reset control [0:0] ENUM RESETS_THE_SSP0_PERI Resets the SSP0 peripheral. 0 SSP0_RESET_DE_ASSERT SSP0 reset de-asserted. 1 I2C_RST_N I2C reset control [1:1] ENUM RESETS_THE_I2C_PERIP Resets the I2C peripheral. 0 I2C_RESET_DE_ASSERTE I2C reset de-asserted. 1 SSP1_RST_N SSP1 reset control [2:2] ENUM RESETS_THE_SSP1_PERI Resets the SSP1 peripheral. 0 SSP1_RESET_DE_ASSERT SSP1 reset de-asserted. 1 RESERVED Reserved [3:3] UART_RST_N UART reset control [4:4] ENUM RESETS_THE_UART_PERI Resets the UART peripheral. 0 UART_RESET_DE_ASSERT UART reset de-asserted. 1 CT16B0_RST_N CT16B0 reset control [5:5] ENUM RESETS_THE_CT16B0_PE Resets the CT16B0 peripheral. 0 CT16B0_RESET_DE_ASSE CT16B0 reset de-asserted. 1 CT16B1_RST_N CT16B1 reset control [6:6] ENUM RESETS_THE_CT16B1_PE Resets the CT16B1 peripheral. 0 CT16B1_RESET_DE_ASSE CT16B1 reset de-asserted. 1 CT32B0_RST_N CT32B0 reset control [7:7] ENUM RESETS_THE_CT32B0_PE Resets the CT32B0 peripheral. 0 CT32B0_RESET_DE_ASSE CT32B0 reset de-asserted. 1 CT32B1_RST_N CT32B1 reset control [8:8] ENUM RESETS_THE_CT32B1_PE Resets the CT32B1 peripheral. 0 CT32B1_RESET_DE_ASSE CT32B1 reset de-asserted. 1 ACOMP_RST_N Analog comparator reset control [9:9] ENUM RESETS_THE_ANALOG_CO Resets the Analog comparator peripheral. 0 ANALOG_COMPARATOR_RE Analog comparator reset de-asserted. 1 DAC_RST_N DAC reset control [10:10] ENUM RESETS_THE_DAC_PERIP Resets the DAC peripheral. 0 DAC_RESET_DE_ASSERTE DAC reset de-asserted. 1 ADC_RST_N ADC reset control [11:11] ENUM RESETS_THE_ADC_PERIP Resets the ADC peripheral. 0 ADC_RESET_DE_ASSERTE ADC reset de-asserted. 1 RESERVED Reserved [31:12] SYSPLLCTRL System PLL control 0x008 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] SYSPLLSTAT System PLL status 0x00C read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] SYSOSCCTRL System oscillator control 0x020 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM OSCILLATOR_IS_NOT_BY Oscillator is not bypassed. 0 BYPASS_ENABLED_PLL_ Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pins. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM 1__20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15__25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved [31:2] WDTOSCCTRL Watchdog oscillator control 0x024 read-write 0x0A0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM OPERATION_IS_UNDEFIN Operation is undefined for this value. Startup code should program a non-zero value in this field as soon after reset as possible. 0 0_6_MHZ 0.6 MHz 0x1 1_05_MHZ 1.05 MHz 0x2 1_4_MHZ 1.4 MHz 0x3 1_75_MHZ 1.75 MHz 0x4 2_1_MHZ 2.1 MHz 0x5 2_4_MHZ 2.4 MHz 0x6 2_7_MHZ 2.7 MHz 0x7 3_0_MHZ 3.0 MHz 0x8 3_25_MHZ 3.25 MHz 0x9 3_5_MHZ 3.5 MHz 0xA 3_75_MHZ 3.75 MHz 0xB 4_0_MHZ 4.0 MHz 0xC 4_2_MHZ 4.2 MHz 0xD 4_4_MHZ 4.4 MHz 0xE 4_6_MHZ 4.6 MHz 0xF RESERVED Reserved [31:9] IRCCTRL IRC oscillator control 0x028 read-write 0x0 0xFFFFFFFF TRIM Trim value [7:0] RESERVED Reserved [31:9] LFOSCCTRL LF oscillator control 0x02C read-write 0x0A0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM OPERATION_IS_UNDEFIN Operation is undefined for this value. Startup code should program a non-zero value in this field as soon after reset as possible. 0 0_6_MHZ 0.6 MHz 0x1 1_05_MHZ 1.05 MHz 0x2 1_4_MHZ 1.4 MHz 0x3 1_75_MHZ 1.75 MHz 0x4 2_1_MHZ 2.1 MHz 0x5 2_4_MHZ 2.4 MHz 0x6 2_7_MHZ 2.7 MHz 0x7 3_0_MHZ 3.0 MHz 0x8 3_25_MHZ 3.25 MHz 0x9 3_5_MHZ 3.5 MHz 0xA 3_75_MHZ 3.75 MHz 0xB 4_0_MHZ 4.0 MHz 0xC 4_2_MHZ 4.2 MHz 0xD 4_4_MHZ 4.4 MHz 0xE 4_6_MHZ 4.6 MHz 0xF RESERVED Reserved [31:9] SYSRSTSTAT System reset status register 0x030 read-write 0 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED POR detected 1 EXTRST External reset status [1:1] ENUM NO_RESET_EVENT_DETEC No RESET event detected 0 RESET_DETECTED RESET detected 1 WDT Status of the Watchdog reset [2:2] ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED WDT reset detected 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED BOD reset detected 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected 1 RESERVED Reserved [31:5] SYSPLLCLKSEL System PLL clock source select 0x040 read-write 0 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC IRC 0x0 CRYSTAL_OSCILLATOR_ Crystal Oscillator (XTAL) 0x1 CLKIN_PIN CLKIN pin 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] SYSPLLCLKUEN System PLL clock source update enable 0x044 read-write 0 0xFFFFFFFF ENA Enable system PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] MAINCLKSEL Main clock source select 0x070 read-write 0 0xFFFFFFFF SEL Clock source for main clock [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 PLL_INPUT PLL input 0x1 LF_OSCILLATOR LF Oscillator 0x2 PLL_OUTPUT PLL output 0x3 RESERVED Reserved [31:2] MAINCLKUEN Main clock source update enable 0x074 read-write 0 0xFFFFFFFF ENA Enable main clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] SYSAHBCLKDIV System clock divider 0x078 read-write 0x001 0xFFFFFFFF DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL System clock control 0x080 read-write 0x01F 0xFFFFFFFF SYS Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1. [0:0] ENUM RESERVED Reserved 0 ENABLE Enable 1 ROM Enables clock for ROM. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 RAM Enables clock for RAM. [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 FLASHREG Enables clock for flash/EEPROM register interface. [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 FLASHARRAY Enables clock for flash/EEPROM array access. [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 I2C Enables clock for I2C. [5:5] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO Enables clock for GPIO. [6:6] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B0 Enables clock for 16-bit counter/timer 0. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 CT16B1 Enables clock for 16-bit counter/timer 1. [8:8] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B0 Enables clock for 32-bit counter/timer 0. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 CT32B1 Enables clock for 32-bit counter/timer 1. [10:10] ENUM DISABLE Disable 0 ENABLE Enable 1 SSP0 Enables clock for SSP0. [11:11] ENUM DISABLE Disable 0 ENABLE Enable 1 UART Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled. [12:12] ENUM DISABLE Disable 0 ENABLE Enable 1 ADC Enables clock for ADC. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [14:14] WDT Enables clock for WDT. [15:15] ENUM DISABLE Disable 0 ENABLE Enable 1 IOCON Enables clock for I/O configuration block. [16:16] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [17:17] SSP1 Enables clock for SSP1. [18:18] ENUM DISABLE Disable 0 ENABLE Enable 1 PINT GPIO Pin interrupts [19:19] ENUM DISABLE Disable 0 ENABLE Enable 1 ACOMP Enables clock for ACOMP. [20:20] ENUM DISABLE Disable 0 ENABLE Enable 1 DAC Enables clock for DAC. [21:21] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [22:22] P0INT GPIO Port 0 interrupt [23:23] ENUM DISABLE Disable 0 ENABLE Enable 1 P1INT GPIO Port 1interrupt [24:24] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [31:25] SSP0CLKDIV SSP0 clock divider 0x094 read-write 0 0xFFFFFFFF DIV SSP0_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTCLKDIV UART clock divider 0x098 read-write 0 0xFFFFFFFF DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SSP1CLKDIV SSP1 clock divider 0x09C read-write 0 0xFFFFFFFF DIV SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTSEL CLKOUT clock source select 0x0E0 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 CRYSTAL_OSCILLATOR_ Crystal oscillator (XTAL) 0x1 LF_OSCILLATOR LF oscillator 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTUEN CLKOUT clock source update enable 0x0E4 read-write 0 0xFFFFFFFF ENA Enable CLKOUT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] CLKOUTDIV CLKOUT clock divider 0x0E8 read-write 0 0xFFFFFFFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] PIOPORCAP0 POR captured PIO status 0 0x100 read-only 0 0x00000000 PIOSTAT State of PIO0_31 through PIO0_0 at power-on reset [31:0] PIOPORCAP1 POR captured PIO status 1 0x104 read-only 0 0x00000000 PIOSTAT State of PIO1_9 through PIO1_0 at power-on reset [9:0] RESERVED Reserved [31:10] BODR Brown-Out Detect 0x150 read-write 0 0xFFFFFFFF RESERVED Reserved [1:0] BODINTVAL BOD interrupt threshold [3:2] ENUM LEVEL_2_THE_INTERRU Level 2: the interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V. 0x2 LEVEL_3_THE_INTERRU Level 3: the interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. 0x3 RESERVED Reserved [4:4] RESERVED Reserved [5:5] BODINT This bit is 1 if the BOD is requesting an interrupt. [6:6] RESERVED Reserved [31:7] SYSTCKCAL System tick counter calibration 0x158 read-write 0x004 0xFFFFFFFF CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] NMISRC NMI Source Control 0x174 read-write 0 0xFFFFFFFF IRQNO The IRQ number of the interrupt that is to act as the Non-Maskable interrupt (NMI) if bit 31 is 1. See Section 4.3 for the list of interrupt sources and their IRQ numbers. [4:0] RESERVED Reserved [30:5] NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. [31:31] 8 0x4 0-7 PINTSEL%s GPIO Pin Interrupt Select register 0 0x178 read-write 0 0xFFFFFFFF INTPIN The pin number within the port identified by the INTPORT field. [4:0] INTPORT Select the port: 0 = P0 pin. 1 = P1 pin. [5:5] RESERVED Reserved [31:6] PDRUNCFG Power configuration register 0x238 read-write 0x0000EDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output power-down [0:0] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 IRC_PD IRC oscillator power-down [1:1] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 FLASH_PD Flash power-down [2:2] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved [3:3] ADC_PD ADC power-down [4:4] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 XTAL_PD Crystal oscillator power-down [5:5] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 WDTOSC_PD Watchdog oscillator power-down [6:6] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 SYSPLL_PD System PLL power-down [7:7] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved [8:8] RESERVED Reserved. This bit must be set to zero during normal operation in Run mode. [9:9] RESERVED Reserved [10:10] RESERVED Reserved. This bit must be set to one in Run mode. [11:11] RESERVED Reserved. [12:12] LFOSC_PD Low frequency oscillator power-down [13:13] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 DAC_PD DAC power-down [14:14] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 TS_PD Temperature Sensor power-down [15:15] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 ACOMP_PD Analog Comparator power-down [16:16] ENUM POWERED_DOWN Powered down 1 POWERED Powered 0 RESERVED Reserved [31:17] DEVICE_ID Device ID 0x3F4 read-only 0 0x00000000 DEVICEID Part ID number for LPC11Axx LPC11A11FBD48/001 = 0x455E C02B LPC11A11FHN33/001 = 0x455E C02B LPC11A12FBD48/101 = 0x4574 802B LPC11A12FHN33/101 = 0x4574 802B LPC11A13FBD48/201 = 0x4582 402B LPC11A13FHI33/201 = 0x4582 402B LPC11A14FBD48/301 = 0x35A0 002B; 0x45A0 002B LPC11A14FHN33/301 = 0x35A0 002B; 0x45A0 002B LPC11A02UK = 0x4D5C C02B LPC11A04UK = 0x4D80 002B [31:0] GPIO_PIN_INT GPIO Modification GPIO_PIN_INT 0x4004C000 0 0xFFF registers PIN_INT0 0 PIN_INT1 1 PIN_INT2 2 PIN_INT3 3 PIN_INT4 4 PIN_INT5 5 PIN_INT6 6 PIN_INT7 7 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE0 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [0:0] PMODE1 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [1:1] PMODE2 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [2:2] PMODE3 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [3:3] PMODE4 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [4:4] PMODE5 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [5:5] PMODE6 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [6:6] PMODE7 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:7] RESERVED Reserved. [31:8] IENR Pin Interrupt Enable (Rising) register 0x004 read-write 0 0xFFFFFFFF ENRL0 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [0:0] ENRL1 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [1:1] ENRL2 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [2:2] ENRL3 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [3:3] ENRL4 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [4:4] ENRL5 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [5:5] ENRL6 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [6:6] ENRL7 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] SIENR Set Pin Interrupt Enable (Rising) register 0x008 write-only 0 0x00000000 SETENRL0 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [0:0] SETENRL1 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [1:1] SETENRL2 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [2:2] SETENRL3 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [3:3] SETENRL4 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [4:4] SETENRL5 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [5:5] SETENRL6 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [6:6] SETENRL7 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] CIENR Clear Pin Interrupt Enable (Rising) register 0x00C write-only 0 0x00000000 CENRL0 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [0:0] CENRL1 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [1:1] CENRL2 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [2:2] CENRL3 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [3:3] CENRL4 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [4:4] CENRL5 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [5:5] CENRL6 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [6:6] CENRL7 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] IENF Pin Interrupt Enable Falling Edge / Active Level register 0x010 read-write 0 0xFFFFFFFF ENAF0 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [0:0] ENAF1 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [1:1] ENAF2 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [2:2] ENAF3 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [3:3] ENAF4 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [4:4] ENAF5 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [5:5] ENAF6 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [6:6] ENAF7 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:7] RESERVED Reserved. [31:8] SIENF Set Pin Interrupt Enable Falling Edge / Active Level register 0x014 write-only 0 0x00000000 SETENAF0 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [0:0] SETENAF1 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [1:1] SETENAF2 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [2:2] SETENAF3 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [3:3] SETENAF4 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [4:4] SETENAF5 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [5:5] SETENAF6 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [6:6] SETENAF7 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:7] RESERVED Reserved. [31:8] CIENF Clear Pin Interrupt Enable Falling Edge / Active Level address 0x018 write-only 0 0x00000000 CENAF0 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [0:0] CENAF1 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [1:1] CENAF2 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [2:2] CENAF3 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [3:3] CENAF4 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [4:4] CENAF5 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [5:5] CENAF6 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [6:6] CENAF7 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:7] RESERVED Reserved. [31:8] RISE Pin Interrupt Rising Edge register 0x01C read-write 0 0xFFFFFFFF RDET0 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [0:0] RDET1 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [1:1] RDET2 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [2:2] RDET3 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [3:3] RDET4 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [4:4] RDET5 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [5:5] RDET6 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [6:6] RDET7 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:7] RESERVED Reserved. [31:8] FALL Pin Interrupt Falling Edge register 0x020 read-write 0 0xFFFFFFFF FDET0 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [0:0] FDET1 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [1:1] FDET2 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [2:2] FDET3 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [3:3] FDET4 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [4:4] FDET5 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [5:5] FDET6 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [6:6] FDET7 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:7] RESERVED Reserved. [31:8] IST Pin Interrupt Status register 0x024 read-write 0 0xFFFFFFFF PSTAT0 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [0:0] PSTAT1 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [1:1] PSTAT2 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [2:2] PSTAT3 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [3:3] PSTAT4 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [4:4] PSTAT5 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [5:5] PSTAT6 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [6:6] PSTAT7 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [7:7] RESERVED Reserved. [31:8] SSP1 0x40058000 0 0xFFF registers SSP1 14 GPIO_GROUP_INT0 GPIO group interrupt GPIO_GROUP_INT0 0x4005C000 0 0xFFF registers GINT0 8 CTRL GPIO grouped interrupt control register 0x000 read-write 0 0xFFFFFFFF INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. [0:0] ENUM NO_INTERRUPT_REQUEST No interrupt request is pending. 0 INTERRUPT_REQUEST_IS Interrupt request is active. 1 COMB Combine enabled inputs for group interrupt [1:1] ENUM OR_FUNCTIONALITY_A_ OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND_FUNCTIONALITY_A AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 1 TRIG Group interrupt trigger [2:2] ENUM EDGE_TRIGGERED Edge-triggered 0 LEVEL_TRIGGERED Level-triggered 1 RESERVED Reserved [31:3] 2 0x4 0-1 PORT_POL%s GPIO grouped interrupt port 0 polarity register 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF POL_0 Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [0:0] POL_1 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [1:1] POL_2 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [2:2] POL_3 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [3:3] POL_4 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [4:4] POL_5 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [5:5] POL_6 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [6:6] POL_7 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [7:7] POL_8 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [8:8] POL_9 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [9:9] POL_10 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [10:10] POL_11 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [11:11] POL_12 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [12:12] POL_13 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [13:13] POL_14 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [14:14] POL_15 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [15:15] POL_16 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [16:16] POL_17 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [17:17] POL_18 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [18:18] POL_19 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [19:19] POL_20 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [20:20] POL_21 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [21:21] POL_22 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [22:22] POL_23 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [23:23] POL_24 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [24:24] POL_25 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [25:25] POL_26 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [26:26] POL_27 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [27:27] POL_28 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [28:28] POL_29 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [29:29] POL_30 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [30:30] POL_31 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [31:31] 2 0x4 0-1 PORT_ENA%s GPIO grouped interrupt port 0/1 enable register 0x040 read-write 0 0xFFFFFFFF ENA_0 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [0:0] ENA_1 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [1:1] ENA_2 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [2:2] ENA_3 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [3:3] ENA_4 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [4:4] ENA_5 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [5:5] ENA_6 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [6:6] ENA_7 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [7:7] ENA_8 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [8:8] ENA_9 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [9:9] ENA_10 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [10:10] ENA_11 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [11:11] ENA_12 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [12:12] ENA_13 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [13:13] ENA_14 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [14:14] ENA_15 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [15:15] ENA_16 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [16:16] ENA_17 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [17:17] ENA_18 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [18:18] ENA_19 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [19:19] ENA_20 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [20:20] ENA_21 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [21:21] ENA_22 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [22:22] ENA_23 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [23:23] ENA_24 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [24:24] ENA_25 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [25:25] ENA_26 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [26:26] ENA_27 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [27:27] ENA_28 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [28:28] ENA_29 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [29:29] ENA_30 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [30:30] ENA_31 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [31:31] GPIO_GROUP_INT1 0x40060000 0 0xFFF registers GINT1 9 GPIO_PORT GPIO port GPIO_PORT 0x50000000 0 0xFFFFF registers 32 0x1 0-31 B%s Byte pin registers port 0; pins PIO0_0 to PIO0_31 0x0000 8 read-write 0 0xFF PBYTE Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 10 0x1 32-41 B%s Byte pin registers port 1 0x0020 8 read-write 0 0xFF PBYTE Read: state of the pin P1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 32 0x4 0-31 W%s Word pin registers port 0 0x1000 read-write 0 0xFFFFFFFF PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] 10 0x4 32-41 W%s Word pin registers port 1 0x1080 read-write 0 0xFFFFFFFF PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] 2 0x4 0-1 DIR%s Direction registers port 0/1 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [0:0] DIRP1 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [1:1] DIRP2 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [2:2] DIRP3 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [3:3] DIRP4 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [4:4] DIRP5 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [5:5] DIRP6 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [6:6] DIRP7 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [7:7] DIRP8 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [8:8] DIRP9 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [9:9] DIRP10 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [10:10] DIRP11 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [11:11] DIRP12 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [12:12] DIRP13 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [13:13] DIRP14 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [14:14] DIRP15 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [15:15] DIRP16 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [16:16] DIRP17 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [17:17] DIRP18 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [18:18] DIRP19 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [19:19] DIRP20 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [20:20] DIRP21 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [21:21] DIRP22 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [22:22] DIRP23 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [23:23] DIRP24 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [24:24] DIRP25 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [25:25] DIRP26 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [26:26] DIRP27 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [27:27] DIRP28 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [28:28] DIRP29 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [29:29] DIRP30 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [30:30] DIRP31 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [31:31] 2 0x4 0-1 MASK%s Mask register port 0/1 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [0:0] MASKP1 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [1:1] MASKP2 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [2:2] MASKP3 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [3:3] MASKP4 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [4:4] MASKP5 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [5:5] MASKP6 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [6:6] MASKP7 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [7:7] MASKP8 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [8:8] MASKP9 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [9:9] MASKP10 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [10:10] MASKP11 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [11:11] MASKP12 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [12:12] MASKP13 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [13:13] MASKP14 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [14:14] MASKP15 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [15:15] MASKP16 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [16:16] MASKP17 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:17] MASKP18 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [18:18] MASKP19 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [19:19] MASKP20 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [20:20] MASKP21 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [21:21] MASKP22 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [22:22] MASKP23 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [23:23] MASKP24 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [24:24] MASKP25 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [25:25] MASKP26 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [26:26] MASKP27 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [27:27] MASKP28 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [28:28] MASKP29 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [29:29] MASKP30 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [30:30] MASKP31 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [31:31] 2 0x4 0-1 PIN%s Portpin register port 0 0x2100 read-write 0 0xFFFFFFFF PORT0 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [0:0] PORT1 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [1:1] PORT2 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [2:2] PORT3 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [3:3] PORT4 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [4:4] PORT5 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [5:5] PORT6 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [6:6] PORT7 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [7:7] PORT8 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [8:8] PORT9 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [9:9] PORT10 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [10:10] PORT11 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [11:11] PORT12 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [12:12] PORT13 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [13:13] PORT14 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [14:14] PORT15 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [15:15] PORT16 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [16:16] PORT17 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:17] PORT18 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [18:18] PORT19 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [19:19] PORT20 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [20:20] PORT21 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [21:21] PORT22 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [22:22] PORT23 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [23:23] PORT24 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [24:24] PORT25 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [25:25] PORT26 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [26:26] PORT27 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [27:27] PORT28 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [28:28] PORT29 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [29:29] PORT30 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [30:30] PORT31 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [31:31] 2 0x4 0-1 MPIN%s Masked port register port 0/1 0x2180 read-write 0 0xFFFFFFFF MPORTP0 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [0:0] MPORTP1 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [1:1] MPORTP2 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [2:2] MPORTP3 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [3:3] MPORTP4 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [4:4] MPORTP5 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [5:5] MPORTP6 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [6:6] MPORTP7 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [7:7] MPORTP8 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [8:8] MPORTP9 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [9:9] MPORTP10 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [10:10] MPORTP11 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [11:11] MPORTP12 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [12:12] MPORTP13 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [13:13] MPORTP14 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [14:14] MPORTP15 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [15:15] MPORTP16 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [16:16] MPORTP17 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:17] MPORTP18 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [18:18] MPORTP19 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [19:19] MPORTP20 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [20:20] MPORTP21 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [21:21] MPORTP22 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [22:22] MPORTP23 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [23:23] MPORTP24 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [24:24] MPORTP25 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [25:25] MPORTP26 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [26:26] MPORTP27 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [27:27] MPORTP28 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [28:28] MPORTP29 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [29:29] MPORTP30 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [30:30] MPORTP31 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [31:31] 2 0x4 0-1 SET%s Write: Set register for port 0/1 Read: output bits for port 0/1 0x2200 read-write 0 0xFFFFFFFF SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [0:0] SETP1 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [1:1] SETP2 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [2:2] SETP3 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [3:3] SETP4 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [4:4] SETP5 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [5:5] SETP6 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [6:6] SETP7 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [7:7] SETP8 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [8:8] SETP9 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [9:9] SETP10 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [10:10] SETP11 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [11:11] SETP12 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [12:12] SETP13 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [13:13] SETP14 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [14:14] SETP15 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [15:15] SETP16 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [16:16] SETP17 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:17] SETP18 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [18:18] SETP19 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [19:19] SETP20 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [20:20] SETP21 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [21:21] SETP22 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [22:22] SETP23 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [23:23] SETP24 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [24:24] SETP25 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [25:25] SETP26 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [26:26] SETP27 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [27:27] SETP28 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [28:28] SETP29 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [29:29] SETP30 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [30:30] SETP31 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [31:31] 2 0x4 0-1 CLR%s Clear port 0/1 0x2280 write-only 0 0x00000000 CLRP00 Clear output bits: 0 = No operation. 1 = Clear output bit. [0:0] CLRP01 Clear output bits: 0 = No operation. 1 = Clear output bit. [1:1] CLRP02 Clear output bits: 0 = No operation. 1 = Clear output bit. [2:2] CLRP03 Clear output bits: 0 = No operation. 1 = Clear output bit. [3:3] CLRP04 Clear output bits: 0 = No operation. 1 = Clear output bit. [4:4] CLRP05 Clear output bits: 0 = No operation. 1 = Clear output bit. [5:5] CLRP06 Clear output bits: 0 = No operation. 1 = Clear output bit. [6:6] CLRP07 Clear output bits: 0 = No operation. 1 = Clear output bit. [7:7] CLRP08 Clear output bits: 0 = No operation. 1 = Clear output bit. [8:8] CLRP09 Clear output bits: 0 = No operation. 1 = Clear output bit. [9:9] CLRP010 Clear output bits: 0 = No operation. 1 = Clear output bit. [10:10] CLRP011 Clear output bits: 0 = No operation. 1 = Clear output bit. [11:11] CLRP012 Clear output bits: 0 = No operation. 1 = Clear output bit. [12:12] CLRP013 Clear output bits: 0 = No operation. 1 = Clear output bit. [13:13] CLRP014 Clear output bits: 0 = No operation. 1 = Clear output bit. [14:14] CLRP015 Clear output bits: 0 = No operation. 1 = Clear output bit. [15:15] CLRP016 Clear output bits: 0 = No operation. 1 = Clear output bit. [16:16] CLRP017 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:17] CLRP018 Clear output bits: 0 = No operation. 1 = Clear output bit. [18:18] CLRP019 Clear output bits: 0 = No operation. 1 = Clear output bit. [19:19] CLRP020 Clear output bits: 0 = No operation. 1 = Clear output bit. [20:20] CLRP021 Clear output bits: 0 = No operation. 1 = Clear output bit. [21:21] CLRP022 Clear output bits: 0 = No operation. 1 = Clear output bit. [22:22] CLRP023 Clear output bits: 0 = No operation. 1 = Clear output bit. [23:23] CLRP024 Clear output bits: 0 = No operation. 1 = Clear output bit. [24:24] CLRP025 Clear output bits: 0 = No operation. 1 = Clear output bit. [25:25] CLRP026 Clear output bits: 0 = No operation. 1 = Clear output bit. [26:26] CLRP027 Clear output bits: 0 = No operation. 1 = Clear output bit. [27:27] CLRP028 Clear output bits: 0 = No operation. 1 = Clear output bit. [28:28] CLRP029 Clear output bits: 0 = No operation. 1 = Clear output bit. [29:29] CLRP030 Clear output bits: 0 = No operation. 1 = Clear output bit. [30:30] CLRP031 Clear output bits: 0 = No operation. 1 = Clear output bit. [31:31] 2 0x4 0-1 NOT%s Toggle port 0/1 0x2300 write-only 0 0x00000000 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [0:0] NOTP1 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [1:1] NOTP2 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [2:2] NOTP3 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [3:3] NOTP4 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [4:4] NOTP5 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [5:5] NOTP6 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [6:6] NOTP7 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [7:7] NOTP8 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [8:8] NOTP9 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [9:9] NOTP10 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [10:10] NOTP11 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [11:11] NOTP12 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [12:12] NOTP13 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [13:13] NOTP14 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [14:14] NOTP15 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [15:15] NOTP16 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [16:16] NOTP17 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:17] NOTP18 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [18:18] NOTP19 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [19:19] NOTP20 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [20:20] NOTP21 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [21:21] NOTP22 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [22:22] NOTP23 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [23:23] NOTP24 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [24:24] NOTP25 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [25:25] NOTP26 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [26:26] NOTP27 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [27:27] NOTP28 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [28:28] NOTP29 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [29:29] NOTP30 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [30:30] NOTP31 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [31:31]