78320 lines
4.1 MiB
78320 lines
4.1 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>Renesas</vendor>
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<vendorID>Renesas</vendorID>
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<name>R7FA6M2AF</name>
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<series>RA6</series>
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<version>1.2</version>
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<description>ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. </description>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>PORT0</name>
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<description>Port 0 Control Registers</description>
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<baseAddress>0x40040000</baseAddress>
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<addressBlock>
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<offset>0x00</offset>
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<size>4</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x00</offset>
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<size>8</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x06</offset>
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<size>6</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x08</offset>
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<size>4</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>PCNTR1</name>
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<description>Port Control Register 1</description>
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<addressOffset>0x00</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>PODR</name>
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|
<description>Pmn Output Data</description>
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<lsb>16</lsb>
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<msb>31</msb>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>0</name>
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|
<description>Low output</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>High output.</description>
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|
<value>#1</value>
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</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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|
<field>
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|
<name>PDR</name>
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|
<description>Pmn Direction</description>
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<lsb>0</lsb>
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<msb>15</msb>
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|
<access>read-write</access>
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|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
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|
<description>Input (functions as an input pin)</description>
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|
<value>#0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>Output (functions as an output pin).</description>
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|
<value>#1</value>
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|
</enumeratedValue>
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|
</enumeratedValues>
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|
</field>
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</fields>
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</register>
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<register>
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|
<name>PODR</name>
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|
<description>Output data register</description>
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<alternateRegister>PCNTR1</alternateRegister>
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|
<addressOffset>0x00</addressOffset>
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<size>16</size>
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<access>read-write</access>
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|
<resetValue>0x0000</resetValue>
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|
<resetMask>0xFFFF</resetMask>
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|
<fields>
|
|
<field>
|
|
<name>PODR</name>
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|
<description>Pmn Output Data</description>
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|
<lsb>0</lsb>
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|
<msb>15</msb>
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|
<access>read-write</access>
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|
<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>High output.</description>
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|
<value>#1</value>
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</enumeratedValue>
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|
</enumeratedValues>
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</field>
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|
</fields>
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</register>
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<register>
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<name>PDR</name>
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<description>Data direction register</description>
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<alternateRegister>PCNTR1</alternateRegister>
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|
<addressOffset>0x02</addressOffset>
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|
<size>16</size>
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<access>read-write</access>
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<resetValue>0x0000</resetValue>
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|
<resetMask>0xFFFF</resetMask>
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|
<fields>
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|
<field>
|
|
<name>PDR</name>
|
|
<description>Pmn Direction</description>
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|
<lsb>0</lsb>
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|
<msb>15</msb>
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|
<access>read-write</access>
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|
<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>0</name>
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|
<description>Input (functions as an input pin)</description>
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|
<value>#0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>Output (functions as an output pin).</description>
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|
<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>PCNTR2</name>
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<description>Port Control Register 2</description>
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<addressOffset>0x04</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFF0000</resetMask>
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<fields>
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<field>
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<name>EIDR</name>
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<description>Pmn Event Input Data</description>
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<lsb>16</lsb>
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<msb>31</msb>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>0</name>
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<description>Low input</description>
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<value>#0</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>1</name>
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<description>High input.</description>
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>PIDR</name>
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<description>Pmn Input Data</description>
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<lsb>0</lsb>
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<msb>15</msb>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
|
|
<name>0</name>
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|
<description>Low input</description>
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<value>#0</value>
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</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>High input.</description>
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>PIDR</name>
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<description>Input data register</description>
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<alternateRegister>PCNTR2</alternateRegister>
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<addressOffset>0x06</addressOffset>
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<size>16</size>
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<access>read-only</access>
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<resetValue>0x0000</resetValue>
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<resetMask>0x0000</resetMask>
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<fields>
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<field>
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<name>PIDR</name>
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|
<description>Pmn Input Data</description>
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|
<lsb>0</lsb>
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|
<msb>15</msb>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>0</name>
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|
<description>Low input</description>
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|
<value>#0</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
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|
<description>High input.</description>
|
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>PCNTR3</name>
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<description>Port Control Register 3</description>
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<addressOffset>0x08</addressOffset>
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<size>32</size>
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<access>write-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>PORR</name>
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<description>Pmn Output Reset</description>
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<lsb>16</lsb>
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<msb>31</msb>
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<access>write-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>0</name>
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<description>No affect to output</description>
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<value>#0</value>
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</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output.</description>
|
|
<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>POSR</name>
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<description>Pmn Output Set</description>
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<lsb>0</lsb>
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<msb>15</msb>
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<access>write-only</access>
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<enumeratedValues>
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<enumeratedValue>
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|
<name>0</name>
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|
<description>No affect to output</description>
|
|
<value>#0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
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</field>
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</fields>
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</register>
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<register>
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<name>PORR</name>
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<description>Output reset register</description>
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<alternateRegister>PCNTR3</alternateRegister>
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<addressOffset>0x08</addressOffset>
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|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
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<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
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<field>
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<name>PORR</name>
|
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<description>Pmn Output Reset</description>
|
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<lsb>0</lsb>
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|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
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<register>
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<name>POSR</name>
|
|
<description>Output set register</description>
|
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<alternateRegister>PCNTR3</alternateRegister>
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<addressOffset>0x0A</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSR</name>
|
|
<description>Pmn Output Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
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|
</fields>
|
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>PORT1</name>
|
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<description>Port 1 Control Registers</description>
|
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<baseAddress>0x40040020</baseAddress>
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|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCNTR1</name>
|
|
<description>Port Control Register 1</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Pmn Output Data</description>
|
|
<lsb>16</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Pmn Direction</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (functions as an input pin)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (functions as an output pin).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PODR</name>
|
|
<description>Output data register</description>
|
|
<alternateRegister>PCNTR1</alternateRegister>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Pmn Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDR</name>
|
|
<description>Data direction register</description>
|
|
<alternateRegister>PCNTR1</alternateRegister>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Pmn Direction</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (functions as an input pin)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (functions as an output pin).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCNTR2</name>
|
|
<description>Port Control Register 2</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFF0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EIDR</name>
|
|
<description>Pmn Event Input Data</description>
|
|
<lsb>16</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Pmn Input Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EIDR</name>
|
|
<description>Event input data register</description>
|
|
<alternateRegister>PCNTR2</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EIDR</name>
|
|
<description>Pmn Event Input Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Input data register</description>
|
|
<alternateRegister>PCNTR2</alternateRegister>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Pmn Input Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCNTR3</name>
|
|
<description>Port Control Register 3</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORR</name>
|
|
<description>Pmn Output Reset</description>
|
|
<lsb>16</lsb>
|
|
<msb>31</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POSR</name>
|
|
<description>Pmn Output Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORR</name>
|
|
<description>Output set register</description>
|
|
<alternateRegister>PCNTR3</alternateRegister>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORR</name>
|
|
<description>Pmn Output Reset</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POSR</name>
|
|
<description>Output reset register</description>
|
|
<alternateRegister>PCNTR3</alternateRegister>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSR</name>
|
|
<description>Pmn Output Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCNTR4</name>
|
|
<description>Port Control Register 4</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EORR</name>
|
|
<description>Pmn Event Output Reset</description>
|
|
<lsb>16</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOSR</name>
|
|
<description>Pmn Event Output Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EORR</name>
|
|
<description>Event output set register</description>
|
|
<alternateRegister>PCNTR4</alternateRegister>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EORR</name>
|
|
<description>Pmn Event Output Reset</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EOSR</name>
|
|
<description>Event output reset register</description>
|
|
<alternateRegister>PCNTR4</alternateRegister>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EOSR</name>
|
|
<description>Pmn Event Output Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No affect to output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT1">
|
|
<name>PORT2</name>
|
|
<description>Port 2 Control Registers</description>
|
|
<baseAddress>0x40040040</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT1">
|
|
<name>PORT3</name>
|
|
<description>Port 3 Control Registers</description>
|
|
<baseAddress>0x40040060</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT1">
|
|
<name>PORT4</name>
|
|
<description>Port 4 Control Registers</description>
|
|
<baseAddress>0x40040080</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORT5</name>
|
|
<description>Port 5 Control Registers</description>
|
|
<baseAddress>0x400400A0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORT6</name>
|
|
<description>Port 6 Control Registers</description>
|
|
<baseAddress>0x400400C0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORT7</name>
|
|
<description>Port 7 Control Registers</description>
|
|
<baseAddress>0x400400E0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORT8</name>
|
|
<description>Port 8 Control Registers</description>
|
|
<baseAddress>0x40040100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORT9</name>
|
|
<description>Port 9 Control Registers</description>
|
|
<baseAddress>0x40040120</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORTA</name>
|
|
<description>Port A Control Registers</description>
|
|
<baseAddress>0x40040140</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="PORT0">
|
|
<name>PORTB</name>
|
|
<description>Port B Control Registers</description>
|
|
<baseAddress>0x40040160</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PFS</name>
|
|
<description>Pmn Pin Function Control Register</description>
|
|
<baseAddress>0x40040800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x03</offset>
|
|
<size>29</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x06</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x07</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x22</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x23</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3A</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3B</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x42</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x43</offset>
|
|
<size>29</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x46</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x47</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x60</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x62</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x63</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x66</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x67</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6A</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6B</offset>
|
|
<size>21</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6E</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6F</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x82</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x83</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x86</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x87</offset>
|
|
<size>33</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8A</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8B</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA8</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xAA</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xAB</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC2</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC3</offset>
|
|
<size>37</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC6</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC7</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE8</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xEA</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xEB</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x102</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x103</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x128</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x12A</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x12B</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x140</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x142</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x143</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16C</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16E</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16F</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x180</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x182</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x183</offset>
|
|
<size>40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A8</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1AA</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1AB</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C0</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C2</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C3</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E4</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E6</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E7</offset>
|
|
<size>36</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E8</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1EA</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1EB</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x200</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x202</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x203</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x240</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x242</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x243</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x254</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x256</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x257</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x280</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x282</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x283</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A0</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A2</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A3</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A8</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2AA</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2AB</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C0</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C2</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C3</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>P000PFS</name>
|
|
<description>P000 Pin Function Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PMR</name>
|
|
<description>Port Mode Control</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Uses the pin as a general I/O pin. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Uses the pin as an I/O port for peripheral functions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P000PFS_HA</name>
|
|
<description>P000 Pin Function Control Register</description>
|
|
<alternateRegister>P000PFS</alternateRegister>
|
|
<addressOffset>0x002</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P000PFS_BY</name>
|
|
<description>P000 Pin Function Control Register</description>
|
|
<alternateRegister>P000PFS</alternateRegister>
|
|
<addressOffset>0x003</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P00%sPFS</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P00%sPFS_HA</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<alternateRegister>P00%sPFS</alternateRegister>
|
|
<addressOffset>0x006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P00%sPFS_BY</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<alternateRegister>P00%sPFS</alternateRegister>
|
|
<addressOffset>0x007</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>P00%sPFS</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>P00%sPFS_HA</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<alternateRegister>P00%sPFS</alternateRegister>
|
|
<addressOffset>0x022</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>P00%sPFS_BY</name>
|
|
<description>P00%s Pin Function Control Register</description>
|
|
<alternateRegister>P00%sPFS</alternateRegister>
|
|
<addressOffset>0x023</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>14-15</dimIndex>
|
|
<name>P0%sPFS</name>
|
|
<description>P0%s Pin Function Control Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>14-15</dimIndex>
|
|
<name>P0%sPFS_HA</name>
|
|
<description>P0%s Pin Function Control Register</description>
|
|
<addressOffset>0x03A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>14-15</dimIndex>
|
|
<name>P0%sPFS_BY</name>
|
|
<description>P0%s Pin Function Control Register</description>
|
|
<addressOffset>0x03B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>P100PFS</name>
|
|
<description>P100 Pin Function Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PMR</name>
|
|
<description>Port Mode Control</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Uses the pin as a general I/O pin. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Uses the pin as an I/O port for peripheral functions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P100PFS_HA</name>
|
|
<description>P100 Pin Function Control Register</description>
|
|
<addressOffset>0x042</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P100PFS_BY</name>
|
|
<description>P100 Pin Function Control Register</description>
|
|
<addressOffset>0x043</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="P100PFS">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P10%sPFS</name>
|
|
<description>P10%s Pin Function Control Register</description>
|
|
<alternateRegister>P10%sPFS</alternateRegister>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_HA">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P10%sPFS_HA</name>
|
|
<description>P10%s Pin Function Control Register</description>
|
|
<alternateRegister>P10%sPFS</alternateRegister>
|
|
<addressOffset>0x046</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_BY">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>P10%sPFS_BY</name>
|
|
<description>P10%s Pin Function Control Register</description>
|
|
<alternateRegister>P10%sPFS</alternateRegister>
|
|
<addressOffset>0x047</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>P108PFS</name>
|
|
<description>P108 Pin Function Control Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010410</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PMR</name>
|
|
<description>Port Mode Control</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Uses the pin as a general I/O pin. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Uses the pin as an I/O port for peripheral functions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P108PFS_HA</name>
|
|
<description>P108 Pin Function Control Register</description>
|
|
<alternateRegister>P108PFS</alternateRegister>
|
|
<addressOffset>0x062</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0410</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P108PFS_BY</name>
|
|
<description>P108 Pin Function Control Register</description>
|
|
<alternateRegister>P108PFS</alternateRegister>
|
|
<addressOffset>0x063</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="P108PFS">
|
|
<name>P109PFS</name>
|
|
<description>P109 Pin Function Control Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010410</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P108PFS_HA">
|
|
<name>P109PFS_HA</name>
|
|
<description>P109 Pin Function Control Register</description>
|
|
<alternateRegister>P109PFS</alternateRegister>
|
|
<addressOffset>0x066</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0410</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P108PFS_BY">
|
|
<name>P109PFS_BY</name>
|
|
<description>P109 Pin Function Control Register</description>
|
|
<alternateRegister>P109PFS</alternateRegister>
|
|
<addressOffset>0x067</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>P110PFS</name>
|
|
<description>P110 Pin Function Control Register</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010010</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PMR</name>
|
|
<description>Port Mode Control</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Uses the pin as a general I/O pin. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Uses the pin as an I/O port for peripheral functions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P110PFS_HA</name>
|
|
<description>P110 Pin Function Control Register</description>
|
|
<alternateRegister>P110PFS</alternateRegister>
|
|
<addressOffset>0x06A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0010</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P110PFS_BY</name>
|
|
<description>P110 Pin Function Control Register</description>
|
|
<alternateRegister>P110PFS</alternateRegister>
|
|
<addressOffset>0x06B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P1%sPFS</name>
|
|
<description>P1%s Pin Function Control Register</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P1%sPFS_HA</name>
|
|
<description>P1%s Pin Function Control Register</description>
|
|
<alternateRegister>P1%sPFS</alternateRegister>
|
|
<addressOffset>0x06E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P1%sPFS_BY</name>
|
|
<description>P1%s Pin Function Control Register</description>
|
|
<alternateRegister>P1%sPFS</alternateRegister>
|
|
<addressOffset>0x06F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<name>P200PFS</name>
|
|
<description>P200 Pin Function Control Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<name>P200PFS_HA</name>
|
|
<description>P200 Pin Function Control Register</description>
|
|
<alternateRegister>P200PFS</alternateRegister>
|
|
<addressOffset>0x082</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<name>P200PFS_BY</name>
|
|
<description>P200 Pin Function Control Register</description>
|
|
<alternateRegister>P200PFS</alternateRegister>
|
|
<addressOffset>0x083</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>P201PFS</name>
|
|
<description>P201 Pin Function Control Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PMR</name>
|
|
<description>Port Mode Control</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Uses the pin as a general I/O pin. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Uses the pin as an I/O port for peripheral functions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P201PFS_HA</name>
|
|
<description>P201 Pin Function Control Register</description>
|
|
<alternateRegister>P201PFS</alternateRegister>
|
|
<addressOffset>0x086</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0010</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASEL</name>
|
|
<description>Analog Input enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Used other than as analog pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as analog pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>IRQ input enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not used as IRQn input pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Used as IRQn input pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>Event on Falling</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect falling edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOR</name>
|
|
<description>Event on Rising</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not care</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCR</name>
|
|
<description>Drive Strength Control Register</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal drive output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle drive output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High-drive output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>P201PFS_BY</name>
|
|
<description>P201 Pin Function Control Register</description>
|
|
<alternateRegister>P201PFS</alternateRegister>
|
|
<addressOffset>0x087</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCODR</name>
|
|
<description>N-Channel Open Drain Control</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMOS output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMOS open-drain output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Pull-up Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an input pull-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an input pull-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDR</name>
|
|
<description>Port Direction</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input (Functions as an input pin.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output (Functions as an output pin.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDR</name>
|
|
<description>Port Input Data</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PODR</name>
|
|
<description>Port Output Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>2-9</dimIndex>
|
|
<name>P20%sPFS</name>
|
|
<description>P20%s Pin Function Control Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>2-9</dimIndex>
|
|
<name>P20%sPFS_HA</name>
|
|
<description>P20%s Pin Function Control Register</description>
|
|
<alternateRegister>P20%sPFS</alternateRegister>
|
|
<addressOffset>0x08A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>2-9</dimIndex>
|
|
<name>P20%sPFS_BY</name>
|
|
<description>P20%s Pin Function Control Register</description>
|
|
<alternateRegister>P20%sPFS</alternateRegister>
|
|
<addressOffset>0x08B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-14</dimIndex>
|
|
<name>P2%sPFS</name>
|
|
<description>P2%s Pin Function Control Register</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-14</dimIndex>
|
|
<name>P2%sPFS_HA</name>
|
|
<description>P2%s Pin Function Control Register</description>
|
|
<alternateRegister>P2%sPFS</alternateRegister>
|
|
<addressOffset>0x0AA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-14</dimIndex>
|
|
<name>P2%sPFS_BY</name>
|
|
<description>P2%s Pin Function Control Register</description>
|
|
<alternateRegister>P2%sPFS</alternateRegister>
|
|
<addressOffset>0x0AB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P110PFS">
|
|
<name>P300PFS</name>
|
|
<description>P300 Pin Function Control Register</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010010</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P110PFS_HA">
|
|
<name>P300PFS_HA</name>
|
|
<description>P300 Pin Function Control Register</description>
|
|
<alternateRegister>P300PFS</alternateRegister>
|
|
<addressOffset>0x0C2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0010</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P110PFS_BY">
|
|
<name>P300PFS_BY</name>
|
|
<description>P300 Pin Function Control Register</description>
|
|
<alternateRegister>P300PFS</alternateRegister>
|
|
<addressOffset>0x0C3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-9</dimIndex>
|
|
<name>P30%sPFS</name>
|
|
<description>P30%s Pin Function Control Register</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-9</dimIndex>
|
|
<name>P30%sPFS_HA</name>
|
|
<description>P30%s Pin Function Control Register</description>
|
|
<alternateRegister>P30%sPFS</alternateRegister>
|
|
<addressOffset>0x0C6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-9</dimIndex>
|
|
<name>P30%sPFS_BY</name>
|
|
<description>P30%s Pin Function Control Register</description>
|
|
<alternateRegister>P30%sPFS</alternateRegister>
|
|
<addressOffset>0x0C7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P3%sPFS</name>
|
|
<description>P3%s Pin Function Control Register</description>
|
|
<addressOffset>0x0E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P3%sPFS_HA</name>
|
|
<description>P30%s Pin Function Control Register</description>
|
|
<alternateRegister>P3%sPFS</alternateRegister>
|
|
<addressOffset>0x0EA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P3%sPFS_BY</name>
|
|
<description>P30%s Pin Function Control Register</description>
|
|
<alternateRegister>P3%sPFS</alternateRegister>
|
|
<addressOffset>0x0EB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P40%sPFS</name>
|
|
<description>P40%s Pin Function Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_HA">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P40%sPFS_HA</name>
|
|
<description>P40%s Pin Function Control Register</description>
|
|
<alternateRegister>P40%sPFS</alternateRegister>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_BY">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P40%sPFS_BY</name>
|
|
<description>P40%s Pin Function Control Register</description>
|
|
<alternateRegister>P40%sPFS</alternateRegister>
|
|
<addressOffset>0x103</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P4%sPFS</name>
|
|
<description>P4%s Pin Function Control Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_HA">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P4%sPFS_HA</name>
|
|
<description>P4%s Pin Function Control Register</description>
|
|
<alternateRegister>P4%sPFS</alternateRegister>
|
|
<addressOffset>0x12A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P100PFS_BY">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P4%sPFS_BY</name>
|
|
<description>P4%s Pin Function Control Register</description>
|
|
<alternateRegister>P4%sPFS</alternateRegister>
|
|
<addressOffset>0x12B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P50%sPFS</name>
|
|
<description>P50%s Pin Function Control Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P50%sPFS_HA</name>
|
|
<description>P50%s Pin Function Control Register</description>
|
|
<alternateRegister>P50%sPFS</alternateRegister>
|
|
<addressOffset>0x142</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P50%sPFS_BY</name>
|
|
<description>P50%s Pin Function Control Register</description>
|
|
<alternateRegister>P50%sPFS</alternateRegister>
|
|
<addressOffset>0x143</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P5%sPFS</name>
|
|
<description>P5%s Pin Function Control Register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P5%sPFS_HA</name>
|
|
<description>P5%s Pin Function Control Register</description>
|
|
<alternateRegister>P5%sPFS</alternateRegister>
|
|
<addressOffset>0x16E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-15</dimIndex>
|
|
<name>P5%sPFS_BY</name>
|
|
<description>P5%s Pin Function Control Register</description>
|
|
<alternateRegister>P5%sPFS</alternateRegister>
|
|
<addressOffset>0x16F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P60%sPFS</name>
|
|
<description>P60%s Pin Function Control Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P60%sPFS_HA</name>
|
|
<description>P60%s Pin Function Control Register</description>
|
|
<alternateRegister>P60%sPFS</alternateRegister>
|
|
<addressOffset>0x182</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>10</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>P60%sPFS_BY</name>
|
|
<description>P60%s Pin Function Control Register</description>
|
|
<alternateRegister>P60%sPFS</alternateRegister>
|
|
<addressOffset>0x183</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P6%sPFS</name>
|
|
<description>P6%s Pin Function Control Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P6%sPFS_HA</name>
|
|
<description>P6%s Pin Function Control Register</description>
|
|
<alternateRegister>P6%sPFS</alternateRegister>
|
|
<addressOffset>0x1AA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>10-15</dimIndex>
|
|
<name>P6%sPFS_BY</name>
|
|
<description>P6%s Pin Function Control Register</description>
|
|
<alternateRegister>P6%sPFS</alternateRegister>
|
|
<addressOffset>0x1AB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P70%sPFS</name>
|
|
<description>P70%s Pin Function Control Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P70%sPFS_HA</name>
|
|
<description>P70%s Pin Function Control Register</description>
|
|
<alternateRegister>P70%sPFS</alternateRegister>
|
|
<addressOffset>0x1C2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>9</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-8</dimIndex>
|
|
<name>P70%sPFS_BY</name>
|
|
<description>P70%s Pin Function Control Register</description>
|
|
<alternateRegister>P70%sPFS</alternateRegister>
|
|
<addressOffset>0x1C3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>P80%sPFS</name>
|
|
<description>P80%s Pin Function Control Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>P80%sPFS_HA</name>
|
|
<description>P80%s Pin Function Control Register</description>
|
|
<alternateRegister>P80%sPFS</alternateRegister>
|
|
<addressOffset>0x202</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>P80%sPFS_BY</name>
|
|
<description>P80%s Pin Function Control Register</description>
|
|
<alternateRegister>P80%sPFS</alternateRegister>
|
|
<addressOffset>0x203</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>P90%sPFS</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>P90%sPFS_HA</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<alternateRegister>P90%sPFS</alternateRegister>
|
|
<addressOffset>0x242</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>P90%sPFS_BY</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<alternateRegister>P90%sPFS</alternateRegister>
|
|
<addressOffset>0x243</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>5-8</dimIndex>
|
|
<name>P90%sPFS</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>5-8</dimIndex>
|
|
<name>P90%sPFS_HA</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<alternateRegister>P90%sPFS</alternateRegister>
|
|
<addressOffset>0x256</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>5-8</dimIndex>
|
|
<name>P90%sPFS_BY</name>
|
|
<description>P90%s Pin Function Control Register</description>
|
|
<alternateRegister>P90%sPFS</alternateRegister>
|
|
<addressOffset>0x257</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PA0%sPFS</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PA0%sPFS_HA</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<alternateRegister>PA0%sPFS</alternateRegister>
|
|
<addressOffset>0x282</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PA0%sPFS_BY</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<alternateRegister>PA0%sPFS</alternateRegister>
|
|
<addressOffset>0x283</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>PA0%sPFS</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>PA0%sPFS_HA</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<alternateRegister>PA0%sPFS</alternateRegister>
|
|
<addressOffset>0x2A2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>8-9</dimIndex>
|
|
<name>PA0%sPFS_BY</name>
|
|
<description>PA0%s Pin Function Control Register</description>
|
|
<alternateRegister>PA0%sPFS</alternateRegister>
|
|
<addressOffset>0x2A3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<name>PA10PFS</name>
|
|
<description>PA10 Pin Function Control Register</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<name>PA10PFS_HA</name>
|
|
<description>PA10 Pin Function Control Register</description>
|
|
<alternateRegister>PA10PFS</alternateRegister>
|
|
<addressOffset>0x2AA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<name>PA10PFS_BY</name>
|
|
<description>PA10 Pin Function Control Register</description>
|
|
<alternateRegister>PA10PFS</alternateRegister>
|
|
<addressOffset>0x2AB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PB0%sPFS</name>
|
|
<description>PB0%s Pin Function Control Register</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_HA">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PB0%sPFS_HA</name>
|
|
<description>PB0%s Pin Function Control Register</description>
|
|
<alternateRegister>PB0%sPFS</alternateRegister>
|
|
<addressOffset>0x2C2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFD</resetMask>
|
|
</register>
|
|
<register derivedFrom="P000PFS_BY">
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PB0%sPFS_BY</name>
|
|
<description>PB0%s Pin Function Control Register</description>
|
|
<alternateRegister>PB0%sPFS</alternateRegister>
|
|
<addressOffset>0x2C3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMISC</name>
|
|
<description>Miscellaneous Port Control Register</description>
|
|
<baseAddress>0x40040D00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PFENET</name>
|
|
<description>Ethernet Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHYMODE0</name>
|
|
<description>Ethernet Mode Setting ch0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RMII mode (ETHERC channel 0)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MII mode (ETHERC channel 0)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWPR</name>
|
|
<description>Write-Protect Register</description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BOWI</name>
|
|
<description>PFSWE Bit Write Disable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing to the PFSWE bit is enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing to the PFSWE bit is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSWE</name>
|
|
<description>PFS Register Write Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing to the PFS register is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing to the PFS register is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>Serial Peripheral Interface 0</description>
|
|
<baseAddress>0x40072000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>25</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SPCR</name>
|
|
<description>SPI Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPRIE</name>
|
|
<description>SPI Receive Buffer Full Interrupt Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the generation of SPI receive buffer full interrupt requests</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the generation of SPI receive buffer full interrupt requests</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI Function Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the SPI function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the SPI function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTIE</name>
|
|
<description>Transmit Buffer Empty Interrupt Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the generation of transmit buffer empty interrupt requests</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the generation of transmit buffer empty interrupt requests</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEIE</name>
|
|
<description>SPI Error Interrupt Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the generation of SPI error interrupt requests</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the generation of SPI error interrupt requests</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>SPI Master/Slave Mode Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODFEN</name>
|
|
<description>Mode Fault Error Detection Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the detection of mode fault error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the detection of mode fault error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMD</name>
|
|
<description>Communications Operating Mode Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Full-duplex synchronous serial communications</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial communications consisting of only transmit operations</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMS</name>
|
|
<description>SPI Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI operation (4-wire method)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock synchronous operation (3-wire method)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSLP</name>
|
|
<description>SPI Slave Select Polarity Register</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSL3P</name>
|
|
<description>SSL3 Signal Polarity Setting</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSL3 signal is active low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSL3 signal is active high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSL2P</name>
|
|
<description>SSL2 Signal Polarity Setting</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSL2 signal is active low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSL2 signal is active high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSL1P</name>
|
|
<description>SSL1 Signal Polarity Setting</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSL1 signal is active low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSL1 signal is active high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSL0P</name>
|
|
<description>SSL0 Signal Polarity Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSL0 signal is active low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSL0 signal is active high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPPCR</name>
|
|
<description>RSPI Pin Control Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOIFE</name>
|
|
<description>MOSI Idle Value Fixing Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MOSI output value equals final data from previous transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MOSI output value equals the value set in the MOIFV bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOIFV</name>
|
|
<description>MOSI Idle Fixed Value</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The level output on the MOSIn pin during MOSI idling corresponds to low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The level output on the MOSIn pin during MOSI idling corresponds to high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLP2</name>
|
|
<description>RSPI Loopback 2</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loopback mode (data is not inverted for transmission)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLP</name>
|
|
<description>RSPI Loopback</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loopback mode (data is inverted for transmission)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPSR</name>
|
|
<description>SPI Status Register</description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPRF</name>
|
|
<description>SPI Receive Buffer Full Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No valid data in SPDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Valid data found in SPDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTEF</name>
|
|
<description>SPI Transmit Buffer Empty Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data found in the transmit buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No data in the transmit buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDRF</name>
|
|
<description>Underrun Error Flag(When MODF is 0, This bit is invalid.)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A mode fault error occurs (MODF=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An underrun error occurs (MODF=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERF</name>
|
|
<description>Parity Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode Fault Error Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Neither mode fault error nor underrun error occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A mode fault error or an underrun error occurs.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLNF</name>
|
|
<description>SPI Idle Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI is in the idle state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI is in the transfer state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVRF</name>
|
|
<description>Overrun Error Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDR</name>
|
|
<description>SPI Data Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPDR</name>
|
|
<description>SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDR_HA</name>
|
|
<description>SPI Data Register ( halfword access )</description>
|
|
<alternateRegister>SPDR</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPDR_HA</name>
|
|
<description>SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPSCR</name>
|
|
<description>SPI Sequence Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPSLN</name>
|
|
<description>RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Length 1 SPDMDx x = 0->0->...</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Length 2 SPDMDx x = 0->1->0->...</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Length 3 SPDMDx x = 0->1->2->0->...</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Length 4 SPDMDx x = 0->1->2->3->0->...</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Length 5 SPDMDx x = 0->1->2->3->4->0->...</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Length 6 SPDMDx x = 0->1->2->3->4->5->0->...</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->...</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->...</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPSSR</name>
|
|
<description>SPI Sequence Status Register</description>
|
|
<addressOffset>0x09</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPECM</name>
|
|
<description>RSPI Error Command</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>SPCMD0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>SPCMD1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>SPCMD2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>SPCMD3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>SPCMD4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>SPCMD5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>SPCMD6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>SPCMD7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPCP</name>
|
|
<description>RSPI Command Pointer</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>SPCMD0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>SPCMD1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>SPCMD2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>SPCMD3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>SPCMD4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>SPCMD5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>SPCMD6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>SPCMD7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPBR</name>
|
|
<description>SPI Bit Rate Register</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPR</name>
|
|
<description>SPBR sets the bit rate in master mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDCR</name>
|
|
<description>SPI Data Control Register</description>
|
|
<addressOffset>0x0B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPBYT</name>
|
|
<description>SPI Byte Access Specification</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPDR is accessed in word or longword (SPLW is valid)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPDR is accessed in byte (SPLW is invalid)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLW</name>
|
|
<description>SPI Word Access/Halfword Access Specification</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPDR_HA is valid to access in halfwords</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPDR is valid (to access in words).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPRDTD</name>
|
|
<description>RSPI Receive/Transmit Data Selection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPDR values are read from the receive buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPDR values are read from the transmit buffer (but only if the transmit buffer is empty)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPFC</name>
|
|
<description>Number of Frames Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1 frame</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2 frames</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3 frames</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 frames.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPCKD</name>
|
|
<description>SPI Clock Delay Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKDL</name>
|
|
<description>RSPCK Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 RSPCK</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 RSPCK</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 RSPCK</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 RSPCK</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 RSPCK</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 RSPCK</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 RSPCK</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 RSPCK</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSLND</name>
|
|
<description>SPI Slave Select Negation Delay Register</description>
|
|
<addressOffset>0x0D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLNDL</name>
|
|
<description>SSL Negation Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 RSPCK</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 RSPCK</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 RSPCK</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 RSPCK</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 RSPCK</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 RSPCK</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 RSPCK</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 RSPCK</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPND</name>
|
|
<description>SPI Next-Access Delay Register</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPNDL</name>
|
|
<description>SPI Next-Access Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 RSPCK + 2 PCLK</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 RSPCK + 2 PCLK</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 RSPCK + 2 PCLK</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 RSPCK + 2 PCLK</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 RSPCK + 2 PCLK</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 RSPCK + 2 PCLK</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 RSPCK + 2 PCLK</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 RSPCK + 2 PCLK</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPCR2</name>
|
|
<description>SPI Control Register 2</description>
|
|
<addressOffset>0x0F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKASE</name>
|
|
<description>RSPCK Auto-Stop Function Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the RSPCK auto-stop function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the RSPCK auto-stop function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTE</name>
|
|
<description>Parity Self-Testing</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the self-diagnosis function of the parity circuit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the self-diagnosis function of the parity circuit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIIE</name>
|
|
<description>SPI Idle Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the generation of idle interrupt requests</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the generation of idle interrupt requests</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOE</name>
|
|
<description>Parity Mode</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects even parity for use in transmission and reception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Selects odd parity for use in transmission and reception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPPE</name>
|
|
<description>Parity Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not add the parity bit to transmit data and does not check the parity bit of receive data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>SPCMD%s</name>
|
|
<description>SPI Command Register %s</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x070D</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKDEN</name>
|
|
<description>RSPCK Delay Setting Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An RSPCK delay of 1 RSPCK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLNDEN</name>
|
|
<description>SSL Negation Delay Setting Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An SSL negation delay of 1 RSPCK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPNDEN</name>
|
|
<description>RSPI Next-Access Delay Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A next-access delay of 1 RSPCK + 2 PCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>RSPI LSB First</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSB first</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LSB first</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPB</name>
|
|
<description>RSPI Data Length Setting</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>20 bits</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>24 bits</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>32 bits</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>32 bits</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>9 bits</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>10 bits</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>11 bits</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>12 bits</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>13 bits</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>14 bits</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>15 bits</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>16 bits</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>8bits</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSLKP</name>
|
|
<description>SSL Signal Level Keeping</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Negate all SSL signals on completion of transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keep SSL signal level from the end of transfer until the beginning</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSLA</name>
|
|
<description>SSL Signal Assertion Setting</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>SSL0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>SSL1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>SSL2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>SSL3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDV</name>
|
|
<description>Bit Rate Division Setting</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>These bits select the base bit rate</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>These bits select the base bit rate divided by 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>These bits select the base bit rate divided by 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>These bits select the base bit rate divided by 8</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>RSPCK Polarity Setting</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RSPCK is low when idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RSPCK is high when idle</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>RSPCK Phase Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data sampling on odd edge, data variation on even edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data variation on odd edge, data sampling on even edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDCR2</name>
|
|
<description>SPI Data Control Register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYSW</name>
|
|
<description>Byte Swap Operating Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Byte Swap Operating Mode disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Byte Swap Operating Mode enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI1</name>
|
|
<description>Serial Peripheral Interface 1</description>
|
|
<baseAddress>0x40072100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPT_OPS</name>
|
|
<description>Output Phase Switching Controller</description>
|
|
<baseAddress>0x40078FF0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>OPSCR</name>
|
|
<description>Output Phase Switching Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFCS</name>
|
|
<description>External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input.</description>
|
|
<lsb>30</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK/1 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4 </description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFEN</name>
|
|
<description>External Input Noise Filter Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not use a noise filter to the external input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use a noise filter to the external input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GODF</name>
|
|
<description>Group output disable function</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This bit function is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Group disable will clear OPSCR.EN Bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRP</name>
|
|
<description>Output disabled source selection</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Select Group A output disable source</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select Group B output disable source</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select Group C output disable source</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select Group D output disable source</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIGN</name>
|
|
<description>Input phase alignment</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input phase is aligned to PCLK.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input phase is aligned PWM.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RV</name>
|
|
<description>Output phase rotation direction reversal</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>U/V/W-Phase output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output to reverse the V / W-phase</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert-Phase Output Control</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Positive Logic (Active High)output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Negative Logic (Active Low)output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>N</name>
|
|
<description>Negative-Phase Output (N) Control</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Level signal output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWM signal output (PWM of GPT0)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>Positive-Phase Output (P) Control</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Level signal output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWM signal output (PWM of GPT0)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FB</name>
|
|
<description>External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. </description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Select the external input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Select the soft setting(OPSCR.UF, VF, WF).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable-Phase Output Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not Output(Hi-Z external terminals).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>W</name>
|
|
<description>Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>V</name>
|
|
<description>Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>U</name>
|
|
<description>Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WF</name>
|
|
<description>Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VF</name>
|
|
<description>Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPT32EH0</name>
|
|
<description>General PWM Timer 0 (32-bit Enhanced High Resolution)</description>
|
|
<baseAddress>0x40078000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>116</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x7C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x74</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x78</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x84</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>GTWP</name>
|
|
<description>General PWM Timer Write-Protection Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRKEY</name>
|
|
<description>GTWP Key Code</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Written to these bits, the WP bits write is permitted. </description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>The WP bits write is not permitted. </description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Register Write Disable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable writes to the register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable writes to the register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSTR</name>
|
|
<description>General PWM Timer Software Start Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTRT13</name>
|
|
<description>Channel 13 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT12</name>
|
|
<description>Channel 12 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT11</name>
|
|
<description>Channel 11 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT10</name>
|
|
<description>Channel 10 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT9</name>
|
|
<description>Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT8</name>
|
|
<description>Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT7</name>
|
|
<description>Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT6</name>
|
|
<description>Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT5</name>
|
|
<description>Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT4</name>
|
|
<description>Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT3</name>
|
|
<description>Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT2</name>
|
|
<description>Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT1</name>
|
|
<description>Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT0</name>
|
|
<description>Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSTP</name>
|
|
<description>General PWM Timer Software Stop Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTOP13</name>
|
|
<description>Channel 13 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP12</name>
|
|
<description>Channel 12 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP11</name>
|
|
<description>Channel 11 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP10</name>
|
|
<description>Channel 10 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP9</name>
|
|
<description>Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP8</name>
|
|
<description>Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP7</name>
|
|
<description>Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP6</name>
|
|
<description>Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP5</name>
|
|
<description>Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP4</name>
|
|
<description>Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP3</name>
|
|
<description>Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP2</name>
|
|
<description>Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP1</name>
|
|
<description>Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP0</name>
|
|
<description>Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCLR</name>
|
|
<description>General PWM Timer Software Clear Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLR13</name>
|
|
<description>Channel 13 GTCNT Count Clear</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR12</name>
|
|
<description>Channel 12 GTCNT Count Clear</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR11</name>
|
|
<description>Channel 11 GTCNT Count Clear</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR10</name>
|
|
<description>Channel 10 GTCNT Count Clear</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR9</name>
|
|
<description>Channel 9 GTCNT Count Clear</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR8</name>
|
|
<description>Channel 8 GTCNT Count Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR7</name>
|
|
<description>Channel 7 GTCNT Count Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR6</name>
|
|
<description>Channel 6 GTCNT Count Clear</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR5</name>
|
|
<description>Channel 5 GTCNT Count Clear</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR4</name>
|
|
<description>Channel 4 GTCNT Count Clear</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR3</name>
|
|
<description>Channel 3 GTCNT Count Clear</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR2</name>
|
|
<description>Channel 2 GTCNT Count Clear</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR1</name>
|
|
<description>Channel 1 GTCNT Count Clear</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR0</name>
|
|
<description>Channel 0 GTCNT Count Clear</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSSR</name>
|
|
<description>General PWM Timer Start Source Select Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTRT</name>
|
|
<description>Software Source Counter Start Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start by the GTSTR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start by the GTSTR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Start Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Start Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Start Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Start Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Start Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Start Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Start Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Start Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPSR</name>
|
|
<description>General PWM Timer Stop Source Select Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTOP</name>
|
|
<description>Software Source Counter Stop Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop by the GTSTP register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop by the GTSTP register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Stop Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTH input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Stop Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTG input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Stop Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Stop Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Stop Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Stop Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Stop Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Stop Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCSR</name>
|
|
<description>General PWM Timer Clear Source Select Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLR</name>
|
|
<description>Software Source Counter Clear Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear by the GTCLR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear by the GTCLR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Clear Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTH input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Clear Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTG input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Clear Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Clear Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Clear Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Clear Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Clear Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Clear Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTUPSR</name>
|
|
<description>General PWM Timer Up Count Source Select Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Count Up Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Count Up Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Count Up Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Count Up Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTE input.put</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Count Up Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Count Up Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Count Up Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Count Up Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDNSR</name>
|
|
<description>General PWM Timer Down Count Source Select Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Count Down Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Count Down Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Count Down Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Count Down Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTE input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Count Down Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Count Down Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Count Down Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Count Down Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTICASR</name>
|
|
<description>General PWM Timer Input Capture Source Select Register A</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASELCH</name>
|
|
<description>ELC_GPTH Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTH input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCG</name>
|
|
<description>ELC_GPTG Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCF</name>
|
|
<description>ELC_GPTF Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCE</name>
|
|
<description>ELC_GPTE Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTE input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCD</name>
|
|
<description>ELC_GPTD Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCC</name>
|
|
<description>ELC_GPTC Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCB</name>
|
|
<description>ELC_GPTB Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCA</name>
|
|
<description>ELC_GPTA Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTICBSR</name>
|
|
<description>General PWM Timer Input Capture Source Select Register B</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSELCH</name>
|
|
<description>ELC_GPTH Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCG</name>
|
|
<description>ELC_GPTG Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCF</name>
|
|
<description>ELC_GPTF Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCE</name>
|
|
<description>ELC_GPTE Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCD</name>
|
|
<description>ELC_GPTD Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCC</name>
|
|
<description>ELC_GPTC Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCB</name>
|
|
<description>ELC_GPTB Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCA</name>
|
|
<description>ELC_GPTA Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCR</name>
|
|
<description>General PWM Timer Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPCS</name>
|
|
<description>Timer Prescaler Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCLK/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCLK/4</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>PCLK/16</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCLK/64</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PCLK/256</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PCLK/1024</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Mode Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Saw-wave PWM mode (single buffer or double buffer possible)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Saw-wave one-shot pulse mode (fixed buffer operation)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Triangle-wave PWM mode 1 (32-bit transfer at crest) (single buffer or double buffer possible)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Triangle-wave PWM mode 3 (64-bit transfer at trough) fixed buffer operation)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CST</name>
|
|
<description>Count Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count operation is stopped</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count operation is performed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTUDDTYC</name>
|
|
<description>General PWM Timer Count Direction and Duty Setting Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OBDTYR</name>
|
|
<description>GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0percent/100percent duty setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Apply masked compare match output value to GTIOB[3:2] function after releasing 0percent/100percent duty setting.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDTYF</name>
|
|
<description>Forcible GTIOCB Output Duty Setting</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDTY</name>
|
|
<description>GTIOCB Output Duty Setting</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>GTIOCB pin duty is depend on compare match</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>GTIOCB pin duty is depend on compare match</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>GTIOCB pin duty 0percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>GTIOCB pin duty 100percent</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTYR</name>
|
|
<description>GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTYF</name>
|
|
<description>Forcible GTIOCA Output Duty Setting</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTY</name>
|
|
<description>GTIOCA Output Duty Setting</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>GTIOCA pin duty is depend on compare match</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>GTIOCA pin duty is depend on compare match</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>GTIOCA pin duty 0 percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>GTIOCA pin duty 100 percent</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDF</name>
|
|
<description>Forcible Count Direction Setting</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UD</name>
|
|
<description>Count Direction Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count down on GTCNT</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counts up on GTCNT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTIOR</name>
|
|
<description>General PWM Timer I/O Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFCSB</name>
|
|
<description>Noise Filter B Sampling Clock Select</description>
|
|
<lsb>30</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK/1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFBEN</name>
|
|
<description>Noise Filter B Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable noise filter for GTIOCB pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable noise filter for GTIOCB pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDF</name>
|
|
<description>GTIOCB Pin Disable Value Setting</description>
|
|
<lsb>25</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prohibit output disable</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Set GTIOCB pin to Hi-Z on output disable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Set GTIOCB pin to 0 on output disable</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Set GTIOCB pin to 1 on output disable.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBE</name>
|
|
<description>GTIOCB Pin Output Enable</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBHLD</name>
|
|
<description>GTIOCB Pin Output Setting at the Start/Stop Count</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTIOCB pin output level on counting start and stop based on the register setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Retain GTIOCB pin output level on counting start and stop</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDFLT</name>
|
|
<description>GTIOCB Pin Output Value Setting at the Count Stop</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on GTIOCB pin when counting stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on GTIOCB pin when counting stops</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTIOB</name>
|
|
<description>GTIOCB Pin Function Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>Initial output is Low. Low output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>Initial output is Low. High output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>Initial output is Low. High output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Initial output is High. Output retained at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>Initial output is High. Low output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Initial output is High. Low output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>Initial output is High. High output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>Initial output is High. High output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Initial output is High. High output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFCSA</name>
|
|
<description>Noise Filter A Sampling Clock Select</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK/1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFAEN</name>
|
|
<description>Noise Filter A Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable noise filter for GTIOCA pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable noise filter for GTIOCA pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADF</name>
|
|
<description>GTIOCA Pin Disable Value Setting</description>
|
|
<lsb>9</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prohibit output disable</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Set GTIOCA pin to Hi-Z on output disable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Set GTIOCA pin to 0 on output disable</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Set GTIOCA pin to 1 on output disable.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAE</name>
|
|
<description>GTIOCA Pin Output Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAHLD</name>
|
|
<description>GTIOCA Pin Output Setting at the Start/Stop Count</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTIOCA pin output level on counting start and stop based on the register setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Retain GTIOCA pin output level on counting start and stop</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADFLT</name>
|
|
<description>GTIOCA Pin Output Value Setting at the Count Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on GTIOCA pin when counting stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on GTIOCA pin when counting stops.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTIOA</name>
|
|
<description>GTIOCA Pin Function Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>Initial output is Low. Low output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>Initial output is Low. High output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>Initial output is Low. High output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Initial output is High. Output retained at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>Initial output is High. Low output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Initial output is High. Low output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>Initial output is High. High output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>Initial output is High. High output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Initial output is High. High output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTINTAD</name>
|
|
<description>General PWM Timer Interrupt Output Setting Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GRPABL</name>
|
|
<description>Same Time Output Level Low Disable Request Enable</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable same time output level low disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable same time output level low disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRPABH</name>
|
|
<description>Same Time Output Level High Disable Request Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable same time output level high disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable same time output level high disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRPDTE</name>
|
|
<description>Dead Time Error Output Disable Request Enable</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable dead time error output disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable dead time error output disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRP</name>
|
|
<description>Output Disable Source Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Select Group A output disable request</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select Group B output disable request</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select Group C output disable request</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select Group D output disable request.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRBDEN</name>
|
|
<description>GTADTRB Compare Match (Down-Counting) A/D Converter Start Request Interrupt Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable A/D converter start request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable A/D converter start request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRBUEN</name>
|
|
<description>GTADTRB Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable A/D converter start request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable A/D converter start request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRADEN</name>
|
|
<description>GTADTRA Compare Match (Down-Counting) A/D Converter Start Request Interrupt Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable A/D converter start request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable A/D converter start request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRAUEN</name>
|
|
<description>GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable A/D converter start request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable A/D converter start request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTST</name>
|
|
<description>General PWM Timer Status Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OABLF</name>
|
|
<description>Same Time Output Level Low Disable Request Enable</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTIOCA pin and GTIOCB pin don't output 0 at the same time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTIOCA pin and GTIOCB pin output 0 at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OABHF</name>
|
|
<description>Same Time Output Level High Disable Request Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTIOCA pin and GTIOCB pin don't output 1 at the same time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTIOCA pin and GTIOCB pin output 1 at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEF</name>
|
|
<description>Dead Time Error Flag</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No dead time error has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A dead time error has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODF</name>
|
|
<description>Output Disable Flag</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No output disable request is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An output disable request is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUCF</name>
|
|
<description>Count Direction Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTCNT counter is counting down</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTCNT counter is counting up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITCNT</name>
|
|
<description>GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.)</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCFPU</name>
|
|
<description>Underflow Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underflow (trough) has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An underflow (trough) has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFPO</name>
|
|
<description>Overflow Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overflow (crest) has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overflow (crest) has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFF</name>
|
|
<description>Input Compare Match Flag F</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRF is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRF is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFE</name>
|
|
<description>Input Compare Match Flag E</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRE is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRE is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFD</name>
|
|
<description>Input Compare Match Flag D</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRD is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRD is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFC</name>
|
|
<description>Input Compare Match Flag C</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRC is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRC is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFB</name>
|
|
<description>Input Capture/Compare Match Flag B</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No input capture/compare match of GTCCRB is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An input capture/compare match of GTCCRB is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFA</name>
|
|
<description>Input Capture/Compare Match Flag A</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No input capture/compare match of GTCCRA is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An input capture/compare match of GTCCRA is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTBER</name>
|
|
<description>General PWM Timer Buffer Enable Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADTDB</name>
|
|
<description>GTADTRB Double Buffer Operation</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single buffer operation (GTADTBRB --> GTADTRB) </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTTB</name>
|
|
<description>GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.</description>
|
|
<lsb>28</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transfer</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Transfer at crest</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transfer at trough</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transfer at both crest and trough</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTDA</name>
|
|
<description>GTADTRA Double Buffer Operation</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single buffer operation (GTADTBRA --> GTADTRA)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTTA</name>
|
|
<description>GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transfer</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Transfer at crest</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transfer at trough</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transfer at both crest and trough</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCRSWT</name>
|
|
<description>GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0.</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>GTPR Buffer Operation</description>
|
|
<lsb>20</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTPBR --> GTPR)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Double buffer operation (GTPDBR --> GTPBR --> GTPR)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Double buffer operation (GTPDBR --> GTPBR --> GTPR)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCRB</name>
|
|
<description>GTCCRB Buffer Operation</description>
|
|
<lsb>18</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTCCRB <--> GTCCRE)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCRA</name>
|
|
<description>GTCCRA Buffer Operation</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTCCRA <--> GTCCRC)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BD</name>
|
|
<description>BD[3]: GTDV Buffer Operation DisableBD[2]: GTADTR Buffer Operation DisableBD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable buffer operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable buffer operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTITC</name>
|
|
<description>General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADTBL</name>
|
|
<description>GTADTRB A/D Converter Start Request Link</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTAL</name>
|
|
<description>GTADTRA A/D Converter Start Request Link</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IVTT</name>
|
|
<description>GPT_OVF/GPT_UDF Interrupt Skipping Count Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No skipping</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Skipping count of 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Skipping count of 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Skipping count of 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Skipping count of 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Skipping count of 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Skipping count of 6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Skipping count of 7.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IVTC</name>
|
|
<description>GPT_OVF/GPT_UDF Interrupt Skipping Function Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Do not perform skipping</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Count and skip both overflow and underflow for saw waves and crest for triangle waves</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Count and skip both overflow and underflow for saw waves and trough for triangle waves</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLF</name>
|
|
<description>GTCCRF Compare Match Interrupt Link</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLE</name>
|
|
<description>GTCCRE Compare Match Interrupt Link</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLD</name>
|
|
<description>GTCCRD Compare Match Interrupt Link</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLC</name>
|
|
<description>GTCCRC Compare Match Interrupt Link</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLB</name>
|
|
<description>GTCCRB Compare Match/Input Capture Interrupt Link</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITLA</name>
|
|
<description>GTCCRA Compare Match/Input Capture Interrupt Link</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Link with GPTn_OVF/GPTn_UDF interrupt skipping function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCNT</name>
|
|
<description>General PWM Timer Counter</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCNT</name>
|
|
<description>Counter </description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRA</name>
|
|
<description>General PWM Timer Compare Capture Register A</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRA</name>
|
|
<description>Compare Capture Register A</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRB</name>
|
|
<description>General PWM Timer Compare Capture Register B</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRB</name>
|
|
<description>Compare Capture Register B</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRC</name>
|
|
<description>General PWM Timer Compare Capture Register C</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRC</name>
|
|
<description>Compare Capture Register C</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRE</name>
|
|
<description>General PWM Timer Compare Capture Register E</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRE</name>
|
|
<description>Compare Capture Register E</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRD</name>
|
|
<description>General PWM Timer Compare Capture Register D</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRD</name>
|
|
<description>Compare Capture Register D</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRF</name>
|
|
<description>General PWM Timer Compare Capture Register F</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRF</name>
|
|
<description>Compare Capture Register F</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPR</name>
|
|
<description>General PWM Timer Cycle Setting Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTPR</name>
|
|
<description>Cycle Setting Register</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPBR</name>
|
|
<description>General PWM Timer Cycle Setting Buffer Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTPBR</name>
|
|
<description>Cycle Setting Buffer Register</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPDBR</name>
|
|
<description>General PWM Timer Cycle Setting Double-Buffer Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTPDBR</name>
|
|
<description>Cycle Setting Double-Buffer Register</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTRA</name>
|
|
<description>A/D Converter Start Request Timing Register A</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTRA</name>
|
|
<description>A/D Converter Start Request Timing Register A</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTRB</name>
|
|
<description>A/D Converter Start Request Timing Register B</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTRB</name>
|
|
<description>A/D Converter Start Request Timing Register B</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTBRA</name>
|
|
<description>A/D Converter Start Request Timing Buffer Register A</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTBRA</name>
|
|
<description>A/D Converter Start Request Timing Buffer Register A</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTBRB</name>
|
|
<description>A/D Converter Start Request Timing Buffer Register B</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTBRB</name>
|
|
<description>A/D Converter Start Request Timing Buffer Register B</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTDBRA</name>
|
|
<description>A/D Converter Start Request Timing Double-Buffer Register A</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTDBRA</name>
|
|
<description>A/D Converter Start Request Timing Double-Buffer Register A</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTADTDBRB</name>
|
|
<description>A/D Converter Start Request Timing Double-Buffer Register B</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTADTDBRB</name>
|
|
<description>A/D Converter Start Request Timing Double-Buffer Register B</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDTCR</name>
|
|
<description>General PWM Timer Dead Time Control Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDFER</name>
|
|
<description>GTDVD Setting</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTDVU and GTDVD separately</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatically set the value written to GTDVU to GTDVD</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDBDE</name>
|
|
<description>GTDVD Buffer Operation Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTDVD buffer operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTDVD buffer operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDBUE</name>
|
|
<description>GTDVU Buffer Operation Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTDVU buffer operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTDVU buffer operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Negative-Phase Waveform Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTCCRB without using GTDVU and GTDVD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use GTDVU and GTDVD to set the compare match value for negative-phase waveform with automatic dead time in GTCCRB.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDVU</name>
|
|
<description>General PWM Timer Dead Time Value Register U</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTDVU</name>
|
|
<description>Dead Time Value Register U</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDVD</name>
|
|
<description>General PWM Timer Dead Time Value Register D</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTDVD</name>
|
|
<description>Dead Time Value Register D</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDBU</name>
|
|
<description>General PWM Timer Dead Time Buffer Register U</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTDVU</name>
|
|
<description>Dead Time Buffer Register U</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDBD</name>
|
|
<description>General PWM Timer Dead Time Buffer Register D</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTDBD</name>
|
|
<description>Dead Time Buffer Register D</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSOS</name>
|
|
<description>General PWM Timer Output Protection Function Status Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOS</name>
|
|
<description>Output Protection Function Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal operation</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Protected state (GTCCRA = 0 is set during transfer at trough or crest)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Protected state (GTCCRA >= GTPR is set during transfer at trough)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Protected state (GTCCRA >= GTPR is set during transfer at crest)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSOTR</name>
|
|
<description>General PWM Timer Output Protection Function Temporary Release Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOTR</name>
|
|
<description>Output Protection Function Temporary Release</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not release protected state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Release protected state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32EH1</name>
|
|
<description>General PWM Timer 1 (32-bit Enhanced High Resolution)</description>
|
|
<baseAddress>0x40078100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32EH2</name>
|
|
<description>General PWM Timer 2 (32-bit Enhanced High Resolution)</description>
|
|
<baseAddress>0x40078200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32EH3</name>
|
|
<description>General PWM Timer 3 (32-bit Enhanced High Resolution)</description>
|
|
<baseAddress>0x40078300</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32E4</name>
|
|
<description>General PWM Timer 4 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32E5</name>
|
|
<description>General PWM Timer 5 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078500</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32E6</name>
|
|
<description>General PWM Timer 6 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078600</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT32EH0">
|
|
<name>GPT32E7</name>
|
|
<description>General PWM Timer 7 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078700</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBHS</name>
|
|
<description>USB 2.0 High-Speed Module</description>
|
|
<baseAddress>0x40060000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x22</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2E</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x36</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x46</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x64</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x68</offset>
|
|
<size>26</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x90</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x92</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD0</offset>
|
|
<size>22</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x140</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x144</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x150</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x160</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYSCFG</name>
|
|
<description>System Configuration Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0020</resetValue>
|
|
<resetMask>0x01F1</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNEN</name>
|
|
<description>Single End Receiver Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single end receiver operation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single end receiver operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSE</name>
|
|
<description>High-Speed Operation Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-speed operation is disabled.(When the function controller function is selected: Full speed, When the host controller function is selected: Full/low speed)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-speed operation is enabled (the controller detects the communication speed).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCFM</name>
|
|
<description>Controller Function Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Function controller function is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host controller function is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRPD</name>
|
|
<description>D+/D- Line Resistor Control</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulling down the line is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulling down the line is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPRPU</name>
|
|
<description>D+ Line Resistor Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulling up the line is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulling up the line is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBE</name>
|
|
<description>USB Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB operation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSWAIT</name>
|
|
<description>CPU Bus Wait Register</description>
|
|
<addressOffset>0x002</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000F</resetValue>
|
|
<resetMask>0x3F3F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BWAIT</name>
|
|
<description>CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles)</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWAIT</name>
|
|
<description>BWAIT wait(s) ( BWAIT + 2 access cycles )</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSSTS0</name>
|
|
<description>System Configuration Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0060</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVCMON</name>
|
|
<description>External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTACT</name>
|
|
<description>Host Sequencer Status Monitor</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host sequencer is stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host sequencer is operating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFEA</name>
|
|
<description>SOF Active Monitor While Host Controller Function is Selected.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SOF output is stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SOF output is operating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMON</name>
|
|
<description>ID0 Pin Monitor</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ID0 = Low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID0 = High</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LNST</name>
|
|
<description>USB Data Line Status Monitor</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SE0 (During Low-Speed Operation:only when the host controller function is selected or During Full-Speed Operation) /Squelch (During Hi-Speed Operation or During Chirp Operation)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>K-State (During Low-Speed Operation:only when the host controller function is selected) /J-State (During Full-Speed Operation) /Unsquelch (During Hi-Speed Operation) /Chirp J (During Chirp Operation)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>J-State (During Low-Speed Operation:only when the host controller function is selected) /K-State (During Full-Speed Operation) /Invalid (During Hi-Speed Operation) /Chirp K (During Chirp Operation)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>SE1 (During Low-Speed Operation:only when the host controller function is selected or During Full-Speed Operation) /Invalid (During Hi-Speed Operation or During Chirp Operation)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSTA</name>
|
|
<description>PLL Status Register</description>
|
|
<addressOffset>0x006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLLOCK</name>
|
|
<description>PLL Lock Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PLL is not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PLL is locked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVSTCTR0</name>
|
|
<description>Device State Control Register 0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0FF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HNPBTOA</name>
|
|
<description>Host Negotiation Protocol (HNP) Control Use this bit when switching from device B to device A in OTGmode. If the HNPBTOA bit is 1, the internal function controlremains in the Suspend state until the HNP processing endseven if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXICEN</name>
|
|
<description>USBHS_EXICEN Output Pin Control</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on external USBHS_EXICEN pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on external USBHS_EXICEN pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSEN</name>
|
|
<description>USBHS_VBUSEN Output Pin Control</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on external USBHS_VBUSEN pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on external USBHS_VBUSEN pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP</name>
|
|
<description>Remote Wakeup Output for the Device Controller Operation</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not output remote wakeup signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output remote wakeup signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUPE</name>
|
|
<description>Remote Wakeup Detection Enable for the Host Controller Operation</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable downstream port remote wakeup</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable downstream port remote wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBRST</name>
|
|
<description>USB Bus Reset Output for the Host Controller Operation</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not output USB bus reset signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output USB bus reset signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>Resume Signal Output for the Host Controller Operation</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not output resume signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output resume signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UACT</name>
|
|
<description>USB Bus Operation Enable for the Host Controller Operation</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable downstream port (disable SOF or micro-SOF transmission)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable downstream port (enable SOF or micro-SOF transmission).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RHST</name>
|
|
<description>USB Bus Reset Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Communication speed not determined</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Low-speed connection(When the host controller function is selected) /USB bus reset in progress or low-speed connection(When the function controller function is selected)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Full-speed connection(When the host controller function is selected) /USB bus reset in progress or full-speed connection(When the function controller function is selected)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>USB bus reset in progress(When the host controller function is selected)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TESTMODE</name>
|
|
<description>USB Test Mode Register </description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTST</name>
|
|
<description>Test Mode</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Normal operation</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Test_J TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Test_K TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Test_SE0_NAK TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Test_Packet TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Reserved TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Reserved TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Reserved TestMode(When the Function Controller Function is Selected)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Test_J TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Test_K TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Test_SE0_NAK TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Test_Packet TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Test_Force_EnableTestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Reserved TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Reserved TestMode(When the Host Controller Function is Selected)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>CFIFO Port Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO Port.Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOL</name>
|
|
<description>CFIFO Port Register L</description>
|
|
<alternateRegister>CFIFO</alternateRegister>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOH</name>
|
|
<description>CFIFO Port Register H</description>
|
|
<alternateRegister>CFIFO</alternateRegister>
|
|
<addressOffset>0x016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOLL</name>
|
|
<description>CFIFO Port Register LL</description>
|
|
<alternateRegister>CFIFOL</alternateRegister>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOHH</name>
|
|
<description>CFIFO Port Register HH</description>
|
|
<alternateRegister>CFIFOH</alternateRegister>
|
|
<addressOffset>0x017</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFO</name>
|
|
<description>D0FIFO Port Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOL</name>
|
|
<description>D0FIFO Port Register L</description>
|
|
<alternateRegister>D0FIFO</alternateRegister>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOH</name>
|
|
<description>D0FIFO Port Register H</description>
|
|
<alternateRegister>D0FIFO</alternateRegister>
|
|
<addressOffset>0x01A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOLL</name>
|
|
<description>D0FIFO Port Register LL</description>
|
|
<alternateRegister>D0FIFOL</alternateRegister>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOHH</name>
|
|
<description>D0FIFO Port Register HH</description>
|
|
<alternateRegister>D0FIFOH</alternateRegister>
|
|
<addressOffset>0x01B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFO</name>
|
|
<description>D1FIFO Port Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOL</name>
|
|
<description>D1FIFO Port Register L</description>
|
|
<alternateRegister>D1FIFO</alternateRegister>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOH</name>
|
|
<description>D1FIFO Port Register H</description>
|
|
<alternateRegister>D1FIFO</alternateRegister>
|
|
<addressOffset>0x01E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOLL</name>
|
|
<description>D1FIFO Port Register LL</description>
|
|
<alternateRegister>D1FIFOL</alternateRegister>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOHH</name>
|
|
<description>D1FIFO Port Register HH</description>
|
|
<alternateRegister>D1FIFOH</alternateRegister>
|
|
<addressOffset>0x01F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOSEL</name>
|
|
<description>CFIFO Port Select Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xCD2F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from CFIFO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Decrement DTLN[11:0] flags each time receive data is read from CFIFO.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not rewind buffer pointer (Writing 0 has no effect.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rewind buffer pointer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>CFIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit width</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16-bit width</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32-bit width</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>FIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>FIFO Port Access Direction when DCP is Selected</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Select reading from the FIFO buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Select writing to the FIFO buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>FIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>DCP</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>PIPE1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>PIPE2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>PIPE3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PIPE4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>PIPE5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PIPE6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PIPE7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>PIPE8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>PIPE9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOSEL</name>
|
|
<description>D0FIFO Port Select Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFD0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DTLN bits are cleared when all of the receive data has been read from the CFIFO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DTLN bits are decremented each time the receive data is read from the CFIFO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer pointer is not rewound</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer pointer is rewound</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCLRM</name>
|
|
<description>Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto buffer clear mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto buffer clear mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQE</name>
|
|
<description>UCL_Dx_DREQ Signal Output Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>FIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit width</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16-bit width</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32-bit width</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>FIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>FIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No pipe specified</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Pipe1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Pipe 2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Pipe 3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Pipe 4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Pipe 5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Pipe 6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Pipe 7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Pipe 8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Pipe 9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOSEL</name>
|
|
<description>D1FIFO Port Select Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFD0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DTLN bits are cleared when all of the receive data has been read from the CFIFO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DTLN bits are decremented each time the receive data is read from the CFIFO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer pointer is not rewound</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer pointer is rewound</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCLRM</name>
|
|
<description>Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto buffer clear mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto buffer clear mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQE</name>
|
|
<description>UCL_Dx_DREQ Signal Output Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>FIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit width</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16-bit width</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32-bit width</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>FIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>FIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No pipe specified</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Pipe 1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Pipe 2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Pipe 3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Pipe 4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Pipe 5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Pipe 6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Pipe 7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Pipe 8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Pipe 9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOCTR</name>
|
|
<description>CFIFO Port Control Register</description>
|
|
<addressOffset>0x022</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xEFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear FIFO buffer on the CPU side.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port ReadyIndicates whether the FIFO port can be accessed.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data Length.Indicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOCTR</name>
|
|
<description>D0FIFO Port Control Register </description>
|
|
<addressOffset>0x02A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xEFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear FIFO buffer on the CPU side.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port ReadyIndicates whether the FIFO port can be accessed.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data Length.Indicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOCTR</name>
|
|
<description>D1FIFO Port Control Register </description>
|
|
<addressOffset>0x02E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xEFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear FIFO buffer on the CPU side.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port ReadyIndicates whether the FIFO port can be accessed.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data Length.Indicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENB0</name>
|
|
<description>Interrupt Enable Register 0</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBSE</name>
|
|
<description>VBUS Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSME</name>
|
|
<description>Resume Interrupt Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFE</name>
|
|
<description>Frame Number Update Interrupt Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVSE</name>
|
|
<description>Device State Transition Interrupt Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRE</name>
|
|
<description>Control Transfer Stage Transition Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEMPE</name>
|
|
<description>Buffer Empty Interrupt Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRDYE</name>
|
|
<description>Buffer Not Ready Response Interrupt Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDYE</name>
|
|
<description>Buffer Ready Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENB1</name>
|
|
<description>Interrupt Enable Register 1 </description>
|
|
<addressOffset>0x032</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xDB71</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRCRE</name>
|
|
<description>OVRCRE Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCHGE</name>
|
|
<description>USB Bus Change Interrupt Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCHE</name>
|
|
<description>Disconnection Detection Interrupt Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATTCHE</name>
|
|
<description>Connection Detection Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1RSMENDE</name>
|
|
<description>L1 Resume End Interrupt Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPMENDE</name>
|
|
<description>LPM Transaction End Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOFERRE</name>
|
|
<description>EOF Error Detection Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIGNE</name>
|
|
<description>Setup Transaction Error Interrupt Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKE</name>
|
|
<description>Setup Transaction Normal Response Interrupt Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDDETINTE</name>
|
|
<description>PDDETINT Detection Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRDYENB</name>
|
|
<description>BRDY Interrupt Enable Register</description>
|
|
<addressOffset>0x036</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPEBRDYE</name>
|
|
<description>BRDY Interrupt Enable for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NRDYENB</name>
|
|
<description>NRDY Interrupt Enable Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPENRDYE</name>
|
|
<description>NRDY Interrupt Enable for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BEMPENB</name>
|
|
<description>BEMP Interrupt Enable Register</description>
|
|
<addressOffset>0x03A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPEBEMPE</name>
|
|
<description>BEMP Interrupt Enable for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFCFG</name>
|
|
<description>SOF Pin Configuration Register </description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x017C</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRNENSEL</name>
|
|
<description>Transaction-Enabled Time Select.The transfer efficiency can be improved by setting this bit to 1 if no low-speed device is connected directly or via FS-HUB to the USB port.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>For non-low-speed communication</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>For low-speed communication</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDYM</name>
|
|
<description>PIPEBRDY Interrupt Status Clear Timing.This bit can be set only in the initial setting (before communications).The setting cannot be changed once communication starts.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software clears the status.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTL</name>
|
|
<description>Interrupt Output Sense Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Edge sense</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Level sense</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGESTS</name>
|
|
<description>Interrupt Edge Processing Status Monitor</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt edge processing is not run</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt edge processing is running</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PHYSET</name>
|
|
<description>PHY Setting Register</description>
|
|
<addressOffset>0x03E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0033</resetValue>
|
|
<resetMask>0x0B3B</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HSEB</name>
|
|
<description>CL-Only Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CL-only mode is not activated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CL-only mode is activated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REPSTART</name>
|
|
<description>Forcibly Start Terminating Resistance Adjustment</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Terminating resistance adjustment is forcibly started</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Terminating resistance adjustment is not forcibly started</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REPSEL</name>
|
|
<description>Terminating Resistance Adjustment Cycle</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No cycle is set.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Adjust terminating resistance at 16-second intervals. </description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Adjust terminating resistance at 64-second intervals.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Adjust terminating resistance at 128-second intervals.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Input System Clock Frequency</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Setting Prohibited</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12 MHz</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>20 MHz</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>24 MHz</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDPEN</name>
|
|
<description>Charging Downstream Port Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable charging downstream port</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable charging downstream port</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLRESET</name>
|
|
<description>PLL Reset Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable PLL reset control for UTMI_PHY</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable PLL reset control for UTMI_PHY</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRPD</name>
|
|
<description>Power-Down Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not enter low-power consumption mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter low-power consumption mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTS0</name>
|
|
<description>Interrupt Status Register 0</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBINT</name>
|
|
<description>VBUS Interrupt Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VBUS interrupt is not generated on detecting a change in the USBHS_VBUS pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VBUS interrupt is generated on detecting a change in the USBHS_VBUS pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESM</name>
|
|
<description>Resume Interrupt Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resume interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resume interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFR</name>
|
|
<description>Frame Number Refresh Interrupt Status</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SOF interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SOF interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVST</name>
|
|
<description>Device State Transition Interrupt Status</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device state transition interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device state transition interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRT</name>
|
|
<description>Control Transfer Stage Transition Interrupt Status</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control transfer stage transition interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control transfer stage transition interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEMP</name>
|
|
<description>Buffer Empty Interrupt Status</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BEMP interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BEMP interrupts are not generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRDY</name>
|
|
<description>Buffer Not Ready Interrupt Status</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NRDY interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NRDY interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDY</name>
|
|
<description>Buffer Ready Interrupt Status</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BRDY interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BRDY interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBSTS</name>
|
|
<description>VBUS Input Status</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The USBHS_VBUS pin is low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The USBHS_VBUS pin is high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVSQ</name>
|
|
<description>Device State</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Powered state</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Default state</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Address state</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Configured state</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Suspended state(1xx)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>USB Request Reception</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Setup packet reception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSQ</name>
|
|
<description>Control Transfer Stage</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Idle or setup stage</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Control read data stage</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Control read status stage</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Control write data stage</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Control write status stage</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Control write (no data) status stage</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Control transfer sequence error</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTS1</name>
|
|
<description>Interrupt Status Register 1</description>
|
|
<addressOffset>0x042</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xDB71</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRCR</name>
|
|
<description>Overcurrent Interrupt Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OVRCR interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OVRCR interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCHG</name>
|
|
<description>USB Bus Change Interrupt Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BCHG interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BCHG interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCH</name>
|
|
<description>USB Disconnection Detection Interrupt Status</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DTCH interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DTCH interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATTCH</name>
|
|
<description>USB Connection Detection Interrupt Status</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ATTCH interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ATTCH interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1RSMEND</name>
|
|
<description>L1 Resume End Interrupt Status</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>L1RSMEND interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>L1RSMEND interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPMEND</name>
|
|
<description>LPM Transaction End Interrupt Status</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPMEND interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPMEND interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOFERR</name>
|
|
<description>EOF Error Detection Interrupt Status</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOFERR interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOFERR interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Setup Transaction Error Interrupt Status</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SIGN interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SIGN interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACK</name>
|
|
<description>Setup Transaction Normal Response Interrupt Status</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SACK interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SACK interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDDETINT</name>
|
|
<description>PDDET Detection Interrupt Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDDET interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDDET interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRDYSTS</name>
|
|
<description>BRDY Interrupt Status Register</description>
|
|
<addressOffset>0x046</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPEBRDY</name>
|
|
<description>BRDY Interrupt Status for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NRDYSTS</name>
|
|
<description>NRDY Interrupt Status Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPENRDY</name>
|
|
<description>NRDY Interrupt Status for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BEMPSTS</name>
|
|
<description>BEMP Interrupt Status Register</description>
|
|
<addressOffset>0x04A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPEBEMP</name>
|
|
<description>BEMP Interrupt Status for Each Pipe</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRMNUM</name>
|
|
<description>Frame Number Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xC7FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRN</name>
|
|
<description>Overrun/Underrun Detection Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCE</name>
|
|
<description>CRC Error Detection Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRNM</name>
|
|
<description>Frame Number.Indicate the latest frame number.</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UFRMNUM</name>
|
|
<description>uFrame Number Register </description>
|
|
<addressOffset>0x04E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x8007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVCHG</name>
|
|
<description>Device State Change</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UFRNM</name>
|
|
<description>MicroframeIndicate the microframe number.</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBADDR</name>
|
|
<description>USB Address Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x077F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STSRECOV0</name>
|
|
<description>Status Recovery</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBADDR</name>
|
|
<description>USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully.</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBREQ</name>
|
|
<description>USB Request Type Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BREQUEST</name>
|
|
<description>USB request bRequest value Finction controller selected : read-only Host controller selected : read-write</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BMREQUESTTYPE</name>
|
|
<description>USB request bmRequestType value Finction controller selected : read-only Host controller selected : read-write</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBVAL</name>
|
|
<description>USB Request Value Register</description>
|
|
<addressOffset>0x056</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WVALUE</name>
|
|
<description>Value of USB request wValue Finction controller selected : read-only Host controller selected : read-write</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINDX</name>
|
|
<description>USB Request Index Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDEX</name>
|
|
<description>Value of USB request wIndex Finction controller selected : read-only Host controller selected : read-write</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBLENG</name>
|
|
<description>USB Request Length Register </description>
|
|
<addressOffset>0x05A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLENGTH</name>
|
|
<description>Value of USB request wLength Finction controller selected : read-only Host controller selected : read-write</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPCFG</name>
|
|
<description>DCP Configuration Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0190</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMD</name>
|
|
<description>Continuous Transfer Mode</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-continuous transfer mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous transfer mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTNAK</name>
|
|
<description>Pipe Blocking on End of Transfer</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The pipe remains open after transfer ends.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The pipe is blocked after transfer ends.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data receiving direction</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data transmitting direction</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPMAXP</name>
|
|
<description>DCP Maximum Packet Size Register </description>
|
|
<addressOffset>0x05E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0xF07F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device SelectThese bits specify the address of the destination function device for control transfer when the host controller function is selected.</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Address 0000</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Address 0001</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Address 0010</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Address 0011</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Address 0100</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Address 0101</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXPS</name>
|
|
<description>Maximum Packet SizeThese bits specify the maximum data payload (maximum packet size) for the DCP.</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPCTR</name>
|
|
<description>DCP Control Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0xF1F7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTS</name>
|
|
<description>Buffer Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUREQ</name>
|
|
<description>SETUP Token Transmission</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmits the setup packet.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCLR</name>
|
|
<description>Split Transaction CSPLIT Status Clear</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the CSSTS bit to 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSSTS</name>
|
|
<description>Split Transaction COMPLETE SPLIT(CSPLIT) Status</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>START-SPLIT(SSPLIT) transaction processing is in progress or processing for devices that do not use Split Transaction is in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CSPLIT transaction processing is in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUREQCLR</name>
|
|
<description>SUREQ Bit Clear</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the SUREQ bit to 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQCLR</name>
|
|
<description>Toggle Bit Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQSET</name>
|
|
<description>Toggle Bit Set</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQMON</name>
|
|
<description>Sequence Toggle Bit Monitor</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DATA0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DATA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBUSY</name>
|
|
<description>Pipe Busy</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The relevant pipe is not used for the USB bus.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The relevant pipe is in use for the USB bus.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINGE</name>
|
|
<description>PING Token Issue Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Issuing PING token is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Normal PING operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPL</name>
|
|
<description>Control Transfer End Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Completion of control transfer is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Completion of control transfer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Response PID</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NAK response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUF response (depending on buffer state)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL response</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>STALL response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPESEL</name>
|
|
<description>Pipe Window Select Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPESEL</name>
|
|
<description>Pipe Window SelectThese bits specify the pipe for registers at addresses 68H to 6EH.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No pipe selected</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>PIPE1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>PIPE2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>PIPE3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PIPE4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>PIPE5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PIPE6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PIPE7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>PIPE8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>PIPE9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPECFG</name>
|
|
<description>Pipe Configuration Register</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xC79F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Transfer Type</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Pipe not used</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bulk transfer</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Interrupt transfer</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Isochronous transfer</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFRE</name>
|
|
<description>BRDY Interrupt Operation Specification</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BRDY interrupt upon transmitting or receiving data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BRDY interrupt upon completion of reading data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLB</name>
|
|
<description>Double Buffer Mode</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMD</name>
|
|
<description>Continuous Transfer Mode</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Discontinuous transfer mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous transfer mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTNAK</name>
|
|
<description>Pipe Disabled at End of Transfer</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The pipe is continued at the end of transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The pipe is disabled at the end of transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiving direction</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitting direction</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>the selected pipe is not used</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>specify the endpoint number for the selected pipe.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPEBUF</name>
|
|
<description>Pipe Buffer Register</description>
|
|
<addressOffset>0x06A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7CFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFSIZE</name>
|
|
<description>Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes</description>
|
|
<lsb>10</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUFSIZE</name>
|
|
<description>( BUFSIZE + 1 ) x 64 kbytes</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFNMB</name>
|
|
<description>Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h).</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x04</minimum>
|
|
<maximum>0x87</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUFNMB</name>
|
|
<description>specify the FIFO buffer number of the selected pipe (04h to 87h).</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPEMAXP</name>
|
|
<description>Pipe Maximum Packet Size Register</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xF7FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device SelectThese bits specify the address of the peripheral device when the host controller function is selected.</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x0</minimum>
|
|
<maximum>0xA</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEVSEL</name>
|
|
<description>Address=DEVSEL</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXPS</name>
|
|
<description>Maximum Packet SizeThese bits specify the maximum data payload (maximum packet size) for the selected pipe.A size of 1h to 40h bytes can be set for PIPE6 to PIPE9.</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x01</minimum>
|
|
<maximum>0x40</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MXPS</name>
|
|
<description>Maximum packet size</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPEPERI</name>
|
|
<description>Pipe Cycle Control Register</description>
|
|
<addressOffset>0x06E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x1007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IFIS</name>
|
|
<description>Isochronous IN Buffer Flush</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer is not flushed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer is flushed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IITV</name>
|
|
<description>Interval Error Detection IntervalThese bits specify the transfer interval timing for the selected pipe as n-th power of 2 of the frame timing.</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>9</dim>
|
|
<dimIncrement>0x002</dimIncrement>
|
|
<dimIndex>1-9</dimIndex>
|
|
<name>PIPE%sCTR</name>
|
|
<description>PIPE Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xF7E3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTS</name>
|
|
<description>Buffer StatusThis bit indicates the FIFO buffer status for the relevant pipe.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INBUFM</name>
|
|
<description>Transmit Buffer MonitorThis bit indicates the FIFO buffer status for the relevant pipe in the transmitting direction.</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmittable data is present in the FIFO buffer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmittable data is present in the FIFO buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCLR</name>
|
|
<description>CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CSSTS bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSSTS</name>
|
|
<description>CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CSplit Transaction processing is in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATREPM</name>
|
|
<description>Auto Response ModeThis bit enables or disables auto response mode for the relevant pipe.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto response mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto response mode is enabled (Transmission: zero-length packet response, Reception: NAK response and NRDY interrupt)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACLRM</name>
|
|
<description>Auto Buffer Clear ModeThis bit enables or disables auto buffer clear mode for the relevant pipe</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled (all buffers are initialized)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQCLR</name>
|
|
<description>Toggle Bit ClearThis bit is set to 1 when the expected value of the sequence toggle bit for the next transaction of the relevant pipe is cleared to DATA0</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQSET</name>
|
|
<description>Toggle Bit SetThis bit is set to 1 when the expected value of the sequence toggle bit for the next transaction of the relevant pipe is set for DATA1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQMON</name>
|
|
<description>Toggle Bit ConfirmationThis bit indicates the expected value of the sequence toggle bit for the next transaction of the relevant pipe</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DATA0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DATA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBUSY</name>
|
|
<description>Pipe BusyThis bit indicates whether the relevant pipe is being used for the USB bus</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The relevant pipe is not used for the USB bus.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The relevant pipe is in use for the USB bus.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Response PIDThese bits specify the response type for the next transaction of the relevant pipe.</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NAK response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUF response (depending on buffer state)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL response</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>STALL response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x004</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>PIPE%sTRE</name>
|
|
<description>PIPE Transaction Counter Enable Register </description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0300</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRENB</name>
|
|
<description>Transaction Counter EnableEnables or disables the transaction counter function.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transaction counter function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The transaction counter function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRCLR</name>
|
|
<description>Transaction Counter ClearSetting this bit to 1 allows clearing the transaction counter to 0.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current counter value is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x004</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>PIPE%sTRN</name>
|
|
<description>PIPE Transaction Counter Register</description>
|
|
<addressOffset>0x092</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRNCNT</name>
|
|
<description>Transaction CounterWhen writing to: Specify the number of total packets (number of transactions) to be received by the relevant PIPE.When read from: When TRENB = 0: Indicate the specified number of transactions.When TRENB = 1: Indicate the number of currently counted transactions.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>10</dim>
|
|
<dimIncrement>0x002</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>DEVADD%s</name>
|
|
<description>Device Address Configuration Register</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7FC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UPPHUB</name>
|
|
<description>Communication Target Connecting Hub Register</description>
|
|
<lsb>11</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x0000</minimum>
|
|
<maximum>0x1010</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Directly connected to the port of the USBHS.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPPHUB</name>
|
|
<description>USB address of the hub</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HUBPORT</name>
|
|
<description>Communication Target Connecting Hub Port</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Directly connected to the port of the USBHS. </description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Port number of the hub</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBSPD</name>
|
|
<description>Transfer Speed of Communication Target Device</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>DEVADDx is not used.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Low speed</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Full speed</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High speed</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVADDA</name>
|
|
<description>Device Address Configuration Register A</description>
|
|
<addressOffset>0x0E4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7FC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UPPHUB</name>
|
|
<description>Communication Target Connecting Hub Register</description>
|
|
<lsb>11</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x0000</minimum>
|
|
<maximum>0x1010</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Directly connected to the port of the USBHS.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPPHUB</name>
|
|
<description>USB address of the hub</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HUBPORT</name>
|
|
<description>Communication Target Connecting Hub Port</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Directly connected to the port of the USBHS. </description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Port number of the hub</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBSPD</name>
|
|
<description>Transfer Speed of Communication Target Device</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>DEVADDA is not used.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Low speed</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Full speed</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High speed</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPCTRL</name>
|
|
<description>Low Power Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0181</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWUPM</name>
|
|
<description>Resume Return Mode Setting</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware does not recover while CPU clock inactive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware recovers while CPU clock inactive.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSTS</name>
|
|
<description>Low Power Status Register</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x510B</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPENDM</name>
|
|
<description>UTMI SuspendM Control</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UTMI suspension mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UTMI normal mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCCTRL</name>
|
|
<description>Battery Charging Control Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x033F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDDETSTS</name>
|
|
<description>PDDET Status</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PDDET pin is at low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PDDET pin is at high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHGDETSTS</name>
|
|
<description>CHGDET Status</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The CHGDET pin is at low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CHGDET pin is at high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCPMODE</name>
|
|
<description>DCP Mode Control</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RDCP_DAT resistor is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RDCP_DAT resistor is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDMSRCE</name>
|
|
<description>VDMSRC Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The VDM_SRC circuit is disabled. (Initial value)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The VDM_SRC circuit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDPSINKE</name>
|
|
<description>IDPSINK Control</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The IDP_SINK circuit is disabled. (Initial value)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The IDP_SINK circuit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDPSRCE</name>
|
|
<description>VDPSRC Control</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The VDP_SRC circuit is disabled. (Initial value)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The VDP_SRC circuit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMSINKE</name>
|
|
<description>IDMSINK Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The IDM_SINK circuit is disabled. (Initial value)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The IDM_SINK circuit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDPSRCE</name>
|
|
<description>IDPSRC Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The IDP_SRC circuit is disabled. (Initial value)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The IDP_SRC circuit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PL1CTRL1</name>
|
|
<description>Function L1 Control Register 1</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x4FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>L1EXTMD</name>
|
|
<description>PHY Control Mode at L1 Return</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SUSPENDM is not set by hardware when Host K is received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SUSPENDM is set by hardware when Host K is received.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIRDTHR</name>
|
|
<description>L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL.</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DVSQ</name>
|
|
<description>DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0].</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Powered state</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Default state</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Address state</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Configured state</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Suspended state</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Suspended state</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Suspended state</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Suspended state</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>L1 state</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>L1 state</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>L1 state</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>L1 state</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1NEGOMD</name>
|
|
<description>L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1RESPMD</name>
|
|
<description>L1 Response Mode</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NYET</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ACK</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>According to the L1NEGOMD bit</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1RESPEN</name>
|
|
<description>L1 Response Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPM is not supported.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPM is supported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PL1CTRL2</name>
|
|
<description>Function L1 Control Register 2</description>
|
|
<addressOffset>0x146</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x1F00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RWEMON</name>
|
|
<description>RWE Value Monitor</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RWE bit value of the LPM token received last is reflected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RWE bit value of the LPM token received last is reflected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIRDMON</name>
|
|
<description>HIRD Value Monitor</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The HIRD field value of the LPM token received last is reflected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The HIRD field value of the LPM token received last is reflected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HL1CTRL1</name>
|
|
<description>Host L1 Control Register 1</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>L1STATUS</name>
|
|
<description>L1 Request Completion Status</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>ACK received</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>NYET received</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL received</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transaction error</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1REQ</name>
|
|
<description>L1 Transition Request</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This bit is cleared to 0 by hardware when the LPM transaction is completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set this bit to 1 when requesting a transition to the L1 state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HL1CTRL2</name>
|
|
<description>Host L1 Control Register 2</description>
|
|
<addressOffset>0x14A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x9F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BESL</name>
|
|
<description>BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L1RWE</name>
|
|
<description>LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIRD</name>
|
|
<description>LPM Token HIRD</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>125 us(BESL = 0) / 100 us(BESL = 1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>200 us(BESL = 0) / 150 us(BESL = 1)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>275 us(BESL = 0) / 250 us(BESL = 1)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>350 us(BESL = 0) / 350 us(BESL = 1)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>425 us(BESL = 0) / 450 us(BESL = 1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>500 us(BESL = 0) / 950 us(BESL = 1)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>575 us(BESL = 0) / 1950 us(BESL = 1)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>650 us(BESL = 0) / 2950 us(BESL = 1)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>725 us(BESL = 0) / 3950 us(BESL = 1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>800 us(BESL = 0) / 4950 us(BESL = 1)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>875 us(BESL = 0) / 5950 us(BESL = 1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>950 us(BESL = 0) / 6950 us(BESL = 1)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L1ADDR</name>
|
|
<description>LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSR0R</name>
|
|
<description>Deep Standby USB Transceiver Control/Pin Monitor Register </description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFF4FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBSTSHM</name>
|
|
<description>VBUS InputIndicates VBUS input signal on the HS side of USB port.</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DOVCBHM</name>
|
|
<description>OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port.</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DOVCAHM</name>
|
|
<description>OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port.</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSR1R</name>
|
|
<description>Deep Standby USB Suspend/Resume Interrupt Register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBSTSH</name>
|
|
<description>Indication of Return from VBUS Interrupt Source</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVCBH</name>
|
|
<description>Indication of Return from OVRCURB Interrupt Source</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVCAH</name>
|
|
<description>Indication of Return from OVRCURA Interrupt Source</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVBSTSHE</name>
|
|
<description>VBUS Interrupt Enable/Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables return from deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVCBHE</name>
|
|
<description>OVRCURB Interrupt Enable Clear</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables return from deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVCAHE</name>
|
|
<description>OVRCURA Interrupt Enable Clear</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables return from deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSR2R</name>
|
|
<description>Deep Standby USB Suspend/Resume Interrupt Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMINTE</name>
|
|
<description>DM Interrupt Enable Clear</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables return from deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPINTE</name>
|
|
<description>DP Interrupt Enable Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables return from deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMVAL</name>
|
|
<description>DM InputIndicates DM input signal on the HS side of USB port.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPVAL</name>
|
|
<description>DP InputIndicates DP input signal on the HS side of USB port.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMINT</name>
|
|
<description>Indication of Return from DM Interrupt Source</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPINT</name>
|
|
<description>Indication of Return from DP Interrupt Source</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates deep software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSRCR</name>
|
|
<description>Deep Standby USB Suspend/Resume Command Register</description>
|
|
<addressOffset>0x16A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIXPHYPD</name>
|
|
<description>USB Transceiver Control Fix for PLL</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Go to/Return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIXPHY</name>
|
|
<description>USB Transceiver Control Fix</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Go to/Return from deep software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCI0</name>
|
|
<description>Serial Communication Interface 0</description>
|
|
<baseAddress>0x40070000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SMR</name>
|
|
<description>Serial Mode Register (SCMR.SMIF = 0)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Communications Mode</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous mode or simple I2C mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock synchronous mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR</name>
|
|
<description>Character Length(Valid only in asynchronous mode)</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable(Valid only in asynchronous mode)</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The parity bit is added (transmitting) / The parity bit is checked (receiving)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Parity Mode (Valid only when the PE bit is 1)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects even parity</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Selects odd parity</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Bit Length(Valid only in asynchronous mode)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>1 stop bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>2 stop bits</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MP</name>
|
|
<description>Multi-Processor Mode(Valid only in asynchronous mode)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Multi-processor communications function is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Multi-processor communications function is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Clock Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4 clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16 clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64 clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMR_SMCI</name>
|
|
<description>Serial mode register (SCMR.SMIF = 1)</description>
|
|
<alternateRegister>SMR</alternateRegister>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GM</name>
|
|
<description>GSM Mode</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GSM mode operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BLK</name>
|
|
<description>Block Transfer Mode</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Block transfer mode operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable(Valid only in asynchronous mode)</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting Prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set this bit to 1 in smart card interface mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Parity Mode (Valid only when the PE bit is 1)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects even parity</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Selects odd parity</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCP</name>
|
|
<description>Stop Bit Length(Valid only in asynchronous mode)</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Clock Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4 clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16 clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64 clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<description>Bit Rate Register</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRR</name>
|
|
<description>BRR is an 8-bit register that adjusts the bit rate.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Serial Control Register (SCMR.SMIF = 0)</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXI interrupt request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXI interrupt request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXI and ERI interrupt requests are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXI and ERI interrupt requests are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmit Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial transmission is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial transmission is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receive Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial reception is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial reception is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPIE</name>
|
|
<description>Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal reception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit End Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TEI interrupt request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TEI interrupt request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKE</name>
|
|
<description>Clock Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR_SMCI</name>
|
|
<description>Serial Control Register (SCMR.SMIF =1)</description>
|
|
<alternateRegister>SCR</alternateRegister>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A TXI interrupt request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A TXI interrupt request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXI and ERI interrupt requests are disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXI and ERI interrupt requests are enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmit Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial transmission is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial transmission is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receive Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial reception is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial reception is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPIE</name>
|
|
<description>Multi-Processor Interrupt EnableSet this bit to 0 in smart card interface mode.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit End Interrupt EnableSet this bit to 0 in smart card interface mode.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKE</name>
|
|
<description>Clock Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Clock Output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDR</name>
|
|
<description>TDR is an 8-bit register that stores transmit data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR</name>
|
|
<description>Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x84</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Empty Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is in TDR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No transmit data is in TDR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Full Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No received data is in RDR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is in RDR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun Error Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FER</name>
|
|
<description>Framing Error Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A framing error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Parity Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEND</name>
|
|
<description>Transmit End Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A character is being transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Character transfer has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPB</name>
|
|
<description>Multi-Processor Bit. Value of the multi-processor bit in the reception frame</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPBT</name>
|
|
<description>Multi-Processor Bit Transfer. Sets the multi-processor bit for adding to the transmission frame</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR_FIFO</name>
|
|
<description>Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)</description>
|
|
<alternateRegister>SSR</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDFE</name>
|
|
<description>Transmit FIFO data empty flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The quantity of transmit data written in FTDR exceeds the specified transmit triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive FIFO data full flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The quantity of receive data written in FRDR falls below the specified receive triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun Error Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FER</name>
|
|
<description>Framing Error Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A framing error has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Parity Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEND</name>
|
|
<description>Transmit End Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A character is being transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Character transfer has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR_SMCI</name>
|
|
<description>Serial Status Register(SCMR.SMIF = 1)</description>
|
|
<alternateRegister>SSR</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x84</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Empty Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data is in TDR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No transmit data is in TDR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Full Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No received data is in RDR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is in RDR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun Error Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERS</name>
|
|
<description>Error Signal Status Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low error signal not responded</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low error signal responded</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Parity Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEND</name>
|
|
<description>Transmit End Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A character is being transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Character transfer has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPB</name>
|
|
<description>This bit should be 0 in smart card interface mode.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPBT</name>
|
|
<description>This bit should be 0 in smart card interface mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x05</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>RDR is an 8-bit register that stores receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMR</name>
|
|
<description>Smart Card Mode Register</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCP2</name>
|
|
<description>Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1</name>
|
|
<description>Character Length 1(Only valid in asynchronous mode)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit/receive in 9-bit data length</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIR</name>
|
|
<description>Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer with LSB first</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer with MSB first </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SINV</name>
|
|
<description>Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TDR contents are transmitted as they are. Receive data is stored as it is in RDR.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMIF</name>
|
|
<description>Smart Card Interface Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Smart card interface mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEMR</name>
|
|
<description>Serial Extended Mode Register</description>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDESEL</name>
|
|
<description>Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The low level on the RXDn pin is detected as the start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A falling edge on the RXDn pin is detected as the start bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGDM</name>
|
|
<description>Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode).</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Baud rate generator outputs the clock with normal frequency.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Baud rate generator outputs the clock with doubled frequency.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFEN</name>
|
|
<description>Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Noise cancellation function for the RXDn/TXDn input signal is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise cancellation function for the RXDn/TXDn input signal is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABCS</name>
|
|
<description>Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Selects 16 base clock cycles for 1-bit period.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Selects 8 base clock cycles for 1-bit period.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABCSE</name>
|
|
<description>Asynchronous Mode Extended Base Clock Select1(Valid only in asynchronous mode and SCR.CKE[1]=0)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRME</name>
|
|
<description>Bit Modulation Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bit rate modulation function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bit rate modulation function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNFR</name>
|
|
<description>Noise Filter Setting Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFCS</name>
|
|
<description>Noise Filter Clock Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>The clock signal divided by 1 is used with the noise filter.(In asynchronous mode)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>The clock signal divided by 1 is used with the noise filter.(In simple I2C mode)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>The clock signal divided by 2 is used with the noise filter.(In simple I2C mode)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>The clock signal divided by 4 is used with the noise filter.(In simple I2C mode)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>The clock signal divided by 8 is used with the noise filter.(In simple I2C mode)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIMR1</name>
|
|
<description>I2C Mode Register 1</description>
|
|
<addressOffset>0x09</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IICDL</name>
|
|
<description>SSDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator.</description>
|
|
<lsb>3</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>No output delay</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>(IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICM</name>
|
|
<description>Simple I2C Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIMR2</name>
|
|
<description>I2C Mode Register 2</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IICACKT</name>
|
|
<description>ACK Transmission Data</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACK transmission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK transmission and reception of ACK/NACK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICCSC</name>
|
|
<description>Clock Synchronization</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No synchronization with the clock signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Synchronization with the clock signal</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICINTM</name>
|
|
<description>I2C Interrupt Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use ACK/NACK interrupts.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use reception and transmission interrupts</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIMR3</name>
|
|
<description>I2C Mode Register 3</description>
|
|
<addressOffset>0x0B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IICSCLS</name>
|
|
<description>SCL Output Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Serial clock output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate a start, restart, or stop condition.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Output the low level on the SSCLn pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Place the SSCLn pin in the high-impedance state.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICSDAS</name>
|
|
<description>SDA Output Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Serial data output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate a start, restart, or stop condition.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Output the low level on the SSDAn pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Place the SSDAn pin in the high-impedance state.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICSTIF</name>
|
|
<description>Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>There are no requests for generating conditions or a condition is being generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A start, restart, or stop condition is completely generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICSTPREQ</name>
|
|
<description>Stop Condition Generation</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A stop condition is not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A stop condition is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICRSTAREQ</name>
|
|
<description>Restart Condition Generation</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A restart condition is not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A restart condition is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICSTAREQ</name>
|
|
<description>Start Condition Generation</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A start condition is not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A start condition is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SISR</name>
|
|
<description>I2C Status Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xCB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IICACKR</name>
|
|
<description>ACK Reception Data Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACK received</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK received</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPMR</name>
|
|
<description>SPI Mode Register</description>
|
|
<addressOffset>0x0D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CKPH</name>
|
|
<description>Clock Phase Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock is not delayed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock is delayed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>Clock Polarity Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock polarity is not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock polarity is inverted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MFF</name>
|
|
<description>Mode Fault Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mode fault error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSS</name>
|
|
<description>Master or slave mode selection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmission is through the TXDn pin and reception is through the RXDn pin (master mode).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTS Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS function is disabled (RTS output function is enabled).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SSn# Pin Function Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSn# pin function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSn# pin function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDRHL</name>
|
|
<description>Transmit 9-bit Data Register</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRHL</name>
|
|
<description>TDRHL is a 16-bit register that stores transmit data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTDRHL</name>
|
|
<description>Transmit FIFO Data Register HL</description>
|
|
<alternateRegister>TDRHL</alternateRegister>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPBT</name>
|
|
<description>Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDAT</name>
|
|
<description>Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTDRH</name>
|
|
<description>Transmit FIFO Data Register H</description>
|
|
<alternateRegister>TDRHL</alternateRegister>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPBT</name>
|
|
<description>Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDATH</name>
|
|
<description>Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTDRL</name>
|
|
<description>Transmit FIFO Data Register L </description>
|
|
<alternateRegister>TDRHL</alternateRegister>
|
|
<addressOffset>0x0F</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDATL</name>
|
|
<description>Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDRHL</name>
|
|
<description>Receive 9-bit Data Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDRHL</name>
|
|
<description>RDRHL is an 16-bit register that stores receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRDRHL</name>
|
|
<description>Receive FIFO Data Register HL</description>
|
|
<alternateRegister>RDRHL</alternateRegister>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive FIFO data full flag(It is same as SSR.RDF)</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun error flag(It is same as SSR.ORER)</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FER</name>
|
|
<description>Framing error flag</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error occurred at the first data of FRDRH and FRDRL.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A framing error has occurred at the first data of FRDRH and FRDRL.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Parity error flag</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred at the first data of FRDRH and FRDRL.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred at the first data of FRDRH and FRDRL.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Receive data ready flag(It is same as SSR.DR)</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next receive data has not been received for a period after normal completed receiving. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPB</name>
|
|
<description>Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDAT</name>
|
|
<description>Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRDRH</name>
|
|
<description>Receive FIFO Data Register H</description>
|
|
<alternateRegister>RDRHL</alternateRegister>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive FIFO data full flag(It is same as SSR.RDF)</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun error flag(It is same as SSR.ORER)</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FER</name>
|
|
<description>Framing error flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error occurred at the first data of FRDRH and FRDRL</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A framing error has occurred at the first data of FRDRH and FRDRL</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Parity error flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred at the first data of FRDRH and FRDRL</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred at the first data of FRDRH and FRDRL</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Receive data ready flag(It is same as SSR.DR)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next receive data has not been received for a period after normal completed receiving. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPB</name>
|
|
<description>Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data transmission cycles</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ID transmission cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDATH</name>
|
|
<description>Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRDRL</name>
|
|
<description>Receive FIFO Data Register L</description>
|
|
<alternateRegister>RDRHL</alternateRegister>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDATL</name>
|
|
<description>Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDDR</name>
|
|
<description>Modulation Duty Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDDR</name>
|
|
<description>MDDR corrects the bit rate adjusted by the BRR register.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCR</name>
|
|
<description>Data Compare Match Control Register</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCME</name>
|
|
<description>Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Address match function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address match function is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDSEL</name>
|
|
<description>ID frame select Bit(Valid only in asynchronous mode(including multi-processor) </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>It's always compared data in spite of the value of the MPB bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>It's compared data when the MPB bit is 1 ( ID frame ) only.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFER</name>
|
|
<description>Data Compare Match Framing Error Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A framing error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPER</name>
|
|
<description>Data Compare Match Parity Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A parity error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCMF</name>
|
|
<description>Data Compare Match Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No matched </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Matched</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF800</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRG</name>
|
|
<description>RTS# Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Trigger number 0</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Triger number n (n= 0-15)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTRG</name>
|
|
<description>Receive FIFO data trigger number</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Trigger number 0</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Triger number n (n= 0-15)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TTRG</name>
|
|
<description>Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Trigger number 0</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Triger number n (n= 0-15)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRES</name>
|
|
<description>Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>reception data full interrupt (RXI)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>receive error interrupt (ERI)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRST</name>
|
|
<description>Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of data stored in FTDRH and FTDRL register are NOT made 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of data stored in FTDRH and FTDRL register are made 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFRST</name>
|
|
<description>Receive FIFO Data Register Reset(Valid only in FCR.FM=1)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The number of data stored in FRDRH and FRDRL register are NOT made 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The number of data stored in FRDRH and FRDRL register are made 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FM</name>
|
|
<description>FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-FIFO mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO mode </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>FIFO Data Count Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T</name>
|
|
<description>Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R</name>
|
|
<description>Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PNUM</name>
|
|
<description>Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FNUM</name>
|
|
<description>Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).</description>
|
|
<lsb>2</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ORER</name>
|
|
<description>Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun error has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDR</name>
|
|
<description>Compare Match Data Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPD</name>
|
|
<description>Compare Match DataCompare data pattern for address match wake-up function </description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPTR</name>
|
|
<description>Serial Port Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPB2IO</name>
|
|
<description>Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The value of SPB2DT bit isn't output in TxD terminal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The value of SPB2DT bit is output in TxD terminal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPB2DT</name>
|
|
<description>Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low level is output in TxD terminal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High level is output in TxD terminal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDMON</name>
|
|
<description>Serial input data monitor bit(The state of the RXD terminal is shown.)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXD terminal is the Low level. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXD terminal is the High level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI1</name>
|
|
<description>Serial Communication Interface 1</description>
|
|
<baseAddress>0x40070020</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI2</name>
|
|
<description>Serial Communication Interface 2</description>
|
|
<baseAddress>0x40070040</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI3</name>
|
|
<description>Serial Communication Interface 3</description>
|
|
<baseAddress>0x40070060</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI4</name>
|
|
<description>Serial Communication Interface 4</description>
|
|
<baseAddress>0x40070080</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI5</name>
|
|
<description>Serial Communication Interface 5</description>
|
|
<baseAddress>0x400700A0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI6</name>
|
|
<description>Serial Communication Interface 6</description>
|
|
<baseAddress>0x400700C0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI7</name>
|
|
<description>Serial Communication Interface 7</description>
|
|
<baseAddress>0x400700E0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI8</name>
|
|
<description>Serial Communication Interface 8</description>
|
|
<baseAddress>0x40070100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SCI0">
|
|
<name>SCI9</name>
|
|
<description>Serial Communication Interface 9</description>
|
|
<baseAddress>0x40070120</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IIC0</name>
|
|
<description>Inter-Integrated Circuit 0</description>
|
|
<baseAddress>0x40053000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0B</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x15</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ICCR1</name>
|
|
<description>I2C Bus Control Register 1 </description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICE</name>
|
|
<description>I2C Bus Interface Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable (SCLn and SDAn pins in inactive state)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable (SCLn and SDAn pins in active state)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICRST</name>
|
|
<description>I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Releases the RIIC reset or internal reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initiates the RIIC reset or internal reset. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLO</name>
|
|
<description>Extra SCL Clock Cycle Output</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not output an extra SCL clock cycle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Outputs an extra SCL clock cycle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOWP</name>
|
|
<description>SCLO/SDAO Write Protect</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enables a value to be written in SCLO bit and SDAO bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disables a value to be written in SCLO bit and SDAO bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLO</name>
|
|
<description>SCL Output Control/Monitor</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDAO</name>
|
|
<description>SDA Output Control/Monitor</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>(Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLI</name>
|
|
<description>SCL Line Monitor</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SCLn line is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCLn line is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDAI</name>
|
|
<description>SDA Line Monitor</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDAn line is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDAn line is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICCR2</name>
|
|
<description>I2C Bus Control Register 2</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BBSY</name>
|
|
<description>Bus Busy Detection Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The I2C bus is released (bus free state).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The I2C bus is occupied (bus busy state). </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master/Slave Mode</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRS</name>
|
|
<description>Transmit/Receive Mode </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a stop condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a stop condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a restart condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a restart condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state).</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a start condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a start condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR1</name>
|
|
<description>I2C Bus Mode Register 1</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x08</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTWP</name>
|
|
<description>MST/TRS Write Protect</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables writing to the MST and TRS bits in ICCR2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables writing to the MST and TRS bits in ICCR2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCLKB/1 clock</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCLKB/2 clock</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>PCLKB/4 clock</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCLKB/8 clock</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PCLKB/16 clock</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PCLKB/32 clock</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>PCLKB/64 clock</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>PCLKB/128 clock</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCWP</name>
|
|
<description>BC Write Protect(This bit is read as 1.)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enables a value to be written in the BC[2:0] bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disables a value to be written in the BC[2:0] bits.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Bit Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>9 bits</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 bits</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 bits</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 bits</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 bits</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 bits</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 bits</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 bits</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR2</name>
|
|
<description>I2C Bus Mode Register 2</description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x06</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLCS</name>
|
|
<description>SDA Output Delay Clock Source Selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDDL</name>
|
|
<description>SDA Output Delay Counter</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No output delay</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOH</name>
|
|
<description>Timeout H Count Control</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count is disabled while the SCLn line is at a high level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count is enabled while the SCLn line is at a high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOL</name>
|
|
<description>Timeout L Count Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count is disabled while the SCLn line is at a low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count is enabled while the SCLn line is at a low level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOS</name>
|
|
<description>Timeout Detection Time Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Long mode is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Short mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR3</name>
|
|
<description>I2C Bus Mode Register 3</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMBS</name>
|
|
<description>SMBus/I2C Bus Selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The I2C bus is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SMBus is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WAIT (The period between ninth clock cycle and first clock cycle is held low.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRFS</name>
|
|
<description>RDRF Flag Set Timing Selection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKWP</name>
|
|
<description>ACKBT Write Protect</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modification of the ACKBT bit is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modification of the ACKBT bit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKBT</name>
|
|
<description>Transmit Acknowledge</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A 0 is sent as the acknowledge bit (ACK transmission).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A 1 is sent as the acknowledge bit (NACK transmission).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKBR</name>
|
|
<description>Receive Acknowledge</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A 0 is received as the acknowledge bit (ACK reception).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A 1 is received as the acknowledge bit (NACK reception).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Filter Stage Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Noise of up to one fIIC cycle is filtered out (single-stage filter).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Noise of up to two fIIC cycles is filtered out (2-stage filter).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Noise of up to three fIIC cycles is filtered out (3-stage filter).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Noise of up to four fIIC cycles is filtered out (4-stage filter)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICFER</name>
|
|
<description>I2C Bus Function Enable Register </description>
|
|
<addressOffset>0x05</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x72</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FMPE</name>
|
|
<description>Fast-mode Plus Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Fm+ slope control circuit is used for the SCLn pin and SDAn pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An Fm+ slope control circuit is used for the SCLn pin and SDAn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLE</name>
|
|
<description>SCL Synchronous Circuit Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL synchronous circuit is used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An SCL synchronous circuit is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFE</name>
|
|
<description>Digital Noise Filter Circuit Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No digital noise filter circuit is used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A digital noise filter circuit is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKE</name>
|
|
<description>NACK Reception Transfer Suspension Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer operation is not suspended during NACK reception (transfer suspension disabled).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer operation is suspended during NACK reception (transfer suspension enabled).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SALE</name>
|
|
<description>Slave Arbitration-Lost Detection Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NALE</name>
|
|
<description>NACK Transmission Arbitration-Lost Detection Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK transmission arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK transmission arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MALE</name>
|
|
<description>Master Arbitration-Lost Detection Enable </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOE</name>
|
|
<description>Timeout Function Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The timeout function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The timeout function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSER</name>
|
|
<description>I2C Bus Status Enable Register</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x09</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOAE</name>
|
|
<description>Host Address Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIDE</name>
|
|
<description>Device-ID Address Detection Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device-ID address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device-ID address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAE</name>
|
|
<description>General Call Address Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General call address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR2E</name>
|
|
<description>Slave Address Register 2 Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL2 and SARU2 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL2 and SARU2 is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR1E</name>
|
|
<description>Slave Address Register 1 Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL1 and SARU1 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL1 and SARU1 is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR0E</name>
|
|
<description>Slave Address Register 0 Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL0 and SARU0 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL0 and SARU0 is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICIER</name>
|
|
<description>I2C Bus Interrupt Enable Register</description>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Data Empty Interrupt Request Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data empty interrupt request (TXI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data empty interrupt request (TXI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit End Interrupt Request Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit end interrupt request (TEI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit end interrupt request (TEI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Data Full Interrupt Request Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data full interrupt request (RXI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data full interrupt request (RXI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NACK Reception Interrupt Request Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK reception interrupt request (NAKI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK reception interrupt request (NAKI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>Stop Condition Detection Interrupt Request Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop condition detection interrupt request (SPI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop condition detection interrupt request (SPI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STIE</name>
|
|
<description>Start Condition Detection Interrupt Request Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start condition detection interrupt request (STI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start condition detection interrupt request (STI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration-Lost Interrupt Request Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Arbitration-lost interrupt request (ALI) is disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Arbitration-lost interrupt request (ALI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOIE</name>
|
|
<description>Timeout Interrupt Request Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout interrupt request (TMOI) is disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout interrupt request (TMOI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR1</name>
|
|
<description>I2C Bus Status Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOA</name>
|
|
<description>Host Address Detection Flag </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host address is not detected. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host address is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DID</name>
|
|
<description>Device-ID Address Detection Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device-ID command is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device-ID command is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCA</name>
|
|
<description>General Call Address Detection Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General call address is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS2</name>
|
|
<description>Slave Address 2 Detection Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 2 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 2 is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS1</name>
|
|
<description>Slave Address 1 Detection Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 1 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 1 is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS0</name>
|
|
<description>Slave Address 0 Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 0 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 0 is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR2</name>
|
|
<description>I2C Bus Status Register 2</description>
|
|
<addressOffset>0x09</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Empty Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ICDRT contains transmit data. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICDRT contains no transmit data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEND</name>
|
|
<description>Transmit End Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is being transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data has been transmitted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Full Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ICDRR contains no receive data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICDRR contains receive data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKF</name>
|
|
<description>NACK Detection Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Condition Detection Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop condition is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop condition is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Condition Detection Flag </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start condition is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start condition is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AL</name>
|
|
<description>Arbitration-Lost Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Arbitration is not lost.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Arbitration is lost.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOF</name>
|
|
<description>Timeout Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SARL%s</name>
|
|
<description>Slave Address Register L%s</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVA</name>
|
|
<description>A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SARU%s</name>
|
|
<description>Slave Address Register U%s</description>
|
|
<addressOffset>0x0B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVA9</name>
|
|
<description>10-Bit Address(bit9)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SVA8</name>
|
|
<description>10-Bit Address(bit8)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FS</name>
|
|
<description>7-Bit/10-Bit Address Format Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The 7-bit address format is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The 10-bit address format is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICBRL</name>
|
|
<description>I2C Bus Bit Rate Low-Level Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRL</name>
|
|
<description>Bit Rate Low-Level Period(Low-level period of SCL clock)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICBRH</name>
|
|
<description>I2C Bus Bit Rate High-Level Register </description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRH</name>
|
|
<description>Bit Rate High-Level Period(High-level period of SCL clock)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICDRT</name>
|
|
<description>I2C Bus Transmit Data Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICDRT</name>
|
|
<description>8-bit read-write register that stores transmit data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICDRR</name>
|
|
<description>I2C Bus Receive Data Register</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICDRR</name>
|
|
<description>8-bit register that stores the received data</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICWUR</name>
|
|
<description>I2C Bus Wake Up Unit Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUE</name>
|
|
<description>Wake Up function Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wake-up function is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wake-up function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUIE</name>
|
|
<description>Wake Up Interrupt Request Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wake Up Interrupt Request (WUI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wake Up Interrupt Request (WUI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>Wake-Up Event Occurrence Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address match during Wake-Up function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address not match during Wake-Up function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUACK</name>
|
|
<description>Asynchronous/Synchronous Operation State Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>State of synchronous operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>State of asynchronous operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUAFA</name>
|
|
<description>Wake-Up Analog Filter Additional Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not add the Wake Up analog filter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add the Wake Up analog filter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICWUR2</name>
|
|
<description>I2C Bus Wake Up Unit Register 2</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUSYF</name>
|
|
<description>Wake-Up function synchronous operation status flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IIC asynchronous circuit enable condition</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IIC synchronous circuit enable condition</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUASYF</name>
|
|
<description>Wake-Up function asynchronous operation status flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IIC synchronous circuit enable condition</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IIC asynchronous circuit enable condition</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUSEN</name>
|
|
<description>Wake-Up function synchronous enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IIC asynchronous circuit enable </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IIC synchronous circuit enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IIC1</name>
|
|
<description>Inter-Integrated Circuit 1</description>
|
|
<baseAddress>0x40053100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0B</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x15</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ICCR1</name>
|
|
<description>I2C Bus Control Register 1 </description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICE</name>
|
|
<description>I2C Bus Interface Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable (SCLn and SDAn pins in inactive state)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable (SCLn and SDAn pins in active state)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICRST</name>
|
|
<description>I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Releases the RIIC reset or internal reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initiates the RIIC reset or internal reset. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLO</name>
|
|
<description>Extra SCL Clock Cycle Output</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not output an extra SCL clock cycle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Outputs an extra SCL clock cycle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOWP</name>
|
|
<description>SCLO/SDAO Write Protect</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enables a value to be written in SCLO bit and SDAO bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disables a value to be written in SCLO bit and SDAO bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLO</name>
|
|
<description>SCL Output Control/Monitor</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDAO</name>
|
|
<description>SDA Output Control/Monitor</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>(Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLI</name>
|
|
<description>SCL Line Monitor</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SCLn line is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCLn line is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDAI</name>
|
|
<description>SDA Line Monitor</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDAn line is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDAn line is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICCR2</name>
|
|
<description>I2C Bus Control Register 2</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BBSY</name>
|
|
<description>Bus Busy Detection Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The I2C bus is released (bus free state).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The I2C bus is occupied (bus busy state). </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master/Slave Mode</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRS</name>
|
|
<description>Transmit/Receive Mode </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a stop condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a stop condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a restart condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a restart condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state).</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not request to issue a start condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests to issue a start condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR1</name>
|
|
<description>I2C Bus Mode Register 1</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x08</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTWP</name>
|
|
<description>MST/TRS Write Protect</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables writing to the MST and TRS bits in ICCR2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables writing to the MST and TRS bits in ICCR2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCLKB/1 clock</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCLKB/2 clock</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>PCLKB/4 clock</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCLKB/8 clock</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PCLKB/16 clock</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PCLKB/32 clock</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>PCLKB/64 clock</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>PCLKB/128 clock</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCWP</name>
|
|
<description>BC Write Protect(This bit is read as 1.)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enables a value to be written in the BC[2:0] bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disables a value to be written in the BC[2:0] bits.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Bit Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>9 bits</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 bits</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 bits</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 bits</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 bits</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 bits</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 bits</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 bits</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR2</name>
|
|
<description>I2C Bus Mode Register 2</description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x06</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLCS</name>
|
|
<description>SDA Output Delay Clock Source Selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDDL</name>
|
|
<description>SDA Output Delay Counter</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No output delay</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOH</name>
|
|
<description>Timeout H Count Control</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count is disabled while the SCLn line is at a high level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count is enabled while the SCLn line is at a high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOL</name>
|
|
<description>Timeout L Count Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count is disabled while the SCLn line is at a low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count is enabled while the SCLn line is at a low level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOS</name>
|
|
<description>Timeout Detection Time Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Long mode is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Short mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICMR3</name>
|
|
<description>I2C Bus Mode Register 3</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMBS</name>
|
|
<description>SMBus/I2C Bus Selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The I2C bus is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SMBus is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WAIT (The period between ninth clock cycle and first clock cycle is held low.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRFS</name>
|
|
<description>RDRF Flag Set Timing Selection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKWP</name>
|
|
<description>ACKBT Write Protect</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Modification of the ACKBT bit is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modification of the ACKBT bit is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKBT</name>
|
|
<description>Transmit Acknowledge</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A 0 is sent as the acknowledge bit (ACK transmission).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A 1 is sent as the acknowledge bit (NACK transmission).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKBR</name>
|
|
<description>Receive Acknowledge</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A 0 is received as the acknowledge bit (ACK reception).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A 1 is received as the acknowledge bit (NACK reception).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Filter Stage Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Noise of up to one fIIC cycle is filtered out (single-stage filter).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Noise of up to two fIIC cycles is filtered out (2-stage filter).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Noise of up to three fIIC cycles is filtered out (3-stage filter).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Noise of up to four fIIC cycles is filtered out (4-stage filter)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICFER</name>
|
|
<description>I2C Bus Function Enable Register </description>
|
|
<addressOffset>0x05</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x72</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FMPE</name>
|
|
<description>Fast-mode Plus Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Fm+ slope control circuit is used for the SCLn pin and SDAn pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An Fm+ slope control circuit is used for the SCLn pin and SDAn pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLE</name>
|
|
<description>SCL Synchronous Circuit Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL synchronous circuit is used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An SCL synchronous circuit is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFE</name>
|
|
<description>Digital Noise Filter Circuit Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No digital noise filter circuit is used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A digital noise filter circuit is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKE</name>
|
|
<description>NACK Reception Transfer Suspension Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer operation is not suspended during NACK reception (transfer suspension disabled).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer operation is suspended during NACK reception (transfer suspension enabled).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SALE</name>
|
|
<description>Slave Arbitration-Lost Detection Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NALE</name>
|
|
<description>NACK Transmission Arbitration-Lost Detection Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK transmission arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK transmission arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MALE</name>
|
|
<description>Master Arbitration-Lost Detection Enable </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master arbitration-lost detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master arbitration-lost detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOE</name>
|
|
<description>Timeout Function Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The timeout function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The timeout function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSER</name>
|
|
<description>I2C Bus Status Enable Register</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x09</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOAE</name>
|
|
<description>Host Address Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIDE</name>
|
|
<description>Device-ID Address Detection Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device-ID address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device-ID address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAE</name>
|
|
<description>General Call Address Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General call address detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR2E</name>
|
|
<description>Slave Address Register 2 Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL2 and SARU2 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL2 and SARU2 is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR1E</name>
|
|
<description>Slave Address Register 1 Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL1 and SARU1 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL1 and SARU1 is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAR0E</name>
|
|
<description>Slave Address Register 0 Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address in SARL0 and SARU0 is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address in SARL0 and SARU0 is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICIER</name>
|
|
<description>I2C Bus Interrupt Enable Register</description>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Data Empty Interrupt Request Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data empty interrupt request (TXI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data empty interrupt request (TXI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit End Interrupt Request Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit end interrupt request (TEI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit end interrupt request (TEI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Data Full Interrupt Request Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data full interrupt request (RXI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data full interrupt request (RXI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NACK Reception Interrupt Request Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK reception interrupt request (NAKI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK reception interrupt request (NAKI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>Stop Condition Detection Interrupt Request Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop condition detection interrupt request (SPI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop condition detection interrupt request (SPI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STIE</name>
|
|
<description>Start Condition Detection Interrupt Request Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start condition detection interrupt request (STI) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start condition detection interrupt request (STI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration-Lost Interrupt Request Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Arbitration-lost interrupt request (ALI) is disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Arbitration-lost interrupt request (ALI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOIE</name>
|
|
<description>Timeout Interrupt Request Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout interrupt request (TMOI) is disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout interrupt request (TMOI) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR1</name>
|
|
<description>I2C Bus Status Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOA</name>
|
|
<description>Host Address Detection Flag </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host address is not detected. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host address is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DID</name>
|
|
<description>Device-ID Address Detection Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device-ID command is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device-ID command is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCA</name>
|
|
<description>General Call Address Detection Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General call address is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS2</name>
|
|
<description>Slave Address 2 Detection Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 2 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 2 is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS1</name>
|
|
<description>Slave Address 1 Detection Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 1 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 1 is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AAS0</name>
|
|
<description>Slave Address 0 Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave address 0 is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave address 0 is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR2</name>
|
|
<description>I2C Bus Status Register 2</description>
|
|
<addressOffset>0x09</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Empty Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ICDRT contains transmit data. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICDRT contains no transmit data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEND</name>
|
|
<description>Transmit End Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is being transmitted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data has been transmitted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Full Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ICDRR contains no receive data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICDRR contains receive data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKF</name>
|
|
<description>NACK Detection Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NACK is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NACK is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Condition Detection Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop condition is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop condition is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Condition Detection Flag </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start condition is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start condition is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AL</name>
|
|
<description>Arbitration-Lost Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Arbitration is not lost.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Arbitration is lost.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOF</name>
|
|
<description>Timeout Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SARL%s</name>
|
|
<description>Slave Address Register L%s</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVA</name>
|
|
<description>A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SARU%s</name>
|
|
<description>Slave Address Register U%s</description>
|
|
<addressOffset>0x0B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVA9</name>
|
|
<description>10-Bit Address(bit9)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SVA8</name>
|
|
<description>10-Bit Address(bit8)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FS</name>
|
|
<description>7-Bit/10-Bit Address Format Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The 7-bit address format is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The 10-bit address format is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICBRL</name>
|
|
<description>I2C Bus Bit Rate Low-Level Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRL</name>
|
|
<description>Bit Rate Low-Level Period(Low-level period of SCL clock)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICBRH</name>
|
|
<description>I2C Bus Bit Rate High-Level Register </description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRH</name>
|
|
<description>Bit Rate High-Level Period(High-level period of SCL clock)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICDRT</name>
|
|
<description>I2C Bus Transmit Data Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICDRT</name>
|
|
<description>8-bit read-write register that stores transmit data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICDRR</name>
|
|
<description>I2C Bus Receive Data Register</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICDRR</name>
|
|
<description>8-bit register that stores the received data</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="IIC1">
|
|
<name>IIC2</name>
|
|
<description>Inter-Integrated Circuit 2</description>
|
|
<baseAddress>0x40053200</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSTEM</name>
|
|
<description>System Control</description>
|
|
<baseAddress>0x4001E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x26</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x32</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x36</offset>
|
|
<size>7</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3E</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x52</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x61</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x413</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x480</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x490</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x492</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA2</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA5</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x92</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x94</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x98</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xAA</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x400</offset>
|
|
<size>13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40E</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x92</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x94</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x98</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xAA</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x400</offset>
|
|
<size>13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40E</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE1</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x417</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE1</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x417</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x41D</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B0</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B4</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B6</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B8</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x500</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x41D</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B0</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B4</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B6</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4B8</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x500</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3FE</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3FE</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x410</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x49A</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x410</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x49A</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x416</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x416</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SCKDIVCR</name>
|
|
<description>System Clock Division Control Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x22022222</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCK</name>
|
|
<description>Flash IF Clock (FCLK) Select</description>
|
|
<lsb>28</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICK</name>
|
|
<description>System Clock (ICLK) Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCK</name>
|
|
<description>External Bus Clock (BCLK) Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKA</name>
|
|
<description>Peripheral Module Clock A (PCLKA) Select </description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKB</name>
|
|
<description>Peripheral Module Clock B (PCLKB) Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKC</name>
|
|
<description>Peripheral Module Clock C (PCLKC) Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKD</name>
|
|
<description>Peripheral Module Clock D (PCLKD) Select </description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4 </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCKDIVCR2</name>
|
|
<description>System Clock Division Control Register 2 </description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UCK</name>
|
|
<description>USB Clock (UCLK) Select </description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/3</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/5</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCKSCR</name>
|
|
<description>System Clock Source Control Register</description>
|
|
<addressOffset>0x026</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>Clock Source Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>HOCO </description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>MOCO</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LOCO </description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Main clock oscillator </description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Sub-clock oscillator </description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PLL</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLCCR</name>
|
|
<description>PLL Clock Control Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1300</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLMUL</name>
|
|
<description>PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0</description>
|
|
<lsb>8</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>#010011</minimum>
|
|
<maximum>#111011</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLSRCSEL</name>
|
|
<description>PLL Clock Source Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Main clock oscillator</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>HOCO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLIDIV</name>
|
|
<description>PLL Input Frequency Division Ratio Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>/1 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>/2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>/3</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLCR</name>
|
|
<description>PLL Control Register</description>
|
|
<addressOffset>0x02A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSTP</name>
|
|
<description>PLL Stop Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operate the PLL</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop the PLL.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCKCR</name>
|
|
<description>External Bus Clock Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCLKDIV</name>
|
|
<description>BCLK Pin Output Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BCLK/2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOSCCR</name>
|
|
<description>Main Clock Oscillator Control Register </description>
|
|
<addressOffset>0x032</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOSTP</name>
|
|
<description>Main Clock Oscillator Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Main clock oscillator is operating.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Main clock oscillator is stopped.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOCOCR</name>
|
|
<description>High-Speed On-Chip Oscillator Control Register</description>
|
|
<addressOffset>0x036</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCSTP</name>
|
|
<description>HOCO Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operate the HOCO clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop the HOCO clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOCOCR</name>
|
|
<description>Middle-Speed On-Chip Oscillator Control Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCSTP</name>
|
|
<description>MOCO Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operate the MOCO clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop the MOCO clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLLCR1</name>
|
|
<description>FLL Control Register 1</description>
|
|
<addressOffset>0x039</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLLEN</name>
|
|
<description>FLL Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLLCR2</name>
|
|
<description>FLL Control Register 2</description>
|
|
<addressOffset>0x03A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLLCNTL</name>
|
|
<description>FLL Multiplication ControlMultiplication ratio of the FLL reference clock select</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCSF</name>
|
|
<description>Oscillation Stabilization Flag Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSF</name>
|
|
<description>PLL Clock Oscillation Stabilization Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PLL clock is stopped or is not yet stable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PLL clock is stable, so is available for use as the system clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOSCSF</name>
|
|
<description>Main Clock Oscillation Stabilization Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Main clock oscillator is stopped (MOSTP = 1) or is not yet stable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Main clock oscillator is stable, so is available for use as the system clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOCOSF</name>
|
|
<description>HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>HOCO clock is stopped or is not yet stable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>HOCO clock is stable, so is available for use as the system clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKOCR</name>
|
|
<description>Clock Out Control Register</description>
|
|
<addressOffset>0x03E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CKOEN</name>
|
|
<description>Clock out enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable clock out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable clock out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKODIV</name>
|
|
<description>Clock out input frequency Division Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>/4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>/128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKOSEL</name>
|
|
<description>Clock out source select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>HOCO</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>MOCO</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LOCO</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>MOSC</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>SOSC</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRCKCR</name>
|
|
<description>Trace Clock Control Register</description>
|
|
<addressOffset>0x03F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRCKEN</name>
|
|
<description>Trace Clock operating Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRCK</name>
|
|
<description>Trace Clock operating frequency select</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>/1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>/2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>/4</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSTDCR</name>
|
|
<description>Oscillation Stop Detection Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSTDE</name>
|
|
<description>Oscillation Stop Detection Function Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable oscillation stop detection function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable oscillation stop detection function</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTDIE</name>
|
|
<description>Oscillation Stop Detection Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable oscillation stop detection interrupt (do not notify the POEG)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable oscillation stop detection interrupt (notify the POEG)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSTDSR</name>
|
|
<description>Oscillation Stop Detection Status Register</description>
|
|
<addressOffset>0x041</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSTDF</name>
|
|
<description>Oscillation Stop Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Main clock oscillation stop not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Main clock oscillation stop detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EBCKOCR</name>
|
|
<description>External Bus Clock Output Control Register</description>
|
|
<addressOffset>0x052</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EBCKOEN</name>
|
|
<description>BCLK Pin Output Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable EBCLK pin output (fixed high)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable EBCLK pin output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCKOCR</name>
|
|
<description>SDRAM Clock Output Control Register</description>
|
|
<addressOffset>0x053</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDCKOEN</name>
|
|
<description>SDCLK Pin Output Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable SDCLK pin output (fixed high)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable SDCLK pin output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOCOUTCR</name>
|
|
<description>MOCO User Trimming Control Register</description>
|
|
<addressOffset>0x061</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOCOUTRM</name>
|
|
<description>MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOCOUTCR</name>
|
|
<description>HOCO User Trimming Control Register</description>
|
|
<addressOffset>0x062</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOCOUTRM</name>
|
|
<description>HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOMCR</name>
|
|
<description>Main Clock Oscillator Mode Oscillation Control Register</description>
|
|
<addressOffset>0x413</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTODRVEN</name>
|
|
<description>Main Clock Oscillator Drive Capability Auto Switching Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOSEL</name>
|
|
<description>Main Clock Oscillator Switching</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resonator</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External clock input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODRV0</name>
|
|
<description>Main Clock Oscillator Drive Capability 0 Switching</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>20MHz to 24MHz</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16MHz to 20MHz</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>8MHz to 16MHz</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>8MHz </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOSCCR</name>
|
|
<description>Sub-clock oscillator control register</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOSTP</name>
|
|
<description>Sub-Clock Oscillator Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operate the sub-clock oscillator</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop the sub-clock oscillator</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOMCR</name>
|
|
<description>Sub Clock Oscillator Mode Control Register</description>
|
|
<addressOffset>0x481</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SODRV1</name>
|
|
<description>Sub Clock Oscillator Drive Capability Switching</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Middle</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCOCR</name>
|
|
<description>Low-Speed On-Chip Oscillator Control Register</description>
|
|
<addressOffset>0x490</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCSTP</name>
|
|
<description>LOCO Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operate the LOCO clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop the LOCO clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCOUTCR</name>
|
|
<description>LOCO User Trimming Control Register</description>
|
|
<addressOffset>0x492</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCOUTRM</name>
|
|
<description>LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOSCWTCR</name>
|
|
<description>Main Clock Oscillator Wait Control Register</description>
|
|
<addressOffset>0x0A2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x05</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTS</name>
|
|
<description>Main clock oscillator wait time setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Wait time = 35 cycles (133.5 μs)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Wait time = 67 cycles (255.6 μs)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Wait time = 131 cycles (499.7 μs)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Wait time = 259 cycles (988.0 μs)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Wait time = 547 cycles (2086.6 μs) (value after reset)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Wait time = 1059 cycles (4039.8 μs)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Wait time = 2147 cycles (8190.2 μs)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Wait time = 4291 cycles (16368.9 μs)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Wait time = 8163 cycles (31139.4 μs).</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOCOWTCR</name>
|
|
<description>High-speed on-chip oscillator wait control register</description>
|
|
<addressOffset>0x0A5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HSTS</name>
|
|
<description>HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) </description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SBYCR</name>
|
|
<description>Standby Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSBY</name>
|
|
<description>Software Standby</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sleep mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Output Port Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state..</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTPCRA</name>
|
|
<description>Module Stop Control Register A</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFBFFF1C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPA22</name>
|
|
<description>DMA Controller/Data Transfer Controller Module Stop</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPA7</name>
|
|
<description>Standny RAM Module Stop</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPA6</name>
|
|
<description>ECCRAM Module Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPA5</name>
|
|
<description>High-Speed RAM Module Stop</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPA1</name>
|
|
<description>RAM1 Module Stop</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPA0</name>
|
|
<description>RAM0 Module Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNZCR</name>
|
|
<description>Snooze Control Register</description>
|
|
<addressOffset>0x092</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SNZE</name>
|
|
<description>Snooze Mode Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable Snooze Mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable Snooze Mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZDTCEN</name>
|
|
<description>DTC Enable in Snooze Mode</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DTC operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DTC operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDREQEN</name>
|
|
<description>RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Ignore RXD0 falling edge in Standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNZEDCR</name>
|
|
<description>Snooze End Control Register</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCI0UMTED</name>
|
|
<description>SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD1UMTED</name>
|
|
<description>AD compare mismatch 1 Snooze End Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD1MATED</name>
|
|
<description>AD compare match 1 Snooze End Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD0UMTED</name>
|
|
<description>AD compare mismatch 0 Snooze End Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD0MATED</name>
|
|
<description>AD compare match 0 Snooze End Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCNZRED</name>
|
|
<description>Not Last DTC transmission completion Snooze End Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCZRED</name>
|
|
<description>Last DTC transmission completion Snooze End Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AGT1UNFED</name>
|
|
<description>AGT1 underflow Snooze End Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the Snooze End request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the Snooze End request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNZREQCR</name>
|
|
<description>Snooze Request Control Register</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SNZREQEN30</name>
|
|
<description>Snooze Request Enable 30Enable AGT1 compare match B snooze request</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN29</name>
|
|
<description>Snooze Request Enable 29Enable AGT1 compare match A snooze request</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN28</name>
|
|
<description>Snooze Request Enable 28Enable AGT1 underflow snooze request</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN25</name>
|
|
<description>Snooze Request Enable 25Enable RTC period snooze request</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN24</name>
|
|
<description>Snooze Request Enable 24Enable RTC alarm snooze request</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN22</name>
|
|
<description>Snooze Request Enable 22Enable Comparator-OC0 snooze request</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN17</name>
|
|
<description>Snooze Request Enable 17Enable KR snooze request</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN15</name>
|
|
<description>Snooze Request Enable 15Enable IRQ15 pin snooze request</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN14</name>
|
|
<description>Snooze Request Enable 14Enable IRQ14 pin snooze request</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN13</name>
|
|
<description>Snooze Request Enable 13Enable IRQ13 pin snooze request</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN12</name>
|
|
<description>Snooze Request Enable 12Enable IRQ12 pin snooze request</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN11</name>
|
|
<description>Snooze Request Enable 11Enable IRQ11 pin snooze request</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN10</name>
|
|
<description>Snooze Request Enable 10Enable IRQ10 pin snooze request</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN9</name>
|
|
<description>Snooze Request Enable 9Enable IRQ9 pin snooze request</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN8</name>
|
|
<description>Snooze Request Enable 8Enable IRQ8 pin snooze request</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN7</name>
|
|
<description>Snooze Request Enable 7Enable IRQ7 pin snooze request</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN6</name>
|
|
<description>Snooze Request Enable 6Enable IRQ6 pin snooze request</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN5</name>
|
|
<description>Snooze Request Enable 5Enable IRQ5 pin snooze request</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN4</name>
|
|
<description>Snooze Request Enable 4Enable IRQ4 pin snooze request</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN3</name>
|
|
<description>Snooze Request Enable 3Enable IRQ3 pin snooze request</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN2</name>
|
|
<description>Snooze Request Enable 2Enable IRQ2 pin snooze request</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN1</name>
|
|
<description>Snooze Request Enable 1Enable IRQ1 pin snooze request</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNZREQEN0</name>
|
|
<description>Snooze Request Enable 0Enable IRQ0 pin snooze request</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable snooze request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable snooze request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPCCR</name>
|
|
<description>Operating Power Control Register</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPCMTSF</name>
|
|
<description>Operating Power Control Mode Transition Status Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transition completed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During transition</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPCM</name>
|
|
<description>Operating Power Control Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>High-speed mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Low-speed mode </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPCCR</name>
|
|
<description>Sub Operating Power Control Register</description>
|
|
<addressOffset>0x0AA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOPCMTSF</name>
|
|
<description>Sub Operating Power Control Mode Transition Status Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transition completed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During transition</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOPCM</name>
|
|
<description>Sub Operating Power Control Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Other than Subosc-speed mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Subosc-speed mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSBYCR</name>
|
|
<description>Deep Standby Control Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPSBY</name>
|
|
<description>Deep Software Standby</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOKEEP</name>
|
|
<description>I/O Port Retention</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEEPCUT</name>
|
|
<description>Power-Supply Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited. </description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIER0</name>
|
|
<description>Deep Standby Interrupt Enable Register 0</description>
|
|
<addressOffset>0x402</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ7E</name>
|
|
<description>IRQ7-DS Pin Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ6E</name>
|
|
<description>IRQ6-DS Pin Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ5E</name>
|
|
<description>IRQ5-DS Pin Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ4E</name>
|
|
<description>IRQ4-DS Pin Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ3E</name>
|
|
<description>IRQ3-DS Pin Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ2E</name>
|
|
<description>IRQ2-DS Pin Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ1E</name>
|
|
<description>IRQ1-DS Pin Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ0E</name>
|
|
<description>IRQ0-DS Pin Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIER1</name>
|
|
<description>Deep Standby Interrupt Enable Register 1</description>
|
|
<addressOffset>0x403</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ14E</name>
|
|
<description>IRQ14-DS Pin Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ13E</name>
|
|
<description>IRQ13-DS Pin Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ12E</name>
|
|
<description>IRQ12-DS Pin Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ11E</name>
|
|
<description>IRQ11-DS Pin Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ10E</name>
|
|
<description>IRQ10-DS Pin Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ9E</name>
|
|
<description>IRQ9-DS Pin Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ8E</name>
|
|
<description>IRQ8-DS Pin Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIER2</name>
|
|
<description>Deep Standby Interrupt Enable Register 2</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DNMIE</name>
|
|
<description>NMI Pin Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRTCAIE</name>
|
|
<description>RTC Alarm interrupt Deep Standby Cancel Signal Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRTCIIE</name>
|
|
<description>RTC Interval interrupt Deep Standby Cancel Signal Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD2IE</name>
|
|
<description>LVD2 Deep Standby Cancel Signal Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD1IE</name>
|
|
<description>LVD1 Deep Standby Cancel Signal Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIER3</name>
|
|
<description>Deep Standby Interrupt Enable Register 3</description>
|
|
<addressOffset>0x405</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAGT1IE</name>
|
|
<description>AGT1 Underflow Deep Standby Cancel Signal Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUSBHSIE</name>
|
|
<description>USBHS Suspend/Resume Deep Standby Cancel Signal Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUSBFSIE</name>
|
|
<description>USBFS Suspend/Resume Deep Standby Cancel Signal Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Canceling deep software standby mode is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Canceling deep software standby mode is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIFR0</name>
|
|
<description>Deep Standby Interrupt Flag Register 0</description>
|
|
<addressOffset>0x406</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ7F</name>
|
|
<description>IRQ7-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ6F</name>
|
|
<description>IRQ6-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ5F</name>
|
|
<description>IRQ5-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ4F</name>
|
|
<description>IRQ4-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ3F</name>
|
|
<description>IRQ3-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ2F</name>
|
|
<description>IRQ2-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ1F</name>
|
|
<description>IRQ1-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ0F</name>
|
|
<description>IRQ0-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIFR1</name>
|
|
<description>Deep Standby Interrupt Flag Register 1</description>
|
|
<addressOffset>0x407</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ14F</name>
|
|
<description>IRQ14-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ13F</name>
|
|
<description>IRQ13-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ12F</name>
|
|
<description>IRQ12-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ11F</name>
|
|
<description>IRQ11-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ10F</name>
|
|
<description>IRQ10-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ9F</name>
|
|
<description>IRQ9-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ8F</name>
|
|
<description>IRQ8-DS Pin Deep Standby Cancel Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIFR2</name>
|
|
<description>Deep Standby Interrupt Flag Register 2</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DNMIF</name>
|
|
<description>NMI Pin Deep Standby Cancel Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRTCAIF</name>
|
|
<description>RTC Alarm interrupt Deep Standby Cancel Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRTCIIF</name>
|
|
<description>RTC Interval interrupt Deep Standby Cancel Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD2IF</name>
|
|
<description>LVD2 Deep Standby Cancel Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD1IF</name>
|
|
<description>LVD1 Deep Standby Cancel Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIFR3</name>
|
|
<description>Deep Standby Interrupt Flag Register 3</description>
|
|
<addressOffset>0x409</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAGT1IF</name>
|
|
<description>AGT1 Underflow Deep Standby Cancel Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUSBHSIF</name>
|
|
<description>USBHS Suspend/Resume Deep Standby Cancel Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUSBFSIF</name>
|
|
<description>USBFS Suspend/Resume Deep Standby Cancel Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The cancel request is not generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The cancel request is generated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIEGR0</name>
|
|
<description>Deep Standby Interrupt Edge Register 0</description>
|
|
<addressOffset>0x40A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ7EG</name>
|
|
<description>IRQ7-DS Pin Edge Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ6EG</name>
|
|
<description>IRQ6-DS Pin Edge Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ5EG</name>
|
|
<description>IRQ5-DS Pin Edge Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ4EG</name>
|
|
<description>IRQ4-DS Pin Edge Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ3EG</name>
|
|
<description>IRQ3-DS Pin Edge Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ2EG</name>
|
|
<description>IRQ2-DS Pin Edge Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ1EG</name>
|
|
<description>IRQ1-DS Pin Edge Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ0EG</name>
|
|
<description>IRQ0-DS Pin Edge Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIEGR1</name>
|
|
<description>Deep Standby Interrupt Edge Register 1</description>
|
|
<addressOffset>0x40B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRQ14EG</name>
|
|
<description>IRQ14-DS Pin Edge Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ13EG</name>
|
|
<description>IRQ13-DS Pin Edge Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ12EG</name>
|
|
<description>IRQ12-DS Pin Edge Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ11EG</name>
|
|
<description>IRQ11-DS Pin Edge Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ10EG</name>
|
|
<description>IRQ10-DS Pin Edge Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ9EG</name>
|
|
<description>IRQ9-DS Pin Edge Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRQ8EG</name>
|
|
<description>IRQ8-DS Pin Edge Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPSIEGR2</name>
|
|
<description>Deep Standby Interrupt Edge Register 2</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DNMIEG</name>
|
|
<description>NMI Pin Edge Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated at a falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated at a rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD2IEG</name>
|
|
<description>LVD2 Edge Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated when VCC<Vdet2 (fall) is detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated when VCC>=Vdet2 (rise) is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLVD1IEG</name>
|
|
<description>LVD1 Edge Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A cancel request is generated when VCC<Vdet1 (fall) is detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A cancel request is generated when VCC>=Vdet1 (rise) is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYOCDCR</name>
|
|
<description>System Control OCD Control Register</description>
|
|
<addressOffset>0x40E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debugger Enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>On-chip debugger is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>On-chip debugger is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOCDF</name>
|
|
<description>Deep Standby OCD flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>On-chip debugger is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>On-chip debugger is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCONR</name>
|
|
<description>Standby Condition Register</description>
|
|
<addressOffset>0x40F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC3</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STCON</name>
|
|
<description>SSTBY condition bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>set this value in case of transferring to Software Standby Mode in using HOCO.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>set this value in case of transferring to Software Standby Mode in using expect for HOCO.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>LVD%sCR1</name>
|
|
<description>Voltage Monitor %s Circuit Control Register 1</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQSEL</name>
|
|
<description>Voltage Monitor Interrupt Type Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Maskable interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDTSEL</name>
|
|
<description>Voltage Monitor Interrupt Generation Condition Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Generate when VCC>=Vdet (rise) is detected</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate when VCC<Vdet (drop) is detected</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Generate when drop and rise are detected</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Settings prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>LVD%sSR</name>
|
|
<description>Voltage Monitor %s Circuit Status Register</description>
|
|
<addressOffset>0x0E1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MON</name>
|
|
<description>Voltage Monitor 1 Signal Monitor Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VCC < Vdet</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VCC >= Vdet or MON bit is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DET</name>
|
|
<description>Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vdet1 passage detection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LVCMPCR</name>
|
|
<description>Voltage Monitor Circuit Control Register</description>
|
|
<addressOffset>0x417</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVD2E</name>
|
|
<description>Voltage Detection 2 Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage detection 2 circuit disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage detection 2 circuit enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1E</name>
|
|
<description>Voltage Detection 1 Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage detection 1 circuit disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage detection 1 circuit enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LVDLVLR</name>
|
|
<description>Voltage Detection Level Select Register</description>
|
|
<addressOffset>0x418</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF3</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVD2LVL</name>
|
|
<description>Voltage Detection 2 Level Select (Standard voltage during fall in voltage)</description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>2.99V (Vdet2_1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>2.92V (Vdet2_2)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>2.85V (Vdet2_3)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1LVL</name>
|
|
<description>Voltage Detection 1 Level Select (Standard voltage during fall in voltage)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>2.99V (Vdet1_1)</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>2.92V (Vdet1_2)</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>2.85V (Vdet1_3)</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>LVD%sCR0</name>
|
|
<description>Voltage Monitor %s Circuit Control Register 0</description>
|
|
<addressOffset>0x41A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8A</resetValue>
|
|
<resetMask>0xF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RN</name>
|
|
<description>Voltage Monitor Reset Negate Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Negation follows a stabilization time (tLVD) after assertion of the LVD reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Voltage Monitor Circuit Mode Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage Monitor interrupt during Vdet1 passage</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage Monitor reset enabled when the voltage falls to and below Vdet1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSAMP</name>
|
|
<description>Sampling Clock Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1/2 LOCO frequency</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/4 LOCO frequency</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/8 LOCO frequency</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/16 LOCO frequency</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPE</name>
|
|
<description>Voltage Monitor Circuit Comparison Result Output Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable voltage monitor 1 circuit comparison result output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable voltage monitor 1 circuit comparison result output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFDIS</name>
|
|
<description>Voltage Monitor Digital Filter Disable Mode Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable digital filter</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable digital filter</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Voltage Monitor Interrupt/Reset Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VBTICTLR</name>
|
|
<description>VBATT Input Control Register</description>
|
|
<addressOffset>0x4BB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VCH2INEN</name>
|
|
<description>RTCIC2 Input Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCH1INEN</name>
|
|
<description>RTCIC1 Input Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCH0INEN</name>
|
|
<description>RTCIC0 Input Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>512</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-511</dimIndex>
|
|
<name>VBTBKR[%s]</name>
|
|
<description>VBATT Backup Register [%s]</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBTBKR</name>
|
|
<description>VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRCR</name>
|
|
<description>Protect Register</description>
|
|
<addressOffset>0x3FE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRKEY</name>
|
|
<description>PRKEY Key Code</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x5A</name>
|
|
<description>Enables writing to the PRCR register.</description>
|
|
<value>0x5A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Disables writing to the PRCR register.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRC3</name>
|
|
<description>Enables writing to the registers related to the LVD.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes not protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRC1</name>
|
|
<description>Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes not protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRC0</name>
|
|
<description>Enables writing to the registers related to the clock generation circuit.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes not protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTSR0</name>
|
|
<description>Reset Status Register 0</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x70</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPSRSTF</name>
|
|
<description>Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Deep software standby mode cancelation not requested by an interrupt. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Deep software standby mode cancelation requested by an interrupt. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD2RF</name>
|
|
<description>Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage Monitor 2 reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage Monitor 2 reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1RF</name>
|
|
<description>Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage Monitor 1 reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage Monitor 1 reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD0RF</name>
|
|
<description>Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage Monitor 0 reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage Monitor 0 reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORF</name>
|
|
<description>Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Power-on reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Power-on reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTSR2</name>
|
|
<description>Reset Status Register 2</description>
|
|
<addressOffset>0x411</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CWSF</name>
|
|
<description>Cold/Warm Start Determination Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cold start</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Warm start</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTSR1</name>
|
|
<description>Reset Status Register 1</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xE0F8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPERF</name>
|
|
<description>SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SP error reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SP error reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSMRF</name>
|
|
<description>Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus Master MPU reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus Master MPU reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSSRF</name>
|
|
<description>Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus Slave MPU reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus Slave MPU reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REERF</name>
|
|
<description>RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM ECC error reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM ECC error reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPERF</name>
|
|
<description>RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM parity error reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM parity error reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRF</name>
|
|
<description>Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTRF</name>
|
|
<description>Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog timer reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog timer reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IWDTRF</name>
|
|
<description>Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Independent watchdog timer reset not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Independent watchdog timer reset detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FWEPROR</name>
|
|
<description>Flash P/E Protect Register</description>
|
|
<addressOffset>0x416</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLWE</name>
|
|
<description>Flash Programming and Erasure</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prohibits programming and erasure of the code flash, data flash or blank checking.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Permits programming and erasure of the code flash, data flash or blank checking.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Prohibits programming and erasure of the code flash, data flash or blank checking.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Prohibits programming and erasure of the code flash, data flash or blank checking.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EDMAC0</name>
|
|
<description>DMA Controller for the Ethernet Controller Channel 0</description>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x48</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x50</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x58</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x64</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x78</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC8</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD4</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EDMR</name>
|
|
<description>EDMAC Mode Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DE</name>
|
|
<description>Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Big endian mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Little endian mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DL</name>
|
|
<description>Transmit/Receive DescriptorLength</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>16 bytes</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>32 bytes</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>64 bytes</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>16 bytes</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software Reset</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDTRR</name>
|
|
<description>EDMAC Transmit Request Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Transmit Request</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDRRR</name>
|
|
<description>EDMAC Receive Request Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RR</name>
|
|
<description>Receive Request</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive descriptor is read, and the receive function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDLAR</name>
|
|
<description>Transmit Descriptor List Start Address Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDLAR</name>
|
|
<description>The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDLAR</name>
|
|
<description>Receive Descriptor List Start Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDLAR</name>
|
|
<description>The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EESR</name>
|
|
<description>ETHERC/EDMAC Status Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TWB</name>
|
|
<description>Write-Back Complete Flag</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write-back has not been completed, or no transmission has been requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write-back to the transmit descriptor has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TABT</name>
|
|
<description>Transmit Abort Detect Flag</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame transmission has not been aborted or no transmission has been requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame transmission has been aborted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABT</name>
|
|
<description>Receive Abort Detect Flag</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame reception has not been aborted or no reception has been requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame reception has been aborted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCOF</name>
|
|
<description>Receive Frame Counter Overflow Flag</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive frame counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADE</name>
|
|
<description>Address Error Flag</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid memory address has not been detected (normal operation).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invalid memory address has been detected. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECI</name>
|
|
<description>ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared.</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ETHERC status interrupt source has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ETHERC status interrupt source has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Frame Transfer Complete Flag</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer have not been completed, or no transfer has been requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Transmit Descriptor Empty Flag</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUF</name>
|
|
<description>Transmit FIFO Underflow Flag</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Underflow has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>Frame Receive Flag</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame has not been received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame has been received. Update of the receive descriptor is complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDE</name>
|
|
<description>Receive Descriptor Empty Flag</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOF</name>
|
|
<description>Receive FIFO Overflow Flag</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Overflow has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CND</name>
|
|
<description>Carrier Not Detect Flag</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A carrier has been detected when transmission starts.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A carrier has not been detected during preamble transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Loss of Carrier Detect Flag</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loss of carrier has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of carrier has been detected during frame transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CD</name>
|
|
<description>Late Collision Detect Flag</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Late collision has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Late collision has been detected during frame transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRO</name>
|
|
<description>Transmit Retry Over Flag</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit retry-over condition has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit retry-over condition has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMAF</name>
|
|
<description>Multicast Address Frame Receive Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Multicast address frame has not been received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Multicast address frame has been received.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Alignment Error Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Alignment error has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alignment error has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTLF</name>
|
|
<description>Frame-Too-Long Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame-too-long error has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame-too-long error has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSF</name>
|
|
<description>Frame-Too-Short Error Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame-too-short error has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame-too-short error has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE</name>
|
|
<description>PHY-LSI Receive Error Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PHY-LSI receive error has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PHY-LSI receive error has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERF</name>
|
|
<description>CRC Error Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EESIPR</name>
|
|
<description>ETHERC/EDMAC Status Interrupt Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TWBIP</name>
|
|
<description>Write-Back Complete Interrupt Request Enable</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write-back complete interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write-back complete interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TABTIP</name>
|
|
<description>Transmit Abort Detect Interrupt Request Enable</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit abort detect interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit abort detect interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABTIP</name>
|
|
<description>Receive Abort Detect Interrupt Request Enable</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive abort detect interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive abort detect interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCOFIP</name>
|
|
<description>Receive Frame Counter Overflow Interrupt Request Enable</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive frame counter overflow interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive frame counter overflow interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEIP</name>
|
|
<description>Address Error Interrupt Request Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Address error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECIIP</name>
|
|
<description>ETHERC Status Register Source Interrupt Request Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ETHERC status interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ETHERC status interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIP</name>
|
|
<description>Frame Transfer Complete Interrupt Request Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame transmission complete interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame transmission complete interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDEIP</name>
|
|
<description>Transmit Descriptor Empty Interrupt Request Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit descriptor empty interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit descriptor empty interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUFIP</name>
|
|
<description>Transmit FIFO Underflow Interrupt Request Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Underflow interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underflow interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRIP</name>
|
|
<description>Frame Receive Interrupt Request Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame reception interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame reception interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDEIP</name>
|
|
<description>Receive Descriptor Empty Interrupt Request Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive descriptor empty interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive descriptor empty interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFOFIP</name>
|
|
<description>Receive FIFO Overflow Interrupt Request Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Overflow interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overflow interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNDIP</name>
|
|
<description>Carrier Not Detect Interrupt Request Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Carrier not detect interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Carrier not detect interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLCIP</name>
|
|
<description>Loss of Carrier Detect Interrupt Request Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loss of carrier detect interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of carrier detect interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDIP</name>
|
|
<description>Late Collision Detect Interrupt Request Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Late collision detect interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Late collision detect interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TROIP</name>
|
|
<description>Transmit Retry Over Interrupt Request Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit retry over interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit retry over interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMAFIP</name>
|
|
<description>Multicast Address Frame Receive Interrupt Request Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Multicast address frame receive interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Multicast address frame receive interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRFIP</name>
|
|
<description>Alignment Error Interrupt Request Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Alignment error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alignment error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTLFIP</name>
|
|
<description>Frame-Too-Long Error Interrupt Request Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame-too-long error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame-too-long error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSFIP</name>
|
|
<description>Frame-Too-Short Error Interrupt Request Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame-too-short error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame-too-short error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PREIP</name>
|
|
<description>PHY-LSI Receive Error Interrupt Request Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PHY-LSI receive error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PHY-LSI receive error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CERFIP</name>
|
|
<description>CRC Error Interrupt Request Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRSCER</name>
|
|
<description>ETHERC/EDMAC Transmit/Receive Status Copy Enable Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMAFCE</name>
|
|
<description>RMAF Flag Copy Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRFCE</name>
|
|
<description>RRF Flag Copy Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMFCR</name>
|
|
<description>Missed-Frame Counter Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MFC</name>
|
|
<description>Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFTR</name>
|
|
<description>Transmit FIFO Threshold Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFT</name>
|
|
<description>Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x000</minimum>
|
|
<maximum>0x200</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x000</name>
|
|
<description>Store and forward mode</description>
|
|
<value>0x000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Transmit FIFO Threshold Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFD</name>
|
|
<description>Receive FIFO Depth</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>4096 bytes</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFD</name>
|
|
<description>Transmit FIFO Depth</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>2048 bytes</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMCR</name>
|
|
<description>Receive Method Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RNR</name>
|
|
<description>Receive Request Reset</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFUCR</name>
|
|
<description>Transmit FIFO Underflow Counter</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNDER</name>
|
|
<description>Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFOCR</name>
|
|
<description>Receive FIFO Overflow Counter</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVER</name>
|
|
<description>Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOSR</name>
|
|
<description>Independent Output Signal Setting Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELB</name>
|
|
<description>External Loopback Mode</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ETn_EXOUT pin outputs low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ETn_EXOUT pin outputs high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFTR</name>
|
|
<description>Flow Control Start FIFO Threshold Setting Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00070007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFFO</name>
|
|
<description>Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.)</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>When 2 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>When 4 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>When 6 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>When 8 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>When 10 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>When 12 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>When 14 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>When 16 receive frames have been stored in the receive FIFO.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFDO</name>
|
|
<description>Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.)</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>When 224 ( 256 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>When 480 ( 512 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>When 736 ( 768 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>When 992 (1024 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>When 1248 (1280 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>When 1504 (1536 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>When 1760 (1792 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>When 2016 (2048 - 32) bytes of data is stored in the receive FIFO.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPADIR</name>
|
|
<description>Receive Data Padding Insert Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PADS</name>
|
|
<description>Padding Size</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No padding is inserted.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1 byte is inserted.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>2 bytes are inserted.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>3 bytes are inserted.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PADR</name>
|
|
<description>Padding Slot</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00h</name>
|
|
<description>Padding is inserted at the head of received data.</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIMD</name>
|
|
<description>Transmit Interrupt Setting Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIM</name>
|
|
<description>Transmit Interrupt Mode</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIS</name>
|
|
<description>Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBWAR</name>
|
|
<description>Receive Buffer Write Address Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBWAR</name>
|
|
<description>Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDFAR</name>
|
|
<description>Receive Descriptor Fetch Address Register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDFAR</name>
|
|
<description>Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBRAR</name>
|
|
<description>Transmit Buffer Read Address Register</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBRAR</name>
|
|
<description>Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDFAR</name>
|
|
<description>Transmit Descriptor Fetch Address Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDFAR</name>
|
|
<description>Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ETHERC0</name>
|
|
<description>Ethernet Controller Channel 0</description>
|
|
<baseAddress>0x40064100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x50</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x60</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC8</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD0</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE4</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ECMR</name>
|
|
<description>ETHERC Mode Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPC</name>
|
|
<description>PAUSE Frame Transmit</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PAUSE frame is transmitted even during a PAUSE period.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PAUSE frame is not transmitted during a PAUSE period.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZPF</name>
|
|
<description>0 Time PAUSE Frame Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PAUSE frame that contains the pause_time parameter of 0 is not used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PAUSE frame that contains the pause_time parameter of 0 is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFR</name>
|
|
<description>PAUSE Frame Receive Mode</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PAUSE frame is not transferred to the EDMAC.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PAUSE frame is transferred to the EDMAC.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXF</name>
|
|
<description>Receive Flow Control Operating Mode</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PAUSE frame detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PAUSE frame detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXF</name>
|
|
<description>Transmit Flow Control Operating Mode</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRCEF</name>
|
|
<description>CRC Error Frame Receive Mode</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EDMAC is notified of a CRC error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EDMAC is not notified of a CRC error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPDE</name>
|
|
<description>Magic Packet Detection Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Magic Packet detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Magic Packet detection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Reception Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmission Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILB</name>
|
|
<description>Internal Loopback Mode</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal data transmission or reception is performed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is looped back in the ETHERC when full-duplex mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTM</name>
|
|
<description>Bit Rate</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>10 Mbps</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>100 Mbps</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DM</name>
|
|
<description>Duplex Mode</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Half-duplex mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Full-duplex mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRM</name>
|
|
<description>Promiscuous Mode</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Promiscuous mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Promiscuous mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFLR</name>
|
|
<description>Receive Frame Maximum Length Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFL</name>
|
|
<description>Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECSR</name>
|
|
<description>ETHERC Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BFR</name>
|
|
<description>Continuous Broadcast Frame Reception Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous reception of broadcast frames has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous reception of broadcast frames has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSRTO</name>
|
|
<description>PAUSE Frame Retransmit Over Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PAUSE frame retransmit count has not reached the upper limit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PAUSE frame retransmit count has reached the upper limit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCHNG</name>
|
|
<description>LCHNG Link Signal Change Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Change in the ETn_LINKSTA signal has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Change in the ETn_LINKSTA signal has been detected (high to low, or low to high).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPD</name>
|
|
<description>Magic Packet Detect Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Magic Packet has not been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Magic Packet has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICD</name>
|
|
<description>False Carrier Detect Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PHY-LSI has not detected a false carrier on the line.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PHY-LSI has detected a false carrier on the line.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECSIPR</name>
|
|
<description>ETHERC Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BFSIPR</name>
|
|
<description>Continuous Broadcast Frame Reception Interrupt Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Notification of continuous broadcast frame reception interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Notification of continuous broadcast frame reception interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSRTOIP</name>
|
|
<description>PAUSE Frame Retransmit Over Interrupt Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Notification of PAUSE frame retransmit over interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Notification of PAUSE frame retransmit over interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCHNGIP</name>
|
|
<description>LINK Signal Change Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Notification of ETn_LINKSTA signal change interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Notification of ETn_LINKSTA signal change interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPDIP</name>
|
|
<description>Magic Packet Detect Interrupt Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Notification of the Magic Packet detect interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Notification of the Magic Packet detect interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICDIP</name>
|
|
<description>False Carrier Detect Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Notification of the false carrier detect interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Notification of the false carrier detect interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIR</name>
|
|
<description>PHY Interface Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDI</name>
|
|
<description>MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MDO</name>
|
|
<description>MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read).</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMD</name>
|
|
<description>MII/RMII Management Mode</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDC</name>
|
|
<description>MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>PHY Status Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LMON</name>
|
|
<description>ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDMLR</name>
|
|
<description>Random Number Generation Counter Upper Limit Setting Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMD</name>
|
|
<description>Random Number Generation Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000h</name>
|
|
<description>Normal operation</description>
|
|
<value>0x00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPGR</name>
|
|
<description>IPG Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000014</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPG</name>
|
|
<description>Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" </description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>14h</name>
|
|
<description>96 bit time (initial value)</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>(IPGx4+16) bit time</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APR</name>
|
|
<description>Automatic PAUSE Frame Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPR</name>
|
|
<description>Manual PAUSE Frame Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFF0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MP</name>
|
|
<description>Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFCF</name>
|
|
<description>Received PAUSE Frame Counter</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RPAUSE</name>
|
|
<description>Received PAUSE Frame CountNumber of received PAUSE frames</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPAUSER</name>
|
|
<description>PAUSE Frame Retransmit Count Setting Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPAUSE</name>
|
|
<description>Automatic PAUSE Frame Retransmit Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0000</name>
|
|
<description>Number of retransmissions is unlimited</description>
|
|
<value>0x0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Maximum number of retransmissions is (TPAUSE)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPAUSECR</name>
|
|
<description>PAUSE Frame Retransmit Counter</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>BCFRR</name>
|
|
<description>Broadcast Frame Receive Count Setting Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCF</name>
|
|
<description>Broadcast Frame Continuous Receive Count Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000h</name>
|
|
<description>Number of receptions is unlimited.</description>
|
|
<value>0x0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Receive (BFC) frame.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAHR</name>
|
|
<description>MAC Address Upper Bit Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAHR</name>
|
|
<description>MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MALR</name>
|
|
<description>MAC Address Lower Bit Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MALR</name>
|
|
<description>MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TROCR</name>
|
|
<description>Transmit Retry Over Counter Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TROCR</name>
|
|
<description>Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDCR</name>
|
|
<description>Late Collision Detect Counter Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>LCCR</name>
|
|
<description>Lost Carrier Counter Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCCR</name>
|
|
<description>Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDCR</name>
|
|
<description>Carrier Not Detect Counter Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNDCR</name>
|
|
<description>Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEFCR</name>
|
|
<description>CRC Error Frame Receive Counter Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEFCR</name>
|
|
<description>CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRECR</name>
|
|
<description>Frame Receive Error Counter Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRECR</name>
|
|
<description>Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSFRCR</name>
|
|
<description>Too-Short Frame Receive Counter Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSFRCR</name>
|
|
<description>Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TLFRCR</name>
|
|
<description>Too-Long Frame Receive Counter Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TLFRCR</name>
|
|
<description>Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFCR</name>
|
|
<description>Received Alignment Error Frame Counter Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFCR</name>
|
|
<description>Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets).</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAFCR</name>
|
|
<description>Multicast Address Frame Receive Counter Register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAFCR</name>
|
|
<description>Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>clear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SDHI0</name>
|
|
<description>SD Host Interface 0</description>
|
|
<baseAddress>0x40062000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>84</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x58</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x68</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1B0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C0</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E0</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SD_CMD</name>
|
|
<description>Command Type Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD12AT</name>
|
|
<description>Multiple Block Transfer Mode (enabled at multiple block transfer)</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>CMD12 is automatically issued at multiple block transfer.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMD12 is not automatically issued at multiple block transfer.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRSTP</name>
|
|
<description>Single/Multiple Block Transfer (enabled when the command with data is handled)</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single block transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Multiple block transfer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDRW</name>
|
|
<description>Write/Read Mode (enabled when the command with data is handled)</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write (SD/MMC host interface -> SD card/MMC)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read (SD/MMC host interface <- SD card/MMC)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDTP</name>
|
|
<description>Data Mode (Command Type)</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command does not include data transfer (bc, bcr, or ac)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command includes data transfer (adtc)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTP</name>
|
|
<description>Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type.</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. </description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Expansion mode and no response</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Expansion mode and R1, R5, R6, or R7 response</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Expansion mode and R1b response</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Expansion mode and R2 response</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Expansion mode and R3 or R4 response</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMD</name>
|
|
<description>Command Type Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>CMD</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ACMD</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_ARG</name>
|
|
<description>SD Command Argument Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_ARG</name>
|
|
<description>Argument RegisterSet command format[39:8] (argument)</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_ARG1</name>
|
|
<description>SD Command Argument Register 1</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_ARG1</name>
|
|
<description>Argument Register 1Set command format[39:24] (argument)</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_STOP</name>
|
|
<description>Data Stop Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables SD_SECCNT setting value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables SD_SECCNT setting value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STP</name>
|
|
<description>Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_SECCNT</name>
|
|
<description>Block Count Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_SECCNT</name>
|
|
<description>Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP10</name>
|
|
<description>SD Card Response Register 10</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP10</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP1</name>
|
|
<description>SD Card Response Register 1</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP1</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP32</name>
|
|
<description>SD Card Response Register 32</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP32</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP3</name>
|
|
<description>SD Card Response Register 3</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP3</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP54</name>
|
|
<description>SD Card Response Register 54</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP54</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP5</name>
|
|
<description>SD Card Response Register 5</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP5</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP76</name>
|
|
<description>SD Card Response Register 76</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP76</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>23</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_RSP7</name>
|
|
<description>SD Card Response Register 7</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_RSP7</name>
|
|
<description>Store the response from the SD card/MMC</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_INFO1</name>
|
|
<description>SD Card Interrupt Flag Register 1</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFB5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDD3MON</name>
|
|
<description>Inticates the SDnDAT3 State</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDnDAT3 is set to 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDnDAT3 is set to 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDD3IN</name>
|
|
<description>SDnDAT3 Card Insertion</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD card insertion not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD card insertion detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDD3RM</name>
|
|
<description>SDnDAT3 Card Removal</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD card removal not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD card removal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDWPMON</name>
|
|
<description>Indicates the SDnWP state</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDnWP is set to 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDnWP is set to 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCDMON</name>
|
|
<description>Indicates the SDnCD state</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCDIN</name>
|
|
<description>SDnCD Card Insertion</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card insertion not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card insertion detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCDRM</name>
|
|
<description>SDnCD Card Removal</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card removal not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card removal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACEND</name>
|
|
<description>Access End</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Access end is not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access end is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPEND</name>
|
|
<description>Response End Detection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Response end is not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Response end is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_INFO2</name>
|
|
<description>SD Card Interrupt Flag Register 2</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<resetMask>0xFFFFFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILA</name>
|
|
<description>Illegal Access Error</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal access error not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal access error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CBSY</name>
|
|
<description>Command Type Register Busy</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A command sequence is being executed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A command sequence has been completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SD_CLK_CTRLEN</name>
|
|
<description>When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SD/MMC bus (CMD, DAT) is not busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWE</name>
|
|
<description>SD_BUF Write Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data can be written in SD_BUF0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data cannot be written in SD_BUF0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRE</name>
|
|
<description>SD_BUF Read Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data can be read from SD_BUF0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data cannot be read from SD_BUF0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDD0MON</name>
|
|
<description>SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDDAT0 is set to 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDDAT0 is set to 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTO</name>
|
|
<description>Response Timeout</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Response timeout not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Response timeout detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILR</name>
|
|
<description>SD_BUF Illegal Read Access</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal read access to the SD_BUF register not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal read access to the SD_BUF register detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILW</name>
|
|
<description>SD_BUF Illegal Write Access</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal write access to the SD_BUF register not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal write access to the SD_BUF register detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTO</name>
|
|
<description>Data Timeout </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data timeout not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data timeout detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDE</name>
|
|
<description>END Error</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>End bit error not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End bit error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCE</name>
|
|
<description>CRC Error</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDE</name>
|
|
<description>Command Error</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command error not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_INFO1_MASK</name>
|
|
<description>SD_INFO1 Interrupt Mask Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000031D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDD3INM</name>
|
|
<description>SDnDAT3 Card Insertion Interrupt Request Mask</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD card insertion interrupt request by the SDnDAT3 is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD card insertion interrupt request by the SDnDAT3 is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDD3RMM</name>
|
|
<description>SDnDAT3 Card Removal Interrupt Request Mask</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD card removal interrupt request by the SDnDAT3 is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD card removal interrupt request by the SDnDAT3 is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCDINM</name>
|
|
<description>SDnCD card Insertion Interrupt Request Mask</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card insertion interrupt request by the SDnCD is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card insertion interrupt request by the SDnCD is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDCDRMM</name>
|
|
<description>SDnCD card Removal Interrupt Request Mask</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Card removal interrupt request by the by the SDnCD is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Card removal interrupt request by the by the SDnCD is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACENDM</name>
|
|
<description> Access End Interrupt Request Mask</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Access end interrupt request is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access end interrupt request is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPENDM</name>
|
|
<description> Response End Interrupt Request Mask</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Response end interrupt request is not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Response end interrupt request is masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_INFO2_MASK</name>
|
|
<description>SD_INFO2 Interrupt Mask Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008B7F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILAM</name>
|
|
<description>Illegal Access Error Interrupt Request Mask</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal access error interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal access error interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWEM</name>
|
|
<description>BWE Interrupt Request Mask</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write enable interrupt request for the SD_BUF register not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write enable interrupt request for the SD_BUF register masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BREM</name>
|
|
<description>BRE Interrupt Request Mask</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read enable interrupt request for the SD buffer not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read enable interrupt request for the SD buffer masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTOM</name>
|
|
<description> Response Timeout Interrupt Request Mask</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Response timeout interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Response timeout interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILRM</name>
|
|
<description>SD_BUF Register Illegal Read Interrupt Request Mask</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal read detection interrupt request for the SD_BUF register not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal read detection interrupt request for the SD_BUF register masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILWM</name>
|
|
<description>SD_BUF Register Illegal Write Interrupt Request Mask</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Illegal write detection interrupt request for the SD_BUF register not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Illegal write detection interrupt request for the SD_BUF register masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTOM</name>
|
|
<description> Data Timeout Interrupt Request Mask</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data timeout interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data timeout interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDEM</name>
|
|
<description> End Bit Error Interrupt Request Mask</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>End bit detection error interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End bit detection error interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCEM</name>
|
|
<description>CRC Error Interrupt Request Mask</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDEM</name>
|
|
<description>Command Error Interrupt Request Mask</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command error interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command error interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_CLK_CTRL</name>
|
|
<description>SD Clock Control Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKCTRLEN</name>
|
|
<description>SD/MMC Clock Output Automatic Control Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic control for SD/MMC Clock output is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic control for SD/MMC Clock output is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>SD/MMC Clock Output Control Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SD/MMC Clock output is disabled. The SDCLK signal is fixed 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SD/MMC Clock output is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>SDHI Clock Frequency Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x00</name>
|
|
<description>PCLKA divided by 2</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x01</name>
|
|
<description>PCLKA divided by 4</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x02</name>
|
|
<description>PCLKA divided by 8</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x04</name>
|
|
<description>PCLKA divided by 16</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x08</name>
|
|
<description>PCLKA divided by 32</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x10</name>
|
|
<description>PCLKA divided by 64</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x20</name>
|
|
<description>PCLKA divided by 128</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x40</name>
|
|
<description>PCLKA divided by 256</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x80</name>
|
|
<description>PCLKA divided by 512</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_SIZE</name>
|
|
<description>Transfer Data Length Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_OPTION</name>
|
|
<description>SD Card Access Control Option Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000040EE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1-bit width (WIDTH8=0 or 1 ) </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIDTH8</name>
|
|
<description>Bus Widthsee b15, WIDTH bit</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOUTMASK</name>
|
|
<description>Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Activate Timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Timeout Counter</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>SDHI clock x 2^(TOP+13)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTOP</name>
|
|
<description>Card Detect Time Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>IMCLK x 2^(CTOP+10)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_ERR_STS1</name>
|
|
<description>SD Error Status Register 1</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCTK</name>
|
|
<description>CRC Status TokenStore the CRC status token value (normal value is 010b)</description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCTKE</name>
|
|
<description> CRC Status Token Error</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occured in the CRC status.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the CRC status.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCRCE</name>
|
|
<description> Read Data CRC Error</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error has detected in read data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error has not detected in read data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPCRCE1</name>
|
|
<description> Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC error has not occured.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error has occured in the response to a command issued within a command sequence.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPCRCE0</name>
|
|
<description> Response CRC Error 0NOTE: other than a response to a command issued within a command sequence</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A CRC error has not occur in a response</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A CRC error has occured in a response</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCLENE</name>
|
|
<description> CRC Status Token Length Error</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occured in the CRC status length.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the CRC status length (and the end bit has not been detected)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDLENE</name>
|
|
<description> Read Data Length Error</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has occurred not in the read data length.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the read data length (and the end bit has not been detected among the valid bits).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPLENE1</name>
|
|
<description> Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occurred in the response length to a command issued within a command sequence.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the response length to a command issued within a command sequence.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPLENE0</name>
|
|
<description> Response Length Error 0NOTE: other than a response to a command issued within a command sequence</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occured in the response length</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the response length</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDE1</name>
|
|
<description>Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occurs in the command index of the response to a command issued within a command sequence.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the command index of the response to a command issued within a command sequence.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMDE0</name>
|
|
<description>Command Error 0NOTE: other than a response to a command issued within a command sequence</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error has not occured in the command index of a response.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error has occured in the command index of a response.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_ERR_STS2</name>
|
|
<description>SD Error Status Register 2</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCBSYTO</name>
|
|
<description>CRC Status Token Busy Timeout</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The busy state continues for longer than N-cycle after the CRC status</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCTO</name>
|
|
<description>CRC Status Token Timeout</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The CRC status is not received though a longer time than N-cycle has elapsed after data writing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDTO</name>
|
|
<description>Read Data Timeout </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSYTO1</name>
|
|
<description> Busy Timeout 1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSYTO0</name>
|
|
<description> Busy Timeout 0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The busy state for longer than N-cycle continues after R1b response.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTO1</name>
|
|
<description>Response Timeout 1 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSPTO0</name>
|
|
<description>Response Timeout 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_BUF0</name>
|
|
<description>SD Buffer Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SD_BUF</name>
|
|
<description>SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. </description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIO_MODE</name>
|
|
<description>SDIO Mode Control Register</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>C52PUB</name>
|
|
<description>SDIO None AbortNOTE: See manual </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IOABT</name>
|
|
<description>SDIO AbortNOTE: See manual</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RWREQ</name>
|
|
<description>Read Wait Request</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Allow SD/MMC to exit read wait state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request for SD/MMC to enter read wait state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description> SDIO Mode</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the SD host interface to receive SDIO interrupt from the SDIO card</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the SD host interface to receive SDIO interrupt from the SDIO card</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIO_INFO1</name>
|
|
<description>SDIO Interrupt Flag Register 1</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXWT</name>
|
|
<description>EXWT Status FlagNOTE: See manual</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
</field>
|
|
<field>
|
|
<name>EXPUB52</name>
|
|
<description>EXPUB52 Status FlagNOTE: See manual</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
</field>
|
|
<field>
|
|
<name>IOIRQ</name>
|
|
<description>SDIO Interrupt Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SDIO interrupt not accepted</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SDIO interrupt accepted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIO_INFO1_MASK</name>
|
|
<description>SDIO_INFO1 Interrupt Mask Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000C007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXWTM</name>
|
|
<description>EXWT Interrupt Request Mask Control</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EXWT interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EXWT interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXPUB52M</name>
|
|
<description>EXPUB52 Interrupt Request Mask Control</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EXPUB52 interrupt request not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EXPUB52 interrupt request masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOIRQM</name>
|
|
<description>IOIRQ Interrupt Mask Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IOIRQ interrupt not masked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IOIRQ interrupt masked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SD_DMAEN</name>
|
|
<description>DMA Mode Enable Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>SD_BUF Read/Write DMA Transfer</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The SD_BUF read/write DMA transfer is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The SD_BUF read/write DMA transfer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFT_RST</name>
|
|
<description>Software Reset Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDRST</name>
|
|
<description>Software Reset of SD I/F Unit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset released</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIF_MODE</name>
|
|
<description>SD Interface Mode Setting Register</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOCHKCR</name>
|
|
<description>CRC Check Mask (for MMC test commands)</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CRC check is valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXT_SWAP</name>
|
|
<description>Swap Control Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRSWP</name>
|
|
<description>SD_BUF0 Swap Read</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The current data are read without swapping.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BWSWP</name>
|
|
<description>SD_BUF0 Swap Write</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The current data are written without swapping.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SDHI0">
|
|
<name>SDHI1</name>
|
|
<description>SD Host Interface 1</description>
|
|
<baseAddress>0x40062400</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>CRC Calculator</description>
|
|
<baseAddress>0x40074000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CRCCR0</name>
|
|
<description>CRC Control Register0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DORCLR</name>
|
|
<description>CRCDOR Register Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the CRCDOR register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMS</name>
|
|
<description>CRC Calculation Switching</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generates CRC for LSB first communication.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generates CRC for MSB first communication.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPS</name>
|
|
<description>CRC Generating Polynomial Switching</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No calculation is executed.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>8-bit CRC-8 (X8 + X2 + X + 1)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>16-bit CRC-16 (X16 + X15 + X2 + 1)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>16-bit CRC-CCITT (X16 + X12 + X5 + 1)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>No calculation is executed.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCCR1</name>
|
|
<description>CRC Control Register1</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCSEN</name>
|
|
<description>Snoop enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCSWR</name>
|
|
<description>Snoop-on-write/read switch bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Snoop-on-read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Snoop-on-write</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDIR</name>
|
|
<description>CRC Data Input Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDIR</name>
|
|
<description>Calculation input Data (Case of CRC-32, CRC-32C )</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDIR_BY</name>
|
|
<description>CRC Data Input Register (byte access)</description>
|
|
<alternateRegister>CRCDIR</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDIR_BY</name>
|
|
<description>Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT )</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDOR</name>
|
|
<description>CRC Data Output Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDOR</name>
|
|
<description>Calculation output Data (Case of CRC-32, CRC-32C )</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDOR_HA</name>
|
|
<description>CRC Data Output Register (halfword access)</description>
|
|
<alternateRegister>CRCDOR</alternateRegister>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDOR_HA</name>
|
|
<description>Calculation output Data (Case of CRC-16 or CRC-CCITT )</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDOR_BY</name>
|
|
<description>CRC Data Output Register(byte access)</description>
|
|
<alternateRegister>CRCDOR</alternateRegister>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCDOR_BY</name>
|
|
<description>Calculation output Data (Case of CRC-8 )</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCSAR</name>
|
|
<description>Snoop Address Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRCSA</name>
|
|
<description>snoop address bitSet the I/O register address to snoop</description>
|
|
<lsb>0</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0003</name>
|
|
<description>SCI0.TDR</description>
|
|
<value>0x0003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0005</name>
|
|
<description>SCI0.RDR</description>
|
|
<value>0x0005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0023</name>
|
|
<description>SCI1.TDR</description>
|
|
<value>0x0023</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0025</name>
|
|
<description>SCI1.RDR</description>
|
|
<value>0x0025</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0043</name>
|
|
<description>SCI2.TDR</description>
|
|
<value>0x0043</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0045</name>
|
|
<description>SCI2.RDR</description>
|
|
<value>0x0045</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0063</name>
|
|
<description>SCI3.TDR</description>
|
|
<value>0x0063</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0065</name>
|
|
<description>SCI3.RDR</description>
|
|
<value>0x0065</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0083</name>
|
|
<description>SCI4.TDR</description>
|
|
<value>0x0083</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0085</name>
|
|
<description>SCI4.RDR</description>
|
|
<value>0x0085</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00A3</name>
|
|
<description>SCI5.TDR</description>
|
|
<value>0x00A3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00A5</name>
|
|
<description>SCI5.RDR</description>
|
|
<value>0x00A5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00C3</name>
|
|
<description>SCI6.TDR</description>
|
|
<value>0x00C3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00C5</name>
|
|
<description>SCI6.RDR</description>
|
|
<value>0x00C5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00E3</name>
|
|
<description>SCI7.TDR</description>
|
|
<value>0x00E3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x00E5</name>
|
|
<description>SCI7.RDR</description>
|
|
<value>0x00E5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0103</name>
|
|
<description>SCI8.TDR</description>
|
|
<value>0x0103</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0105</name>
|
|
<description>SCI8.RDR</description>
|
|
<value>0x0105</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0123</name>
|
|
<description>SCI9.TDR</description>
|
|
<value>0x0123</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x0125</name>
|
|
<description>SCI9.RDR</description>
|
|
<value>0x0125</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CTSU</name>
|
|
<description>Capacitive Touch Sensing Unit</description>
|
|
<baseAddress>0x40081000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>9</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0B</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTSUCR0</name>
|
|
<description>CTSU Control Register 0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUTXVSEL</name>
|
|
<description>CTSU Transmission power supply selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Select Vcc</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Select internal logic power supply</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUINIT</name>
|
|
<description>CTSU Control Block Initialization</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing a 0 has no effect, this bit is read as 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>initializes the CTSU control block and registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSNZ</name>
|
|
<description>CTSU Wait State Power-Saving Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Power-saving function during wait state is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Power-saving function during wait state is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUCAP</name>
|
|
<description>CTSU Measurement Operation Start Trigger Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSTRT</name>
|
|
<description>CTSU Measurement Operation Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Measurement operation stops.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Measurement operation starts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCR1</name>
|
|
<description>CTSU Control Register 1</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUMD</name>
|
|
<description>CTSU Measurement Mode Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Self-capacitance single scan mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Self-capacitance multi-scan mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mutual capacitance simple scan mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Mutual capacitance full scan mode</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUCLK</name>
|
|
<description>CTSU Operating Clock Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/2 (PCLK divided by 2)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/2 (PCLK divided by 4)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUATUNE1</name>
|
|
<description>CTSU Power Supply Capacity Adjustment </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-current output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUCSW</name>
|
|
<description>CTSU LPF Capacitance Charging Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Turned off capacitance switch</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Turned on capacitance switch</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUPON</name>
|
|
<description>CTSU Power Supply Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Powered off the CTSU</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Powered on the CTSU</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSDPRS</name>
|
|
<description>CTSU Synchronous Noise Reduction Setting Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSOFF</name>
|
|
<description>CTSU High-Pass Noise Reduction Function Off Setting</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High-pass noise reduction function turned on</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-pass noise reduction function turned off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUPRMODE</name>
|
|
<description>CTSU Base Period and Pulse Count Setting</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>510 pulses</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>126 pulses</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>62 pulses (recommended setting value)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUPRRATIO</name>
|
|
<description>CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b)</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSST</name>
|
|
<description>CTSU Sensor Stabilization Wait Control Register </description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSST</name>
|
|
<description>CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUMCH0</name>
|
|
<description>CTSU Measurement Channel Register 0</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUMCH0</name>
|
|
<description>CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'11111 in mode other than self-capacitor single scan mode, the measurement is stopped.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTSUMCH0</name>
|
|
<description>The value of CTSUMCH0 indicate to channel to be measured.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUMCH1</name>
|
|
<description>CTSU Measurement Channel Register 1</description>
|
|
<addressOffset>0x05</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUMCH1</name>
|
|
<description>CTSU Measurement Channel 1 Note1: If the value of CTSUMCH1 was set to b'11111, the measurement is stopped.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTSUMCH1</name>
|
|
<description>The value of CTSUMCH1 indicate to channel to be measured.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHAC0</name>
|
|
<description>CTSU Channel Enable Control Register 0</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUCHAC0</name>
|
|
<description>CTSU Channel Enable Control 0.0: Not measurement target1: Measurement targetNote: CTSUCHAC0[0] corresponds to TS00 and CTSUCHAC0[7] corresponds to TS07.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTSUCHAC0</name>
|
|
<description>TS pin which correspond to the bit number of CTSUCHAC0 register set whether the measurement target.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHAC1</name>
|
|
<description>CTSU Channel Enable Control Register 1</description>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUCHAC1</name>
|
|
<description>CTSU Channel Enable Control 1.0: Not measurement target1: Measurement targetNote: CTSUCHAC1[0] corresponds to TS08 and CTSUCHAC1[7] corresponds to TS15. </description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTSUCHAC1</name>
|
|
<description>TS pin which correspond to the bit number of CTSUCHAC1 register set whether the measurement target.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHAC2</name>
|
|
<description>CTSU Channel Enable Control Register 2</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHTRC0</name>
|
|
<description>CTSU Channel Transmit/Receive Control Register 0</description>
|
|
<addressOffset>0x0B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUCHTRC0</name>
|
|
<description>CTSU Channel Transmit/Receive Control 0CTSUCHTRC0[0] corresponds to TS00 and CTSUCHTRC0[7] corresponds to TS07. ( 0: Reception / 1: Transmission )</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHTRC1</name>
|
|
<description>CTSU Channel Transmit/Receive Control Register 1</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUCHTRC1</name>
|
|
<description>CTSU Channel Transmit/Receive Control 1CTSUCHTRC1[0] corresponds to TS08 and CTSUCHTRC1[7] corresponds to TS15. ( 0: Reception / 1: Transmission )</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUCHTRC2</name>
|
|
<description>CTSU Channel Transmit/Receive Control Register 2</description>
|
|
<addressOffset>0x0D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CTSUDCLKC</name>
|
|
<description>CTSU High-Pass Noise Reduction Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSSCNT</name>
|
|
<description>CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b.</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSSMOD</name>
|
|
<description>CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b.</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUST</name>
|
|
<description>CTSU Status Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUPS</name>
|
|
<description>CTSU Mutual Capacitance Status Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>First measurement</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Second measurement</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUROVF</name>
|
|
<description>CTSU Reference Counter Overflow Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overflow</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overflow</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSOVF</name>
|
|
<description>CTSU Sensor Counter Overflow Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overflow</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overflow</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUDTSR</name>
|
|
<description>CTSU Data Transfer Status Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Measurement result has been read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Measurement result has not been read</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSTC</name>
|
|
<description>CTSU Measurement Status Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Status 0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Status 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Status 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Status 3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Status 4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Status 5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSSC</name>
|
|
<description>CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register </description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSSDIV</name>
|
|
<description>CTSU Spectrum Diffusion Frequency Division Setting</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>4.00 <= fb</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>2.00 <= fb < 4.00</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>1.33 <= fb < 2.00</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>1.00 <= fb < 1.33</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>0.80 <= fb < 1.00</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>0.67 <= fb < 0.80</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>0.57 <= fb < 0.67</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>0.50 <= fb < 0.57</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>0.44 <= fb < 0.50</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>0.40 <= fb < 0.44</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>0.36 <= fb < 0.40</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>0.33 <= fb < 0.36</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>0.31 <= fb < 0.33</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>0.29 <= fb < 0.31</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>0.27 <= fb < 0.29</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>fb < 0.27 </description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSO0</name>
|
|
<description>CTSU Sensor Offset Register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSNUM</name>
|
|
<description>CTSU Measurement Count Setting</description>
|
|
<lsb>10</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSO</name>
|
|
<description>CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 )</description>
|
|
<lsb>0</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSO1</name>
|
|
<description>CTSU Sensor Offset Register 1</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUICOG</name>
|
|
<description>CTSU ICO Gain Adjustment</description>
|
|
<lsb>13</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>100% gain</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>66% gain</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>50% gain</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>40% gain</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSUSDPA</name>
|
|
<description>CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSURICOA</name>
|
|
<description>CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 )</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUSC</name>
|
|
<description>CTSU Sensor Counter</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUSC</name>
|
|
<description>CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSURC</name>
|
|
<description>CTSU Reference Counter</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSURC</name>
|
|
<description>CTSU Reference Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTSUERRS</name>
|
|
<description>CTSU Error Status Register </description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTSUICOMP</name>
|
|
<description>TSCAP Voltage Error Monitor</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal TSCAP voltage</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Abnormal TSCAP voltage</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MMPU</name>
|
|
<description>Bus Master MPU</description>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>3072</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x200</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x600</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA00</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x204</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x604</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA04</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x208</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x608</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA08</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x102</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x502</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x902</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x400</dimIncrement>
|
|
<dimIndex>A,B,C</dimIndex>
|
|
<name>MMPUCTL%s</name>
|
|
<description>Bus Master MPU Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the OAD and ENABLE bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Operation after detection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Master Group enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master Group is disabled. Permission of all regions.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master Group is enabled. Protection of all regions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MMPUACA%s</name>
|
|
<description>Group A Region %s Access Control Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Read protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Group m Region n unit is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Group m Region n unit is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUACB%s</name>
|
|
<description>Group B Region %s Access Control Register</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Read protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Group m Region n unit is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Group m Region n unit is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUACC%s</name>
|
|
<description>Group C Region %s Access Control Register</description>
|
|
<addressOffset>0xA00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Write protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Read protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read permission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read protection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Group m Region n unit is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Group m Region n unit is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MMPUSA%s</name>
|
|
<description>Group A Region %s Start Address Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUSA</name>
|
|
<description>Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUSB%s</name>
|
|
<description>Group B Region %s Start Address Register</description>
|
|
<addressOffset>0x604</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUSB</name>
|
|
<description>Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUSC%s</name>
|
|
<description>Group C Region %s Start Address Register</description>
|
|
<addressOffset>0xA04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUSC</name>
|
|
<description>Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MMPUEA%s</name>
|
|
<description>Group A Region %s End Address Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUEA</name>
|
|
<description>Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUEB%s</name>
|
|
<description>Group B Region %s End Address Register</description>
|
|
<addressOffset>0x608</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUEB</name>
|
|
<description>Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x010</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MMPUEC%s</name>
|
|
<description>Group C Region %s End Address Register</description>
|
|
<addressOffset>0xA08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MMPUEC</name>
|
|
<description>Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMPUPTA</name>
|
|
<description>Group A Protection of Register</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register(MMPUSAn, MMPUEAn and MMPUACAn)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All Bus Master MPU Group A register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All Bus Master MPU Group A register writing is protected. Read is possible.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMPUPTB</name>
|
|
<description>Group B Protection of Register</description>
|
|
<addressOffset>0x502</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register(MMPUSBn, MMPUEBn and MMPUACBn)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All Bus Master MPU Group B register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All Bus Master MPU Group B register writing is protected. Read is possible.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMPUPTC</name>
|
|
<description>Group C protection of register</description>
|
|
<addressOffset>0x902</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register (MMPUSCn, MMPUECn and MMPUACCn)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All Bus Master MPU Group C register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All Bus Master MPU Group C register writing is protected. Read is possible.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SMPU</name>
|
|
<description>Bus Slave MPU</description>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>26</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SMPUCTL</name>
|
|
<description>Slave MPU Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT and OAD bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All Bus Slave register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All Bus Slave register writing is protected. Read is possible.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Master Group enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPUMBIU</name>
|
|
<description>Access Control Register for MBIU</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WPSRAMHS</name>
|
|
<description>SRAMHS Write Protection</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for SRAMHS writes from master group A, B, and C disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for SRAMHS writes from master group A, B, and C enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPSRAMHS</name>
|
|
<description>SRAMHS Read Protection</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for SRAMHS reads from master group A, B, and C disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for SRAMHS reads from master group A, B, and C enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPFLI</name>
|
|
<description>Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.)</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for code flash memory writes from master group A, B, and C enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPFLI</name>
|
|
<description>Code Flash Memory Read Protection</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for code flash memory reads from master group A, B, and C disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for code flash memory reads from master group A, B, and C enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPGRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group C writes disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group C writes enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPGRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group C reads disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group C reads enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPGRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group B writes disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group B writes enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPGRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group B reads disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group B reads enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPGRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group A writes disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group A writes enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPGRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory protection for master group A reads disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory protection for master group A reads enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPUFBIU</name>
|
|
<description>Access Control Register for FBIU</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00C0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP_GRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C write of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C read of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_CPU</name>
|
|
<description>CPU Write protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_CPU</name>
|
|
<description>CPU Read protection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>SMPUSRAM%s</name>
|
|
<description>Access Control Register for SRAM%s</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP_GRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_CPU</name>
|
|
<description>CPU Write protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_CPU</name>
|
|
<description>CPU Read protection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,2,6,7</dimIndex>
|
|
<name>SMPUP%sBIU</name>
|
|
<description>Access Control Register for P%sBIU</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00F0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP_GRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C write of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C read of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B write of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B read of memory protection is enabled. The write value should always be 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_CPU</name>
|
|
<description>CPU Write protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_CPU</name>
|
|
<description>CPU Read protection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPUEXBIU</name>
|
|
<description>Access Control Register for EXBIU</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP_GRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_CPU</name>
|
|
<description>CPU Write protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_CPU</name>
|
|
<description>CPU Read protection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPUEXBIU2</name>
|
|
<description>Access Control Register for EXBIU2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WP_GRPC</name>
|
|
<description>Master Group C Write protection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPC</name>
|
|
<description>Master Group C Read protection</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group C read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group C read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPB</name>
|
|
<description>Master Group B Write protection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPB</name>
|
|
<description>Master Group B Read protection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group B read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group B read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_GRPA</name>
|
|
<description>Master Group A Write protection</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_GRPA</name>
|
|
<description>Master Group A Read protection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master group A read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master group A read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP_CPU</name>
|
|
<description>CPU Write protection</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU write of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU write of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RP_CPU</name>
|
|
<description>CPU Read protection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CPU read of memory protection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CPU read of memory protection is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPMON</name>
|
|
<description>CPU Stack Pointer Monitor</description>
|
|
<baseAddress>0x40000D00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MSPMPUOAD</name>
|
|
<description>Stack Pointer Monitor Operation After Detection Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the OAD bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the OAD bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Operation after detection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSPMPUCTL</name>
|
|
<description>Stack Pointer Monitor Access Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>SP_main monitor error flag</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SP_main has not overflowed or underflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SP_main has overflowed or underflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SP_main monitor enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SP_main monitor is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SP_main monitor is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSPMPUPT</name>
|
|
<description>Stack Pointer Monitor Protection Register</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stack Pointer Monitor register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stack Pointer Monitor register writing is protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSPMPUSA</name>
|
|
<description>Main Stack Pointer Monitor Start Address Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSPMPUSA</name>
|
|
<description>Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0.</description>
|
|
<lsb>2</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x1FF00000</minimum>
|
|
<maximum>0x200FFFFC</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSPMPUEA</name>
|
|
<description>Main Stack Pointer Monitor End Address Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSPMPUEA</name>
|
|
<description>Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1.</description>
|
|
<lsb>2</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x1FF00003</minimum>
|
|
<maximum>0x200FFFFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSPMPUOAD</name>
|
|
<description>Stack Pointer Monitor Operation After Detection Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the OAD bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the OAD bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Operation after detection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSPMPUCTL</name>
|
|
<description>Stack Pointer Monitor Access Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFEFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>SP_process monitor error flag</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SP_process has not overflowed or underflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SP_process has overflowed or underflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SP_process monitor enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SP_process monitor is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SP_process monitor is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSPMPUPT</name>
|
|
<description>Stack Pointer Monitor Protection Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write Keyword The data written to these bits are not stored.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.</description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the PROTECT bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>Protection of register (PSPMPUAC, PSPMPUSA and PSPMPUSE)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stack Pointer Monitor register writing is possible.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stack Pointer Monitor register writing is protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSPMPUSA</name>
|
|
<description>Process Stack Pointer Monitor Start Address Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSPMPUSA</name>
|
|
<description>Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0.</description>
|
|
<lsb>2</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x1FF00000</minimum>
|
|
<maximum>0x200FFFFC</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSPMPUEA</name>
|
|
<description>Process Stack Pointer Monitor End Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSPMPUEA</name>
|
|
<description>Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1.</description>
|
|
<lsb>2</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x1FF00003</minimum>
|
|
<maximum>0x200FFFFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC120</name>
|
|
<description>12bit A/D Converter 0</description>
|
|
<baseAddress>0x4005C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x62</offset>
|
|
<size>22</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x7A</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>9</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x90</offset>
|
|
<size>21</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA6</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA8</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB0</offset>
|
|
<size>33</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD2</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xDD</offset>
|
|
<size>11</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xEA</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1B0</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1B4</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ADCSR</name>
|
|
<description>A/D Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADST</name>
|
|
<description>A/D Conversion Start</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stops A/D conversion process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Starts A/D conversion process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCS</name>
|
|
<description>Scan Mode Select</description>
|
|
<lsb>13</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Single scan mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Group scan mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Continuous scan mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGE</name>
|
|
<description>Trigger Start Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables A/D conversion to be started by the synchronous or asynchronous trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables A/D conversion to be started by the synchronous or asynchronous trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTRG</name>
|
|
<description>Trigger Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A/D conversion is started by the synchronous trigger (ELCTRG0).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A/D conversion is started by the asynchronous trigger (ADTRG0#).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLE</name>
|
|
<description>Double Trigger Mode Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Double trigger mode non-selection</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double trigger mode selection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GBADIE</name>
|
|
<description>Group B Scan End Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables S12GBADI0 interrupt generation upon group B scan completion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables S12GBADI0 interrupt generation upon group B scan completion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLANS</name>
|
|
<description>Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSA0</name>
|
|
<description>A/D Channel Select Register A0</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSA07</name>
|
|
<description>AN007 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN007 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN007 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA06</name>
|
|
<description>AN006 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN006 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN006 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA05</name>
|
|
<description>AN005 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN005 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN005 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA04</name>
|
|
<description>AN004 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN004 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN004 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA03</name>
|
|
<description>AN003 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN003 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN003 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA02</name>
|
|
<description>AN002 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN002 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN002 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA01</name>
|
|
<description>AN001 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN001 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN001 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA00</name>
|
|
<description>AN000 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN000 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN000 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSA1</name>
|
|
<description>A/D Channel Select Register A1</description>
|
|
<addressOffset>0x006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSA20</name>
|
|
<description>AN020 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN020 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN020 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA19</name>
|
|
<description>AN019 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN019 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN019 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA18</name>
|
|
<description>AN018 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN018 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN018 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA17</name>
|
|
<description>AN017 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN017 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN017 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA16</name>
|
|
<description>AN016 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN016 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN016 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADS0</name>
|
|
<description>A/D-Converted Value Addition/Average Channel Select Register 0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS07</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN007 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN007 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN007 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS06</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN006 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN006 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN006 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS05</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN005 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN005 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN005 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS04</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN004 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN004 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN004 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS03</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN003 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN003 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN003 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS02</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN002 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN002 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN002 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS01</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN001 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN001 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN001 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS00</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN000 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN000 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN000 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADS1</name>
|
|
<description>A/D-Converted Value Addition/Average Channel Select Register 1</description>
|
|
<addressOffset>0x00A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS20</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN020 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN020 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN020 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS19</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN019 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN019 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN019 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS18</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN018 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN018 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN018 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS17</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN017 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN017 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN017 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS16</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN016 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN016 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN016 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADC</name>
|
|
<description>A/D-Converted Value Addition/Average Count Select Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVEE</name>
|
|
<description>Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b)</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1-time conversion (no addition; same as normal conversion)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2-time conversion (addition once)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3-time conversion (addition twice)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4-time conversion (addition three times)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCER</name>
|
|
<description>A/D Control Extended Register</description>
|
|
<addressOffset>0x00E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRFMT</name>
|
|
<description>A/D Data Register Format Select</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flush-right is selected for the A/D data register format.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flush-left is selected for the A/D data register format.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGM</name>
|
|
<description>Self-Diagnosis Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables self-diagnosis of ADC12.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables self-diagnosis of ADC12.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGLD</name>
|
|
<description>Self-Diagnosis Mode Select</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rotation mode for self-diagnosis voltage</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fixed mode for self-diagnosis voltage</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGVAL</name>
|
|
<description>Self-Diagnosis Conversion Voltage Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>When the self-diagnosis fixation mode is selected, it set prohibits it. </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The self-diagnosis by using the voltage of 0V.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The self-diagnosis by using the voltage of reference supply x 1/2. </description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The self-diagnosis by using the voltage of the reference supply. </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACE</name>
|
|
<description>A/D Data Register Automatic Clearing Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables automatic clearing.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic clearing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADPRC</name>
|
|
<description>A/D Conversion Accuracy Specify</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>A/D conversion is performed with 12-bit accuracy.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>A/D conversion is performed with 10-bit accuracy.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>A/D conversion is performed with 8-bit accuracy.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSTRGR</name>
|
|
<description>A/D Conversion Start Trigger Select Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRSA</name>
|
|
<description>A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected.</description>
|
|
<lsb>8</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRSB</name>
|
|
<description>A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADEXICR</name>
|
|
<description>A/D Conversion Extended Input Control Register</description>
|
|
<addressOffset>0x012</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OCSB</name>
|
|
<description>Internal Reference Voltage A/D Conversion Select for Group B</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference voltage is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference voltage is selected for group B in group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSB</name>
|
|
<description>Temperature Sensor Output A/D Conversion Select for Group B</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The temperature sensor output is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The temperature sensor output is not selected for group B in group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCSA</name>
|
|
<description>Internal Reference Voltage A/D Conversion Select</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference voltage is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSA</name>
|
|
<description>Temperature Sensor Output A/D Conversion Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The temperature sensor output is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The temperature sensor output is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCSAD</name>
|
|
<description>Internal Reference Voltage A/D converted Value Addition/Average Mode Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal reference voltage A/D-converted value addition/average mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference voltage A/D-converted value addition/average mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSAD</name>
|
|
<description>Temperature Sensor Output A/D converted Value Addition/Average Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Temperature sensor output A/D-converted value addition/average mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Temperature sensor output A/D-converted value addition/average mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSB0</name>
|
|
<description>A/D Channel Select Register B0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSB07</name>
|
|
<description>AN007 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN007 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN007 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB06</name>
|
|
<description>AN006 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN006 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN006 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB05</name>
|
|
<description>AN005 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN005 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN005 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB04</name>
|
|
<description>AN004 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN004 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN004 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB03</name>
|
|
<description>AN003 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN003 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN003 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB02</name>
|
|
<description>AN002 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN002 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN002 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB01</name>
|
|
<description>AN001 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN001 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN001 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB00</name>
|
|
<description>AN000 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN000 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN000 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSB1</name>
|
|
<description>A/D Channel Select Register B1</description>
|
|
<addressOffset>0x016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSB20</name>
|
|
<description>AN020 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN020 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN020 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB19</name>
|
|
<description>AN019 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN019 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN019 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB18</name>
|
|
<description>AN018 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN018 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN018 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB17</name>
|
|
<description>AN017 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN017 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN017 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB16</name>
|
|
<description>AN016 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN016 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN016 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDR</name>
|
|
<description>A/D Data Duplication Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDR</name>
|
|
<description>This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADTSDR</name>
|
|
<description>A/D Temperature Sensor Data Register</description>
|
|
<addressOffset>0x01A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADTSDR</name>
|
|
<description>This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOCDR</name>
|
|
<description>A/D Internal Reference Voltage Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADOCDR</name>
|
|
<description>This is a 16-bit read-only register for storing the A/D result of internal reference voltage.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADRD</name>
|
|
<description>A/D Self-Diagnosis Data Register</description>
|
|
<addressOffset>0x01E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIAGST</name>
|
|
<description>Self-Diagnosis Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Self-diagnosis has never been executed since power-on.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Self-diagnosis using the voltage of 0 V has been executed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Self-diagnosis using the voltage of reference power supply(VREFH) has been executed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed "0" </description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>ADDR%s</name>
|
|
<description>A/D Data Register %s</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>16-20</dimIndex>
|
|
<name>ADDR%s</name>
|
|
<description>A/D Data Register %s</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSHCR</name>
|
|
<description>A/D Sample and Hold Circuit Control Register</description>
|
|
<addressOffset>0x066</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0018</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHANS2</name>
|
|
<description>AN002 sample-and-hold circuit Select</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHANS1</name>
|
|
<description>AN001 sample-and-hold circuit Select</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHANS0</name>
|
|
<description>AN000 sample-and-hold circuit Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSTSH</name>
|
|
<description>Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x04</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDISCR</name>
|
|
<description>A/D Disconnection Detection Control Register</description>
|
|
<addressOffset>0x07A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHARGE</name>
|
|
<description>Selection of Precharge or Discharge</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Discharge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Precharge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADNDIS</name>
|
|
<description>The charging time</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disconnection detection is disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>( 1 / ADCLK ) x ADNDIS </description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSHMSR</name>
|
|
<description>A/D Sample and Hold Operation Mode Select Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHMD</name>
|
|
<description>Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling by channel-dedicated sample-and-hold circuit is disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling by channel-dedicated sample-and-hold circuit is enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADGSPCR</name>
|
|
<description>A/D Group Scan Priority Control Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GBRP</name>
|
|
<description>Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single scan for group B is not continuously activated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single scan for group B is continuously activated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GBRSCN</name>
|
|
<description>Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Scanning for group B is not restarted after having been discontinued due to group A priority control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Scanning for group B is restarted after having been discontinued due to group A priority control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGS</name>
|
|
<description>Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operation is without group A priority control</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operation is with group A priority control</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDRA</name>
|
|
<description>A/D Data Duplication Register A</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDRA</name>
|
|
<description>This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDRB</name>
|
|
<description>A/D Data Duplication Register B</description>
|
|
<addressOffset>0x086</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDRB</name>
|
|
<description>This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINMON</name>
|
|
<description>A/D Compare Function Window A/B Status Monitor Register</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONCMPB</name>
|
|
<description>Comparison Result Monitor B</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window B comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window B comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONCMPA</name>
|
|
<description>Comparison Result Monitor A</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window A comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window A comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONCOMB</name>
|
|
<description>Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window A / window B composite conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window A / window B composite conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPCR</name>
|
|
<description>A/D Compare Function Control Register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPAIE</name>
|
|
<description>Compare A Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCMPE</name>
|
|
<description>Window Function Setting</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBIE</name>
|
|
<description>Compare B Interrupt Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPAE</name>
|
|
<description>Compare Window A Operation Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare window A operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBE</name>
|
|
<description>Compare Window B Operation Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare window B operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPAB</name>
|
|
<description>Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1).</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSER</name>
|
|
<description>A/D Compare Function Window A Extended Input Select Register</description>
|
|
<addressOffset>0x092</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPOCA</name>
|
|
<description>Internal reference voltage Compare selection bit.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes the internal reference voltage from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes the internal reference voltage in the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPTSA</name>
|
|
<description>Temperature sensor output Compare selection bit.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes the temperature sensor output from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes the temperature sensor output in the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLER</name>
|
|
<description>A/D Compare Function Window A Extended Input Comparison Condition Setting Register</description>
|
|
<addressOffset>0x093</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLOCA</name>
|
|
<description>Compare Window A Internal Reference Voltage ComparisonCondition Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLTSA</name>
|
|
<description>Compare Window A Temperature Sensor Output Comparison Condition Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSR0</name>
|
|
<description>A/D Compare Function Window A Channel Select Register 0</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPCHA07</name>
|
|
<description>Compare Window A Channel AN007 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN007</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN007</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA06</name>
|
|
<description>Compare Window A Channel AN006 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN006</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN006</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA05</name>
|
|
<description>Compare Window A Channel AN005 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN005</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN005</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA04</name>
|
|
<description>Compare Window A Channel AN004 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN004</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN004</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA03</name>
|
|
<description>Compare Window A Channel AN003 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN003</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN003</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA02</name>
|
|
<description>Compare Window A Channel AN002 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN002</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN002</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA01</name>
|
|
<description>Compare Window A Channel AN001 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN001</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN001</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA00</name>
|
|
<description>Compare Window A Channel AN000 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN000</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN000</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSR1</name>
|
|
<description>A/D Compare Function Window A Channel Select Register 1</description>
|
|
<addressOffset>0x096</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPCHA20</name>
|
|
<description>AN020 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN020 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN020 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA19</name>
|
|
<description>AN019 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN019 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN019 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA18</name>
|
|
<description>AN018 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN018 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN018 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA17</name>
|
|
<description>AN017 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN017 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN017 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA16</name>
|
|
<description>AN016 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN016 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN016 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLR0</name>
|
|
<description>A/D Compare Function Window A Comparison Condition Setting Register 0</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLCHA07</name>
|
|
<description>Comparison condition of AN007</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA06</name>
|
|
<description>Comparison condition of AN006</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA05</name>
|
|
<description>Comparison condition of AN005</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA04</name>
|
|
<description>Comparison condition of AN004</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA03</name>
|
|
<description>Comparison condition of AN003</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA02</name>
|
|
<description>Comparison condition of AN002</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA01</name>
|
|
<description>Comparison condition of AN001</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA00</name>
|
|
<description>Comparison condition of AN000</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLR1</name>
|
|
<description>A/D Compare Function Window A Comparison Condition Setting Register 1</description>
|
|
<addressOffset>0x09A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLCHA20</name>
|
|
<description>Comparison condition of AN020</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA19</name>
|
|
<description>Comparison condition of AN019</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA18</name>
|
|
<description>Comparison condition of AN018</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA17</name>
|
|
<description>Comparison condition of AN017</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA16</name>
|
|
<description>Comparison condition of AN016</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPDR0</name>
|
|
<description>A/D Compare Function Window A Lower-Side Level Setting Register</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCMPDR0</name>
|
|
<description>The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPDR1</name>
|
|
<description>A/D Compare Function Window A Upper-Side Level Setting Register</description>
|
|
<addressOffset>0x09E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCMPDR1</name>
|
|
<description>The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A..</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSR0</name>
|
|
<description>A/D Compare Function Window A Channel Status Register 0</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTCHA07</name>
|
|
<description>Compare window A flag of AN007</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA06</name>
|
|
<description>Compare window A flag of AN006</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA05</name>
|
|
<description>Compare window A flag of AN005</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA04</name>
|
|
<description>Compare window A flag of AN004</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA03</name>
|
|
<description>Compare window A flag of AN003</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA02</name>
|
|
<description>Compare window A flag of AN002</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA01</name>
|
|
<description>Compare window A flag of AN001</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA00</name>
|
|
<description>Compare window A flag of AN000</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSR1</name>
|
|
<description>A/D Compare Function Window A Channel Status Register 1</description>
|
|
<addressOffset>0x0A2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTCHA20</name>
|
|
<description>Compare window A flag of AN020</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA19</name>
|
|
<description>Compare window A flag of AN019</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA18</name>
|
|
<description>Compare window A flag of AN018</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA17</name>
|
|
<description>Compare window A flag of AN017</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA16</name>
|
|
<description>Compare window A flag of AN016</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSER</name>
|
|
<description>A/D Compare Function Window A Extended Input Channel Status Register</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTOCA</name>
|
|
<description>Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTTSA</name>
|
|
<description>Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPBNSR</name>
|
|
<description>A/D Compare Function Window B Channel Selection Register</description>
|
|
<addressOffset>0x0A6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLB</name>
|
|
<description>Compare window B Compare condition setting bit.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHB</name>
|
|
<description>Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x00</name>
|
|
<description>AN000</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x01</name>
|
|
<description>AN001</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x02</name>
|
|
<description>AN002</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x03</name>
|
|
<description>AN003</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x04</name>
|
|
<description>AN004</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x05</name>
|
|
<description>AN005</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x06</name>
|
|
<description>AN006</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x07</name>
|
|
<description>AN007</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x10</name>
|
|
<description>AN016</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x11</name>
|
|
<description>AN017</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x12</name>
|
|
<description>AN018</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x13</name>
|
|
<description>AN019</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x14</name>
|
|
<description>AN020</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x20</name>
|
|
<description>Temperature sensor</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x21</name>
|
|
<description>Internal reference voltage</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3F</name>
|
|
<description>No channel is selected</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINLLB</name>
|
|
<description>A/D Compare Function Window B Lower-Side Level Setting Register</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADWINLLB</name>
|
|
<description>This register is used to compare A window function is used to set the lower level of the window B.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINULB</name>
|
|
<description>A/D Compare Function Window B Upper-Side Level Setting Register</description>
|
|
<addressOffset>0x0AA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADWINULB</name>
|
|
<description>This register is used to compare A window function is used to set the higher level of the window B.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPBSR</name>
|
|
<description>A/D Compare Function Window B Status Register</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTB</name>
|
|
<description>Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN007,AN016-AN020, temperature sensor, and internal reference voltage) made the object of window B relation condition.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRL</name>
|
|
<description>A/D Sampling State Register L</description>
|
|
<addressOffset>0x0DD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (AN016-AN020)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRT</name>
|
|
<description>A/D Sampling State Register T</description>
|
|
<addressOffset>0x0DE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (temperature sensor output)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRO</name>
|
|
<description>A/D Sampling State Register O</description>
|
|
<addressOffset>0x0DF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (Internal reference voltage)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>ADSSTR0%s</name>
|
|
<description>A/D Sampling State Register %s (Corresponding Channel is AN00%s )</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling time setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGACR</name>
|
|
<description>A/D Programmable Gain Amplifier Control Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x9999</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P002GEN</name>
|
|
<description>PGA P002 gain setting and enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P002</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P002</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002SEL0</name>
|
|
<description>A through amplifier is enable for PGA P002</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001GEN</name>
|
|
<description>PGA P001 gain setting and enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P001</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P001</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001SEL0</name>
|
|
<description>A through amplifier is enable for PGA P001</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000GEN</name>
|
|
<description>PGA P000 gain setting and enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P000</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P000</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000SEL0</name>
|
|
<description>A through amplifier is enable for PGA P000</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGAGS0</name>
|
|
<description>A/D Programmable Gain Amplifier Gain Setting Register 0</description>
|
|
<addressOffset>0x1A2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P002GAIN</name>
|
|
<description>PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0.</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001GAIN</name>
|
|
<description>PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0.</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000GAIN</name>
|
|
<description>PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGADCR0</name>
|
|
<description>A/D Programmable Gain Amplifier Differential Input Control Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P003DG</name>
|
|
<description>P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b.</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002DEN</name>
|
|
<description>P002 Differential Input Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002DG</name>
|
|
<description>P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b.</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001DEN</name>
|
|
<description>P001 Differential Input Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001DG</name>
|
|
<description>P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b.</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000DEN</name>
|
|
<description>P000 Differential Input Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000DG</name>
|
|
<description>P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b.</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC121</name>
|
|
<description>12bit A/D Converter 1</description>
|
|
<baseAddress>0x4005C200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>26</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x62</offset>
|
|
<size>22</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x7A</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>9</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x90</offset>
|
|
<size>21</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA6</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA8</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB0</offset>
|
|
<size>33</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD2</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xDD</offset>
|
|
<size>7</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xE5</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xEA</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1B0</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1B4</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ADCSR</name>
|
|
<description>A/D Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADST</name>
|
|
<description>A/D Conversion Start</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stops A/D conversion process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Starts A/D conversion process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCS</name>
|
|
<description>Scan Mode Select</description>
|
|
<lsb>13</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Single scan mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Group scan mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Continuous scan mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGE</name>
|
|
<description>Trigger Start Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables A/D conversion to be started by the synchronous or asynchronous trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables A/D conversion to be started by the synchronous or asynchronous trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTRG</name>
|
|
<description>Trigger Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A/D conversion is started by the synchronous trigger (ELCTRG1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A/D conversion is started by the asynchronous trigger (ADTRG1#).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLE</name>
|
|
<description>Double Trigger Mode Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Double trigger mode non-selection</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double trigger mode selection</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GBADIE</name>
|
|
<description>Group B Scan End Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables S12GBADI1 interrupt generation upon group B scan completion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables S12GBADI1 interrupt generation upon group B scan completion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLANS</name>
|
|
<description>Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSA0</name>
|
|
<description>A/D Channel Select Register A0</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSA07</name>
|
|
<description>AN107 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN107 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN107 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA06</name>
|
|
<description>AN106 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN106 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN106 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA05</name>
|
|
<description>AN105 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN105 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN105 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA03</name>
|
|
<description>AN103 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN103 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN103 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA02</name>
|
|
<description>AN102 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN102 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN102 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA01</name>
|
|
<description>AN101 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN101 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN101 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA00</name>
|
|
<description>AN100 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN100 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN100 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSA1</name>
|
|
<description>A/D Channel Select Register A1</description>
|
|
<addressOffset>0x006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSA19</name>
|
|
<description>AN119 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN119 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN119 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA18</name>
|
|
<description>AN118 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN118 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN118 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA17</name>
|
|
<description>AN117 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN117 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN117 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSA16</name>
|
|
<description>AN116 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN116 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN116 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADS0</name>
|
|
<description>A/D-Converted Value Addition/Average Channel Select Register 0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS07</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN107 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN107 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN107 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS06</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN106 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN106 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN106 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS05</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN105 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN105 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN105 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS03</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN103 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN103 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN103 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS02</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN102 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN102 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN102 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS01</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN101 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN101 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN101 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS00</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN100 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN100 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN100 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADS1</name>
|
|
<description>A/D-Converted Value Addition/Average Channel Select Register 1</description>
|
|
<addressOffset>0x00A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS19</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN119 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN119 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN119 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS18</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN118 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN118 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN118 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS17</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN117 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN117 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN117 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADS16</name>
|
|
<description>A/D-Converted Value Addition/Average Channel AN116 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN116 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN116 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADADC</name>
|
|
<description>A/D-Converted Value Addition/Average Count Select Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVEE</name>
|
|
<description>Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b)</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1-time conversion (no addition; same as normal conversion)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2-time conversion (addition once)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3-time conversion (addition twice)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4-time conversion (addition three times)</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCER</name>
|
|
<description>A/D Control Extended Register</description>
|
|
<addressOffset>0x00E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRFMT</name>
|
|
<description>A/D Data Register Format Select</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flush-right is selected for the A/D data register format.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flush-left is selected for the A/D data register format.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGM</name>
|
|
<description>Self-Diagnosis Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables self-diagnosis of ADC12.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables self-diagnosis of ADC12.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGLD</name>
|
|
<description>Self-Diagnosis Mode Select</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Rotation mode for self-diagnosis voltage</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fixed mode for self-diagnosis voltage</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIAGVAL</name>
|
|
<description>Self-Diagnosis Conversion Voltage Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>When the self-diagnosis fixation mode is selected, it set prohibits it. </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The self-diagnosis by using the voltage of 0V.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The self-diagnosis by using the voltage of reference supply x 1/2. </description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The self-diagnosis by using the voltage of the reference supply. </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACE</name>
|
|
<description>A/D Data Register Automatic Clearing Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables automatic clearing.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic clearing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADPRC</name>
|
|
<description>A/D Conversion Accuracy Specify</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>A/D conversion is performed with 12-bit accuracy.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>A/D conversion is performed with 10-bit accuracy.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>A/D conversion is performed with 8-bit accuracy.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSTRGR</name>
|
|
<description>A/D Conversion Start Trigger Select Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRSA</name>
|
|
<description>A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected.</description>
|
|
<lsb>8</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRSB</name>
|
|
<description>A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADEXICR</name>
|
|
<description>A/D Conversion Extended Input Control Register</description>
|
|
<addressOffset>0x012</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OCSB</name>
|
|
<description>Internal Reference Voltage A/D Conversion Select for Group B</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference voltage is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference voltage is selected for group B in group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSB</name>
|
|
<description>Temperature Sensor Output A/D Conversion Select for Group B</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The temperature sensor output is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The temperature sensor output is not selected for group B in group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCSA</name>
|
|
<description>Internal Reference Voltage A/D Conversion Select</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The internal reference voltage is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSA</name>
|
|
<description>Temperature Sensor Output A/D Conversion Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The temperature sensor output is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The temperature sensor output is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCSAD</name>
|
|
<description>Internal Reference Voltage A/D converted Value Addition/Average Mode Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal reference voltage A/D-converted value addition/average mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference voltage A/D-converted value addition/average mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSSAD</name>
|
|
<description>Temperature Sensor Output A/D converted Value Addition/Average Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Temperature sensor output A/D-converted value addition/average mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Temperature sensor output A/D-converted value addition/average mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSB0</name>
|
|
<description>A/D Channel Select Register B0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSB07</name>
|
|
<description>AN107 Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN107 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN107 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB06</name>
|
|
<description>AN106 Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN106 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN106 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB05</name>
|
|
<description>AN105 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN105 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN105 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB03</name>
|
|
<description>AN103 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN103 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN103 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB02</name>
|
|
<description>AN102 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN102 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN102 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB01</name>
|
|
<description>AN101 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN101 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN101 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB00</name>
|
|
<description>AN100 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN100 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN100 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADANSB1</name>
|
|
<description>A/D Channel Select Register B1</description>
|
|
<addressOffset>0x016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ANSB19</name>
|
|
<description>AN119 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN119 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN119 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB18</name>
|
|
<description>AN118 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN118 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN118 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB17</name>
|
|
<description>AN117 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN117 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN117 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ANSB16</name>
|
|
<description>AN116 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AN116 is not subjected to conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AN116 is subjected to conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDR</name>
|
|
<description>A/D Data Duplication Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDR</name>
|
|
<description>This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADTSDR</name>
|
|
<description>A/D Temperature Sensor Data Register</description>
|
|
<addressOffset>0x01A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADTSDR</name>
|
|
<description>This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOCDR</name>
|
|
<description>A/D Internal Reference Voltage Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADOCDR</name>
|
|
<description>This is a 16-bit read-only register for storing the A/D result of internal reference voltage.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADRD</name>
|
|
<description>A/D Self-Diagnosis Data Register</description>
|
|
<addressOffset>0x01E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIAGST</name>
|
|
<description>Self-Diagnosis Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Self-diagnosis has never been executed since power-on.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Self-diagnosis using the voltage of 0 V has been executed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Self-diagnosis using the voltage of reference power supply(VREFH) has been executed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed "0" </description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>ADDR%s</name>
|
|
<description>A/D Data Register %s</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>5-7</dimIndex>
|
|
<name>ADDR%s</name>
|
|
<description>A/D Data Register %s</description>
|
|
<addressOffset>0x02A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>16-19</dimIndex>
|
|
<name>ADDR%s</name>
|
|
<description>A/D Data Register %s</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSHCR</name>
|
|
<description>A/D Sample and Hold Circuit Control Register</description>
|
|
<addressOffset>0x066</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0018</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHANS2</name>
|
|
<description>AN102 sample-and-hold circuit Select</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHANS1</name>
|
|
<description>AN101 sample-and-hold circuit Select</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHANS0</name>
|
|
<description>AN100 sample-and-hold circuit Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass the sample-and-hold circuit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use the sample-and-hold circuit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSTSH</name>
|
|
<description>Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x04</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDISCR</name>
|
|
<description>A/D Disconnection Detection Control Register</description>
|
|
<addressOffset>0x07A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHARGE</name>
|
|
<description>Selection of Precharge or Discharge</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Discharge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Precharge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADNDIS</name>
|
|
<description>The charging time</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disconnection detection is disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>( 1 / ADCLK ) x ADNDIS </description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSHMSR</name>
|
|
<description>A/D Sample and Hold Operation Mode Select Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHMD</name>
|
|
<description>Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling by channel-dedicated sample-and-hold circuit is disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling by channel-dedicated sample-and-hold circuit is enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADGSPCR</name>
|
|
<description>A/D Group Scan Priority Control Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GBRP</name>
|
|
<description>Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single scan for group B is not continuously activated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single scan for group B is continuously activated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GBRSCN</name>
|
|
<description>Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Scanning for group B is not restarted after having been discontinued due to group A priority control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Scanning for group B is restarted after having been discontinued due to group A priority control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGS</name>
|
|
<description>Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operation is without group A priority control</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operation is with group A priority control</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDRA</name>
|
|
<description>A/D Data Duplication Register A</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDRA</name>
|
|
<description>This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDBLDRB</name>
|
|
<description>A/D Data Duplication Register B</description>
|
|
<addressOffset>0x086</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDBLDRB</name>
|
|
<description>This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINMON</name>
|
|
<description>A/D Compare Function Window A/B Status Monitor Register</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONCMPB</name>
|
|
<description>Comparison Result Monitor B</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window B comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window B comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONCMPA</name>
|
|
<description>Comparison Result Monitor A</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window A comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window A comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONCOMB</name>
|
|
<description>Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window A / window B composite conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window A / window B composite conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPCR</name>
|
|
<description>A/D Compare Function Control Register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPAIE</name>
|
|
<description>Compare A Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCMPE</name>
|
|
<description>Window Function Setting</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBIE</name>
|
|
<description>Compare B Interrupt Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPAE</name>
|
|
<description>Compare Window A Operation Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare window A operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBE</name>
|
|
<description>Compare Window B Operation Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare window B operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPAB</name>
|
|
<description>Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1).</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSER</name>
|
|
<description>A/D Compare Function Window A Extended Input Select Register</description>
|
|
<addressOffset>0x092</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPOCA</name>
|
|
<description>Internal reference voltage Compare selection bit.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes the internal reference voltage from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes the internal reference voltage in the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPTSA</name>
|
|
<description>Temperature sensor output Compare selection bit.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes the temperature sensor output from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes the temperature sensor output in the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLER</name>
|
|
<description>A/D Compare Function Window A Extended Input Comparison Condition Setting Register</description>
|
|
<addressOffset>0x093</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLOCA</name>
|
|
<description>Compare Window A Internal Reference Voltage ComparisonCondition Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLTSA</name>
|
|
<description>Compare Window A Temperature Sensor Output Comparison Condition Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSR0</name>
|
|
<description>A/D Compare Function Window A Channel Select Register 0</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPCHA05</name>
|
|
<description>Compare Window A Channel AN105 Select</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN105</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN105</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA03</name>
|
|
<description>Compare Window A Channel AN103 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN103</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN103</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA02</name>
|
|
<description>Compare Window A Channel AN102 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN102</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN102</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA01</name>
|
|
<description>Compare Window A Channel AN101 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN101</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN101</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA00</name>
|
|
<description>Compare Window A Channel AN100 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare function for AN100</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare function for AN100</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPANSR1</name>
|
|
<description>A/D Compare Function Window A Channel Select Register 1</description>
|
|
<addressOffset>0x096</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPCHA20</name>
|
|
<description>AN120 Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN120 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN120 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA19</name>
|
|
<description>AN119 Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN119 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN119 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA18</name>
|
|
<description>AN118 Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN118 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN118 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA17</name>
|
|
<description>AN117 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN117 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN117 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHA16</name>
|
|
<description>AN116 Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Excludes AN116 from the compare window A target range.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Includes AN116 from the compare window A target range.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLR0</name>
|
|
<description>A/D Compare Function Window A Comparison Condition Setting Register 0</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLCHA07</name>
|
|
<description>Comparison condition of AN107</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA06</name>
|
|
<description>Comparison condition of AN106</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA05</name>
|
|
<description>Comparison condition of AN105</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA03</name>
|
|
<description>Comparison condition of AN103</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA02</name>
|
|
<description>Comparison condition of AN102</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA01</name>
|
|
<description>Comparison condition of AN101</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA00</name>
|
|
<description>Comparison condition of AN100</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPLR1</name>
|
|
<description>A/D Compare Function Window A Comparison Condition Setting Register 1</description>
|
|
<addressOffset>0x09A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLCHA19</name>
|
|
<description>Comparison condition of AN119</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA18</name>
|
|
<description>Comparison condition of AN118</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA17</name>
|
|
<description>Comparison condition of AN117</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPLCHA16</name>
|
|
<description>Comparison condition of AN116</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPDR0</name>
|
|
<description>A/D Compare Function Window A Lower-Side Level Setting Register</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCMPDR0</name>
|
|
<description>The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPDR1</name>
|
|
<description>A/D Compare Function Window A Upper-Side Level Setting Register</description>
|
|
<addressOffset>0x09E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCMPDR1</name>
|
|
<description>The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A..</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSR0</name>
|
|
<description>A/D Compare Function Window A Channel Status Register 0</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTCHA07</name>
|
|
<description>Compare window A flag of AN007</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA06</name>
|
|
<description>Compare window A flag of AN006</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA05</name>
|
|
<description>Compare window A flag of AN005</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA03</name>
|
|
<description>Compare window A flag of AN003</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA02</name>
|
|
<description>Compare window A flag of AN002</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA01</name>
|
|
<description>Compare window A flag of AN001</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA00</name>
|
|
<description>Compare window A flag of AN000</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSR1</name>
|
|
<description>A/D Compare Function Window A Channel Status Register 1</description>
|
|
<addressOffset>0x0A2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTCHA19</name>
|
|
<description>Compare window A flag of AN019</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA18</name>
|
|
<description>Compare window A flag of AN018</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA17</name>
|
|
<description>Compare window A flag of AN017</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTCHA16</name>
|
|
<description>Compare window A flag of AN016</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPSER</name>
|
|
<description>A/D Compare Function Window A Extended Input Channel Status Register</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTOCA</name>
|
|
<description>Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSTTSA</name>
|
|
<description>Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPBNSR</name>
|
|
<description>A/D Compare Function Window B Channel Selection Register</description>
|
|
<addressOffset>0x0A6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPLB</name>
|
|
<description>Compare window B Compare condition setting bit.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCHB</name>
|
|
<description>Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x00</name>
|
|
<description>AN100</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x01</name>
|
|
<description>AN101</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x02</name>
|
|
<description>AN102</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x03</name>
|
|
<description>AN103</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x05</name>
|
|
<description>AN105</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x06</name>
|
|
<description>AN106</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x07</name>
|
|
<description>AN107</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x10</name>
|
|
<description>AN116</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x11</name>
|
|
<description>AN117</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x12</name>
|
|
<description>AN118</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x13</name>
|
|
<description>AN119</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x20</name>
|
|
<description>Temperature sensor</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x21</name>
|
|
<description>Internal reference voltage</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3F</name>
|
|
<description>No channel is selected</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINLLB</name>
|
|
<description>A/D Compare Function Window B Lower-Side Level Setting Register</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADWINLLB</name>
|
|
<description>This register is used to compare A window function is used to set the lower level of the window B.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADWINULB</name>
|
|
<description>A/D Compare Function Window B Upper-Side Level Setting Register</description>
|
|
<addressOffset>0x0AA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADWINULB</name>
|
|
<description>This register is used to compare A window function is used to set the higher level of the window B.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCMPBSR</name>
|
|
<description>A/D Compare Function Window B Status Register</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSTB</name>
|
|
<description>Compare window B flag.It is a status flag that shows the comparative result of CH (AN100-AN103, AN105-AN107, AN116-AN119, temperature sensor, and internal reference voltage) made the object of window B relation condition.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparison conditions are not met.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparison conditions are met.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRL</name>
|
|
<description>A/D Sampling State Register L</description>
|
|
<addressOffset>0x0DD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (AN116-AN119)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRT</name>
|
|
<description>A/D Sampling State Register T</description>
|
|
<addressOffset>0x0DE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (temperature sensor output)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADSSTRO</name>
|
|
<description>A/D Sampling State Register O</description>
|
|
<addressOffset>0x0DF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling Time Setting (Internal reference voltage)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>ADSSTR0%s</name>
|
|
<description>A/D Sampling State Register %s (Corresponding Channel is AN10%s )</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling time setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>5-7</dimIndex>
|
|
<name>ADSSTR0%s</name>
|
|
<description>A/D Sampling State Register %s (Corresponding Channel is AN10%s )</description>
|
|
<addressOffset>0x0E5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0B</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Sampling time setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<writeConstraint>
|
|
<range>
|
|
<minimum>0x05</minimum>
|
|
<maximum>0xFF</maximum>
|
|
</range>
|
|
</writeConstraint>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGACR</name>
|
|
<description>A/D Programmable Gain Amplifier Control Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x9999</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P002GEN</name>
|
|
<description>PGA P002 gain setting and enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P002</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P002</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002SEL0</name>
|
|
<description>A through amplifier is enable for PGA P002</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001GEN</name>
|
|
<description>PGA P001 gain setting and enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P001</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P001</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001SEL0</name>
|
|
<description>A through amplifier is enable for PGA P001</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000GEN</name>
|
|
<description>PGA P000 gain setting and enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The gain setting is invalidated (AIN is not input in PGA). </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The gain setting is effectively done (AIN is input in PGA).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000ENAMP</name>
|
|
<description>Amplifier enable bit for PGA P000</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The amplifier in PGA is not used. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The amplifier in PGA is used. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000SEL1</name>
|
|
<description>The amplifier passing is enable for PGA P000</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>By way of the amplifier in PGA. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Note 1 that by way of amplifier in PGA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000SEL0</name>
|
|
<description>A through amplifier is enable for PGA P000</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not through the PGA in amplifier</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I will through in the PGA amplifier.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGAGS0</name>
|
|
<description>A/D Programmable Gain Amplifier Gain Setting Register 0</description>
|
|
<addressOffset>0x1A2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P002GAIN</name>
|
|
<description>PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0.</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001GAIN</name>
|
|
<description>PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0.</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000GAIN</name>
|
|
<description>PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>x 2.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>x 2.667 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>x 2.857 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>x 3.077 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>x 3.636 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>x 4.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>x 4.444 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>x 5.714 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>x 8.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>x 10.000 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>x 13.333 (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADPGADCR0</name>
|
|
<description>A/D Programmable Gain Amplifier Differential Input Control Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P003DG</name>
|
|
<description>P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b.</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002DEN</name>
|
|
<description>P002 Differential Input Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P002DG</name>
|
|
<description>P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b.</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001DEN</name>
|
|
<description>P001 Differential Input Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P001DG</name>
|
|
<description>P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b.</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000DEN</name>
|
|
<description>P000 Differential Input Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Differential input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Differential input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P000DG</name>
|
|
<description>P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b.</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>x 1.5 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 2.333</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 4.0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 5.667</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MSTP</name>
|
|
<description>Module Stop Control B,C,D</description>
|
|
<baseAddress>0x40047000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MSTPCRB</name>
|
|
<description>Module Stop Control Register B</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPB31</name>
|
|
<description>Serial Communication Interface 0 Module Stop</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB30</name>
|
|
<description>Serial Communication Interface 1 Module Stop</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB29</name>
|
|
<description>Serial Communication Interface 2 Module Stop</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB28</name>
|
|
<description>Serial Communication Interface 3 Module Stop</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB27</name>
|
|
<description>Serial Communication Interface 4 Module Stop</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB26</name>
|
|
<description>Serial Communication Interface 5 Module Stop</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB25</name>
|
|
<description>Serial Communication Interface 6 Module Stop</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB24</name>
|
|
<description>Serial Communication Interface 7 Module Stop</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB23</name>
|
|
<description>Serial Communication Interface 8 Module Stop</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB22</name>
|
|
<description>Serial Communication Interface 9 Module Stop</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB19</name>
|
|
<description>Serial Peripheral Interface 0 Module Stop</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB18</name>
|
|
<description>Serial Peripheral Interface Module Stop</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB15</name>
|
|
<description>ETHERC0 and EDMAC0 Module Stop</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB13</name>
|
|
<description>EPTPC and PTPEDMAC Module Stop</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB12</name>
|
|
<description>Universal Serial Bus 2.0 HS Interface Module Stop</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB11</name>
|
|
<description>Universal Serial Bus 2.0 FS Interface Module Stop</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB9</name>
|
|
<description>I2C Bus Interface 0 Module Stop</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB8</name>
|
|
<description>I2C Bus Interface 1 Module Stop</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB7</name>
|
|
<description>I2C Bus Interface 2 Module Stop</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB6</name>
|
|
<description>Queued Serial Peripheral Interface Module Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB5</name>
|
|
<description>IrDA Module Stop</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB2</name>
|
|
<description>RCAN0 Module Stop</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPB1</name>
|
|
<description>RCAN1 Module Stop</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTPCRC</name>
|
|
<description>Module Stop Control Register C</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPC31</name>
|
|
<description>TSIP Module Stop</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC14</name>
|
|
<description>Event Link Controller Module Stop</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC13</name>
|
|
<description>Data Operation Circuit Module Stop</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC12</name>
|
|
<description>Synchronous Digital Hierarchy/ Multi Media Card 0 Module Stop</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC11</name>
|
|
<description>Synchronous Digital Hierarchy/ Multi Media Card 1 Module Stop</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC9</name>
|
|
<description>Sampling Rate Converter Module Stop</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC8</name>
|
|
<description>Synchronous Serial Interface 0 Module Stop</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC7</name>
|
|
<description>Synchronous Serial Interface 1 Module Stop</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC6</name>
|
|
<description>2DG engine Module Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC5</name>
|
|
<description>JPEG codec engine Module Stop</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC4</name>
|
|
<description>Grafic LCD Controler Module Stop</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC3</name>
|
|
<description>Capacitive Touch Sensing Unit Module Stop</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC2</name>
|
|
<description>Parallel Data Capture Module Stop</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC1</name>
|
|
<description>CRC Calculator Module Stop</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPC0</name>
|
|
<description>CAC Module Stop</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTPCRD</name>
|
|
<description>Module Stop Control Register D</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPD28</name>
|
|
<description>Comparator-OC0 Module Stop</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD27</name>
|
|
<description>Comparator-OC1 Module Stop</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD26</name>
|
|
<description>Comparator-OC2 Module Stop</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD25</name>
|
|
<description>Comparator-OC3 Module Stop</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD24</name>
|
|
<description>Comparator-OC4 Module Stop</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD23</name>
|
|
<description>Comparator-OC5 Module Stop</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD22</name>
|
|
<description>Temperature Sensor Module Stop</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD20</name>
|
|
<description>D/A Converter 0 Module Stop</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD16</name>
|
|
<description>12-bit A/D Converter 0 Module Stop</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD15</name>
|
|
<description>12-bit A/D Converter 1 Module Stop</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD14</name>
|
|
<description>PGI Module Stop</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD6</name>
|
|
<description>GPT ch13-ch8 Module Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD5</name>
|
|
<description>GPT ch7-ch0 Module Stop</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD3</name>
|
|
<description>AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTPD2</name>
|
|
<description>AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Cancel the module-stop state</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enter the module-stop state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPT328</name>
|
|
<description>General PWM Timer 8 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>116</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x7C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x74</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x78</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x84</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>GTWP</name>
|
|
<description>General PWM Timer Write-Protection Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRKEY</name>
|
|
<description>GTWP Key Code</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xA5</name>
|
|
<description>Written to these bits, the WP bits write is permitted. </description>
|
|
<value>0xA5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>The WP bits write is not permitted. </description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP</name>
|
|
<description>Register Write Disable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable writes to the register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable writes to the register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSTR</name>
|
|
<description>General PWM Timer Software Start Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTRT13</name>
|
|
<description>Channel 13 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT12</name>
|
|
<description>Channel 12 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT11</name>
|
|
<description>Channel 11 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT10</name>
|
|
<description>Channel 10 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT9</name>
|
|
<description>Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT8</name>
|
|
<description>Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT7</name>
|
|
<description>Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT6</name>
|
|
<description>Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT5</name>
|
|
<description>Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT4</name>
|
|
<description>Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT3</name>
|
|
<description>Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT2</name>
|
|
<description>Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT1</name>
|
|
<description>Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTRT0</name>
|
|
<description>Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter stop (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter starts (write) / Counter running (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSTP</name>
|
|
<description>General PWM Timer Software Stop Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTOP13</name>
|
|
<description>Channel 13 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP12</name>
|
|
<description>Channel 12 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP11</name>
|
|
<description>Channel 11 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP10</name>
|
|
<description>Channel 10 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP9</name>
|
|
<description>Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP8</name>
|
|
<description>Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP7</name>
|
|
<description>Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP6</name>
|
|
<description>Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP5</name>
|
|
<description>Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP4</name>
|
|
<description>Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP3</name>
|
|
<description>Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP2</name>
|
|
<description>Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP1</name>
|
|
<description>Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTOP0</name>
|
|
<description>Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect (write) / counter running (read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter stops (write) / Counter stop (read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCLR</name>
|
|
<description>General PWM Timer Software Clear Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLR13</name>
|
|
<description>Channel 13 GTCNT Count Clear</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3213.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR12</name>
|
|
<description>Channel 12 GTCNT Count Clear</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3212.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR11</name>
|
|
<description>Channel 11 GTCNT Count Clear</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3211.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR10</name>
|
|
<description>Channel 10 GTCNT Count Clear</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT3210.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR9</name>
|
|
<description>Channel 9 GTCNT Count Clear</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT329.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR8</name>
|
|
<description>Channel 8 GTCNT Count Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT328.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR7</name>
|
|
<description>Channel 7 GTCNT Count Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E7.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR6</name>
|
|
<description>Channel 6 GTCNT Count Clear</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E6.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR5</name>
|
|
<description>Channel 5 GTCNT Count Clear</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E5.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR4</name>
|
|
<description>Channel 4 GTCNT Count Clear</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32E4.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR3</name>
|
|
<description>Channel 3 GTCNT Count Clear</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH3.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR2</name>
|
|
<description>Channel 2 GTCNT Count Clear</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH2.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR1</name>
|
|
<description>Channel 1 GTCNT Count Clear</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH1.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLR0</name>
|
|
<description>Channel 0 GTCNT Count Clear</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GPT32EH0.GTCNT counter clears</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTSSR</name>
|
|
<description>General PWM Timer Start Source Select Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTRT</name>
|
|
<description>Software Source Counter Start Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start by the GTSTR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start by the GTSTR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Start Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Start Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Start Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Start Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Start Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Start Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Start Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Start Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Start Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Start Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter start on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter start on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPSR</name>
|
|
<description>General PWM Timer Stop Source Select Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTOP</name>
|
|
<description>Software Source Counter Stop Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop by the GTSTP register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop by the GTSTP register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Stop Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELCH event inpu</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Stop Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTG input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Stop Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Stop Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Stop Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Stop Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Stop Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Stop Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on ELC_GPTA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Stop Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Stop Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter stop on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter stop on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCSR</name>
|
|
<description>General PWM Timer Clear Source Select Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLR</name>
|
|
<description>Software Source Counter Clear Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear by the GTCLR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear by the GTCLR register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Clear Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTH input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Clear Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTG input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Clear Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTF input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Clear Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Clear Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Clear Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Clear Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Clear Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on ELC_GPTA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Clear Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the falling edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Clear Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter clear on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter clear on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTUPSR</name>
|
|
<description>General PWM Timer Up Count Source Select Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Count Up Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Count Up Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Count Up Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Count Up Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTE input.put</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Count Up Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Count Up Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Count Up Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Count Up Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGD input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Count Up Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Count Up Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count up on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count up on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDNSR</name>
|
|
<description>General PWM Timer Down Count Source Select Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSELCH</name>
|
|
<description>ELC_GPTH Event Source Counter Count Down Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCG</name>
|
|
<description>ELC_GPTG Event Source Counter Count Down Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCF</name>
|
|
<description>ELC_GPTF Event Source Counter Count Down Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCE</name>
|
|
<description>ELC_GPTE Event Source Counter Count Down Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTE input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCD</name>
|
|
<description>ELC_GPTD Event Source Counter Count Down Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCC</name>
|
|
<description>ELC_GPTC Event Source Counter Count Down Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCB</name>
|
|
<description>ELC_GPTB Event Source Counter Count Down Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSELCA</name>
|
|
<description>ELC_GPTA Event Source Counter Count Down Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source Counter Count Down Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source Counter Count Down Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable counter count down on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable counter count down on the rising edge of GTETRGA input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTICASR</name>
|
|
<description>General PWM Timer Input Capture Source Select Register A</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASELCH</name>
|
|
<description>ELC_GPTH Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTH input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCG</name>
|
|
<description>ELC_GPTG Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCF</name>
|
|
<description>ELC_GPTF Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCE</name>
|
|
<description>ELC_GPTE Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTE input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCD</name>
|
|
<description>ELC_GPTD Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCC</name>
|
|
<description>ELC_GPTC Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCB</name>
|
|
<description>ELC_GPTB Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTB input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASELCA</name>
|
|
<description>ELC_GPTA Event Source GTCCRA Input Capture Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRA input capture on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRA input capture on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTICBSR</name>
|
|
<description>General PWM Timer Input Capture Source Select Register B</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSELCH</name>
|
|
<description>ELC_GPTH Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTH input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTH input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCG</name>
|
|
<description>ELC_GPTG Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTG input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTG input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCF</name>
|
|
<description>ELC_GPTF Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTF input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTF input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCE</name>
|
|
<description>ELC_GPTE Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTE input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTE input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCD</name>
|
|
<description>ELC_GPTD Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCC</name>
|
|
<description>ELC_GPTC Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTC input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCB</name>
|
|
<description>ELC_GPTB Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSELCA</name>
|
|
<description>ELC_GPTA Event Source GTCCRB Input Capture Enable</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on ELC_GPTA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on ELC_GPTA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBFAH</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBFAL</name>
|
|
<description>GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBRAH</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCBRAL</name>
|
|
<description>GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCAFBH</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCAFBL</name>
|
|
<description>GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCARBH</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSCARBL</name>
|
|
<description>GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGDF</name>
|
|
<description>GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGDR</name>
|
|
<description>GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGD input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGD input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGCF</name>
|
|
<description>GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGCR</name>
|
|
<description>GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGC input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGC input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGBF</name>
|
|
<description>GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGBR</name>
|
|
<description>GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGB input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGB input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGAF</name>
|
|
<description>GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the falling edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the falling edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSGTRGAR</name>
|
|
<description>GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable GTCCRB input capture on the rising edge of GTETRGA input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable GTCCRB input capture on the rising edge of GTETRGA input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCR</name>
|
|
<description>General PWM Timer Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPCS</name>
|
|
<description>Timer Prescaler Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCLK/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCLK/4</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>PCLK/16</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCLK/64</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PCLK/256</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PCLK/1024</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Mode Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Saw-wave PWM mode (single buffer or double buffer possible)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Saw-wave one-shot pulse mode (fixed buffer operation)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Triangle-wave PWM mode 1 (32-bit transfer at crest) (single buffer or double buffer possible)</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Triangle-wave PWM mode 3 (64-bit transfer at trough) fixed buffer operation)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CST</name>
|
|
<description>Count Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count operation is stopped</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count operation is performed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTUDDTYC</name>
|
|
<description>General PWM Timer Count Direction and Duty Setting Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OBDTYR</name>
|
|
<description>GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0percent/100percent duty setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Apply masked compare match output value to GTIOB[3:2] function after releasing 0percent/100percent duty setting.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDTYF</name>
|
|
<description>Forcible GTIOCB Output Duty Setting</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDTY</name>
|
|
<description>GTIOCB Output Duty Setting</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>GTIOCB pin duty is depend on compare match</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>GTIOCB pin duty is depend on compare match</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>GTIOCB pin duty 0percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>GTIOCB pin duty 100percent</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTYR</name>
|
|
<description>GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTYF</name>
|
|
<description>Forcible GTIOCA Output Duty Setting</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADTY</name>
|
|
<description>GTIOCA Output Duty Setting</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>GTIOCA pin duty is depend on compare match</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>GTIOCA pin duty is depend on compare match</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>GTIOCA pin duty 0 percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>GTIOCA pin duty 100 percent</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDF</name>
|
|
<description>Forcible Count Direction Setting</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not force setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Force setting</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UD</name>
|
|
<description>Count Direction Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count down on GTCNT</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counts up on GTCNT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTIOR</name>
|
|
<description>General PWM Timer I/O Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFCSB</name>
|
|
<description>Noise Filter B Sampling Clock Select</description>
|
|
<lsb>30</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK/1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFBEN</name>
|
|
<description>Noise Filter B Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable noise filter for GTIOCB pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable noise filter for GTIOCB pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDF</name>
|
|
<description>GTIOCB Pin Disable Value Setting</description>
|
|
<lsb>25</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prohibit output disable</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Set GTIOCB pin to Hi-Z on output disable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Set GTIOCB pin to 0 on output disable</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Set GTIOCB pin to 1 on output disable.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBE</name>
|
|
<description>GTIOCB Pin Output Enable</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBHLD</name>
|
|
<description>GTIOCB Pin Output Setting at the Start/Stop Count</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTIOCB pin output level on counting start and stop based on the register setting</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Retain GTIOCB pin output level on counting start and stop</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBDFLT</name>
|
|
<description>GTIOCB Pin Output Value Setting at the Count Stop</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on GTIOCB pin when counting stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on GTIOCB pin when counting stops</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTIOB</name>
|
|
<description>GTIOCB Pin Function Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>Initial output is Low. Low output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>Initial output is Low. High output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>Initial output is Low. High output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Initial output is High. Output retained at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>Initial output is High. Low output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Initial output is High. Low output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>Initial output is High. High output at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>Initial output is High. High output at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Initial output is High. High output at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFCSA</name>
|
|
<description>Noise Filter A Sampling Clock Select</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLK/1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLK/4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLK/16</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLK/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFAEN</name>
|
|
<description>Noise Filter A Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable noise filter for GTIOCA pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable noise filter for GTIOCA pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADF</name>
|
|
<description>GTIOCA Pin Disable Value Setting</description>
|
|
<lsb>9</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prohibit output disable</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Set GTIOCA pin to Hi-Z on output disable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Set GTIOCA pin to 0 on output disable</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Set GTIOCA pin to 1 on output disable.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAE</name>
|
|
<description>GTIOCA Pin Output Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OAHLD</name>
|
|
<description>GTIOCA Pin Output Setting at the Start/Stop Count</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTIOCA pin output level on counting start and stop based on the register setting.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Retain GTIOCA pin output level on counting start and stop</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OADFLT</name>
|
|
<description>GTIOCA Pin Output Value Setting at the Count Stop</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output low on GTIOCA pin when counting stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output high on GTIOCA pin when counting stops.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTIOA</name>
|
|
<description>GTIOCA Pin Function Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>Initial output is Low. Low output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>Initial output is Low. High output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>Initial output is Low. High output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>Initial output is High. Output retained at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>Initial output is High. Low output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Initial output is High. Low output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>Initial output is High. High output at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>Initial output is High. High output at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Initial output is High. High output at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTINTAD</name>
|
|
<description>General PWM Timer Interrupt Output Setting Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GRPABL</name>
|
|
<description>Same Time Output Level Low Disable Request Enable</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable same time output level low disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable same time output level low disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRPABH</name>
|
|
<description>Same Time Output Level High Disable Request Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable same time output level high disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable same time output level high disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GRP</name>
|
|
<description>Output Disable Source Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Select Group A output disable request</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select Group B output disable request</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select Group C output disable request</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select Group D output disable request.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTST</name>
|
|
<description>General PWM Timer Status Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OABLF</name>
|
|
<description>Same Time Output Level Low Disable Request Enable</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTIOCA pin and GTIOCB pin don't output 0 at the same time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTIOCA pin and GTIOCB pin output 0 at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OABHF</name>
|
|
<description>Same Time Output Level High Disable Request Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTIOCA pin and GTIOCB pin don't output 1 at the same time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTIOCA pin and GTIOCB pin output 1 at the same time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODF</name>
|
|
<description>Output Disable Flag</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No output disable request is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An output disable request is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUCF</name>
|
|
<description>Count Direction Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTCNT counter is counting down</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTCNT counter is counting up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFPU</name>
|
|
<description>Underflow Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underflow (trough) has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An underflow (trough) has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPFO</name>
|
|
<description>Overflow Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overflow (crest) has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overflow (crest) has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFF</name>
|
|
<description>Input Compare Match Flag F</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRF is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRF is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFE</name>
|
|
<description>Input Compare Match Flag E</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRE is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRE is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFD</name>
|
|
<description>Input Compare Match Flag D</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRD is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRD is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFC</name>
|
|
<description>Input Compare Match Flag C</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No compare match of GTCCRC is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A compare match of GTCCRC is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFB</name>
|
|
<description>Input Capture/Compare Match Flag B</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No input capture/compare match of GTCCRB is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An input capture/compare match of GTCCRB is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCFA</name>
|
|
<description>Input Capture/Compare Match Flag A</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No input capture/compare match of GTCCRA is generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An input capture/compare match of GTCCRA is generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTBER</name>
|
|
<description>General PWM Timer Buffer Enable Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCRSWT</name>
|
|
<description>GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0.</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>GTPR Buffer Operation</description>
|
|
<lsb>20</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTPBR --> GTPR)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCRB</name>
|
|
<description>GTCCRB Buffer Operation</description>
|
|
<lsb>18</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTCCRB <--> GTCCRE)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCRA</name>
|
|
<description>GTCCRA Buffer Operation</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Buffer operation is not performed</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Single buffer operation (GTCCRA <--> GTCCRC)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BD1</name>
|
|
<description>GTPR Buffer Operation Disable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable buffer operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable buffer operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BD2</name>
|
|
<description>GTCCR Buffer Operation Disable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable buffer operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable buffer operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCNT</name>
|
|
<description>General PWM Timer Counter</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCNT</name>
|
|
<description>Counter </description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRA</name>
|
|
<description>General PWM Timer Compare Capture Register A</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRA</name>
|
|
<description>Compare Capture Register A</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRB</name>
|
|
<description>General PWM Timer Compare Capture Register B</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRB</name>
|
|
<description>Compare Capture Register B</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRC</name>
|
|
<description>General PWM Timer Compare Capture Register C</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRC</name>
|
|
<description>Compare Capture Register C</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRE</name>
|
|
<description>General PWM Timer Compare Capture Register E</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRE</name>
|
|
<description>Compare Capture Register E</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRD</name>
|
|
<description>General PWM Timer Compare Capture Register D</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRD</name>
|
|
<description>Compare Capture Register D</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTCCRF</name>
|
|
<description>General PWM Timer Compare Capture Register F</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTCCRF</name>
|
|
<description>Compare Capture Register F</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPR</name>
|
|
<description>General PWM Timer Cycle Setting Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTPR</name>
|
|
<description>Cycle Setting Register</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPBR</name>
|
|
<description>General PWM Timer Cycle Setting Buffer Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTPBR</name>
|
|
<description>Cycle Setting Buffer Register</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDTCR</name>
|
|
<description>General PWM Timer Dead Time Control Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Negative-Phase Waveform Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set GTCCRB without using GTDVU and GTDVD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use GTDVU and GTDVD to set the compare match value for negative-phase waveform with automatic dead time in GTCCRB.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDVU</name>
|
|
<description>General PWM Timer Dead Time Value Register U</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GTDVU</name>
|
|
<description>Dead Time Value Register U</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT328">
|
|
<name>GPT329</name>
|
|
<description>General PWM Timer 9 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078900</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT328">
|
|
<name>GPT3210</name>
|
|
<description>General PWM Timer 10 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078A00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT328">
|
|
<name>GPT3211</name>
|
|
<description>General PWM Timer 11 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078B00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT328">
|
|
<name>GPT3212</name>
|
|
<description>General PWM Timer 12 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT328">
|
|
<name>GPT3213</name>
|
|
<description>General PWM Timer 13 (32-bit Enhanced)</description>
|
|
<baseAddress>0x40078D00</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Realtime Clock</description>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x06</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x06</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0A</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x12</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x12</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x16</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1E</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x22</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x52</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x52</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x56</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x56</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x5A</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x5A</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x5C</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>R64CNT</name>
|
|
<description>64-Hz Counter</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>F1HZ</name>
|
|
<description>1Hz</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F2HZ</name>
|
|
<description>2Hz</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F4HZ</name>
|
|
<description>4Hz</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F8HZ</name>
|
|
<description>8Hz</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F16HZ</name>
|
|
<description>16Hz</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F32HZ</name>
|
|
<description>32Hz</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F64HZ</name>
|
|
<description>64Hz</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSECCNT</name>
|
|
<description>Second Counter</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC10</name>
|
|
<description>10-Second Count Counts from 0 to 5 for 60-second counting.</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEC1</name>
|
|
<description>1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT0</name>
|
|
<description>Binary Counter 0</description>
|
|
<alternateRegister>RSECCNT</alternateRegister>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT0</name>
|
|
<description>The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMINCNT</name>
|
|
<description>Minute Counter</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MIN10</name>
|
|
<description>10-Minute Count Counts from 0 to 5 for 60-minute counting.</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MIN1</name>
|
|
<description>1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT1</name>
|
|
<description>Binary Counter 1</description>
|
|
<alternateRegister>RMINCNT</alternateRegister>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT1</name>
|
|
<description>The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHRCNT</name>
|
|
<description>Hour Counter</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Time Counter Setting for a.m./p.m.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>a.m.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>p.m.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HR10</name>
|
|
<description>10-Hour Count Counts from 0 to 2 once per carry from the ones place.</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HR1</name>
|
|
<description>1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT2</name>
|
|
<description>Binary Counter 2</description>
|
|
<alternateRegister>RHRCNT</alternateRegister>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT2</name>
|
|
<description>The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWKCNT</name>
|
|
<description>Day-of-Week Counter</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAYW</name>
|
|
<description>Day-of-Week Counting</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Sunday</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Monday</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Tuesday</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Wednesday</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Thursday</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Friday</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Saturday</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting Prohibited </description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT3</name>
|
|
<description>Binary Counter 3</description>
|
|
<alternateRegister>RWKCNT</alternateRegister>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT3</name>
|
|
<description>The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDAYCNT</name>
|
|
<description>Day Counter</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATE10</name>
|
|
<description>10-Day Count Counts from 0 to 3 once per carry from the ones place.</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATE1</name>
|
|
<description>1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMONCNT</name>
|
|
<description>Month Counter</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xE0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MON10</name>
|
|
<description>10-Month Count Counts from 0 to 1 once per carry from the ones place.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON1</name>
|
|
<description>1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RYRCNT</name>
|
|
<description>Year Counter</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YR10</name>
|
|
<description>10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place.</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>YR1</name>
|
|
<description>1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place.</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSECAR</name>
|
|
<description>Second Alarm Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RSECCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RSECCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEC10</name>
|
|
<description>10-Seconds Value for the tens place of seconds</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEC1</name>
|
|
<description>1-Second Value for the ones place of seconds</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT0AR</name>
|
|
<description>Binary Counter 0 Alarm Register</description>
|
|
<alternateRegister>RSECAR</alternateRegister>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT0AR</name>
|
|
<description>he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMINAR</name>
|
|
<description>Minute Alarm Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RMINCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RMINCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MIN10</name>
|
|
<description>10-Minute Count Value for the tens place of minutes</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MIN1</name>
|
|
<description>1-Minute Count Value for the ones place of minutes</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT1AR</name>
|
|
<description>Binary Counter 1 Alarm Register</description>
|
|
<alternateRegister>RMINAR</alternateRegister>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT1AR</name>
|
|
<description>he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RHRAR</name>
|
|
<description>Hour Alarm Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RHRCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RHRCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Time Counter Setting for a.m./p.m.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>a.m.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>p.m.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HR10</name>
|
|
<description>10-Hour Count Value for the tens place of hours</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HR1</name>
|
|
<description>1-Hour Count Value for the ones place of hours</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT2AR</name>
|
|
<description>Binary Counter 2 Alarm Register</description>
|
|
<alternateRegister>RHRAR</alternateRegister>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT2AR</name>
|
|
<description>The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWKAR</name>
|
|
<description>Day-of-Week Alarm Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RWKCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RWKCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAYW</name>
|
|
<description>Day-of-Week Counting</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Sunday</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Monday</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Tuesday</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Wednesday</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Thursday</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Friday</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Saturday</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting Prohibited </description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT3AR</name>
|
|
<description>Binary Counter 3 Alarm Register</description>
|
|
<alternateRegister>RWKAR</alternateRegister>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT3AR</name>
|
|
<description>The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDAYAR</name>
|
|
<description>Date Alarm Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RDAYCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RDAYCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATE10</name>
|
|
<description>10 Days Value for the tens place of days</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATE1</name>
|
|
<description>1 Day Value for the ones place of days</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT0AER</name>
|
|
<description>Binary Counter 0 Alarm Enable Register</description>
|
|
<alternateRegister>RDAYAR</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMONAR</name>
|
|
<description>Month Alarm Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RMONCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RMONCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MON10</name>
|
|
<description>10 Months Value for the tens place of months</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON1</name>
|
|
<description>1 Month Value for the ones place of months</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT1AER</name>
|
|
<description>Binary Counter 1 Alarm Enable Register</description>
|
|
<alternateRegister>RMONAR</alternateRegister>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RYRAR</name>
|
|
<description>Year Alarm Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YR10</name>
|
|
<description>10 Years Value for the tens place of years</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>YR1</name>
|
|
<description>1 Year Value for the ones place of years</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT2AER</name>
|
|
<description>Binary Counter 2 Alarm Enable Register</description>
|
|
<alternateRegister>RYRAR</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RYRAREN</name>
|
|
<description>Year Alarm Enable Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>Compare enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The register value is not compared with the RYRCNT counter value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The register value is compared with the RYRCNT counter value.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCNT3AER</name>
|
|
<description>Binary Counter 3 Alarm Enable Register</description>
|
|
<alternateRegister>RYRAREN</alternateRegister>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENB</name>
|
|
<description>The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. </description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR1</name>
|
|
<description>RTC Control Register 1</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0A</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PES</name>
|
|
<description>Periodic Interrupt Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1).</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>A periodic interrupt is generated every 1/128 second.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>A periodic interrupt is generated every 1/64 second.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>A periodic interrupt is generated every 1/32 second.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>A periodic interrupt is generated every 1/16 second.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>A periodic interrupt is generated every 1/8 second.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>A periodic interrupt is generated every 1/4 second.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>A periodic interrupt is generated every 1/2 second.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>A periodic interrupt is generated every 1 second.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>A periodic interrupt is generated every 2 seconds.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>No periodic interrupts are generated.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCOS</name>
|
|
<description>RTCOUT Output Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTCOUT outputs 1 Hz.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTCOUT outputs 64 Hz.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIE</name>
|
|
<description>Periodic Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A periodic interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A periodic interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIE</name>
|
|
<description>Carry Interrupt Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A carry interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A carry interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIE</name>
|
|
<description>Alarm Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An alarm interrupt request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An alarm interrupt request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR2</name>
|
|
<description>RTC Control Register 2</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0E</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMD</name>
|
|
<description>Count Mode Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The calendar count mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The binary count mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HR24</name>
|
|
<description>Hours Mode</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RTC operates in 12-hour mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RTC operates in 24-hour mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADJP</name>
|
|
<description>Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.)</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADJE</name>
|
|
<description>Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.)</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic adjustment is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic adjustment is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCOE</name>
|
|
<description>RTCOUT Output Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTCOUT output disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTCOUT output enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADJ30</name>
|
|
<description>30-Second Adjustment</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>30-second adjustment is executed.(write) / During 30-second adjustment.(read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>RTC Software Reset</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler and time counter are stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler and time counter operate normally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR4</name>
|
|
<description>RTC Control Register 4</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCKSEL</name>
|
|
<description>Count Source Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sub-clock oscillator is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LOCO clock oscillator is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFRH</name>
|
|
<description>Frequency Register H</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFC16</name>
|
|
<description>Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFRL</name>
|
|
<description>Frequency Register L</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFC</name>
|
|
<description>Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RADJ</name>
|
|
<description>Time Error Adjustment Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMADJ</name>
|
|
<description>Plus-Minus</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Adjustment is not performed.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Adjustment is performed by the addition to the prescaler.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Adjustment is performed by the subtraction from the prescaler.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADJ</name>
|
|
<description>Adjustment Value These bits specify the adjustment value from the prescaler.</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RTCCR%s</name>
|
|
<description>Time Capture Control Register %s</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCNF</name>
|
|
<description>Time Capture Noise Filter Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The noise filter is off.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The noise filter is on (count source).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The noise filter is on (count source by divided by 32).</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCST</name>
|
|
<description>Time Capture Status</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No event is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An event is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCCT</name>
|
|
<description>Time Capture Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No event is detected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Rising edge is detected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Falling edge is detected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both edges are detected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RSECCP%s</name>
|
|
<description>Second Capture Register %s</description>
|
|
<addressOffset>0x52</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC10</name>
|
|
<description>10-Second Capture Capture value for the tens place of seconds</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SEC1</name>
|
|
<description>1-Second Capture Capture value for the ones place of seconds</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>BCNT0CP%s</name>
|
|
<description>BCNT0 Capture Register %s</description>
|
|
<alternateRegister>RSECCP%s</alternateRegister>
|
|
<addressOffset>0x52</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT0CP</name>
|
|
<description>BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RMINCP%s</name>
|
|
<description>Minute Capture Register %s</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MIN10</name>
|
|
<description>10-Minute Capture Capture value for the tens place of minutes</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MIN1</name>
|
|
<description>1-Minute Capture Capture value for the ones place of minutes</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>BCNT1CP%s</name>
|
|
<description>BCNT1 Capture Register %s</description>
|
|
<alternateRegister>RMINCP%s</alternateRegister>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT1CP</name>
|
|
<description>BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RHRCP%s</name>
|
|
<description>Hour Capture Register %s</description>
|
|
<addressOffset>0x56</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>A.m./p.m. select for time counter setting.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>a.m.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>p.m.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HR10</name>
|
|
<description>10-Minute Capture Capture value for the tens place of minutes</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HR1</name>
|
|
<description>1-Minute Capture Capture value for the ones place of minutes</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>BCNT2CP%s</name>
|
|
<description>BCNT2 Capture Register %s</description>
|
|
<alternateRegister>RHRCP%s</alternateRegister>
|
|
<addressOffset>0x56</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT2CP</name>
|
|
<description>BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RDAYCP%s</name>
|
|
<description>Date Capture Register %s</description>
|
|
<addressOffset>0x5A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATE10</name>
|
|
<description>10-Day Capture Capture value for the tens place of minutes</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATE1</name>
|
|
<description>1-Day Capture Capture value for the ones place of minutes</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>BCNT3CP%s</name>
|
|
<description>BCNT3 Capture Register %s</description>
|
|
<alternateRegister>RDAYCP%s</alternateRegister>
|
|
<addressOffset>0x5A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCNT3CP</name>
|
|
<description>BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>RMONCP%s</name>
|
|
<description>Month Capture Register %s</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MON10</name>
|
|
<description>10-Month Capture Capture value for the tens place of months</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MON1</name>
|
|
<description>1-Month Capture Capture value for the ones place of months</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSIE0</name>
|
|
<description>Serial Sound Interface Enhanced (SSIE)</description>
|
|
<baseAddress>0x4004E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SSICR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Oversampling Clock Select</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AUDIO_CLK input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUIEN</name>
|
|
<description>Transmit Underflow Interrupt Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an underflow interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an underflow interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIEN</name>
|
|
<description>Transmit Overflow Interrupt Enable</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an overflow interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an overflow interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUIEN</name>
|
|
<description>Receive Underflow Interrupt Enable</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an underflow interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an underflow interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROIEN</name>
|
|
<description>Receive Overflow Interrupt Enable</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an overflow interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an overflow interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IIEN</name>
|
|
<description>Idle Mode Interrupt Enable</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables an idle mode interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables an idle mode interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHNL</name>
|
|
<description>Channels</description>
|
|
<lsb>22</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>One channel</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWL</name>
|
|
<description>Data Word Length</description>
|
|
<lsb>19</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>8 bits</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>16 bits</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>18 bits</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>20 bits</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>22 bits</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>24 bits</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWL</name>
|
|
<description>System Word LengthSet the system word length to the bit clock frequency/2 fs.</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>8 bits (serial bit clock frequency = 16fs )</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>16 bits (serial bit clock frequency = 32fs )</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>24 bits (serial bit clock frequency = 48fs )</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>32 bits (serial bit clock frequency = 64fs )</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSD</name>
|
|
<description>Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited.</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial word select is input, slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial word select is output, master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKP</name>
|
|
<description>Serial Bit Clock Polarity</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSP</name>
|
|
<description>Serial WS Polarity</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSIWS is low for 1st channel, high for 2nd channel.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSIWS is high for 1st channel, low for 2nd channel.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPDP</name>
|
|
<description>Serial Padding Polarity</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Padding bits are low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Padding bits are high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDTA</name>
|
|
<description>Serial Data Alignment</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitting and receiving in the order of serial data and padding bits</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitting and receiving in the order of padding bits and serial data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDTA</name>
|
|
<description>Parallel Data Alignment</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEL</name>
|
|
<description>Serial Data Delay</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>1 clock cycle delay between SSIWS and SSIDATA</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No delay between SSIWS and SSIDATA</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKDV</name>
|
|
<description>Serial Oversampling Clock Division Ratio</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>CLK</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x1</name>
|
|
<description>CLK/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x2</name>
|
|
<description>CLK/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3</name>
|
|
<description>CLK/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x4</name>
|
|
<description>CLK/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x5</name>
|
|
<description>CLK/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x6</name>
|
|
<description>CLK/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x7</name>
|
|
<description>CLK/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x8</name>
|
|
<description>CLK/6</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x9</name>
|
|
<description>CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0xA</name>
|
|
<description>CLK/24</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0xB</name>
|
|
<description>CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0xC</name>
|
|
<description>CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUEN</name>
|
|
<description>Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This module is not muted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This module is muted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmit Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the transmit operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the transmit operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receive Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the receive operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the receive operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSISR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000013</resetValue>
|
|
<resetMask>0x3E00007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TUIRQ</name>
|
|
<description>Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit underflow has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A transmit underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIRQ</name>
|
|
<description>Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit overflow has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A transmit overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUIRQ</name>
|
|
<description>Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive underflow has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A receive underflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROIRQ</name>
|
|
<description>Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive overflow has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A receive overflow has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IIRQ</name>
|
|
<description>Idle Mode Interrupt Status Flag</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This module is not in idle state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This module is in idle state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCHNO</name>
|
|
<description>Transmit Channel Number</description>
|
|
<lsb>5</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSWNO</name>
|
|
<description>Transmit Serial Word Number</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCHNO</name>
|
|
<description>Receive Channel Number.These bits are read as 00b.</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSWNO</name>
|
|
<description>Receive Serial Word Number</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDST</name>
|
|
<description>Idle Mode Status Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial bus is operating.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current communication is stopped.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIFCR</name>
|
|
<description>FIFO Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUCKE</name>
|
|
<description>Oversampling Clock Enable</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The oversampling clock is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The oversampling clock is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSIRST</name>
|
|
<description>SSI soft ware reset</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clears the SSI software reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>initiates the SSI software reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TTRG</name>
|
|
<description>Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set.</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>7 (1)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>6 (2)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>4 (4)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>2 (6)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTRG</name>
|
|
<description>Receive Data Trigger Number</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>6</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data empty interrupt (TXI) request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data empty interrupt (TXI) request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data full interrupt (RXI) request is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data full interrupt (RXI) request is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRST</name>
|
|
<description>Transmit FIFO Data Register Reset</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clears the transmit data FIFO reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initiates the transmit data FIFO reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFRST</name>
|
|
<description>Receive FIFO Data Register Reset</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clears the receive data FIFO reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initiates the receive data FIFO reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIFSR</name>
|
|
<description>FIFO Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDC</name>
|
|
<description>Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR)</description>
|
|
<lsb>24</lsb>
|
|
<msb>27</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs.</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDC</name>
|
|
<description>Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR)</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Number of received data bytes in SSIFRDR is less than the set receive trigger number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIFTDR</name>
|
|
<description>Transmit FIFO Data Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSIFTDR</name>
|
|
<description>SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIFRDR</name>
|
|
<description>Receive FIFO Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSIFRDR</name>
|
|
<description>SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIOFR</name>
|
|
<description>Audio Format Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BCKASTP</name>
|
|
<description>Whether to Enable Stopping BCK Output When SSIE is in Idle Status</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Always outputs BCK to the SSIBCK pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatically controls output of BCK to the SSIBCK pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRCONT</name>
|
|
<description>Whether to Enable LRCK/FS Continuation</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables LRCK/FS continuation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables LRCK/FS continuation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OMOD</name>
|
|
<description>Audio Format Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>I2S format</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>TDM format</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Monaural format</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSISCR</name>
|
|
<description>Status Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDES</name>
|
|
<description>TDE Setting Condition Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>SSIFTDR has one stage or more free space</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>SSIFTDR has two stages or more free space (snip)</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>SSIFTDR has thirty-one stages or more free space</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>SSIFTDR has thirty-two stages or more free space.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDFS</name>
|
|
<description>RDF Setting Condition Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>SSIFRDR has one stage or more data size</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>SSIFRDR has two stages or more data size (snip)</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>SSIFRDR has thirty-one stages or more data size</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>SSIFRDR has thirty-two stages or more data size.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSIE0">
|
|
<name>SSIE1</name>
|
|
<description>Serial Sound Interface Enhanced (SSIE)</description>
|
|
<baseAddress>0x4004E100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBFS</name>
|
|
<description>USB 2.0 FS Module</description>
|
|
<baseAddress>0x40090000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x36</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x46</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x64</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x68</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6C</offset>
|
|
<size>22</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x90</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x92</offset>
|
|
<size>20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD0</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xF0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x400</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYSCFG</name>
|
|
<description>System Configuration Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKE</name>
|
|
<description>USB Clock Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stops supplying the clock signal to the USB.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables supplying the clock signal to the USB.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCFM</name>
|
|
<description>Controller Function Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Function controller is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host controller is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRPD</name>
|
|
<description>D+/D- Line Resistor Control</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulling down the lines is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulling down the lines is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPRPU</name>
|
|
<description>D+ Line Resistor Control</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulling up the line is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulling up the line is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBE</name>
|
|
<description>USB Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB operation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSSTS0</name>
|
|
<description>System Configuration Status Register 0 </description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVCMON</name>
|
|
<description>External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTACT</name>
|
|
<description>USB Host Sequencer Status Monitor</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host sequencer of the USB is completely stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host sequencer of the USB is not completely stopped.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFEA</name>
|
|
<description>Active Monitor When the Host Controller is Selected.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SOF output is stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SOF output is operating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMON</name>
|
|
<description>External ID0 Input Pin Monitor</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB0_ID pin is low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB0_ID pin is high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LNST</name>
|
|
<description>USB Data Line Status Monitor</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SE0 </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>J-State </description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>K-State</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>SE1</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVSTCTR0</name>
|
|
<description>Device State Control Register 0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HNPBTOA</name>
|
|
<description>Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal Operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Switching from device B to device A is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXICEN</name>
|
|
<description>USB0_EXICEN Output Pin Control</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External USB0_EXICEN pin outputs low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External USB0_EXICEN pin outputs high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSEN</name>
|
|
<description>USB0_VBUSEN Output Pin Control</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External USB0_VBUSEN pin outputs low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External USB0_VBUSEN pin outputs high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP</name>
|
|
<description>Wakeup Output</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Remote wakeup signal is not output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote wakeup signal is output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUPE</name>
|
|
<description>Wakeup Detection Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Downstream port wakeup is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Downstream port wakeup is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBRST</name>
|
|
<description>USB Bus Reset Output</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB bus reset signal is not output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB bus reset signal is output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>Resume Output</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resume signal is not output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resume signal is output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UACT</name>
|
|
<description>USB Bus Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Downstream port is disabled (SOF transmission is disabled).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Downstream port is enabled (SOF transmission is enabled).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RHST</name>
|
|
<description>USB Bus Reset Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Communication speed not determined</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>USB bus reset in progress(When the host controller function is selected)</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFO</name>
|
|
<description>CFIFO Port Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOL</name>
|
|
<description>CFIFO Port Register L</description>
|
|
<alternateRegister>CFIFO</alternateRegister>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFO</name>
|
|
<description>D0FIFO Port Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOL</name>
|
|
<description>D0FIFO Port Register L</description>
|
|
<alternateRegister>D0FIFO</alternateRegister>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFO</name>
|
|
<description>D1FIFO Port Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOPORT</name>
|
|
<description>FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOL</name>
|
|
<description>D1FIFO Port Register L</description>
|
|
<alternateRegister>D1FIFO</alternateRegister>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOSEL</name>
|
|
<description>CFIFO Port Select Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer pointer is not rewound.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer pointer is rewound.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>CFIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>8-bit width</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>16-bit width</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>CFIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISEL</name>
|
|
<description>CFIFO Port Access Direction When DCP is Selected</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reading from the buffer memory is selected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing to the buffer memory is selected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>CFIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>DCP (Default control pipe)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Pipe 1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Pipe 2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Pipe 3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Pipe 4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Pipe 5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Pipe 6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Pipe 7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Pipe 8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Pipe 9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFIFOCTR</name>
|
|
<description>CFIFO Port Control Register</description>
|
|
<addressOffset>0x022</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the buffer memory on the CPU side</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port Ready</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data LengthIndicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOSEL</name>
|
|
<description>D0FIFO Port Select Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer pointer is not rewound.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer pointer is rewound.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCLRM</name>
|
|
<description>Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto buffer clear mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto buffer clear mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQE</name>
|
|
<description>DMA/DTC Transfer Request Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA/DTC transfer request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA/DTC transfer request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>FIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>8-bit width</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>16-bit width</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>FIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>FIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>DCP (Default control pipe)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Pipe 1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Pipe 2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Pipe 3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Pipe 4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Pipe 5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Pipe 6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Pipe 7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Pipe 8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Pipe 9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D0FIFOCTR</name>
|
|
<description>D0FIFO Port Control Register</description>
|
|
<addressOffset>0x02A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the buffer memory on the CPU side</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port Ready</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data LengthIndicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOSEL</name>
|
|
<description>D1FIFO Port Select Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Read Count Mode</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REW</name>
|
|
<description>Buffer Pointer Rewind</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer pointer is not rewound.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer pointer is rewound.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCLRM</name>
|
|
<description>Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto buffer clear mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto buffer clear mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQE</name>
|
|
<description>DMA/DTC Transfer Request Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA/DTC transfer request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA/DTC transfer request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBW</name>
|
|
<description>FIFO Port Access Bit Width</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>8-bit width</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>16-bit width</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIGEND</name>
|
|
<description>FIFO Port Endian Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CURPIPE</name>
|
|
<description>FIFO Port Access Pipe Specification</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>DCP (Default control pipe)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Pipe 1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Pipe 2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Pipe 3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Pipe 4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Pipe 5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Pipe 6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Pipe 7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Pipe 8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Pipe 9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D1FIFOCTR</name>
|
|
<description>D1FIFO Port Control Register</description>
|
|
<addressOffset>0x02E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BVAL</name>
|
|
<description>Buffer Memory Valid Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing ended</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLR</name>
|
|
<description>CPU Buffer Clear</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the buffer memory on the CPU side</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRDY</name>
|
|
<description>FIFO Port Ready</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO port access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO port access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTLN</name>
|
|
<description>Receive Data LengthIndicates the length of the receive data.</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENB0</name>
|
|
<description>Interrupt Enable Register 0</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBSE</name>
|
|
<description>VBUS Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSME</name>
|
|
<description>Resume Interrupt Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFE</name>
|
|
<description>Frame Number Update Interrupt Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVSE</name>
|
|
<description>Device State Transition Interrupt Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRE</name>
|
|
<description>Control Transfer Stage Transition Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEMPE</name>
|
|
<description>Buffer Empty Interrupt Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRDYE</name>
|
|
<description>Buffer Not Ready Response Interrupt Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDYE</name>
|
|
<description>Buffer Ready Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENB1</name>
|
|
<description>Interrupt Enable Register 1 </description>
|
|
<addressOffset>0x032</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRCRE</name>
|
|
<description>Overcurrent Input Change Interrupt Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCHGE</name>
|
|
<description>USB Bus Change Interrupt Enable</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCHE</name>
|
|
<description>Disconnection Detection Interrupt Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATTCHE</name>
|
|
<description>Connection Detection Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOFERRE</name>
|
|
<description>EOF Error Detection Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIGNE</name>
|
|
<description>Setup Transaction Error Interrupt Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKE</name>
|
|
<description>Setup Transaction Normal Response Interrupt Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRDYENB</name>
|
|
<description>BRDY Interrupt Enable Register</description>
|
|
<addressOffset>0x036</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0BRDYE</name>
|
|
<description>BRDY Interrupt Enable for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NRDYENB</name>
|
|
<description>NRDY Interrupt Enable Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0NRDYE</name>
|
|
<description>NRDY Interrupt Enable for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BEMPENB</name>
|
|
<description>BEMP Interrupt Enable Register</description>
|
|
<addressOffset>0x03A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0BEMPE</name>
|
|
<description>BEMP Interrupt Enable for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt output disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFCFG</name>
|
|
<description>SOF Output Configuration Register </description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRNENSEL</name>
|
|
<description>Transaction-Enabled Time Select </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>For non-low-speed communication</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>For low-speed communication</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDYM</name>
|
|
<description>BRDY Interrupt Status Clear Timing</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software clears the status.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The USB clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGESTS</name>
|
|
<description>Edge Interrupt Output Status Monitor </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>before stopping the clock supply to the USB module</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>the edge interrupt output signal is in the middle of the edge processing</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTS0</name>
|
|
<description>Interrupt Status Register 0</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBINT</name>
|
|
<description>VBUS Interrupt Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VBUS interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VBUS interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESM</name>
|
|
<description>Resume Interrupt Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resume interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resume interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFR</name>
|
|
<description>Frame Number Refresh Interrupt Status</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SOF interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SOF interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVST</name>
|
|
<description>Device State Transition Interrupt Status</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Device state transition interrupts are not generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Device state transition interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRT</name>
|
|
<description>Control Transfer Stage Transition Interrupt Status</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control transfer stage transition interrupts are not generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control transfer stage transition interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEMP</name>
|
|
<description>Buffer Empty Interrupt Status</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BEMP interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BEMP interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NRDY</name>
|
|
<description>Buffer Not Ready Interrupt Status</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NRDY interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NRDY interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRDY</name>
|
|
<description>Buffer Ready Interrupt Status</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BRDY interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BRDY interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBSTS</name>
|
|
<description>VBUS Input Status</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>USB0_VBUS pin is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>USB0_VBUS pin is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVSQ</name>
|
|
<description>Device State</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Powered state</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Default state</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Address state</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Configured state</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Suspended state</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>USB Request Reception</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Setup packet is not received</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Setup packet is received</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSQ</name>
|
|
<description>Control Transfer Stage</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Idle or setup stage</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Control read data stage</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Control read status stage</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Control write data stage</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Control write status stage</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Control write (no data) status stage</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Control transfer sequence error</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTS1</name>
|
|
<description>Interrupt Status Register 1</description>
|
|
<addressOffset>0x042</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRCR</name>
|
|
<description>Overcurrent Input Change Interrupt Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OVRCR interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OVRCR interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCHG</name>
|
|
<description>USB Bus Change Interrupt Status</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BCHG interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BCHG interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCH</name>
|
|
<description>USB Disconnection Detection Interrupt Status</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DTCH interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DTCH interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATTCH</name>
|
|
<description>ATTCH Interrupt Status</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ATTCH interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ATTCH interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOFERR</name>
|
|
<description>EOF Error Detection Interrupt Status</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EOFERR interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EOFERR interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Setup Transaction Error Interrupt Status</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SIGN interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SIGN interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACK</name>
|
|
<description>Setup Transaction Normal Response Interrupt Status</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SACK interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SACK interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRDYSTS</name>
|
|
<description>BRDY Interrupt Status Register</description>
|
|
<addressOffset>0x046</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0BRDY</name>
|
|
<description>BRDY Interrupt Status for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NRDYSTS</name>
|
|
<description>NRDY Interrupt Status Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0NRDY</name>
|
|
<description>NRDY Interrupt Status for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BEMPSTS</name>
|
|
<description>BEMP Interrupt Status Register</description>
|
|
<addressOffset>0x04A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPE9BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE9</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE8BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE8</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE7BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE6BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE5BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE4BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE3BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE2BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE1BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIPE0BEMP</name>
|
|
<description>BEMP Interrupt Status for PIPE0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts are not generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupts are generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRMNUM</name>
|
|
<description>Frame Number Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVRN</name>
|
|
<description>Overrun/Underrun Detection Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCE</name>
|
|
<description>Receive Data Error</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRNM</name>
|
|
<description>Frame NumberLatest frame number</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVCHGR</name>
|
|
<description>Device State Change Register</description>
|
|
<addressOffset>0x04E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVCHG</name>
|
|
<description>Device State Change</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBADDR</name>
|
|
<description>USB Address Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STSRECOV</name>
|
|
<description>Status Recovery</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b;(Recovery when the host controller is selected))</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b;(Recovery when the host controller is selected))</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state);(Recovery when the function controller is selected)</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state);(Recovery when the function controller is selected)</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state);(Recovery when the function controller is selected)</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBADDR</name>
|
|
<description>USB AddressWhen the function controller is selected, these bits indicate the USB address assigned by the host when the SET_ADDRESS request is successfully processed.</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBREQ</name>
|
|
<description>USB Request Type Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BREQUEST</name>
|
|
<description>RequestThese bits store the USB request bRequest value.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BMREQUESTTYPE</name>
|
|
<description>Request TypeThese bits store the USB request bmRequestType value.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBVAL</name>
|
|
<description>USB Request Value Register</description>
|
|
<addressOffset>0x056</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WVALUE</name>
|
|
<description>ValueThese bits store the USB request wValue value.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINDX</name>
|
|
<description>USB Request Index Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDEX</name>
|
|
<description>IndexThese bits store the USB request wIndex value.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBLENG</name>
|
|
<description>USB Request Length Register</description>
|
|
<addressOffset>0x05A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLENGTH</name>
|
|
<description>LengthThese bits store the USB request wLength value.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPCFG</name>
|
|
<description>DCP Configuration Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHTNAK</name>
|
|
<description>Pipe Disabled at End of Transfer</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pipe continued at the end of transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pipe disabled at the end of transfer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data receiving direction</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data transmitting direction</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPMAXP</name>
|
|
<description>DCP Maximum Packet Size Register</description>
|
|
<addressOffset>0x05E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Address 0000</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Address 0001</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Address 0010</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Address 0011</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Address 0100</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Address 0101</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXPS</name>
|
|
<description>Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP.</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCPCTR</name>
|
|
<description>DCP Control Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTS</name>
|
|
<description>Buffer Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUREQ</name>
|
|
<description>Setup Token Transmission</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmits the setup packet.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUREQCLR</name>
|
|
<description>SUREQ Bit Clear</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the SUREQ bit to 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQCLR</name>
|
|
<description>Sequence Toggle Bit Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQSET</name>
|
|
<description>Sequence Toggle Bit Set</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQMON</name>
|
|
<description>Sequence Toggle Bit Monitor</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DATA0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DATA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBUSY</name>
|
|
<description>Pipe Busy</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DCP is not used for the transaction.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DCP is used for the transaction.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPL</name>
|
|
<description>Control Transfer End Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Completion of control transfer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Response PID</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NAK response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUF response (depending on the buffer state)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL response</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>STALL response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPESEL</name>
|
|
<description>Pipe Window Select Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIPESEL</name>
|
|
<description>Pipe Window Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No pipe selected</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>PIPE1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>PIPE2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>PIPE3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PIPE4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>PIPE5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PIPE6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PIPE7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>PIPE8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>PIPE9</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPECFG</name>
|
|
<description>Pipe Configuration Register</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Transfer Type</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Pipe not used</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFRE</name>
|
|
<description>BRDY Interrupt Operation Specification</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BRDY interrupt upon transmitting or receiving data</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>BRDY interrupt upon completion of reading data</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLB</name>
|
|
<description>Double Buffer Mode</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Single buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTNAK</name>
|
|
<description>Pipe Disabled at End of Transfer</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pipe assignment continued at the end of transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pipe assignment disabled at the end of transfer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer Direction</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiving direction</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitting direction</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPEMAXP</name>
|
|
<description>Pipe Maximum Packet Size Register </description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFBF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>Device Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Address 0000</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Address 0001</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Address 0010</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Address 0011</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Address 0100</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Address 0101</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXPS</name>
|
|
<description>Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.)</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIPEPERI</name>
|
|
<description>Pipe Cycle Control Register</description>
|
|
<addressOffset>0x06E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IFIS</name>
|
|
<description>Isochronous IN Buffer Flush</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The buffer is not flushed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The buffer is flushed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IITV</name>
|
|
<description>Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2.</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x002</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>PIPE%sCTR</name>
|
|
<description>Pipe %s Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTS</name>
|
|
<description>Buffer Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer access by the CPU is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer access by the CPU is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INBUFM</name>
|
|
<description>Transmit Buffer Monitor</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data to be transmitted is in the FIFO buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data to be transmitted is in the FIFO buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATREPM</name>
|
|
<description>Auto Response Mode</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto response is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto response is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACLRM</name>
|
|
<description>Auto Buffer Clear Mode</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled (all buffers are initialized)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQCLR</name>
|
|
<description>Sequence Toggle Bit Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQSET</name>
|
|
<description>Sequence Toggle Bit Set</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQMON</name>
|
|
<description>Sequence Toggle Bit Confirmation</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DATA0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DATA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBUSY</name>
|
|
<description>Pipe Busy</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The relevant pipe is not used for the transaction.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The relevant pipe is used for the transaction.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Response PID</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NAK response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUF response (depending on the buffer state)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL response</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>STALL response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x002</dimIncrement>
|
|
<dimIndex>6-9</dimIndex>
|
|
<name>PIPE%sCTR</name>
|
|
<description>Pipe %s Control Register</description>
|
|
<addressOffset>0x07A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSTS</name>
|
|
<description>Buffer Status</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Buffer access is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Buffer access is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACLRM</name>
|
|
<description>Auto Buffer Clear Mode</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Auto buffer clear mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Auto buffer clear mode is enabled (all buffers are initialized)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQCLR</name>
|
|
<description>Sequence Toggle Bit Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQSET</name>
|
|
<description>Sequence Toggle Bit Set</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Specifies DATA1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQMON</name>
|
|
<description>Sequence Toggle Bit Confirmation</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DATA0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DATA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBUSY</name>
|
|
<description>Pipe Busy</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The relevant pipe is not used at the USB bus.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The relevant pipe is used at the USB bus.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Response PID</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NAK response</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUF response (depending on the buffer state)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>STALL response</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>STALL response</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x004</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>PIPE%sTRE</name>
|
|
<description>Pipe %s Transaction Counter Enable Register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRENB</name>
|
|
<description>Transaction Counter Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transaction counter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transaction counter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRCLR</name>
|
|
<description>Transaction Counter Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current counter value is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x004</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>PIPE%sTRN</name>
|
|
<description>Pipe %s Transaction Counter Register</description>
|
|
<addressOffset>0x092</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRNCNT</name>
|
|
<description>Transaction Counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x002</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>DEVADD%s</name>
|
|
<description>Device Address %s Configuration Register</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBSPD</name>
|
|
<description>Transfer Speed of Communication Target Device</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>DEVADDn is not used</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Low speed</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Full speed</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PHYSLEW</name>
|
|
<description>PHY Cross Point Adjustment Register </description>
|
|
<addressOffset>0x0F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000E</resetValue>
|
|
<resetMask>0xFF4CFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLEWF01</name>
|
|
<description>Receiver Cross Point Adjustment 01</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reserved</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host or device controller mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEWF00</name>
|
|
<description>Receiver Cross Point Adjustment 00</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reserved</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host or device controller mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEWR01</name>
|
|
<description>Receiver Cross Point Adjustment 01</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reserved</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host or device controller mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEWR00</name>
|
|
<description>Receiver Cross Point Adjustment 00</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reserved</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host or device controller mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSR0R</name>
|
|
<description>Deep Software Standby USB Transceiver Control/Pin Monitor Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFF4CFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBSTS0</name>
|
|
<description>USB VBUS InputIndicates the VBUS input signal of the USB.</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DOVCB0</name>
|
|
<description>USB OVRCURB InputIndicates the OVRCURB input signal of the USB.</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DOVCA0</name>
|
|
<description>USB OVRCURA InputIndicates the OVRCURA input signal of the USB.</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DM0</name>
|
|
<description>USB D-InputIndicates the D- input signal of the USB.</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DP0</name>
|
|
<description>USB0 D+ InputIndicates the D+ input signal of the USB.</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIXPHY0</name>
|
|
<description>USB Transceiver Output Fix</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The outputs are fixed in normal mode and on return from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The outputs are fixed on transitions to deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRPD0</name>
|
|
<description>D+/D- Pull-Down Resistor Control</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables DP/DM pull-down resistor.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables DP/DM pull-down resistor.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPUE0</name>
|
|
<description>DP Pull-Up Resistor Control</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables DP pull-up resistor.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables DP pull-up resistor.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRPC0</name>
|
|
<description>USB Single End Receiver Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input through the DP and DM inputs is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input through the DP and DM inputs is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPUSR1R</name>
|
|
<description>Deep Software Standby USB Suspend/Resume Interrupt Register</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBINT0</name>
|
|
<description>USB VBUS Interrupt Source Recovery</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The system has not returned from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The system has returned from deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVRCRB0</name>
|
|
<description>USB OVRCURB Interrupt Source Recovery</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The system has not returned from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The system has returned from deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVRCRA0</name>
|
|
<description>USB OVRCURA Interrupt Source Recovery</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The system has not returned from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The system has returned from deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMINT0</name>
|
|
<description>USB DM Interrupt Source Recovery</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The system has not returned from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The system has returned from deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPINT0</name>
|
|
<description>USB DP Interrupt Source Recovery</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The system has not returned from deep software standby mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The system has returned from deep software standby mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DVBSE0</name>
|
|
<description>USB VBUS Interrupt Enable/Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery from deep software standby mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery from deep software standby mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVRCRBE0</name>
|
|
<description>USB OVRCURB Interrupt Enable/Clear</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery from deep software standby mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery from deep software standby mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOVRCRAE0</name>
|
|
<description>USB OVRCURA Interrupt Enable/Clear</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery from deep software standby mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery from deep software standby mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMINTE0</name>
|
|
<description>USB DM Interrupt Enable/Clear</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery from deep software standby mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery from deep software standby mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPINTE0</name>
|
|
<description>USB DP Interrupt Enable/Clear</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery from deep software standby mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery from deep software standby mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SRCRAM</name>
|
|
<description>Sampling Rate Converter RAM</description>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>22208</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>5552</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5551</dimIndex>
|
|
<name>SRCFCTR[%s]</name>
|
|
<description>Filter Coefficient Table [%s]</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFC00000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRCFCOE</name>
|
|
<description>Stores a filter coefficient value.</description>
|
|
<lsb>0</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SRC</name>
|
|
<description>Sampling Rate Converter</description>
|
|
<baseAddress>0x4004DFF0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SRCID</name>
|
|
<description>Input Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRCID</name>
|
|
<description>SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCOD</name>
|
|
<description>Output Data Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRCOD</name>
|
|
<description>SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCIDCTRL</name>
|
|
<description>Input Data Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IED</name>
|
|
<description>Input Data Endian</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Endian formats 1 are the same between the CPU and input data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Endian formats 1 are different between the CPU and input data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEN</name>
|
|
<description>Input FIFO Empty Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input FIFO empty interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input FIFO empty interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFTRG</name>
|
|
<description>Input FIFO Data Triggering Number</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>6</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCODCTRL</name>
|
|
<description>Output Data Control Register</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OCH</name>
|
|
<description>Output Data Channel Exchange</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not exchange the channels (the same order as data input)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Exchanges the channels (the opposite order from data input)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OED</name>
|
|
<description>Output Data Endian</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Endian formats are the same between the chip and input data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Endian formats are different between the chip and input data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEN</name>
|
|
<description>Output Data FIFO Full Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output data FIFO full interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output data FIFO full interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFTRG</name>
|
|
<description>Output FIFO Data Trigger Number</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>8</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>12</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCCTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FICRAE</name>
|
|
<description>Filter Coefficient Table Access Enable</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reading/writing to filter coefficient table RAM is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reading/writing to filter coefficient table RAM is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEEN</name>
|
|
<description>Conversion End Interrupt Enable</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables conversion end interrupt requests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables conversion end interrupt requests.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRCEN</name>
|
|
<description>Module Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables this module operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables this module operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDEN</name>
|
|
<description>Output Data FIFO Underflow Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables output data FIFO underflow interrupt requests.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables output data FIFO underflow interrupt requests.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVEN</name>
|
|
<description>Output Data FIFO Overwrite Interrupt Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output data FIFO overwrite interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output data FIFO overwrite interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FL</name>
|
|
<description>Internal Work Memory Flush</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL</name>
|
|
<description>Internal Work Memory Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFS</name>
|
|
<description>Input Sampling Rate</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>8.0 kHz</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>11.025 kHz</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>12.0 kHz</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>16.0 kHz</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>22.05 kHz</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>24.0 kHz</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>32.0 kHz</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>44.1 kHz</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>48.0 kHz</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Output Sampling Rate</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>44.1 kHz</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>48.0 kHz</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>32.0 kHz</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>8.0 kHz ( Valid only when IFS[3:0] =1001b )</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>16.0 kHz ( Valid only when IFS[3:0] =1001b )</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Settings other than above are prohibited.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCSTAT</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0002</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDN</name>
|
|
<description>Output FIFO Data Count</description>
|
|
<lsb>11</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFDN</name>
|
|
<description>The value of OFDN indicatethe number of data units in the output FIFO.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFDN</name>
|
|
<description>Input FIFO Data Count</description>
|
|
<lsb>7</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IFDN</name>
|
|
<description>The value of IFDN indicatethe number of data units in the input FIFO.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEF</name>
|
|
<description>Conversion End Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All of the output data has not been read out.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All of the output data has been read out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLF</name>
|
|
<description>Flush Processing Status Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash processing is completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash processing is in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDF</name>
|
|
<description>Output FIFO Underflow Interrupt Request Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output data FIFO has not been read out.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output data FIFO has been read out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Output Data FIFO Overwrite Interrupt Request Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Next data conversion processing is not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Next data conversion processing is completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IINT</name>
|
|
<description>Input Data FIFO Empty Interrupt Request Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Number of data units in the input FIFO has become equal to or smaller than the specified triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINT</name>
|
|
<description>Output Data FIFO Full Interrupt Request Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Number of data units in the output FIFO has not become equal to or greater than the specified triggering number.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Number of data units in the output FIFO has become equal to or greater than the specified triggering number.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ICU</name>
|
|
<description>Interrupt Controller</description>
|
|
<baseAddress>0x40006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x140</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x120</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x130</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x300</offset>
|
|
<size>384</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x280</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x200</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A0</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IEL0</name>
|
|
<description>ICU Interrupt 0</description>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL1</name>
|
|
<description>ICU Interrupt 1</description>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL2</name>
|
|
<description>ICU Interrupt 2</description>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL3</name>
|
|
<description>ICU Interrupt 3</description>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL4</name>
|
|
<description>ICU Interrupt 4</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL5</name>
|
|
<description>ICU Interrupt 5</description>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL6</name>
|
|
<description>ICU Interrupt 6</description>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL7</name>
|
|
<description>ICU Interrupt 7</description>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL8</name>
|
|
<description>ICU Interrupt 8</description>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL9</name>
|
|
<description>ICU Interrupt 9</description>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL10</name>
|
|
<description>ICU Interrupt 10</description>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL11</name>
|
|
<description>ICU Interrupt 11</description>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL12</name>
|
|
<description>ICU Interrupt 12</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL13</name>
|
|
<description>ICU Interrupt 13</description>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL14</name>
|
|
<description>ICU Interrupt 14</description>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL15</name>
|
|
<description>ICU Interrupt 15</description>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL16</name>
|
|
<description>ICU Interrupt 16</description>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL17</name>
|
|
<description>ICU Interrupt 17</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL18</name>
|
|
<description>ICU Interrupt 18</description>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL19</name>
|
|
<description>ICU Interrupt 19</description>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL20</name>
|
|
<description>ICU Interrupt 20</description>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL21</name>
|
|
<description>ICU Interrupt 21</description>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL22</name>
|
|
<description>ICU Interrupt 22</description>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL23</name>
|
|
<description>ICU Interrupt 23</description>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL24</name>
|
|
<description>ICU Interrupt 24</description>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL25</name>
|
|
<description>ICU Interrupt 25</description>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL26</name>
|
|
<description>ICU Interrupt 26</description>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL27</name>
|
|
<description>ICU Interrupt 27</description>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL28</name>
|
|
<description>ICU Interrupt 28</description>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL29</name>
|
|
<description>ICU Interrupt 29</description>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL30</name>
|
|
<description>ICU Interrupt 30</description>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL31</name>
|
|
<description>ICU Interrupt 31</description>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL32</name>
|
|
<description>ICU Interrupt 32</description>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL33</name>
|
|
<description>ICU Interrupt 33</description>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL34</name>
|
|
<description>ICU Interrupt 34</description>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL35</name>
|
|
<description>ICU Interrupt 35</description>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL36</name>
|
|
<description>ICU Interrupt 36</description>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL37</name>
|
|
<description>ICU Interrupt 37</description>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL38</name>
|
|
<description>ICU Interrupt 38</description>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL39</name>
|
|
<description>ICU Interrupt 39</description>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL40</name>
|
|
<description>ICU Interrupt 40</description>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL41</name>
|
|
<description>ICU Interrupt 41</description>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL42</name>
|
|
<description>ICU Interrupt 42</description>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL43</name>
|
|
<description>ICU Interrupt 43</description>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL44</name>
|
|
<description>ICU Interrupt 44</description>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL45</name>
|
|
<description>ICU Interrupt 45</description>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL46</name>
|
|
<description>ICU Interrupt 46</description>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL47</name>
|
|
<description>ICU Interrupt 47</description>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL48</name>
|
|
<description>ICU Interrupt 48</description>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL49</name>
|
|
<description>ICU Interrupt 49</description>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL50</name>
|
|
<description>ICU Interrupt 50</description>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL51</name>
|
|
<description>ICU Interrupt 51</description>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL52</name>
|
|
<description>ICU Interrupt 52</description>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL53</name>
|
|
<description>ICU Interrupt 53</description>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL54</name>
|
|
<description>ICU Interrupt 54</description>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL55</name>
|
|
<description>ICU Interrupt 55</description>
|
|
<value>55</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL56</name>
|
|
<description>ICU Interrupt 56</description>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL57</name>
|
|
<description>ICU Interrupt 57</description>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL58</name>
|
|
<description>ICU Interrupt 58</description>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL59</name>
|
|
<description>ICU Interrupt 59</description>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL60</name>
|
|
<description>ICU Interrupt 60</description>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL61</name>
|
|
<description>ICU Interrupt 61</description>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL62</name>
|
|
<description>ICU Interrupt 62</description>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL63</name>
|
|
<description>ICU Interrupt 63</description>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL64</name>
|
|
<description>ICU Interrupt 64</description>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL65</name>
|
|
<description>ICU Interrupt 65</description>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL66</name>
|
|
<description>ICU Interrupt 66</description>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL67</name>
|
|
<description>ICU Interrupt 67</description>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL68</name>
|
|
<description>ICU Interrupt 68</description>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL69</name>
|
|
<description>ICU Interrupt 69</description>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL70</name>
|
|
<description>ICU Interrupt 70</description>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL71</name>
|
|
<description>ICU Interrupt 71</description>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL72</name>
|
|
<description>ICU Interrupt 72</description>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL73</name>
|
|
<description>ICU Interrupt 73</description>
|
|
<value>73</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL74</name>
|
|
<description>ICU Interrupt 74</description>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL75</name>
|
|
<description>ICU Interrupt 75</description>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL76</name>
|
|
<description>ICU Interrupt 76</description>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL77</name>
|
|
<description>ICU Interrupt 77</description>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL78</name>
|
|
<description>ICU Interrupt 78</description>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL79</name>
|
|
<description>ICU Interrupt 79</description>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL80</name>
|
|
<description>ICU Interrupt 80</description>
|
|
<value>80</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL81</name>
|
|
<description>ICU Interrupt 81</description>
|
|
<value>81</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL82</name>
|
|
<description>ICU Interrupt 82</description>
|
|
<value>82</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL83</name>
|
|
<description>ICU Interrupt 83</description>
|
|
<value>83</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL84</name>
|
|
<description>ICU Interrupt 84</description>
|
|
<value>84</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL85</name>
|
|
<description>ICU Interrupt 85</description>
|
|
<value>85</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL86</name>
|
|
<description>ICU Interrupt 86</description>
|
|
<value>86</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL87</name>
|
|
<description>ICU Interrupt 87</description>
|
|
<value>87</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL88</name>
|
|
<description>ICU Interrupt 88</description>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL89</name>
|
|
<description>ICU Interrupt 89</description>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL90</name>
|
|
<description>ICU Interrupt 90</description>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL91</name>
|
|
<description>ICU Interrupt 91</description>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL92</name>
|
|
<description>ICU Interrupt 92</description>
|
|
<value>92</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL93</name>
|
|
<description>ICU Interrupt 93</description>
|
|
<value>93</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL94</name>
|
|
<description>ICU Interrupt 94</description>
|
|
<value>94</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>IEL95</name>
|
|
<description>ICU Interrupt 95</description>
|
|
<value>95</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>IRQCR%s</name>
|
|
<description>IRQ Control Register %s</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTEN</name>
|
|
<description>IRQ Digital Filter Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCLKSEL</name>
|
|
<description>IRQ Digital Filter Sampling Clock</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLKB</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLKB/8</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLKB/32</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLKB/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQMD</name>
|
|
<description>IRQ Detection Sense Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Falling edge</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Rising edge</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Rising and falling edges</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Low level</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMISR</name>
|
|
<description>Non-Maskable Interrupt Status Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPEST</name>
|
|
<description>MPU Stack Error Interrupt Status Flag</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Stack Error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Stack Error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSMST</name>
|
|
<description>MPU Bus Master Error Interrupt Status Flag</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Bus Master Error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Bus Master Error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSSST</name>
|
|
<description>MPU Bus Slave Error Interrupt Status Flag</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Bus Slave Error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Bus Slave Error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RECCST</name>
|
|
<description>RAM ECC Error Interrupt Status Flag</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM ECC Error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM ECC Error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPEST</name>
|
|
<description>RAM Parity Error Interrupt Status Flag</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM Parity Error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM Parity Error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIST</name>
|
|
<description>NMI Status Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NMI pin interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMI pin interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTST</name>
|
|
<description>Oscillation Stop Detection Interrupt Status Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Oscillation stop detection interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillation stop detection interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD2ST</name>
|
|
<description>Voltage-Monitoring 2 Interrupt Status Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage-monitoring 2 interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage-monitoring 2 interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1ST</name>
|
|
<description>Voltage-Monitoring 1 Interrupt Status Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage-monitoring 1 interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage-monitoring 1 interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTST</name>
|
|
<description>WDT Underflow/Refresh Error Status Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDT underflow/refresh error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDT underflow/refresh error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IWDTST</name>
|
|
<description>IWDT Underflow/Refresh Error Status Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IWDT underflow/refresh error interrupt is not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IWDT underflow/refresh error interrupt is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMIER</name>
|
|
<description>Non-Maskable Interrupt Enable Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPEEN</name>
|
|
<description>MPU Stack Error Interrupt Enable</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Stack Error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Stack Error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSMEN</name>
|
|
<description>MPU Bus Master Error Interrupt Enable</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Bus Master Error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Bus Master Error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSSEN</name>
|
|
<description>MPU Bus Slave Error Interrupt Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MPU Bus Slave Error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MPU Bus Slave Error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RECCEN</name>
|
|
<description>RAM ECC Error Interrupt Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM ECC Error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM ECC Error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPEEN</name>
|
|
<description>RAM Parity Error Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RAM Parity Error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RAM Parity Error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIEN</name>
|
|
<description>NMI Pin Interrupt Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NMI pin interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>NMI pin interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTEN</name>
|
|
<description>Oscillation Stop Detection Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Oscillation stop detection interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillation stop detection interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD2EN</name>
|
|
<description>Voltage-Monitoring 2 Interrupt Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage-monitoring 2 interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage-monitoring 2 interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1EN</name>
|
|
<description>Voltage-Monitoring 1 Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Voltage-monitoring 1 interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Voltage-monitoring 1 interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTEN</name>
|
|
<description>WDT Underflow/Refresh Error Interrupt Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDT underflow/refresh error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDT underflow/refresh error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IWDTEN</name>
|
|
<description>IWDT Underflow/Refresh Error Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IWDT underflow/refresh error interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IWDT underflow/refresh error interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMICLR</name>
|
|
<description>Non-Maskable Interrupt Status Clear Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPECLR</name>
|
|
<description>SPEST Clear</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.SPEST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSMCLR</name>
|
|
<description>BUSMST Clear</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.BUSMST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSSCLR</name>
|
|
<description>BUSSST Clear</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.BUSSST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RECCCLR</name>
|
|
<description>RECCST Clear</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.RECCST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPECLR</name>
|
|
<description>RPEST Clear</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.RPEST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMICLR</name>
|
|
<description>NMIST Clear</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.NMIST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTCLR</name>
|
|
<description>OSTST Clear</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.OSTST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD2CLR</name>
|
|
<description>LVD2ST Clear</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.LVD2ST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1CLR</name>
|
|
<description>LVD1ST Clear</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.LVD1ST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTCLR</name>
|
|
<description>WDTST Clear</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.WDTST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IWDTCLR</name>
|
|
<description>IWDTST Clear</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear the NMISR.IWDTST flag. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMICR</name>
|
|
<description>NMI Pin Interrupt Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFLTEN</name>
|
|
<description>NMI Digital Filter Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFCLKSEL</name>
|
|
<description>NMI Digital Filter Sampling Clock</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PCLKB</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PCLKB/8</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PCLKB/32</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PCLKB/64</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIMD</name>
|
|
<description>NMI Detection Set</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>96</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-95</dimIndex>
|
|
<name>IELSR%s</name>
|
|
<description>INT Event Link Setting Register %s</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCE</name>
|
|
<description>DTC Activation Enable</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DTC activation is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DTC activation is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IR</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt request is generated ( "1" write to the IR bit is prohibited. )</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IELS</name>
|
|
<description>Event selection to NVIC</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x000</name>
|
|
<description>Nothing is selected</description>
|
|
<value>0x000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>See Event Table</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DELSR%s</name>
|
|
<description>DMAC Event Link Setting Register %s</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IR</name>
|
|
<description>Interrupt Status Flag for DMAC</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt request is generated ( "1" write to the IR bit is prohibited. )</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DELS</name>
|
|
<description>DMAC Event Link Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x000</name>
|
|
<description>Nothing is selected.</description>
|
|
<value>0x000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>See Event Table</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SELSR0</name>
|
|
<description>SYS Event Link Setting Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SELS</name>
|
|
<description>SYS Event Link Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000000</name>
|
|
<description>Disable event output to the associated low-power mode module</description>
|
|
<value>#000000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Event signal number to be linked.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WUPEN</name>
|
|
<description>Wake Up interrupt enable register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IIC0WUPEN</name>
|
|
<description>IIC0 address match interrupt S/W standby returns enable bit</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IIC0 address match interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IIC0 address match interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AGT1CBWUPEN</name>
|
|
<description>AGT1 compare match B interrupt S/W standby returns enable bit</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by AGT1 compare match B interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by AGT1 compare match B interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AGT1CAWUPEN</name>
|
|
<description>AGT1 compare match A interrupt S/W standby returns enable bit</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by AGT1 compare match A interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by AGT1 compare match A interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AGT1UDWUPEN</name>
|
|
<description>AGT1 underflow interrupt S/W standby returns enable bit</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by AGT1 underflow interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by AGT1 underflow interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBFSWUPEN</name>
|
|
<description>USBFS interrupt S/W standby returns enable bit</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by USBFS interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by USBFS interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBHSWUPEN</name>
|
|
<description>USBHS interrupt S/W standby returns enable bit</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by USBHS interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by USBHS interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCPRDWUPEN</name>
|
|
<description>RCT period interrupt S/W standby returns enable bit</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by RTC period interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by RTC period interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCALMWUPEN</name>
|
|
<description>RTC alarm interrupt S/W standby returns enable bit</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by RTC alarm interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by RTC alarm interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMPHS0WUPEN</name>
|
|
<description>ACMPHS0 interrupt S/W standby returns enable bit</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by ACMPHS0 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by ACMPHS0 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD2WUPEN</name>
|
|
<description>LVD2 interrupt S/W standby returns enable bit</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by LVD2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by LVD2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVD1WUPEN</name>
|
|
<description>LVD1 interrupt S/W standby returns enable bit</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by LVD1 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by LVD1 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYWUPEN</name>
|
|
<description>Key interrupt S/W standby returns enable bit</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by KEY interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by KEY interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IWDTWUPEN</name>
|
|
<description>IWDT interrupt S/W standby returns enable bit</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IWDT interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IWDT interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN15</name>
|
|
<description>IRQ15 interrupt S/W standby returns enable bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ15 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ15 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN14</name>
|
|
<description>IRQ14 interrupt S/W standby returns enable bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ14 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ14 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN13</name>
|
|
<description>IRQ13 interrupt S/W standby returns enable bit</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ13 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ13 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN12</name>
|
|
<description>IRQ12 interrupt S/W standby returns enable bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ12 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ12 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN11</name>
|
|
<description>IRQ11 interrupt S/W standby returns enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ11 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ11 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN10</name>
|
|
<description>IRQ10 interrupt S/W standby returns enable bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ10 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ10 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN9</name>
|
|
<description>IRQ9 interrupt S/W standby returns enable bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ9 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ9 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN8</name>
|
|
<description>IRQ8 interrupt S/W standby returns enable bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ8 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ8 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN7</name>
|
|
<description>IRQ7 interrupt S/W standby returns enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ7 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ7 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN6</name>
|
|
<description>IRQ6 interrupt S/W standby returns enable bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ6 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ6 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN5</name>
|
|
<description>IRQ5 interrupt S/W standby returns enable bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ5 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ5 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN4</name>
|
|
<description>IRQ4 interrupt S/W standby returns enable bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ4 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ4 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN3</name>
|
|
<description>IRQ3 interrupt S/W standby returns enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ3 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ3 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN2</name>
|
|
<description>IRQ2 interrupt S/W standby returns enable bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN1</name>
|
|
<description>IRQ1 interrupt S/W standby returns enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ1 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ1 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQWUPEN0</name>
|
|
<description>IRQ0 interrupt S/W standby returns enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>S/W standby returns by IRQ0 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>S/W standby returns by IRQ0 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SRAM</name>
|
|
<description>SRAM Control</description>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD4</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xD8</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PARIOAD</name>
|
|
<description>SRAM Parity Error Operation After Detection Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Operation after Detection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMPRCR</name>
|
|
<description>SRAM Protection Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KW</name>
|
|
<description>Write Key Code</description>
|
|
<lsb>1</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1111000</name>
|
|
<description>Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b.</description>
|
|
<value>#1111000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the RAMPRCR bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAMPRCR</name>
|
|
<description>Register Write Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable writes to protected registers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable writes to protected registers</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMWTSC</name>
|
|
<description>RAM Wait State Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0E</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRAM1WTEN</name>
|
|
<description>SRAM1 Wait Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not add wait state in read access cycle to SRAM1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add wait state in read access cycle to SRAM1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM0WTEN</name>
|
|
<description>SRAM0 Wait Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not add wait state in read access cycle to SRAM0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add wait state in read access cycle to SRAM0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECCRAMRDWTEN</name>
|
|
<description>ECCRAM Read wait enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not add wait state in read access cycle to SRAM0 (ECC area)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Add wait state in read access cycle to SRAM0 (ECC area)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCMODE</name>
|
|
<description>ECCRAM Operating Mode Control Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ECCMOD</name>
|
|
<description>ECC Operating Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Disable ECC function</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Enable ECC function without error checking</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Enable ECC function with error checking.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECC2STS</name>
|
|
<description>ECCRAM 2-Bit Error Status Register</description>
|
|
<addressOffset>0xC1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ECC2ERR</name>
|
|
<description>ECC 2-Bit Error Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No 2-bit ECC error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>2-bit ECC error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECC1STSEN</name>
|
|
<description>ECCRAM 1-Bit Error Information Update Enable Register</description>
|
|
<addressOffset>0xC2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E1STSEN</name>
|
|
<description>ECC 1-Bit Error Information Update Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables updating of the 1-bit ECC error information.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables updating of the 1-bit ECC error information.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECC1STS</name>
|
|
<description>ECCRAM 1-Bit Error Status Register</description>
|
|
<addressOffset>0xC3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ECC1ERR</name>
|
|
<description>ECC 1-Bit Error Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No 1-bit ECC error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1-bit ECC error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCPRCR</name>
|
|
<description>ECCRAM Protection Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KW</name>
|
|
<description>Write Key Code</description>
|
|
<lsb>1</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1111000</name>
|
|
<description>Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b.</description>
|
|
<value>#1111000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the ECCRAMPRCR bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECCPRCR</name>
|
|
<description>ECCRAMETST Register Write Control</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable writes to protected registers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable writes to protected registers</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCETST</name>
|
|
<description>ECC Test Control Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTBYP</name>
|
|
<description>ECC Bypass Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ECC bypass disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ECC bypass enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCOAD</name>
|
|
<description>RAM ECC Error Operation After Detection Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OAD</name>
|
|
<description>Operation after Detection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non maskable interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPT_ODC</name>
|
|
<description>PWM Delay Generation Circuit</description>
|
|
<baseAddress>0x4007B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1A</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2A</offset>
|
|
<size>16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>GTDLYCR</name>
|
|
<description>PWM Output Delay Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLYRST</name>
|
|
<description>PWM Delay Generation Circuit Reset</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLLEN</name>
|
|
<description>DLL Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DLL operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DLL operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTDLYCR2</name>
|
|
<description>PWM Output Delay Control Register2</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLYEN3</name>
|
|
<description>PWM Delay Generation Circuit enable for channel 3</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable delay generation circuit of channel 3</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable delay generation circuit of channel 3</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYEN2</name>
|
|
<description>PWM Delay Generation Circuit enable for channel 2</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable delay generation circuit of channel 2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable delay generation circuit of channel 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYEN1</name>
|
|
<description>PWM Delay Generation Circuit enable for channel 1</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable delay generation circuit of channel 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable delay generation circuit of channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYEN0</name>
|
|
<description>PWM Delay Generation Circuit enable for channel 0</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable delay generation circuit of channel 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable delay generation circuit of channel 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS3</name>
|
|
<description>PWM Delay Generation Circuit bypass for channel 3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass delay generation circuit of channel 3</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Do not bypass delay generation circuit of channel 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS2</name>
|
|
<description>PWM Delay Generation Circuit bypass for channel 2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass delay generation circuit of channel 2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Do not bypass delay generation circuit of channel 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS1</name>
|
|
<description>PWM Delay Generation Circuit bypass for channel 1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass delay generation circuit of channel 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Do not bypass delay generation circuit of channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYBS0</name>
|
|
<description>PWM Delay Generation Circuit bypass for channel 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass delay generation circuit of channel 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Do not bypass delay generation circuit of channel 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GTDLYR%sA</name>
|
|
<description>GTIOC%sA Rising Output Delay Register</description>
|
|
<alternateRegister>GTDLYR%s</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>GTIOCnA Output Rising Edge Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>No delay on rising edges</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Delay of DLY/32 times the PCLKD period is applied.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GTDLYR%sB</name>
|
|
<description>GTIOC%sB Rising Output Delay Register</description>
|
|
<alternateRegister>GTDLYR%s</alternateRegister>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>GTIOCnB Output Rising Edge Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>No delay on rising edges</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Delay of DLY/32 times the PCLKD period is applied.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GTDLYF%sA</name>
|
|
<description>GTIOC%sA Falling Output Delay Register</description>
|
|
<alternateRegister>GTDLYF%s</alternateRegister>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>GTIOCnA Output Falling Edge Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>No delay on rising edges</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Delay of DLY/32 times the PCLKD period is applied.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GTDLYF%sB</name>
|
|
<description>GTIOC%sB Falling Output Delay Register</description>
|
|
<alternateRegister>GTDLYF%s</alternateRegister>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>GTIOCnB Output Falling Edge Delay Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>No delay on rising edges</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Delay of DLY/32 times the PCLKD period is applied.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AGT0</name>
|
|
<description>Asynchronous General purpose Timer 0</description>
|
|
<baseAddress>0x40084000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>AGT</name>
|
|
<description>AGT Counter Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AGT</name>
|
|
<description>16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTCMA</name>
|
|
<description>AGT Compare Match A Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AGTCMA</name>
|
|
<description>AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTCMB</name>
|
|
<description>AGT Compare Match B Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AGTCMB</name>
|
|
<description>AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTCR</name>
|
|
<description>AGT Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCMBF</name>
|
|
<description>AGT compare match B flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Match</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCMAF</name>
|
|
<description>AGT compare match A flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Match</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUNDF</name>
|
|
<description>AGT underflow flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underflow</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underflow</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEDGF</name>
|
|
<description>Active edge judgement flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge received</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active edge received</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTOP</name>
|
|
<description>AGT count forced stop</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The count is forcibly stopped.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCSTF</name>
|
|
<description>AGT count status flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count starts</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTART</name>
|
|
<description>AGT count start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count stops</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count starts</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTMR1</name>
|
|
<description>AGT Mode Register 1</description>
|
|
<addressOffset>0x09</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCK</name>
|
|
<description>AGT count source select</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCLKB</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCLKB/8</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCLKB/2</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divided clock LOCO specified by AGTMR2.CKS bit.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Underflow event signal from AGT</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divided clock fSUB specified by AGTMR2.CKS bit.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEDGPL</name>
|
|
<description>AGTIO edge polarity select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Both edges</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMOD</name>
|
|
<description>AGT operating mode select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Timer mode</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Pulse output mode</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Event counter mode</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Pulse width measurement mode</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Pulse period measurement mode</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTMR2</name>
|
|
<description>AGT Mode Register 2</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPM</name>
|
|
<description>AGT Low Power Mode</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low Power mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>fsub/LOCO count source clock frequency division ratio select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1/1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>1/4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>1/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>1/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>1/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>1/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>1/128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTIOC</name>
|
|
<description>AGT I/O Control Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIOGT</name>
|
|
<description>AGTIO count control</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Event is always counted</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Event is counted during polarity period specified for AGTEE</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIPF</name>
|
|
<description>AGTIO input filter select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Filter sampled at PCLKB</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Filter sampled at PCLKB/8</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Filter sampled at PCLKB/32</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOE</name>
|
|
<description>AGTO output enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AGTO output disabled (port) </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AGTO output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEDGSEL</name>
|
|
<description>I/O polarity switchFunction varies depending on the operating mode. </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTISR</name>
|
|
<description>AGT Event Pin Select Register</description>
|
|
<addressOffset>0x0D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEPS</name>
|
|
<description>AGTEE polarty selection</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An event is counted during the low-level period</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An event is counted during the high-level period</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTCMSR</name>
|
|
<description>AGT Compare Match Function Select Register</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPOLB</name>
|
|
<description>AGTOB polarity select</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AGTOB Output is started at low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AGTOB Output is started at high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOEB</name>
|
|
<description>AGTOB output enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AGTOB output disabled (port)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AGTOB output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCMEB</name>
|
|
<description>Compare match B register enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare match B register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare match B register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOPOLA</name>
|
|
<description>AGTOA polarity select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AGTOA Output is started at low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AGTOA Output is started at high</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOEA</name>
|
|
<description>AGTOA output enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>AGTOA output disabled (port)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AGTOA output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCMEA</name>
|
|
<description>Compare match A register enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable compare match A register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable compare match A register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AGTIOSEL</name>
|
|
<description>AGT Pin Select Register</description>
|
|
<addressOffset>0x0F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIES</name>
|
|
<description>AGTIO input enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>external event input disable during software standby mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>external event input enable during software standby mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>AGTIO pin select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>AGTIO_A can not be used as AGTIO input pin in deep software standby mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="AGT0">
|
|
<name>AGT1</name>
|
|
<description>Asynchronous General purpose Timer 1</description>
|
|
<baseAddress>0x40084100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FCACHE</name>
|
|
<description>Flash Cache</description>
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x32</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x104</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x11C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x120</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x124</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x127</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x130</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x138</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FCACHEE</name>
|
|
<description>Flash Cache Enable Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCACHEEN</name>
|
|
<description>FCACHE Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FCACHE is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FCACHE is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCACHEIV</name>
|
|
<description>Flash Cache Invalidate Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCACHEIV</name>
|
|
<description>FCACHE Invalidation</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>(Read)not in progress / (Write) no effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>(Read)in progress /(Write) Starting Cache Invalidation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLWT</name>
|
|
<description>Flash Wait Cycle Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLWT</name>
|
|
<description>Flash Wait Cycle</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>0 wait (ICLK<=80MHz)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 wait (80MHz < ICLK <=160MHz)</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 waits (160MHz < ICLK <=240MHz)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>BUS</name>
|
|
<description>BUS Control</description>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x802</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x812</offset>
|
|
<size>112</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80A</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x880</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>128</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC00</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC10</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC14</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC20</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC24</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC40</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC44</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC50</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1800</offset>
|
|
<size>176</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1804</offset>
|
|
<size>176</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1000</offset>
|
|
<size>10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100C</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1010</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1100</offset>
|
|
<size>10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x110C</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1128</offset>
|
|
<size>24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CS0CR</name>
|
|
<description>CS0 Control Register</description>
|
|
<addressOffset>0x0802</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0021</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPXEN</name>
|
|
<description>Address/Data Multiplexed I/O Interface Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Separate bus interface is selected for area n</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMODE</name>
|
|
<description>Endian Mode</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little Endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big Endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSIZE</name>
|
|
<description>External Bus Width Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>A 16-bit bus space</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>An 8-bit bus space</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXENB</name>
|
|
<description>Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-7</dimIndex>
|
|
<name>CS%sCR</name>
|
|
<description>CS%s Control Register</description>
|
|
<addressOffset>0x0812</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPXEN</name>
|
|
<description>Address/Data Multiplexed I/O Interface Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Separate bus interface is selected for area n</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMODE</name>
|
|
<description>Endian Mode</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little Endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big Endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BSIZE</name>
|
|
<description>External Bus Width Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>A 16-bit bus space</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>An 8-bit bus space</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXENB</name>
|
|
<description>Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CS%sREC</name>
|
|
<description>CS%s Recovery Cycle Register</description>
|
|
<addressOffset>0x080A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRCV</name>
|
|
<description>Write Recovery</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No recovery cycle is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>WRCV recovery cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRCV</name>
|
|
<description>Read Recovery</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No recovery cycle is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>RRCV recovery cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSRECEN</name>
|
|
<description>CS Recovery Cycle Insertion Enable Register</description>
|
|
<addressOffset>0x0880</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3E3E</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCVENM7</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 7</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM6</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 6</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM5</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 5</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM4</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 4</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM3</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 3</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM2</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 2</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM1</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 1</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVENM0</name>
|
|
<description>Multiplexed Bus Recovery Cycle Insertion Enable 0</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN7</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN6</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN5</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN4</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN3</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN2</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN1</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCVEN0</name>
|
|
<description>Separate Bus Recovery Cycle Insertion Enable 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Recovery cycle insertion is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Recovery cycle insertion is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CS%sMOD</name>
|
|
<description>CS%s Mode Register</description>
|
|
<addressOffset>0x0002</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRMOD</name>
|
|
<description>Page Read Access Mode Select</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal access compatible mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>External data read continuous assertion mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWENB</name>
|
|
<description>Page Write Access Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRENB</name>
|
|
<description>Page Read Access Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWENB</name>
|
|
<description>External Wait Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRMOD</name>
|
|
<description>Write Access Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Byte strobe mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single write strobe mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CS%sWCR1</name>
|
|
<description>CS%s Wait Control Register 1</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x07070707</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSRWAIT</name>
|
|
<description>Normal Read Cycle Wait Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x00</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSRWAIT clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWWAIT</name>
|
|
<description>Normal Write Cycle Wait Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x00</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSWWAIT clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSPRWAIT</name>
|
|
<description>Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSPRWAIT clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSPWWAIT</name>
|
|
<description>Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSPWWAIT clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CS%sWCR2</name>
|
|
<description>CS%s Wait Control Register 2</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSON</name>
|
|
<description>CS Assert Wait Select</description>
|
|
<lsb>28</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSON clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDON</name>
|
|
<description>Write Data Output Wait Select</description>
|
|
<lsb>24</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of WDON clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRON</name>
|
|
<description>WR Assert Wait Select</description>
|
|
<lsb>20</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of WRON clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDON</name>
|
|
<description>RD Assert Wait Select</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of RDON clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AWAIT</name>
|
|
<description>Address Cycle Wait Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of AWAIT clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOFF</name>
|
|
<description>Write Data Output Extension Cycle Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of WDOFF clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWOFF</name>
|
|
<description>Write-Access CS Extension Cycle Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSWOFF clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSROFF</name>
|
|
<description>Read-Access CS Extension Cycle Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>No wait is inserted.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Wait with a length of CSROFF clock cycle is inserted.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCCR</name>
|
|
<description>SDC Control Register</description>
|
|
<addressOffset>0x0C00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSIZE</name>
|
|
<description>SDRAM Bus Width Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>A 16-bit bus space</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>An 8-bit bus space</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXENB</name>
|
|
<description>Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCMOD</name>
|
|
<description>SDC Mode Register</description>
|
|
<addressOffset>0x0C01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMODE</name>
|
|
<description>Endian Mode</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Endian order of SDRAM address space is the same as the endian order of the operating mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Endian order of SDRAM address space is not the endian order of the operating mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDAMOD</name>
|
|
<description>SDRAM Access Mode Register</description>
|
|
<addressOffset>0x0C02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>Continuous Access Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDSELF</name>
|
|
<description>SDRAM Self-Refresh Control Register</description>
|
|
<addressOffset>0x0C10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFEN</name>
|
|
<description>SDRAM Self-Refresh Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDRFCR</name>
|
|
<description>SDRAM Refresh Control Register</description>
|
|
<addressOffset>0x0C14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFW</name>
|
|
<description>Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) </description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFC</name>
|
|
<description>Auto-Refresh Request Interval Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>RFC+1 cycles inserted</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDRFEN</name>
|
|
<description>SDRAM Auto-Refresh Control Register</description>
|
|
<addressOffset>0x0C16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFEN</name>
|
|
<description>Auto-Refresh Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDICR</name>
|
|
<description>SDRAM Initialization Sequence Control Register</description>
|
|
<addressOffset>0x0C20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIRQ</name>
|
|
<description>Initialization Sequence Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization sequence starts</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIR</name>
|
|
<description>SDRAM Initialization Register</description>
|
|
<addressOffset>0x0C24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0010</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRC</name>
|
|
<description>Initialization Precharge Cycle Count (PRC+3 cycles)</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARFC</name>
|
|
<description>Initialization Auto-Refresh Count</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x0</name>
|
|
<description>Setting prohibited</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>ARFC times</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARFI</name>
|
|
<description>Initialization Auto-Refresh Interval (ARFI+3 cycles )</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDADR</name>
|
|
<description>SDRAM Address Register</description>
|
|
<addressOffset>0x0C40</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MXC</name>
|
|
<description>Address Multiplex Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit shift</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>9-bit shift</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>10-bit shift</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>11-bit shift</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDTR</name>
|
|
<description>SDRAM Timing Register</description>
|
|
<addressOffset>0x0C44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAS</name>
|
|
<description>Row Active Interval</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 cycle</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 cycles</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 cycles</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 cycles</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 cycles</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 cycles</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 cycles</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCD</name>
|
|
<description>Row Column Latency ( RCD+1 cycles )</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Row Precharge Interval ( RP+1 cycles )</description>
|
|
<lsb>9</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WR</name>
|
|
<description>Write Recovery Interval</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>1 cycle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>2 cycles</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL</name>
|
|
<description>SDRAMC Column Latency</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 cycle</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 cycles</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 cycles</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDMOD</name>
|
|
<description>SDRAM Mode Register</description>
|
|
<addressOffset>0x0C48</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR</name>
|
|
<description>Mode Register SettingWriting to these bits: Mode register set command is issued.</description>
|
|
<lsb>0</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDSR</name>
|
|
<description>SDRAM Status Register</description>
|
|
<addressOffset>0x0C50</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRFST</name>
|
|
<description>Self-Refresh Transition/Recovery Status</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transition/recovery not in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transition/recovery in progress</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIST</name>
|
|
<description>Initialization Status</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Initialization sequence not in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization sequence in progress</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MRSST</name>
|
|
<description>Mode Register Setting Status</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mode register setting not in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode register setting in progress</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>11</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-11</dimIndex>
|
|
<name>BUS%sERRADD</name>
|
|
<description>Bus Error Address Register %s</description>
|
|
<addressOffset>0x1800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BERAD</name>
|
|
<description>Bus Error AddressWhen a bus error occurs, It stores an error address.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>11</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>1-11</dimIndex>
|
|
<name>BUS%sERRSTAT</name>
|
|
<description>Bus Error Status Register %s</description>
|
|
<addressOffset>0x1804</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERRSTAT</name>
|
|
<description>Bus Error StatusWhen bus error assert, error flag occurs.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCSTAT</name>
|
|
<description>Error access statusThe status at the time of the error</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read access</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write Access</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>M4I,M4D</dimIndex>
|
|
<name>BUSMCNT%s</name>
|
|
<description>Master Bus Control Register %s</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IERES</name>
|
|
<description>Ignore Error Responses</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus error will be reported.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error will not be reported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSMCNTSYS</name>
|
|
<description>Master Bus Control Register SYS</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IERES</name>
|
|
<description>Ignore Error Responses</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus error will be reported.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error will not be reported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSMCNTDMA</name>
|
|
<description>Master Bus Control Register DMA</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IERES</name>
|
|
<description>Ignore Error Responses</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus error will be reported.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error will not be reported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>EDM,GPX</dimIndex>
|
|
<name>BUSMCNT%s</name>
|
|
<description>Master Bus Control Register %s</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IERES</name>
|
|
<description>Ignore Error Responses</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus error will be reported.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error will not be reported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>FLI,RAMH</dimIndex>
|
|
<name>BUSSCNT%s</name>
|
|
<description>Slave Bus Control Register %s</description>
|
|
<addressOffset>0x1100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSSCNTMBIU</name>
|
|
<description>Slave Bus Control Register MBIU</description>
|
|
<addressOffset>0x1108</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>RAM0,RAM1</dimIndex>
|
|
<name>BUSSCNT%s</name>
|
|
<description>Slave Bus Control Register %s</description>
|
|
<addressOffset>0x110C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>P0B,P2B,P3B,P4B</dimIndex>
|
|
<name>BUSSCNT%s</name>
|
|
<description>Slave Bus Control Register %s</description>
|
|
<addressOffset>0x1114</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>P6B,P7B</dimIndex>
|
|
<name>BUSSCNT%s</name>
|
|
<description>Slave Bus Control Register %s</description>
|
|
<addressOffset>0x1128</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>FBU,EXT,EXT2,GPX</dimIndex>
|
|
<name>BUSSCNT%s</name>
|
|
<description>Slave Bus Control Register %s</description>
|
|
<addressOffset>0x1130</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWRES</name>
|
|
<description>Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not accepted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accepted but error response is ignored. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBMET</name>
|
|
<description>Arbitration MethodSpecify the priority between groups</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>fixed priority</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>round-robin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC12</name>
|
|
<description>12-bit D/A converter</description>
|
|
<baseAddress>0x4005E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>7</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x101C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>DADR%s</name>
|
|
<description>D/A Data Register %s</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADR</name>
|
|
<description>D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACR</name>
|
|
<description>D/A Control Register </description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAOE1</name>
|
|
<description>D/A Output Enable 1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog output of channel 1 (DA1) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAOE0</name>
|
|
<description>D/A Output Enable 0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog output of channel 0 (DA0) is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAE</name>
|
|
<description>D/A Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D/A conversion is independently controlled on channels 0 and 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D/A conversion on channels 0 and 1 is controlled as a single whole.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DADPR</name>
|
|
<description>DADRm Format Select Register </description>
|
|
<addressOffset>0x0005</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPSEL</name>
|
|
<description>DADRm Format Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Right justified format.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Left justified format.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAADSCR</name>
|
|
<description>D/A-A/D Synchronous Start Control Register </description>
|
|
<addressOffset>0x0006</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAADST</name>
|
|
<description>D/A-A/D Synchronous Conversion</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAAMPCR</name>
|
|
<description>D/A Output Amplifier Control Register </description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAAMP1</name>
|
|
<description>Amplifier Control 1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output amplifier of channel 1 is not used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output amplifier of channel 1 is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAAMP0</name>
|
|
<description>Amplifier Control 0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output amplifier of channel 0 is not used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output amplifier of channel 0 is used.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAASWCR</name>
|
|
<description>D/A Amplifier Stabilization Wait Control Register</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAASW1</name>
|
|
<description>D/A Amplifier Stabilization Wait 1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Amplifier stabilization wait off (output) for channel 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Amplifier stabilization wait on (high-Z) for channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAASW0</name>
|
|
<description>D/A Amplifier Stabilization Wait 0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Amplifier stabilization wait off (output) for channel 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Amplifier stabilization wait on (high-Z) for channel 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AMI</name>
|
|
<description>ADC-DAC Interface</description>
|
|
<baseAddress>0x4005F000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DAADUSR</name>
|
|
<description>D/A A/D Synchronous Unit Select Register </description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMADSEL1</name>
|
|
<description>A/D Unit 1 Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Unit 1 is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Unit 1 is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>POEG</name>
|
|
<description>Port Output Enable Module for GPT</description>
|
|
<baseAddress>0x40042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1024</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x100</dimIncrement>
|
|
<dimIndex>A,B,C,D</dimIndex>
|
|
<name>POEGG%s</name>
|
|
<description>POEG Group %s Setting Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NFCS</name>
|
|
<description>Noise Filter Clock Select</description>
|
|
<lsb>30</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Sampling GTETRG pin input level for three times in every PCLKB. </description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Sampling GTETRG pin input level for three times in every PCLKB /8.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Sampling GTETRG pin input level for three times in every PCLKB /32.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Sampling GTETRG pin input level for three times in every PCLKB /128. </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NFEN</name>
|
|
<description>Noise Filter Enable</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Filtering noise disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Filtering noise enabled </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>GTETRG Input Reverse</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTETRG Input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTETRG Input Reversed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>GTETRG Input Status Flag</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>GTETRG input after filtering is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>GTETRG input after filtering is 1. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE5</name>
|
|
<description>Comparator Disable Request Enable 5Note: Can be modified only once after a reset.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 5 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 5 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE4</name>
|
|
<description>Comparator Disable Request Enable 4Note: Can be modified only once after a reset.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 4 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 4 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE3</name>
|
|
<description>Comparator Disable Request Enable 3Note: Can be modified only once after a reset.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 3 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 3 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE2</name>
|
|
<description>Comparator Disable Request Enable 2Note: Can be modified only once after a reset.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 2 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 2 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE1</name>
|
|
<description>Comparator Disable Request Enable 1Note: Can be modified only once after a reset.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 1 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 1 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDRE0</name>
|
|
<description>Comparator Disable Request Enable 0Note: Can be modified only once after a reset.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A disable request of comparator 0 disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A disable request of comparator 0 enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTPE</name>
|
|
<description>Oscillation Stop Detection EnableNote: Can be modified only once after a reset.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from the oscillation stop detection disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from the oscillation stop detection enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOCE</name>
|
|
<description>Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable output-disable requests from GPT disable request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable output-disable requests from GPT disable request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDE</name>
|
|
<description>Port Input Detection EnableNote: Can be modified only once after a reset.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from the GTETRG pins disabled. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from the GTETRG pins enabled. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSF</name>
|
|
<description>Software Stop Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from software has not been generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from software has been generated. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTPF</name>
|
|
<description>Oscillation Stop Detection Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from the oscillation stop detection has not been generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from the oscillation stop detection has been generated. </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOCF</name>
|
|
<description>Real Time Overcurrent Detection Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from GPT disable request or comparator interrupt has not been generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from GPT disable request or comparator interrupt has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIDF</name>
|
|
<description>Port Input Detection Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A output-disable request from the GTETRG pin has not been generated. </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A output-disable request from the GTETRG pin has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IRDA</name>
|
|
<description>Infrared Data Association</description>
|
|
<baseAddress>0x40070F00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IRCR</name>
|
|
<description>IrDA Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRE</name>
|
|
<description>IrDA Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial I/O pins are used for normal serial communication.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Serial I/O pins are used for IrDA data communication.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRTXINV</name>
|
|
<description>IRTXD Polarity Switching </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data to be transmitted is output to IRTXD as is.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data to be transmitted is output to IRTXD after the polarity is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRRXINV</name>
|
|
<description>IRRXD Polarity Switching</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IRRXD input is used as received data as is.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRRXD input is used as received data after the polarity is inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN0</name>
|
|
<description>CAN0 Module </description>
|
|
<baseAddress>0x40050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x200</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x204</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x206</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x207</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x208</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x209</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20A</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20B</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20C</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20D</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20E</offset>
|
|
<size>512</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x400</offset>
|
|
<size>48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x42C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x820</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x820</offset>
|
|
<size>57</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_ID</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDE</name>
|
|
<description>ID Extension</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard ID</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended ID</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SID</name>
|
|
<description>Standard ID </description>
|
|
<lsb>18</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EID</name>
|
|
<description>Extended ID</description>
|
|
<lsb>0</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_DL</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLC</name>
|
|
<description>Data Length Code</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Data length = 0 byte</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Data length = 1 byte</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Data length = 2 bytes</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Data length = 3 bytes</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Data length = 4 bytes</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Data length = 5 bytes</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Data length = 6 bytes</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Data length = 7 bytes</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Data length = 8 bytes</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D0</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x206</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D1</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x207</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D2</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D3</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x209</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D4</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x20A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D5</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x20B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D6</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_D7</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x20D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MB%s_TS</name>
|
|
<description>Mailbox Register </description>
|
|
<addressOffset>0x20E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSH</name>
|
|
<description>Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSL</name>
|
|
<description>Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MKR[%s]</name>
|
|
<description>Mask Register </description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SID</name>
|
|
<description>Standard ID </description>
|
|
<lsb>18</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EID</name>
|
|
<description>Extended ID</description>
|
|
<lsb>0</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>FIDCR%s</name>
|
|
<description>FIFO Received ID Compare Registers </description>
|
|
<addressOffset>0x420</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDE</name>
|
|
<description>ID Extension</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard ID</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended ID</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SID</name>
|
|
<description>Standard ID </description>
|
|
<lsb>18</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EID</name>
|
|
<description>Extended ID</description>
|
|
<lsb>0</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MKIVLR</name>
|
|
<description>Mask Invalid Register </description>
|
|
<addressOffset>0x428</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MB31</name>
|
|
<description>mailbox 31 Mask Invalid </description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB30</name>
|
|
<description>mailbox 30 Mask Invalid </description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB29</name>
|
|
<description>mailbox 29 Mask Invalid</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB28</name>
|
|
<description>mailbox 28 Mask Invalid</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB27</name>
|
|
<description>mailbox 27 Mask Invalid</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB26</name>
|
|
<description>mailbox 26 Mask Invalid </description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB25</name>
|
|
<description>mailbox 25 Mask Invalid </description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB24</name>
|
|
<description>mailbox 24 Mask Invalid </description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB23</name>
|
|
<description>mailbox 23 Mask Invalid </description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB22</name>
|
|
<description>mailbox 22 Mask Invalid </description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB21</name>
|
|
<description>mailbox 21 Mask Invalid </description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB20</name>
|
|
<description>mailbox 20 Mask Invalid </description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB19</name>
|
|
<description>mailbox 19 Mask Invalid </description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB18</name>
|
|
<description>mailbox 18 Mask Invalid </description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB17</name>
|
|
<description>mailbox 17 Mask Invalid </description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB16</name>
|
|
<description>mailbox 16 Mask Invalid </description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB15</name>
|
|
<description>mailbox 15 Mask Invalid </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB14</name>
|
|
<description>mailbox 14 Mask Invalid </description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB13</name>
|
|
<description>mailbox 13 Mask Invalid </description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB12</name>
|
|
<description>mailbox 12 Mask Invalid </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB11</name>
|
|
<description>mailbox 11 Mask Invalid </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB10</name>
|
|
<description>mailbox 10 Mask Invalid </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB9</name>
|
|
<description>mailbox 9 Mask Invalid </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB8</name>
|
|
<description>mailbox 8 Mask Invalid </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB7</name>
|
|
<description>mailbox 7 Mask Invalid </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB6</name>
|
|
<description>mailbox 6 Mask Invalid </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB5</name>
|
|
<description>mailbox 5 Mask Invalid </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB4</name>
|
|
<description>mailbox 4 Mask Invalid </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB3</name>
|
|
<description>mailbox 3 Mask Invalid </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB2</name>
|
|
<description>mailbox 2 Mask Invalid </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB1</name>
|
|
<description>mailbox 1 Mask Invalid </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB0</name>
|
|
<description>mailbox 0 Mask Invalid </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask invalid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER</name>
|
|
<description>Mailbox Interrupt Enable Register</description>
|
|
<addressOffset>0x42C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MB31</name>
|
|
<description>mailbox 31 Interrupt Enable </description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB30</name>
|
|
<description>mailbox 30 Interrupt Enable </description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB29</name>
|
|
<description>mailbox 29 Interrupt Enable </description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB28</name>
|
|
<description>mailbox 28 Interrupt Enable </description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB27</name>
|
|
<description>mailbox 27 Interrupt Enable </description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB26</name>
|
|
<description>mailbox 26 Interrupt Enable </description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB25</name>
|
|
<description>mailbox 25 Interrupt Enable </description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB24</name>
|
|
<description>mailbox 24 Interrupt Enable </description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB23</name>
|
|
<description>mailbox 23 Interrupt Enable </description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB22</name>
|
|
<description>mailbox 22 Interrupt Enable </description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB21</name>
|
|
<description>mailbox 21 Interrupt Enable </description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB20</name>
|
|
<description>mailbox 20 Interrupt Enable </description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB19</name>
|
|
<description>mailbox 19 Interrupt Enable </description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB18</name>
|
|
<description>mailbox 18 Interrupt Enable </description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB17</name>
|
|
<description>mailbox 17 Interrupt Enable </description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB16</name>
|
|
<description>mailbox 16 Interrupt Enable </description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB15</name>
|
|
<description>mailbox 15 Interrupt Enable </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB14</name>
|
|
<description>mailbox 14 Interrupt Enable </description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB13</name>
|
|
<description>mailbox 13 Interrupt Enable </description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB12</name>
|
|
<description>mailbox 12 Interrupt Enable </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB11</name>
|
|
<description>mailbox 11 Interrupt Enable </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB10</name>
|
|
<description>mailbox 10 Interrupt Enable </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB9</name>
|
|
<description>mailbox 9 Interrupt Enable </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB8</name>
|
|
<description>mailbox 8 Interrupt Enable </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB7</name>
|
|
<description>mailbox 7 Interrupt Enable </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB6</name>
|
|
<description>mailbox 6 Interrupt Enable </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB5</name>
|
|
<description>mailbox 5 Interrupt Enable </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB4</name>
|
|
<description>mailbox 4 Interrupt Enable </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB3</name>
|
|
<description>mailbox 3 Interrupt Enable </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB2</name>
|
|
<description>mailbox 2 Interrupt Enable </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB1</name>
|
|
<description>mailbox 1 Interrupt Enable </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB0</name>
|
|
<description>mailbox 0 Interrupt Enable </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER_FIFO</name>
|
|
<description>Mailbox Interrupt Enable Register for FIFO Mailbox Mode</description>
|
|
<alternateRegister>MIER</alternateRegister>
|
|
<addressOffset>0x42C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MB29</name>
|
|
<description>Receive FIFO Interrupt Generation Timing Control</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Every time reception is completed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When the receive FIFO becomes buffer warning by completion of reception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB28</name>
|
|
<description>Receive FIFO Interrupt Enable </description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB25</name>
|
|
<description>Transmit FIFO Interrupt Generation Timing Control</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Every time transmission is completed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When the transmit FIFO becomes empty due to completion of transmission</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB24</name>
|
|
<description>Transmit FIFO Interrupt Enable </description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB23</name>
|
|
<description>mailbox 23 Interrupt Enable </description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB22</name>
|
|
<description>mailbox 22 Interrupt Enable </description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB21</name>
|
|
<description>mailbox 21 Interrupt Enable </description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB20</name>
|
|
<description>mailbox 20 Interrupt Enable </description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB19</name>
|
|
<description>mailbox 19 Interrupt Enable </description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB18</name>
|
|
<description>mailbox 18 Interrupt Enable </description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB17</name>
|
|
<description>mailbox 17 Interrupt Enable </description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB16</name>
|
|
<description>mailbox 16 Interrupt Enable </description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB15</name>
|
|
<description>mailbox 15 Interrupt Enable </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB14</name>
|
|
<description>mailbox 14 Interrupt Enable </description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB13</name>
|
|
<description>mailbox 13 Interrupt Enable </description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB12</name>
|
|
<description>mailbox 12 Interrupt Enable </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB11</name>
|
|
<description>mailbox 11 Interrupt Enable </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB10</name>
|
|
<description>mailbox 10 Interrupt Enable </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB9</name>
|
|
<description>mailbox 9 Interrupt Enable </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB8</name>
|
|
<description>mailbox 8 Interrupt Enable </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB7</name>
|
|
<description>mailbox 7 Interrupt Enable </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB6</name>
|
|
<description>mailbox 6 Interrupt Enable </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB5</name>
|
|
<description>mailbox 5 Interrupt Enable </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB4</name>
|
|
<description>mailbox 4 Interrupt Enable </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB3</name>
|
|
<description>mailbox 3 Interrupt Enable </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB2</name>
|
|
<description>mailbox 2 Interrupt Enable </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB1</name>
|
|
<description>mailbox 1 Interrupt Enable </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MB0</name>
|
|
<description>mailbox 0 Interrupt Enable </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MCTL_TX[%s]</name>
|
|
<description>Message Control Register for Transmit</description>
|
|
<addressOffset>0x820</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRMREQ</name>
|
|
<description>Transmit Mailbox Request</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not configured for transmission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured for transmission</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RECREQ</name>
|
|
<description>Receive Mailbox Request </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not configured for reception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured for reception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One-shot reception or one-shot transmission disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>One-shot reception or one-shot transmission enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRMABT</name>
|
|
<description>Transmission Abort Complete Flag (Transmit mailbox setting enabled)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmission abort is completed </description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRMACTIVE</name>
|
|
<description>Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmission is pending or transmission is not requested</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>From acceptance of transmission request to completion of transmission, or error/arbitration-lost</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SENTDATA</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmission is not completed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmission is completed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>MCTL_RX[%s]</name>
|
|
<description>Message Control Register for Receive</description>
|
|
<alternateRegister>MCTL_TX[%s]</alternateRegister>
|
|
<addressOffset>0x820</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRMREQ</name>
|
|
<description>Transmit Mailbox Request</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not configured for transmission</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured for transmission</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RECREQ</name>
|
|
<description>Receive Mailbox Request </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not configured for reception</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured for reception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOT</name>
|
|
<description>One-Shot Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One-shot reception or one-shot transmission disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>One-shot reception or one-shot transmission enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSGLOST</name>
|
|
<description>Message Lost Flag(Receive mailbox setting enabled)</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Message is not overwritten or overrun</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Message is overwritten or overrun</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVALDATA</name>
|
|
<description>Reception-in-Progress Status Flag (Receive mailbox setting enabled)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Message valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Message being updated</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEWDATA</name>
|
|
<description>Reception Complete Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data has been received or 0 is written to the NEWDATA bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A new message is being stored or has been stored to the mailbox</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTLR</name>
|
|
<description>Control Register </description>
|
|
<addressOffset>0x840</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0500</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBOC</name>
|
|
<description>Forcible Return From Bus-Off</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Nothing occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Forcible return from bus-off</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOM</name>
|
|
<description>Bus-Off Recovery Mode by a program request</description>
|
|
<lsb>11</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal mode (ISO11898-1 compliant)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Entry to CAN halt mode automatically at bus-off entry</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Entry to CAN halt mode automatically at bus-off end</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Entry to CAN halt mode (during bus-off recovery period) </description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLPM</name>
|
|
<description>CAN Sleep Mode</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Other than CAN sleep mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CAN sleep mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CANM</name>
|
|
<description>CAN Operating Mode Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>CAN operation mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CAN reset mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CAN halt mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>CAN reset mode (forcible transition)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSPS</name>
|
|
<description>Time Stamp Prescaler Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Every bit time</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Every 2-bit time</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Every 4-bit time</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Every 8-bit time</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRC</name>
|
|
<description>Time Stamp Counter Reset Command</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Nothing occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPM</name>
|
|
<description>Transmission Priority Mode Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ID priority transmit mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mailbox number priority transmit mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MLM</name>
|
|
<description>Message Lost Mode Select</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Overwrite mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overrun mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDFM</name>
|
|
<description>ID Format Mode Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. </description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Do not use this combination</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBM</name>
|
|
<description>CAN Mailbox Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal mailbox mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO mailbox mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STR</name>
|
|
<description>Status Register </description>
|
|
<addressOffset>0x842</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0500</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECST</name>
|
|
<description>Receive Status Flag (receiver) </description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus idle or transmission in progress </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reception in progress</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRMST</name>
|
|
<description>Transmit Status Flag (transmitter)</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus idle or reception in progress </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmission in progress or in bus-off state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOST</name>
|
|
<description>Bus-Off Status Flag </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in bus-off state </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In bus-off state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPST</name>
|
|
<description>Error-Passive Status Flag</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in error-passive state </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In error-passive state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLPST</name>
|
|
<description>CAN Sleep Status Flag </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in CAN sleep mode </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In CAN sleep mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HLTST</name>
|
|
<description>CAN Halt Status Flag </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in CAN halt mode </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In CAN halt mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTST</name>
|
|
<description>CAN Reset Status Flag </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not in CAN reset mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>In CAN reset mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EST</name>
|
|
<description>Error Status Flag </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TABST</name>
|
|
<description>Transmission Abort Status Flag </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mailbox with TRMABT bit = 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mailbox(es) with TRMABT bit = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMLST</name>
|
|
<description>FIFO Mailbox Message Lost Status Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RFMLF bit = 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RFMLF bit = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMLST</name>
|
|
<description>Normal Mailbox Message Lost Status Flag </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mailbox with MSGLOST bit = 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mailbox(es) with MSGLOST bit = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFST</name>
|
|
<description>Transmit FIFO Status Flag </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is full</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is not full</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFST</name>
|
|
<description>Receive FIFO Status Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No message in receive FIFO (empty)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Message in receive FIFO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDST</name>
|
|
<description>SENTDATA Status Flag </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mailbox with SENTDATA bit = 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mailbox(es) with SENTDATA bit = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDST</name>
|
|
<description>NEWDATA Status Flag </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mailbox with NEWDATA bit = 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mailbox(es) with NEWDATA bit = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR</name>
|
|
<description>Bit Configuration Register </description>
|
|
<addressOffset>0x844</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEG1</name>
|
|
<description>Time Segment 1 Control </description>
|
|
<lsb>28</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>4 Tq</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>5 Tq</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>6 Tq</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>7 Tq</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>8 Tq</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>9 Tq</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>10 Tq</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>11 Tq</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>12 Tq</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>13 Tq</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>14 Tq</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>15 Tq</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>16 Tq</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRP</name>
|
|
<description>Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK).</description>
|
|
<lsb>16</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>Resynchronization Jump Width Control </description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1 Tq</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2 Tq</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3 Tq</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 Tq</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSEG2</name>
|
|
<description>Time Segment 2 Control</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 Tq</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 Tq</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 Tq</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 Tq</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 Tq</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 Tq</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 Tq</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCLKS</name>
|
|
<description>CAN Clock Source Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCLK (generated by the PLL clock)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CANMCLK (generated by the main clock)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFCR</name>
|
|
<description>Receive FIFO Control Register</description>
|
|
<addressOffset>0x848</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFEST</name>
|
|
<description>Receive FIFO Empty Status Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Unread message in receive FIFO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No unread message in receive FIFO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFWST</name>
|
|
<description>Receive FIFO Buffer Warning Status Flag </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not buffer warning</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is buffer warning (3 unread messages)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFFST</name>
|
|
<description>Receive FIFO Full Status Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not full</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is full (4 unread messages)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFMLF</name>
|
|
<description>Receive FIFO Message Lost Flag </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive FIFO message lost has occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO message lost has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFUST</name>
|
|
<description>Receive FIFO Unread Message Number Status </description>
|
|
<lsb>1</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No unread message</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 unread message</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 unread messages</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 unread messages</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 unread messages</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>Receive FIFO Enable </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFPCR</name>
|
|
<description>Receive FIFO Pointer Control Register </description>
|
|
<addressOffset>0x849</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFPCR</name>
|
|
<description>The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFCR</name>
|
|
<description>Transmit FIFO Control Register </description>
|
|
<addressOffset>0x84A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFEST</name>
|
|
<description>Transmit FIFO Empty Status</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Unsent message in transmit FIFO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No unsent message in transmit FIFO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFFST</name>
|
|
<description>Transmit FIFO Full Status </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not full</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is full (4 unsent messages)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFUST</name>
|
|
<description>Transmit FIFO Unsent Message Number Status </description>
|
|
<lsb>1</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>No unsent message</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 unsent message</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 unsent messages</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 unsent messages</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 unsent messages</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Enable </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFPCR</name>
|
|
<description>Transmit FIFO Pointer Control Register </description>
|
|
<addressOffset>0x84B</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFPCR</name>
|
|
<description>The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EIER</name>
|
|
<description>Error Interrupt Enable Register </description>
|
|
<addressOffset>0x84C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BLIE</name>
|
|
<description>Bus Lock Interrupt Enable </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus lock interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus lock interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OLIE</name>
|
|
<description>Overload Frame Transmit Interrupt Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Overload frame transmit interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overload frame transmit interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive overrun interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BORIE</name>
|
|
<description>Bus-Off Recovery Interrupt Enable </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus-off recovery interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus-off recovery interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOEIE</name>
|
|
<description>Bus-Off Entry Interrupt Enable </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus-off entry interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus-off entry interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>Error-Passive Interrupt Enable </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Error-passive interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error-passive interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWIE</name>
|
|
<description>Error-Warning Interrupt Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Error-warning interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error-warning interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>Bus Error Interrupt Enable </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EIFR</name>
|
|
<description>Error Interrupt Factor Judge Register </description>
|
|
<addressOffset>0x84D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BLIF</name>
|
|
<description>Bus Lock Detect Flag </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus lock detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus lock detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OLIF</name>
|
|
<description>Overload Frame Transmission Detect Flag </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overload frame transmission detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Overload frame transmission detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIF</name>
|
|
<description>Receive Overrun Detect Flag </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive overrun detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BORIF</name>
|
|
<description>Bus-Off Recovery Detect Flag </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus-off recovery detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus-off recovery detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOEIF</name>
|
|
<description>Bus-Off Entry Detect Flag </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus-off entry detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus-off entry detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIF</name>
|
|
<description>Error-Passive Detect Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error-passive detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error-passive detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWIF</name>
|
|
<description>Error-Warning Detect Flag </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error-warning detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error-warning detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEIF</name>
|
|
<description>Bus Error Detect Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bus error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RECR</name>
|
|
<description>Receive Error Count Register </description>
|
|
<addressOffset>0x84E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECR</name>
|
|
<description>Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TECR</name>
|
|
<description>Transmit Error Count Register </description>
|
|
<addressOffset>0x84F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TECR</name>
|
|
<description>Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECSR</name>
|
|
<description>Error Code Store Register </description>
|
|
<addressOffset>0x850</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDPM</name>
|
|
<description>Error Display Mode Select</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output of first detected error code</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output of accumulated error code</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEF</name>
|
|
<description>ACK Delimiter Error Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No ACK delimiter error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACK delimiter error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BE0F</name>
|
|
<description>Bit Error (dominant) Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bit error (dominant) detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bit error (dominant) detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BE1F</name>
|
|
<description>Bit Error (recessive) Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No bit error (recessive) detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bit error (recessive) detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEF</name>
|
|
<description>CRC Error Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No CRC error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CRC error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AEF</name>
|
|
<description>ACK Error Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No ACK error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACK error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>Form Error Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No form error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Form error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEF</name>
|
|
<description>Stuff Error Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No stuff error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stuff error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSSR</name>
|
|
<description>Channel Search Support Register </description>
|
|
<addressOffset>0x851</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSSR</name>
|
|
<description>When the value for the channel search is input, the channel number is output to MSSR.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSSR</name>
|
|
<description>Mailbox Search Status Register </description>
|
|
<addressOffset>0x852</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEST</name>
|
|
<description>Search Result Status</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Search result found</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No search result</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBNST</name>
|
|
<description>Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSMR</name>
|
|
<description>Mailbox Search Mode Register </description>
|
|
<addressOffset>0x853</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MBSM</name>
|
|
<description>Mailbox Search Mode Select </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Receive mailbox search mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Transmit mailbox search mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Message lost search mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Channel search mode</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSR</name>
|
|
<description>Time Stamp Register </description>
|
|
<addressOffset>0x854</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSR</name>
|
|
<description>Free-running counter value for the time stamp function</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<description>Acceptance Filter Support Register </description>
|
|
<addressOffset>0x856</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AFSR</name>
|
|
<description>After the standard ID of a received message is written, the value converted for data table search can be read.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Test Control Register </description>
|
|
<addressOffset>0x858</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTM</name>
|
|
<description>CAN Test Mode Select </description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Other than CAN test mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Listen-only mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Self-test mode 0 (external loopback)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Self-test mode 1 (internal loopback)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTE</name>
|
|
<description>CAN Test Mode Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CAN test mode disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CAN test mode enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CAN0">
|
|
<name>CAN1</name>
|
|
<description>CAN1 Module </description>
|
|
<baseAddress>0x40051000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PDC</name>
|
|
<description>Parallel Data Capture Unit</description>
|
|
<baseAddress>0x40094000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCCR0</name>
|
|
<description>PDC Control Register 0</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDS</name>
|
|
<description>Endian Select</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKDIV</name>
|
|
<description>PCKO Frequency Division Ratio Select</description>
|
|
<lsb>11</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>PCKO/2</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>PCKO/4</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>PCKO/6</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>PCKO/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PCKO/10</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PCKO/12</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>PCKO/14</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>PCKO/16</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKOE</name>
|
|
<description>PCKO Output Enable</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCKO output is disabled (fixed to the high level)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCKO output is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HERIE</name>
|
|
<description>Horizontal Byte Number Setting Error Interrupt Enable</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of horizontal byte number setting error interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of horizontal byte number setting error interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VERIE</name>
|
|
<description>Vertical Line Number Setting Error Interrupt Enable</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of vertical line number setting error interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of vertical line number setting error interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDRIE</name>
|
|
<description>Underrun Interrupt Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of underrun interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of underrun interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVIE</name>
|
|
<description>Overrun Interrupt Enable </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of overrun interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of overrun interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Frame End Interrupt Enable</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of frame end interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of frame end interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFIE</name>
|
|
<description>Receive Data Ready Interrupt Enable </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Generation of receive data ready interrupt requests is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generation of receive data ready interrupt requests is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRST</name>
|
|
<description>PDC Reset</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDC reset is not applied.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDC is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPS</name>
|
|
<description>HSYNC Signal Polarity Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>HSYNC signal is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>HSYNC signal is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VPS</name>
|
|
<description>VSYNC Signal Polarity Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VSYNC signal is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VSYNC signal is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCKE</name>
|
|
<description>Channel 0 GTCNT Count Clear</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operations for reception are stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operations for reception are ongoing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCCR1</name>
|
|
<description>PDC Control Register 1 </description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>PDC Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operations for reception are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operations for reception are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSR</name>
|
|
<description>PDC Status Register </description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HERF</name>
|
|
<description>Horizontal Byte Number Setting Error Flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Horizontal byte number setting error has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Horizontal byte number setting error has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VERF</name>
|
|
<description>Vertical Line Number Setting Error Flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vertical line number setting error has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vertical line number setting error has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDRF</name>
|
|
<description>Underrun Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Underrun has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underrun has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVRF</name>
|
|
<description>Overrun Flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO overrun has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO overrun has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>Frame End Flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame end has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame end has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEMPF</name>
|
|
<description>FIFO Empty Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBSY</name>
|
|
<description>Frame Busy Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operations for reception are stopped.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operations for reception are ongoing.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCMONR</name>
|
|
<description>PDC Pin Monitor Register </description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HSYNC</name>
|
|
<description>HSYNC Signal Status Flag </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>HSYNC signal is at the low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>HSYNC signal is at the high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VSYNC</name>
|
|
<description>VSYNC Signal Status Flag </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VSYNC signal is at the low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VSYNC signal is at the high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCDR</name>
|
|
<description>PDC Receive Data Register </description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCDR</name>
|
|
<description>The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VCR</name>
|
|
<description>Vertical Capture Register </description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VSZ</name>
|
|
<description>Vertical Capture Size Number of lines to be captured.</description>
|
|
<lsb>16</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VST</name>
|
|
<description>Vertical Capture Start Line PositionNumber of the line where capture is to start.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCR</name>
|
|
<description>Horizontal Capture Register </description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HSZ</name>
|
|
<description>Horizontal Capture Size Number of bytes to capture horizontally.</description>
|
|
<lsb>16</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HST</name>
|
|
<description>Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start.</description>
|
|
<lsb>0</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>QSPI</name>
|
|
<description>Quad-SPI</description>
|
|
<baseAddress>0x64000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4C</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x800</offset>
|
|
<size>12</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SFMSMD</name>
|
|
<description>Transfer Mode Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMCCE</name>
|
|
<description>Read instruction code selection.</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Default instruction code set for each instruction</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Instruction code written in the SFMSIC register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMOSW</name>
|
|
<description>Setup time adjustment for serial transmission</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not extend the low-level width of SCK at transmission time</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extends the low-level width of SCK by 1*PCLKA at transmission time</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMOHW</name>
|
|
<description>Hold time adjustment for serial transmission</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not extend the high-level width of SCK at transmission time</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extends the high-level width of SCK by 1*PCLKA at transmission time</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMOEX</name>
|
|
<description>Extension of the I/O buffer output enable signal for the serial interface</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not extend the output enable signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extends the output enable signal by 1*QSPCLK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMMD3</name>
|
|
<description>SPI mode selection. An initial value is determined by input to CFGMD3.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI mode 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI mode 3</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMPAE</name>
|
|
<description>Selection of the function for stopping prefetch at locations other than on byte boundaries</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables prefetch stopping at locations other than on byte boundaries</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables prefetch stopping at locations other than on byte boundaries</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMPFE</name>
|
|
<description>Selection of the prefetch function</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables prefetch</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables prefetch</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMSE</name>
|
|
<description>Selection of the prefetch function</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Does not extend QSSL</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Extends QSSL by 33*QSPCLK</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Extends QSSL by 129*QSPCLK</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Extends QSSL infinitely</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMRM</name>
|
|
<description>Serial interface read mode selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Standard Read</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Fast Read</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Fast Read Dual Output</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Fast Read Dual I/O</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Fast Read Quad Output</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Fast Read Quad I/O</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSSC</name>
|
|
<description>Chip Selection Control Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000037</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMSLD</name>
|
|
<description>QSSL signal output timing selection</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMSHD</name>
|
|
<description>QSSL signal release timing selection</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Releases QSSL 0.5*SCK after the last rising edge of QSPCLK</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Releases QSSL 1.5*SCK after the last rising edge of QSPCLK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMSW</name>
|
|
<description>Selection of a minimum high-level width of the QSSL signal</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>1 x QSPCLK</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>2 x QSPCLK</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>3 x QSPCLK</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>4 x QSPCLK</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>5 x QSPCLK</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>6 x QSPCLK</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>7 x QSPCLK</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>8 x QSPCLK</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>9 x QSPCLK</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>10 x QSPCLK</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>11 x QSPCLK</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>12 x QSPCLK</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>13 x QSPCLK</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>14 x QSPCLK</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>15 x QSPCLK</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>16 x QSPCLK</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSKC</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMDTY</name>
|
|
<description>Selection of a duty ratio correction function for the SCK signal</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Serial interface reference cycle selection (* Pay attention to the irregularity.)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMDV</name>
|
|
<description>Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>18 x PCLKA</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>20 x PCLKA</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>22 x PCLKA</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>24 x PCLKA</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>26 x PCLKA</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>28 x PCLKA</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>30 x PCLKA</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>32 x PCLKA</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>34 x PCLKA</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>36 x PCLKA</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>38 x PCLKA</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>40 x PCLKA</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>42 x PCLKA</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>44 x PCLKA</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>46 x PCLKA</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>48 x PCLKA</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>( SFMDV + 2 ) x PCLKA </description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSST</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFOFF</name>
|
|
<description>Prefetch function operation state</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The prefetch function is operating.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The prefetch function is not enabled or is not operating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFFUL</name>
|
|
<description>Prefetch buffer state</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The prefetch buffer has a free space.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The prefetch buffer is full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFCNT</name>
|
|
<description>Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.)</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>Nodata has been prefetched.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Data of (PFCNT) bytes hs been prefetched.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMCOM</name>
|
|
<description>Communication Port Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFF00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMD</name>
|
|
<description>Port for direct communication with the SPI bus.Input/output to and from this port is converted to an SPI bus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMCMD</name>
|
|
<description>Communication Mode Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCOM</name>
|
|
<description>Selection of a mode of communication with the SPI bus</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ROM access mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Direct communication mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMCST</name>
|
|
<description>Communication Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EROMR</name>
|
|
<description>Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ROM access is not detected in direct communication mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ROM access is detected in direct communication mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBSY</name>
|
|
<description>SPI bus cycle completion state in direct communication</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>There is no serial transfer being processed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>There is a serial transfer being processed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSIC</name>
|
|
<description>Instruction Code Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMCIC</name>
|
|
<description>Serial ROM instruction code to substitute</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSAC</name>
|
|
<description>Address Mode Control Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFM4BC</name>
|
|
<description>Selection of a default instruction code, when Serial Interface address width is selected 4 bytes.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not use 4 Byte address read Instruction code</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use 4 Byte address read Instruction code</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMAS</name>
|
|
<description>Selection the number of address bits of the serial interface</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1byte</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2bytes</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3bytes</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 bytes</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSDC</name>
|
|
<description>Dummy Cycle Control Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FF00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMXD</name>
|
|
<description>Mode data for serial ROM. (Control XIP mode)</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>XIP mode is prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>XIP mode is permitted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMXEN</name>
|
|
<description>XIP mode permission</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>XIP mode is prohibited</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>XIP mode is permitted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMXST</name>
|
|
<description>XIP mode status</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal (non-XIP) mode is operating</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>XIP mode is operating</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMDN</name>
|
|
<description>Selection of the number of dummy cycles of Fast Read instructions</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Default dummy cycles of each instruction.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>( SFMDN + 2 ) x SCK</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMSPC</name>
|
|
<description>SPI Protocol Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMSDE</name>
|
|
<description>Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not allocate minimum switch time</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allocate the minimum switch time equivalent to 1*QSPXLK</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SFMSPI</name>
|
|
<description>Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately.</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Extended SPI protocol</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Dual SPI protocol</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Quad SPI protocol</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMPMD</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFMWPL</name>
|
|
<description>Specify level of WP pin</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low level</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High level</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFMCNT1</name>
|
|
<description>External QSPI Address Register 1</description>
|
|
<addressOffset>0x804</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QSPI_EXT</name>
|
|
<description>BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.</description>
|
|
<lsb>26</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MMF</name>
|
|
<description>Memory Mirror Function</description>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MMSFR</name>
|
|
<description>MemMirror Special Function Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>MMSFR Key Code</description>
|
|
<lsb>24</lsb>
|
|
<msb>31</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xDB</name>
|
|
<description>Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB.</description>
|
|
<value>0xDB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the MEMMIRADDR bits are invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMMIRADDR</name>
|
|
<description>Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0.</description>
|
|
<lsb>7</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMEN</name>
|
|
<description>MemMirror Enable Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>MMEN Key Code</description>
|
|
<lsb>24</lsb>
|
|
<msb>31</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0xDB</name>
|
|
<description>Writing to the EN bit is valid, when the KEY bits are written 0xDB.</description>
|
|
<value>0xDB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Writing to the EN bit is invalid.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Memory Mirror Function Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory Mirror Function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory Mirror Function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAC0</name>
|
|
<description>Direct memory access controller 0</description>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x13</offset>
|
|
<size>3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>7</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DMSAR</name>
|
|
<description>DMA Source Address Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMSAR</name>
|
|
<description>Specifies the transfer source start address.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMDAR</name>
|
|
<description>DMA Destination Address Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMDAR</name>
|
|
<description>Specifies the transfer destination start address.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMCRA</name>
|
|
<description>DMA Transfer Count Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMCRAH</name>
|
|
<description>Upper bits of transfer count</description>
|
|
<lsb>16</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMCRAL</name>
|
|
<description>Lower bits of transfer count</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMCRB</name>
|
|
<description>DMA Block Transfer Count Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMCRB</name>
|
|
<description>Specifies the number of block transfer operations or repeat transfer operations.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>65,536 blocks</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>DMCRB blocks</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMTMD</name>
|
|
<description>DMA Transfer Mode Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Transfer Mode Select</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal transfer</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Repeat transfer</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Block transfer</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTS</name>
|
|
<description>Repeat Area Select</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Specify destination as the repeat area or block area</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Specify source as the repeat area or block area</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Do not specify repeat area or block area</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SZ</name>
|
|
<description>Transfer Data Size Select</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8 bits</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16 bits</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32 bits</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCTG</name>
|
|
<description>Transfer Request Source Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Software</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Interrupts from peripheral modules or external interrupt input pins</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMINT</name>
|
|
<description>DMA Interrupt Setting Register</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTIE</name>
|
|
<description>Transfer End Interrupt Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESIE</name>
|
|
<description>Transfer Escape End Interrupt Enable</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPTIE</name>
|
|
<description>Repeat Size End Interrupt Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARIE</name>
|
|
<description>Source Address Extended Repeat Area Overflow Interrupt Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DARIE</name>
|
|
<description>Destination Address Extended Repeat Area Overflow Interrupt Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAMD</name>
|
|
<description>DMA Address Mode Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SM</name>
|
|
<description>Source Address Update Mode</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fixed address</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Offset addition</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Incremented address</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Decremented address.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARA</name>
|
|
<description>Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings.</description>
|
|
<lsb>8</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DM</name>
|
|
<description>Destination Address Update Mode</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fixed address</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Offset addition</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Incremented address</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Decremented address.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DARA</name>
|
|
<description>Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings.</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMOFR</name>
|
|
<description>DMA Offset Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMOFR</name>
|
|
<description>Specifies the offset when offset addition is selected as the address update mode for transfer source or destination.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMCNT</name>
|
|
<description>DMA Transfer Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMREQ</name>
|
|
<description>DMA Software Start Register</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRS</name>
|
|
<description>DMA Software Start Bit Auto Clear Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear SWREQ bit after DMA transfer is started by software</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Do not clear SWREQ bit after DMA transfer is started by software</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWREQ</name>
|
|
<description>DMA Software Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not request DMA transfer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request DMA transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMSTS</name>
|
|
<description>DMAC Module Activation Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACT</name>
|
|
<description>DMA Active Flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMAC operation is suspended.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMAC is operating.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTIF</name>
|
|
<description>Transfer End Interrupt Flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESIF</name>
|
|
<description>Transfer Escape End Interrupt Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A transfer escape end interrupt has not been generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A transfer escape end interrupt has been generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC1</name>
|
|
<description>Direct memory access controller 1</description>
|
|
<baseAddress>0x40005040</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC2</name>
|
|
<description>Direct memory access controller 2</description>
|
|
<baseAddress>0x40005080</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC3</name>
|
|
<description>Direct memory access controller 3</description>
|
|
<baseAddress>0x400050C0</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC4</name>
|
|
<description>Direct memory access controller 4</description>
|
|
<baseAddress>0x40005100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC5</name>
|
|
<description>Direct memory access controller 5</description>
|
|
<baseAddress>0x40005140</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC6</name>
|
|
<description>Direct memory access controller 6</description>
|
|
<baseAddress>0x40005180</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAC0">
|
|
<name>DMAC7</name>
|
|
<description>Direct memory access controller 7</description>
|
|
<baseAddress>0x400051C0</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>DMAC Module Activation</description>
|
|
<baseAddress>0x40005200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DMAST</name>
|
|
<description>DMA Module Activation Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMST</name>
|
|
<description>DMAC Operation Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMAC activation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMAC activation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DTC</name>
|
|
<description>Data Transfer Controller</description>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0E</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DTCCR</name>
|
|
<description>DTC Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x08</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RRS</name>
|
|
<description>DTC Transfer Information Read Skip Enable.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not skip transfer information read</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Skip transfer information read when vector numbers match</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCVBR</name>
|
|
<description>DTC Vector Base Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCVBR</name>
|
|
<description>DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCST</name>
|
|
<description>DTC Module Start Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCST</name>
|
|
<description>DTC Module Start</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DTC module stop</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DTC module start</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCSTS</name>
|
|
<description>DTC Status Register</description>
|
|
<addressOffset>0x0E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACT</name>
|
|
<description>DTC Active Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DTC transfer operation is not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DTC transfer operation is in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECN</name>
|
|
<description>DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1)</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DBG</name>
|
|
<description>Debug Function</description>
|
|
<baseAddress>0x4001B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DBGSTR</name>
|
|
<description>Debug Status Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDBGPWRUPACK</name>
|
|
<description>Debug power-up acknowledge</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Debug power-up request is not acknowledged</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Debug power-up request is acknowledged</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDBGPWRUPREQ</name>
|
|
<description>Debug power-up request</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OCD is not requesting debug power-up</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OCD is requesting debug power-up</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGSTOPCR</name>
|
|
<description>Debug Stop Control Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGSTOP_RECCR</name>
|
|
<description>Mask bit for RAM ECC error reset/interrupt</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable RAM ECC error reset/interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask RAM ECC error reset/interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGSTOP_RPER</name>
|
|
<description>Mask bit for RAM parity error reset/interrupt</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable RAM parity error reset/interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mask RAM parity error reset/interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGSTOP_LVD</name>
|
|
<description>b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask)</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGSTOP_WDT</name>
|
|
<description>Mask bit for WDT reset/interrupt</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask WDT reset/interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable WDT reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGSTOP_IWDT</name>
|
|
<description>Mask bit for IWDT reset/interrupt</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mask IWDT reset/interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable IWDT reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRACECTR</name>
|
|
<description>Trace Control Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENETBFULL</name>
|
|
<description>Enable bit for halt request by ETB full</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ETB full does not cause CPU halt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ETB full cause CPU halt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TSN</name>
|
|
<description>Temperature Sensor</description>
|
|
<baseAddress>0x4005D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TSCR</name>
|
|
<description>Temperature Sensor Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Temperature Sensor Output Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stops the temperature sensor.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Starts the temperature sensor.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSOE</name>
|
|
<description>Temperature Sensor Enable</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables output from the temperature sensor to the 12-bit A/D converter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables output from the temperature sensor to the 12-bit A/D converter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMPHS0</name>
|
|
<description>High-Speed Analog Comparator 0</description>
|
|
<baseAddress>0x40085000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CMPCTL</name>
|
|
<description>Comparator Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCMPON</name>
|
|
<description>Comparator operation control</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operation stopped (the comparator outputs a low-level signal)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operation enabled (input to the comparator pins is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDFS</name>
|
|
<description>Noise filter selection</description>
|
|
<lsb>5</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Noise filter not used.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Noise filter sampling frequency is 2^3/PCLKB.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Noise filter sampling frequency is 2^4/PCLKB. </description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Noise filter sampling frequency is 2^5/PCLKB.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEG</name>
|
|
<description>Selection of valid edge (Edge selector) </description>
|
|
<lsb>3</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No edge selection.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Rising edge selection.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Falling edge selection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both-edge selection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTEN</name>
|
|
<description>Interrupt Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output via the Edge selector</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Direct output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COE</name>
|
|
<description>Comparator output enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output disabled (the output signal is low level).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINV</name>
|
|
<description>Comparator output polarity selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output not inverted </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output inverted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPSEL0</name>
|
|
<description>Comparator Input Select Register </description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSEL</name>
|
|
<description>Comparator input selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No input</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>IVCMP0 selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>IVCMP1 selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>IVCMP2 selected</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>IVCMP3 selected</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPSEL1</name>
|
|
<description>Comparator Reference Voltage Select Register </description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRVS</name>
|
|
<description>Reference voltage selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No reference voltage</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>IVREF0 selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>IVREF1 selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>IVREF2 selected</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>IVREF3 selected</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMON</name>
|
|
<description>Comparator Output Monitor Register </description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPMON</name>
|
|
<description>Comparator output monitor </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output Low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output High</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPIOC</name>
|
|
<description>Comparator Output Control Register </description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>Internal Vref enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal Vref disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal Vref enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOE</name>
|
|
<description>Comparator output selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VCOUT pin output of the comparator is disabled (the output signal is low level).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VCOUT pin output of the comparator is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMPHS1</name>
|
|
<description>High-Speed Analog Comparator 1</description>
|
|
<baseAddress>0x40085100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0C</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CMPCTL</name>
|
|
<description>Comparator Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCMPON</name>
|
|
<description>Comparator operation control</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Operation stopped (the comparator outputs a low-level signal)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Operation enabled (input to the comparator pins is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDFS</name>
|
|
<description>Noise filter selection</description>
|
|
<lsb>5</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Noise filter not used.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Noise filter sampling frequency is 2^3/PCLKB.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Noise filter sampling frequency is 2^4/PCLKB. </description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Noise filter sampling frequency is 2^5/PCLKB.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEG</name>
|
|
<description>Selection of valid edge (Edge selector) </description>
|
|
<lsb>3</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No edge selection.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Rising edge selection.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Falling edge selection</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Both-edge selection</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSTEN</name>
|
|
<description>Interrupt Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output via the Edge selector</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Direct output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COE</name>
|
|
<description>Comparator output enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output disabled (the output signal is low level).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINV</name>
|
|
<description>Comparator output polarity selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output not inverted </description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output inverted</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPSEL0</name>
|
|
<description>Comparator Input Select Register </description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPSEL</name>
|
|
<description>Comparator input selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No input</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>IVCMP0 selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>IVCMP1 selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>IVCMP2 selected</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>IVCMP3 selected</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPSEL1</name>
|
|
<description>Comparator Reference Voltage Select Register </description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRVS</name>
|
|
<description>Reference voltage selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>No reference voltage</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>IVREF0 selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>IVREF1 selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>IVREF2 selected</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>IVREF3 selected</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPMON</name>
|
|
<description>Comparator Output Monitor Register </description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPMON</name>
|
|
<description>Comparator output monitor </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Comparator output Low</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Comparator output High</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPIOC</name>
|
|
<description>Comparator Output Control Register </description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>Internal Vref enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal Vref disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal Vref enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOE</name>
|
|
<description>Comparator output selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VCOUT pin output of the comparator is disabled (the output signal is low level).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VCOUT pin output of the comparator is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ACMPHS1">
|
|
<name>ACMPHS2</name>
|
|
<description>High-Speed Analog Comparator 2</description>
|
|
<baseAddress>0x40085200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ACMPHS1">
|
|
<name>ACMPHS3</name>
|
|
<description>High-Speed Analog Comparator 3</description>
|
|
<baseAddress>0x40085300</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ACMPHS1">
|
|
<name>ACMPHS4</name>
|
|
<description>High-Speed Analog Comparator 4</description>
|
|
<baseAddress>0x40085400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ACMPHS1">
|
|
<name>ACMPHS5</name>
|
|
<description>High-Speed Analog Comparator 5</description>
|
|
<baseAddress>0x40085500</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ELC</name>
|
|
<description>Event Link Controller </description>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>76</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ELCR</name>
|
|
<description>Event Link Controller Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELCON</name>
|
|
<description>All Event Link Enable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable ELC function</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable ELC function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x2</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>ELSEGR%s</name>
|
|
<description>Event Link Software Event Generation Register %s</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WI</name>
|
|
<description>ELSEGR Register Write Disable</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable writes to ELSEGR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable writes to ELSEGR register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>SEG Bit Write Enable</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable writes to SEG bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable writes to SEG bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEG</name>
|
|
<description>Software Event Generation</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generate a software event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>19</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-18</dimIndex>
|
|
<name>ELSR%s</name>
|
|
<description>Event Link Setting Register %s</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELS</name>
|
|
<description>Event Link Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x000</name>
|
|
<description>Event output to the corresponding peripheral module is disabled.</description>
|
|
<value>0x000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>Set the number for the event signal to be linked.</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<description>Watchdog Timer </description>
|
|
<baseAddress>0x40044200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>WDTRR</name>
|
|
<description>WDT Refresh Register </description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDTRR</name>
|
|
<description>WDTRR is an 8-bit register that refreshes the down-counter of the WDT.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTCR</name>
|
|
<description>WDT Control Register </description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x33F3</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RPSS</name>
|
|
<description>Window Start Position Selection</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>25 percent</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>50 percent</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>75 percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>100 percent (window start position is not specified)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPES</name>
|
|
<description>Window End Position Selection</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>75 percent</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>50 percent</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>25 percent</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>0 percent (window end position is not specified)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Clock Division Ratio Selection</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>PCLK/4</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>PCLK/64</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>PCLK/128</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>PCLK/512</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>PCLK/2048</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>PCLK/8192</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>others</name>
|
|
<description>setting prohibited</description>
|
|
<isDefault>true</isDefault>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOPS</name>
|
|
<description>Timeout Period Selection</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1,024 cycles (03FFh)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>4,096 cycles (0FFFh)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>8,192 cycles (1FFFh)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>16,384 cycles (3FFFh)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTSR</name>
|
|
<description>WDT Status Register </description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFEF</name>
|
|
<description>Refresh Error Flag </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No refresh error occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Refresh error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNDFF</name>
|
|
<description>Underflow Flag</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No underflow occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underflow occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTVAL</name>
|
|
<description>Down-Counter ValueValue counted by the down-counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTRCR</name>
|
|
<description>WDT Reset Control Register </description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTIRQS</name>
|
|
<description>Reset Interrupt Request Selection</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-maskable interrupt request or interrupt request output is enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset output is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTCSTPR</name>
|
|
<description>WDT Count Stop Control Register </description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLCSTP</name>
|
|
<description>Sleep-Mode Count Stop Control</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Count stop is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count is stopped at a transition to sleep mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IWDT</name>
|
|
<description>Independent Watchdog Timer</description>
|
|
<baseAddress>0x40044400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IWDTRR</name>
|
|
<description>IWDT Refresh Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IWDTRR</name>
|
|
<description>The counter is refreshed by writing 0x00 and then writing 0xFF to this register.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IWDTSR</name>
|
|
<description>IWDT Status Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFEF</name>
|
|
<description>Refresh Error Flag</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Refresh error not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Refresh error occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNDFF</name>
|
|
<description>Underflow Flag</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Underflow not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Underflow occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTVAL</name>
|
|
<description>Counter ValueValue counted by the counter</description>
|
|
<lsb>0</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>KINT</name>
|
|
<description>Key Interrupt Function</description>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x04</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x08</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>KRCTL</name>
|
|
<description>KEY Return Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KRMD</name>
|
|
<description>Usage of Key Interrupt Flags(KR0 to KR7)</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not use key interrupt flags</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use key interrupt flags.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KREG</name>
|
|
<description>Detection Edge Selection (KRF0 to KRF7)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KRF</name>
|
|
<description>KEY Return Flag Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KRF7</name>
|
|
<description>Key interrupt flag 7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF6</name>
|
|
<description>Key interrupt flag 6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF5</name>
|
|
<description>Key interrupt flag 5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF4</name>
|
|
<description>Key interrupt flag 4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF3</name>
|
|
<description>Key interrupt flag 3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF2</name>
|
|
<description>Key interrupt flag 2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF1</name>
|
|
<description>Key interrupt flag 1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRF0</name>
|
|
<description>Key interrupt flag 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>zeroToClear</modifiedWriteValues>
|
|
<readAction>modify</readAction>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KRM</name>
|
|
<description>KEY Return Mode Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KRM7</name>
|
|
<description>Key interrupt mode control 7</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM6</name>
|
|
<description>Key interrupt mode control 6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM5</name>
|
|
<description>Key interrupt mode control 5</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM4</name>
|
|
<description>Key interrupt mode control 4</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM3</name>
|
|
<description>Key interrupt mode control 3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM2</name>
|
|
<description>Key interrupt mode control 2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM1</name>
|
|
<description>Key interrupt mode control 1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRM0</name>
|
|
<description>Key interrupt mode control 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not detect key interrupt signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Detect key interrupt signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DOC</name>
|
|
<description>Data Operation Circuit</description>
|
|
<baseAddress>0x40054100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x02</offset>
|
|
<size>4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DOCR</name>
|
|
<description>DOC Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOPCFCL</name>
|
|
<description>DOPCF Clear</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Maintains the DOPCF flag state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the DOPCF flag.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOPCF</name>
|
|
<description>Data Operation Circuit FlagIndicates the result of an operation.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCSEL</name>
|
|
<description>Detection Condition Select</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DOPCF is set when data mismatch is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DOPCF is set when data match is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OMS</name>
|
|
<description>Operating Mode Select</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Data comparison mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Data addition mode</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Data subtraction mode</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DODIR</name>
|
|
<description>DOC Data Input Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DODIR</name>
|
|
<description>16-bit read-write register in which 16-bit data for use in the operations are stored.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DODSR</name>
|
|
<description>DOC Data Setting Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DODSR</name>
|
|
<description>This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAC</name>
|
|
<description>Clock Frequency Accuracy Measurement Circuit </description>
|
|
<baseAddress>0x40044600</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x06</offset>
|
|
<size>6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CACR0</name>
|
|
<description>CAC Control Register 0 </description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CFME</name>
|
|
<description>Clock Frequency Measurement Enable.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACR1</name>
|
|
<description>CAC Control Register 1</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGES</name>
|
|
<description>Valid Edge Select</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Rising edge</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Falling edge</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both rising and falling edges</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCSS</name>
|
|
<description>Measurement Target Clock Frequency Division Ratio Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No division</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>x 1/4 clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>x 1/8 clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>x 1/32 clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMCS</name>
|
|
<description>Measurement Target Clock Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Main clock</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Sub-clock</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>HOCO clock</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>MOCO clock</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LOCO clock</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Peripheral module clock(PCLKB)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IWDTCLK clock</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CACREFE</name>
|
|
<description>CACREF Pin Input Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACR2</name>
|
|
<description>CAC Control Register 2 </description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Digital Filter Selection</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Digital filtering is disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The sampling clock for the digital filter is the frequency measuring clock.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The sampling clock for the digital filter is the frequency measuring clock divided by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The sampling clock for the digital filter is the frequency measuring clock divided by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCDS</name>
|
|
<description>Measurement Reference Clock Frequency Division Ratio Select</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1/32 clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1/128 clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>1/1024 clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>1/8192 clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCS</name>
|
|
<description>Measurement Reference Clock Select</description>
|
|
<lsb>1</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Main clock</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Sub-clock</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>HOCO clock</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>MOCO clock</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LOCO clock</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Peripheral module clock(PCLKB)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IWDTCLK clock</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Setting prohibited</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPS</name>
|
|
<description>Reference Signal Select </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CACREF pin input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal clock (internally generated signal)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAICR</name>
|
|
<description>CAC Interrupt Control Register </description>
|
|
<addressOffset>0x03</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFFCL</name>
|
|
<description>OVFF Clear </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect on operations</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the OVFF flag</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MENDFCL</name>
|
|
<description>MENDF Clear </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect on operations</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the MENDF flag</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FERRFCL</name>
|
|
<description>FERRF Clear</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect on operations</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears the FERRF flag</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFIE</name>
|
|
<description>Overflow Interrupt Request Enable</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MENDIE</name>
|
|
<description>Measurement End Interrupt Request Enable</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FERRIE</name>
|
|
<description>Frequency Error Interrupt Request Enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CASTR</name>
|
|
<description>CAC Status Register </description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFF</name>
|
|
<description>Counter Overflow Flag </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MENDF</name>
|
|
<description>Measurement End Flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Measurement is in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Measurement has ended.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FERRF</name>
|
|
<description>Frequency Error Flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The clock frequency is within the range corresponding to the settings.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The clock frequency has deviated beyond the range corresponding to the settings (frequency error).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAULVR</name>
|
|
<description>CAC Upper-Limit Value Setting Register </description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAULVR</name>
|
|
<description>CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALLVR</name>
|
|
<description>CAC Lower-Limit Value Setting Register </description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CALLVR</name>
|
|
<description>CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency.</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACNTBR</name>
|
|
<description>CAC Counter Buffer Register</description>
|
|
<addressOffset>0x0A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CACNTBR</name>
|
|
<description>CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> |