Renesas Renesas R7FA6M2AF RA6 1.2 ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 120MHz, etc. CM4 r0p1 little true true true 4 false 8 32 PORT0 Port 0 Control Registers 0x40040000 0x00 4 registers 0x00 8 registers 0x06 6 registers 0x08 4 registers PCNTR1 Port Control Register 1 0x00 32 read-write 0x00000000 0xFFFFFFFF PODR Pmn Output Data 16 31 read-write 0 Low output #0 1 High output. #1 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Output data register PCNTR1 0x00 16 read-write 0x0000 0xFFFF PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PDR Data direction register PCNTR1 0x02 16 read-write 0x0000 0xFFFF PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PCNTR2 Port Control Register 2 0x04 32 read-only 0x00000000 0xFFFF0000 EIDR Pmn Event Input Data 16 31 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PIDR Input data register PCNTR2 0x06 16 read-only 0x0000 0x0000 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x08 32 write-only 0x00000000 0xFFFFFFFF PORR Pmn Output Reset 16 31 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORR Output reset register PCNTR3 0x08 16 write-only 0x0000 0xFFFF PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0x0A 16 write-only 0x0000 0xFFFF POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT1 Port 1 Control Registers 0x40040020 0x00 4 registers 0x00 8 registers 0x04 8 registers 0x08 8 registers 0x0C 4 registers PCNTR1 Port Control Register 1 0x00 32 read-write 0x00000000 0xFFFFFFFF PODR Pmn Output Data 16 31 read-write 0 Low output #0 1 High output. #1 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Output data register PCNTR1 0x00 16 read-write 0x0000 0xFFFF PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PDR Data direction register PCNTR1 0x02 16 read-write 0x0000 0xFFFF PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PCNTR2 Port Control Register 2 0x04 32 read-only 0x00000000 0xFFFF0000 EIDR Pmn Event Input Data 16 31 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EIDR Event input data register PCNTR2 0x04 16 read-only 0x0000 0x0000 EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PIDR Input data register PCNTR2 0x06 16 read-only 0x0000 0x0000 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x08 32 write-only 0x00000000 0xFFFFFFFF PORR Pmn Output Reset 16 31 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORR Output set register PCNTR3 0x08 16 write-only 0x0000 0xFFFF PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0x0A 16 write-only 0x0000 0xFFFF POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0x0C 32 read-write 0x00000000 0xFFFFFFFF EORR Pmn Event Output Reset 16 31 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 EORR Event output set register PCNTR4 0x0C 16 read-write 0x0000 0xFFFF EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0x0E 16 read-write 0x0000 0xFFFF EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PORT2 Port 2 Control Registers 0x40040040 PORT3 Port 3 Control Registers 0x40040060 PORT4 Port 4 Control Registers 0x40040080 PORT5 Port 5 Control Registers 0x400400A0 PORT6 Port 6 Control Registers 0x400400C0 PORT7 Port 7 Control Registers 0x400400E0 PORT8 Port 8 Control Registers 0x40040100 PORT9 Port 9 Control Registers 0x40040120 PORTA Port A Control Registers 0x40040140 PORTB Port B Control Registers 0x40040160 PFS Pmn Pin Function Control Register 0x40040800 0x00 4 registers 0x02 2 registers 0x03 29 registers 0x06 28 registers 0x07 28 registers 0x20 8 registers 0x22 8 registers 0x23 8 registers 0x38 8 registers 0x3A 8 registers 0x3B 8 registers 0x40 4 registers 0x42 2 registers 0x43 29 registers 0x46 28 registers 0x47 28 registers 0x60 4 registers 0x62 2 registers 0x63 5 registers 0x66 2 registers 0x67 5 registers 0x6A 2 registers 0x6B 21 registers 0x6E 20 registers 0x6F 20 registers 0x80 4 registers 0x82 2 registers 0x83 5 registers 0x86 2 registers 0x87 33 registers 0x8A 32 registers 0x8B 32 registers 0xA8 20 registers 0xAA 20 registers 0xAB 20 registers 0xC0 4 registers 0xC2 2 registers 0xC3 37 registers 0xC6 36 registers 0xC7 36 registers 0xE8 24 registers 0xEA 24 registers 0xEB 24 registers 0x100 40 registers 0x102 40 registers 0x103 40 registers 0x128 24 registers 0x12A 24 registers 0x12B 24 registers 0x140 36 registers 0x142 36 registers 0x143 36 registers 0x16C 20 registers 0x16E 20 registers 0x16F 20 registers 0x180 40 registers 0x182 40 registers 0x183 40 registers 0x1A8 24 registers 0x1AA 24 registers 0x1AB 24 registers 0x1C0 36 registers 0x1C2 36 registers 0x1C3 36 registers 0x1E4 36 registers 0x1E6 36 registers 0x1E7 36 registers 0x1E8 16 registers 0x1EA 16 registers 0x1EB 16 registers 0x200 28 registers 0x202 28 registers 0x203 28 registers 0x240 8 registers 0x242 8 registers 0x243 8 registers 0x254 16 registers 0x256 16 registers 0x257 16 registers 0x280 8 registers 0x282 8 registers 0x283 8 registers 0x2A0 8 registers 0x2A2 8 registers 0x2A3 8 registers 0x2A8 4 registers 0x2AA 2 registers 0x2AB 1 registers 0x2C0 8 registers 0x2C2 8 registers 0x2C3 8 registers P000PFS P000 Pin Function Control Register 0x000 32 read-write 0x00008000 0xFFFFFFFD PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P000PFS_HA P000 Pin Function Control Register P000PFS 0x002 16 read-write 0x8000 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P000PFS_BY P000 Pin Function Control Register P000PFS 0x003 8 read-write 0x00 0xFD NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 7 0x4 1-7 P00%sPFS P00%s Pin Function Control Register 0x004 32 read-write 0x00008000 0xFFFFFFFD 7 0x4 1-7 P00%sPFS_HA P00%s Pin Function Control Register P00%sPFS 0x006 16 read-write 0x8000 0xFFFD 7 0x4 1-7 P00%sPFS_BY P00%s Pin Function Control Register P00%sPFS 0x007 8 read-write 0x00 0xFD 2 0x4 8-9 P00%sPFS P00%s Pin Function Control Register 0x020 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 8-9 P00%sPFS_HA P00%s Pin Function Control Register P00%sPFS 0x022 16 read-write 0x0000 0xFFFD 2 0x4 8-9 P00%sPFS_BY P00%s Pin Function Control Register P00%sPFS 0x023 8 read-write 0x00 0xFD 2 0x4 14-15 P0%sPFS P0%s Pin Function Control Register 0x038 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 14-15 P0%sPFS_HA P0%s Pin Function Control Register 0x03A 16 read-write 0x0000 0xFFFD 2 0x4 14-15 P0%sPFS_BY P0%s Pin Function Control Register 0x03B 8 read-write 0x00 0xFD P100PFS P100 Pin Function Control Register 0x040 32 read-write 0x00000000 0xFFFFFFFD PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P100PFS_HA P100 Pin Function Control Register 0x042 16 read-write 0x0000 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P100PFS_BY P100 Pin Function Control Register 0x043 8 read-write 0x00 0xFD NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 7 0x4 1-7 P10%sPFS P10%s Pin Function Control Register P10%sPFS 0x044 32 read-write 0x00000000 0xFFFFFFFD 7 0x4 1-7 P10%sPFS_HA P10%s Pin Function Control Register P10%sPFS 0x046 16 read-write 0x0000 0xFFFD 7 0x4 1-7 P10%sPFS_BY P10%s Pin Function Control Register P10%sPFS 0x047 8 read-write 0x00 0xFD P108PFS P108 Pin Function Control Register 0x060 32 read-write 0x00010410 0xFFFFFFFD PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P108PFS_HA P108 Pin Function Control Register P108PFS 0x062 16 read-write 0x0410 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P108PFS_BY P108 Pin Function Control Register P108PFS 0x063 8 read-write 0x10 0xFD NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P109PFS P109 Pin Function Control Register 0x064 32 read-write 0x00010410 0xFFFFFFFD P109PFS_HA P109 Pin Function Control Register P109PFS 0x066 16 read-write 0x0410 0xFFFD P109PFS_BY P109 Pin Function Control Register P109PFS 0x067 8 read-write 0x10 0xFD P110PFS P110 Pin Function Control Register 0x068 32 read-write 0x00010010 0xFFFFFFFD PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P110PFS_HA P110 Pin Function Control Register P110PFS 0x06A 16 read-write 0x0010 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P110PFS_BY P110 Pin Function Control Register P110PFS 0x06B 8 read-write 0x10 0xFD NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 5 0x4 11-15 P1%sPFS P1%s Pin Function Control Register 0x06C 32 read-write 0x00000000 0xFFFFFFFD 5 0x4 11-15 P1%sPFS_HA P1%s Pin Function Control Register P1%sPFS 0x06E 16 read-write 0x0000 0xFFFD 5 0x4 11-15 P1%sPFS_BY P1%s Pin Function Control Register P1%sPFS 0x06F 8 read-write 0x00 0xFD P200PFS P200 Pin Function Control Register 0x080 32 read-write 0x00000000 0xFFFFFFFD P200PFS_HA P200 Pin Function Control Register P200PFS 0x082 16 read-write 0x0000 0xFFFD P200PFS_BY P200 Pin Function Control Register P200PFS 0x083 8 read-write 0x00 0xFD P201PFS P201 Pin Function Control Register 0x084 32 read-write 0x00000010 0xFFFFFFFD PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 28 read-write PMR Port Mode Control 16 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P201PFS_HA P201 Pin Function Control Register P201PFS 0x086 16 read-write 0x0010 0xFFFD ASEL Analog Input enable 15 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 ISEL IRQ input enable 14 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 EOF Event on Falling 13 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 12 read-write 0 Do not care #0 1 Detect rising edge #1 DSCR Drive Strength Control Register 10 11 read-write 00 Normal drive output #00 01 Middle drive output #01 10 Setting prohibited #10 11 High-drive output #11 NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 P201PFS_BY P201 Pin Function Control Register P201PFS 0x087 8 read-write 0x10 0xFD NCODR N-Channel Open Drain Control 6 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 0 read-write 0 Low output #0 1 High output #1 8 0x4 2-9 P20%sPFS P20%s Pin Function Control Register 0x088 32 read-write 0x00000000 0xFFFFFFFD 8 0x4 2-9 P20%sPFS_HA P20%s Pin Function Control Register P20%sPFS 0x08A 16 read-write 0x0000 0xFFFD 8 0x4 2-9 P20%sPFS_BY P20%s Pin Function Control Register P20%sPFS 0x08B 8 read-write 0x00 0xFD 5 0x4 10-14 P2%sPFS P2%s Pin Function Control Register 0x0A8 32 read-write 0x00000000 0xFFFFFFFD 5 0x4 10-14 P2%sPFS_HA P2%s Pin Function Control Register P2%sPFS 0x0AA 16 read-write 0x0000 0xFFFD 5 0x4 10-14 P2%sPFS_BY P2%s Pin Function Control Register P2%sPFS 0x0AB 8 read-write 0x00 0xFD P300PFS P300 Pin Function Control Register 0x0C0 32 read-write 0x00010010 0xFFFFFFFD P300PFS_HA P300 Pin Function Control Register P300PFS 0x0C2 16 read-write 0x0010 0xFFFD P300PFS_BY P300 Pin Function Control Register P300PFS 0x0C3 8 read-write 0x10 0xFD 9 0x4 1-9 P30%sPFS P30%s Pin Function Control Register 0x0C4 32 read-write 0x00000000 0xFFFFFFFD 9 0x4 1-9 P30%sPFS_HA P30%s Pin Function Control Register P30%sPFS 0x0C6 16 read-write 0x0000 0xFFFD 9 0x4 1-9 P30%sPFS_BY P30%s Pin Function Control Register P30%sPFS 0x0C7 8 read-write 0x00 0xFD 6 0x4 10-15 P3%sPFS P3%s Pin Function Control Register 0x0E8 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 10-15 P3%sPFS_HA P30%s Pin Function Control Register P3%sPFS 0x0EA 16 read-write 0x0000 0xFFFD 6 0x4 10-15 P3%sPFS_BY P30%s Pin Function Control Register P3%sPFS 0x0EB 8 read-write 0x00 0xFD 10 0x4 0-9 P40%sPFS P40%s Pin Function Control Register 0x100 32 read-write 0x00000000 0xFFFFFFFD 10 0x4 0-9 P40%sPFS_HA P40%s Pin Function Control Register P40%sPFS 0x102 16 read-write 0x0000 0xFFFD 10 0x4 0-9 P40%sPFS_BY P40%s Pin Function Control Register P40%sPFS 0x103 8 read-write 0x00 0xFD 6 0x4 10-15 P4%sPFS P4%s Pin Function Control Register 0x128 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 10-15 P4%sPFS_HA P4%s Pin Function Control Register P4%sPFS 0x12A 16 read-write 0x0000 0xFFFD 6 0x4 10-15 P4%sPFS_BY P4%s Pin Function Control Register P4%sPFS 0x12B 8 read-write 0x00 0xFD 9 0x4 0-8 P50%sPFS P50%s Pin Function Control Register 0x140 32 read-write 0x00000000 0xFFFFFFFD 9 0x4 0-8 P50%sPFS_HA P50%s Pin Function Control Register P50%sPFS 0x142 16 read-write 0x0000 0xFFFD 9 0x4 0-8 P50%sPFS_BY P50%s Pin Function Control Register P50%sPFS 0x143 8 read-write 0x00 0xFD 5 0x4 11-15 P5%sPFS P5%s Pin Function Control Register 0x16C 32 read-write 0x00000000 0xFFFFFFFD 5 0x4 11-15 P5%sPFS_HA P5%s Pin Function Control Register P5%sPFS 0x16E 16 read-write 0x0000 0xFFFD 5 0x4 11-15 P5%sPFS_BY P5%s Pin Function Control Register P5%sPFS 0x16F 8 read-write 0x00 0xFD 10 0x4 0-9 P60%sPFS P60%s Pin Function Control Register 0x180 32 read-write 0x00000000 0xFFFFFFFD 10 0x4 0-9 P60%sPFS_HA P60%s Pin Function Control Register P60%sPFS 0x182 16 read-write 0x0000 0xFFFD 10 0x4 0-9 P60%sPFS_BY P60%s Pin Function Control Register P60%sPFS 0x183 8 read-write 0x00 0xFD 6 0x4 10-15 P6%sPFS P6%s Pin Function Control Register 0x1A8 32 read-write 0x00000000 0xFFFFFFFD 6 0x4 10-15 P6%sPFS_HA P6%s Pin Function Control Register P6%sPFS 0x1AA 16 read-write 0x0000 0xFFFD 6 0x4 10-15 P6%sPFS_BY P6%s Pin Function Control Register P6%sPFS 0x1AB 8 read-write 0x00 0xFD 9 0x4 0-8 P70%sPFS P70%s Pin Function Control Register 0x1C0 32 read-write 0x00000000 0xFFFFFFFD 9 0x4 0-8 P70%sPFS_HA P70%s Pin Function Control Register P70%sPFS 0x1C2 16 read-write 0x0000 0xFFFD 9 0x4 0-8 P70%sPFS_BY P70%s Pin Function Control Register P70%sPFS 0x1C3 8 read-write 0x00 0xFD 7 0x4 0-6 P80%sPFS P80%s Pin Function Control Register 0x200 32 read-write 0x00000000 0xFFFFFFFD 7 0x4 0-6 P80%sPFS_HA P80%s Pin Function Control Register P80%sPFS 0x202 16 read-write 0x0000 0xFFFD 7 0x4 0-6 P80%sPFS_BY P80%s Pin Function Control Register P80%sPFS 0x203 8 read-write 0x00 0xFD 2 0x4 0-1 P90%sPFS P90%s Pin Function Control Register 0x240 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 0-1 P90%sPFS_HA P90%s Pin Function Control Register P90%sPFS 0x242 16 read-write 0x0000 0xFFFD 2 0x4 0-1 P90%sPFS_BY P90%s Pin Function Control Register P90%sPFS 0x243 8 read-write 0x00 0xFD 4 0x4 5-8 P90%sPFS P90%s Pin Function Control Register 0x254 32 read-write 0x00000000 0xFFFFFFFD 4 0x4 5-8 P90%sPFS_HA P90%s Pin Function Control Register P90%sPFS 0x256 16 read-write 0x0000 0xFFFD 4 0x4 5-8 P90%sPFS_BY P90%s Pin Function Control Register P90%sPFS 0x257 8 read-write 0x00 0xFD 2 0x4 0-1 PA0%sPFS PA0%s Pin Function Control Register 0x280 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 0-1 PA0%sPFS_HA PA0%s Pin Function Control Register PA0%sPFS 0x282 16 read-write 0x0000 0xFFFD 2 0x4 0-1 PA0%sPFS_BY PA0%s Pin Function Control Register PA0%sPFS 0x283 8 read-write 0x00 0xFD 2 0x4 8-9 PA0%sPFS PA0%s Pin Function Control Register 0x2A0 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 8-9 PA0%sPFS_HA PA0%s Pin Function Control Register PA0%sPFS 0x2A2 16 read-write 0x0000 0xFFFD 2 0x4 8-9 PA0%sPFS_BY PA0%s Pin Function Control Register PA0%sPFS 0x2A3 8 read-write 0x00 0xFD PA10PFS PA10 Pin Function Control Register 0x2A8 32 read-write 0x00000000 0xFFFFFFFD PA10PFS_HA PA10 Pin Function Control Register PA10PFS 0x2AA 16 read-write 0x0000 0xFFFD PA10PFS_BY PA10 Pin Function Control Register PA10PFS 0x2AB 8 read-write 0x00 0xFD 2 0x4 0-1 PB0%sPFS PB0%s Pin Function Control Register 0x2C0 32 read-write 0x00000000 0xFFFFFFFD 2 0x4 0-1 PB0%sPFS_HA PB0%s Pin Function Control Register PB0%sPFS 0x2C2 16 read-write 0x0000 0xFFFD 2 0x4 0-1 PB0%sPFS_BY PB0%s Pin Function Control Register PB0%sPFS 0x2C3 8 read-write 0x00 0xFD PMISC Miscellaneous Port Control Register 0x40040D00 0x00 4 registers PFENET Ethernet Control Register 0x00 8 read-write 0x00 0xFF PHYMODE0 Ethernet Mode Setting ch0 4 4 read-write 0 RMII mode (ETHERC channel 0) #0 1 MII mode (ETHERC channel 0) #1 PWPR Write-Protect Register 0x03 8 read-write 0x80 0xFF BOWI PFSWE Bit Write Disable 7 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PFSWE PFS Register Write Enable 6 6 read-write 0 Writing to the PFS register is disabled #0 1 Writing to the PFS register is enabled #1 SPI0 Serial Peripheral Interface 0 0x40072000 0x00 8 registers 0x04 2 registers 0x08 25 registers SPCR SPI Control Register 0x00 8 read-write 0x00 0xFF SPRIE SPI Receive Buffer Full Interrupt Enable 7 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPE SPI Function Enable 6 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 SPEIE SPI Error Interrupt Enable 4 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 MSTR SPI Master/Slave Mode Select 3 3 read-write 0 Slave mode #0 1 Master mode #1 MODFEN Mode Fault Error Detection Enable 2 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 TXMD Communications Operating Mode Select 1 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPMS SPI Mode Select 0 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SSLP SPI Slave Select Polarity Register 0x01 8 read-write 0x00 0xFF SSL3P SSL3 Signal Polarity Setting 3 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL0P SSL0 Signal Polarity Setting 0 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SPPCR RSPI Pin Control Register 0x02 8 read-write 0x00 0xFF MOIFE MOSI Idle Value Fixing Enable 5 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 SPLP2 RSPI Loopback 2 1 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPLP RSPI Loopback 0 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPSR SPI Status Register 0x03 8 read-write 0x20 0xFF SPRF SPI Receive Buffer Full Flag 7 7 read-write zeroToClear modify 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 SPTEF SPI Transmit Buffer Empty Flag 5 5 read-write zeroToClear modify 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag(When MODF is 0, This bit is invalid.) 4 4 read-write zeroToClear modify 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 PERF Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurs #0 1 A parity error occurs #1 MODF Mode Fault Error Flag 2 2 read-write zeroToClear modify 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 IDLNF SPI Idle Flag 1 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 OVRF Overrun Error Flag 0 0 read-write zeroToClear modify 0 No overrun error occurs #0 1 An overrun error occurs #1 SPDR SPI Data Register 0x04 32 read-write 0x00000000 0xFFFFFFFF SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x04 16 read-write 0x0000 0xFFFF SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPSCR SPI Sequence Control Register 0x08 8 read-write 0x00 0xFF SPSLN RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. 0 2 read-write 000 Length 1 SPDMDx x = 0->0->... #000 001 Length 2 SPDMDx x = 0->1->0->... #001 010 Length 3 SPDMDx x = 0->1->2->0->... #010 011 Length 4 SPDMDx x = 0->1->2->3->0->... #011 100 Length 5 SPDMDx x = 0->1->2->3->4->0->... #100 101 Length 6 SPDMDx x = 0->1->2->3->4->5->0->... #101 110 Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... #110 111 Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... #111 SPSSR SPI Sequence Status Register 0x09 8 read-only 0x00 0xFF SPECM RSPI Error Command 4 6 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPCP RSPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPBR SPI Bit Rate Register 0x0A 8 read-write 0xFF 0xFF SPR SPBR sets the bit rate in master mode. 0 7 read-write SPDCR SPI Data Control Register 0x0B 8 read-write 0x00 0xFF SPBYT SPI Byte Access Specification 6 6 read-write 0 SPDR is accessed in word or longword (SPLW is valid) #0 1 SPDR is accessed in byte (SPLW is invalid) #1 SPLW SPI Word Access/Halfword Access Specification 5 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames. #11 SPCKD SPI Clock Delay Register 0x0C 8 read-write 0x00 0xFF SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLND SPI Slave Select Negation Delay Register 0x0D 8 read-write 0x00 0xFF SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPND SPI Next-Access Delay Register 0x0E 8 read-write 0x00 0xFF SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPCR2 SPI Control Register 2 0x0F 8 read-write 0x00 0xFF SCKASE RSPCK Auto-Stop Function Enable 4 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 PTE Parity Self-Testing 3 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 SPIIE SPI Idle Interrupt Enable 2 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 8 0x2 0-7 SPCMD%s SPI Command Register %s 0x10 16 read-write 0x070D 0xFFFF SCKDEN RSPCK Delay Setting Enable 15 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPNDEN RSPI Next-Access Delay Enable 13 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 LSBF RSPI LSB First 12 12 read-write 0 MSB first #0 1 LSB first #1 SPB RSPI Data Length Setting 8 11 read-write 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 others 8bits true SSLKP SSL Signal Level Keeping 7 7 read-write 0 Negate all SSL signals on completion of transfer #0 1 Keep SSL signal level from the end of transfer until the beginning #1 SSLA SSL Signal Assertion Setting 4 6 read-write 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 others Setting prohibited true BRDV Bit Rate Division Setting 2 3 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPOL RSPCK Polarity Setting 1 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 CPHA RSPCK Phase Setting 0 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 SPDCR2 SPI Data Control Register 2 0x20 8 read-write 0x00 0xFF BYSW Byte Swap Operating Mode Select 0 0 read-write 0 Byte Swap Operating Mode disabled #0 1 Byte Swap Operating Mode enabled #1 SPI1 Serial Peripheral Interface 1 0x40072100 GPT_OPS Output Phase Switching Controller 0x40078FF0 0x00 4 registers OPSCR Output Phase Switching Control Register 0x00 32 read-write 0x00000000 0xFFFFFFFF NFCS External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFEN External Input Noise Filter Enable 29 29 read-write 0 Do not use a noise filter to the external input. #0 1 Use a noise filter to the external input. #1 GODF Group output disable function 26 26 read-write 0 This bit function is ignored. #0 1 Group disable will clear OPSCR.EN Bit. #1 GRP Output disabled source selection 24 25 read-write 00 Select Group A output disable source #00 01 Select Group B output disable source #01 10 Select Group C output disable source #10 11 Select Group D output disable source #11 ALIGN Input phase alignment 21 21 read-write 0 Input phase is aligned to PCLK. #0 1 Input phase is aligned PWM. #1 RV Output phase rotation direction reversal 20 20 read-write 0 U/V/W-Phase output #0 1 Output to reverse the V / W-phase #1 INV Invert-Phase Output Control 19 19 read-write 0 Positive Logic (Active High)output #0 1 Negative Logic (Active Low)output #1 N Negative-Phase Output (N) Control 18 18 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 P Positive-Phase Output (P) Control 17 17 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 FB External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. 16 16 read-write 0 Select the external input. #0 1 Select the soft setting(OPSCR.UF, VF, WF). #1 EN Enable-Phase Output Control 8 8 read-write 0 Not Output(Hi-Z external terminals). #0 1 Output #1 W Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 6 6 read-only V Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 5 5 read-only U Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 4 4 read-only WF Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 2 2 read-write VF Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 1 1 read-write UF Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 0 0 read-write GPT32EH0 General PWM Timer 0 (32-bit Enhanced High Resolution) 0x40078000 0x00 116 registers 0x7C 4 registers 0x74 4 registers 0x80 4 registers 0x78 4 registers 0x84 32 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xFFFFFFFF PRKEY GTWP Key Code 8 15 write-only 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 others The WP bits write is not permitted. true WP Register Write Disable 0 0 read-write 0 Enable writes to the register #0 1 Disable writes to the register #1 GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xFFFFFFFF CSTRT13 Channel 13 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 13 13 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3213.GTCNT counter starts (write) / Counter running (read) #1 CSTRT12 Channel 12 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 12 12 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3212.GTCNT counter starts (write) / Counter running (read) #1 CSTRT11 Channel 11 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 11 11 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3211.GTCNT counter starts (write) / Counter running (read) #1 CSTRT10 Channel 10 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 10 10 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3210.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT329.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT328.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E7.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E6.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E5.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E4.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH3.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH2.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH1.GTCNT counter starts (write) / Counter running (read) #1 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH0.GTCNT counter starts (write) / Counter running (read) #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF CSTOP13 Channel 13 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 13 13 read-write 0 No effect (write) / counter running (read) #0 1 GPT3213.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP12 Channel 12 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 12 12 read-write 0 No effect (write) / counter running (read) #0 1 GPT3212.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP11 Channel 11 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 11 11 read-write 0 No effect (write) / counter running (read) #0 1 GPT3211.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP10 Channel 10 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 10 10 read-write 0 No effect (write) / counter running (read) #0 1 GPT3210.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT329.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT328.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E7.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E6.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E5.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E4.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH3.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH2.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH1.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH0.GTCNT counter stops (write) / Counter stop (read) #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xFFFFFFFF CCLR13 Channel 13 GTCNT Count Clear 13 13 write-only 0 No effect #0 1 GPT3213.GTCNT counter clears #1 CCLR12 Channel 12 GTCNT Count Clear 12 12 write-only 0 No effect #0 1 GPT3212.GTCNT counter clears #1 CCLR11 Channel 11 GTCNT Count Clear 11 11 write-only 0 No effect #0 1 GPT3211.GTCNT counter clears #1 CCLR10 Channel 10 GTCNT Count Clear 10 10 write-only 0 No effect #0 1 GPT3210.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 9 write-only 0 No effect #0 1 GPT329.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 8 write-only 0 No effect #0 1 GPT328.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 7 write-only 0 No effect #0 1 GPT32E7.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 6 write-only 0 No effect #0 1 GPT32E6.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 5 write-only 0 No effect #0 1 GPT32E5.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 4 write-only 0 No effect #0 1 GPT32E4.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 3 write-only 0 No effect #0 1 GPT32EH3.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 2 write-only 0 No effect #0 1 GPT32EH2.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 1 write-only 0 No effect #0 1 GPT32EH1.GTCNT counter clears #1 CCLR0 Channel 0 GTCNT Count Clear 0 0 write-only 0 No effect #0 1 GPT32EH0.GTCNT counter clears #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xFFFFFFFF CSTRT Software Source Counter Start Enable 31 31 read-write 0 Disable counter start by the GTSTR register #0 1 Enable counter start by the GTSTR register #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Disable counter start on ELC_GPTH input #0 1 Enable counter start on ELC_GPTH input. #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Disable counter start on ELC_GPTG input #0 1 Enable counter start on ELC_GPTG input. #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Disable counter start on ELC_GPTF input #0 1 Enable counter start on ELC_GPTF input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Disable counter start on ELC_GPTE input #0 1 Enable counter start on ELC_GPTE input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Disable counter start on ELC_GPTD input #0 1 Enable counter start on ELC_GPTD input. #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Disable counter start on ELC_GPTC input #0 1 Enable counter start on ELC_GPTC input. #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Disable counter start on ELC_GPTB input #0 1 Enable counter start on ELC_GPTB input. #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Disable counter start on ELC_GPTA input #0 1 Enable counter start on ELC_GPTA input. #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 15 read-write 0 Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 1. #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 14 read-write 0 Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 0. #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 13 read-write 0 Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 1. #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 12 read-write 0 Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 0. #1 SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 11 read-write 0 Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 1. #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 10 read-write 0 Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 0. #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 9 read-write 0 Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 8 read-write 0 Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 0. #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Disable counter start on the falling edge of GTETRGD input #0 1 Enable counter start on the falling edge of GTETRGD input. #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Disable counter start on the rising edge of GTETRGD input #0 1 Enable counter start on the rising edge of GTETRGD input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Disable counter start on the falling edge of GTETRGC input #0 1 Enable counter start on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Disable counter start on the rising edge of GTETRGC input #0 1 Enable counter start on the rising edge of GTETRGC input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Disable counter start on the falling edge of GTETRGB input #0 1 Enable counter start on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Disable counter start on the rising edge of GTETRGB input #0 1 Enable counter start on the rising edge of GTETRGB input. #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Disable counter start on the falling edge of GTETRGA input #0 1 Enable counter start on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Disable counter start on the rising edge of GTETRGA input #0 1 Enable counter start on the rising edge of GTETRGA input. #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xFFFFFFFF CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Disable counter stop by the GTSTP register #0 1 Enable counter stop by the GTSTP register #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Disable counter stop on ELC_GPTH input #0 1 Enable counter stop on ELC_GPTH input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Disable counter stop on ELC_GPTG input #0 1 Enable counter stop on ELC_GPTG input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Disable counter stop on ELC_GPTF input #0 1 Enable counter stop on ELC_GPTF input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Disable counter stop on ELC_GPTE input #0 1 Enable counter stop on ELC_GPTE input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Disable counter stop on ELC_GPTD input #0 1 Enable counter stop on ELC_GPTD input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Disable counter stop on ELC_GPTC input #0 1 Enable counter stop on ELC_GPTC input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Disable counter stop on ELC_GPTB input #0 1 Enable counter stop on ELC_GPTB input #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Disable counter stop on ELC_GPTA input #0 1 Enable counter stop on ELC_GPTA input #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 15 read-write 0 Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 14 read-write 0 Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 13 read-write 0 Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 12 read-write 0 Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 11 read-write 0 Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 10 read-write 0 Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 9 read-write 0 Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 8 read-write 0 Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Disable counter stop on the falling edge of GTETRGD input #0 1 Enable counter stop on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Disable counter stop on the rising edge of GTETRGD input #0 1 Enable counter stop on the rising edge of GTETRGD input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Disable counter stop on the falling edge of GTETRGC input #0 1 Enable counter stop on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Disable counter stop on the rising edge of GTETRGC input #0 1 Enable counter stop on the rising edge of GTETRGC input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Disable counter stop on the falling edge of GTETRGB input #0 1 Enable counter stop on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Disable counter stop on the rising edge of GTETRGB input #0 1 Enable counter stop on the rising edge of GTETRGB input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Disable counter stop on the falling edge of GTETRGA input #0 1 Enable counter stop on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Disable counter stop on the rising edge of GTETRGA input #0 1 Enable counter stop on the rising edge of GTETRGA input #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xFFFFFFFF CCLR Software Source Counter Clear Enable 31 31 read-write 0 Disable counter clear by the GTCLR register #0 1 Enable counter clear by the GTCLR register #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Disable counter clear on ELC_GPTH input #0 1 Enable counter clear on ELC_GPTH input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Disable counter clear on ELC_GPTG input #0 1 Enable counter clear on ELC_GPTG input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Disable counter clear on ELC_GPTF input #0 1 Enable counter clear on ELC_GPTF input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Disable counter clear on ELC_GPTE input #0 1 Enable counter clear on ELC_GPTE input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Disable counter clear on ELC_GPTD input #0 1 Enable counter clear on ELC_GPTD input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Disable counter clear on ELC_GPTC input #0 1 Enable counter clear on ELC_GPTC input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Disable counter clear on ELC_GPTB input #0 1 Enable counter clear on ELC_GPTB input #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Disable counter clear on ELC_GPTA input #0 1 Enable counter clear on ELC_GPTA input #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 15 read-write 0 Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 14 read-write 0 Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 13 read-write 0 Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 12 read-write 0 Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 11 read-write 0 Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 10 read-write 0 Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 9 read-write 0 Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 8 read-write 0 Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Disable counter clear on the falling edge of GTETRGD input #0 1 Enable counter clear on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Disable counter clear on the falling edge of GTETRGC input #0 1 Enable counter clear on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Disable counter clear on the falling edge of GTETRGB input #0 1 Enable counter clear on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Disable counter clear on the falling edge of GTETRGA input #0 1 Enable counter clear on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Disable counter clear on the rising edge of GTETRGA input #0 1 Enable counter clear on the rising edge of GTETRGA input #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Disable counter count up on ELC_GPTH input #0 1 Enable counter count up on ELC_GPTH input. #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Disable counter count up on ELC_GPTG input #0 1 Enable counter count up on ELC_GPTG input. #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Disable counter count up on ELC_GPTF input #0 1 Enable counter count up on ELC_GPTF input. #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Disable counter count up on ELC_GPTE input #0 1 Enable counter count up on ELC_GPTE input.put #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Disable counter count up on ELC_GPTD input #0 1 Enable counter count up on ELC_GPTD input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Disable counter count up on ELC_GPTC input #0 1 Enable counter count up on ELC_GPTC input. #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Disable counter count up on ELC_GPTB input #0 1 Enable counter count up on ELC_GPTB input. #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Disable counter count up on ELC_GPTA input #0 1 Enable counter count up on ELC_GPTA input. #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 15 read-write 0 Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1. #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 14 read-write 0 Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0. #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 13 read-write 0 Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1. #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 12 read-write 0 Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0. #1 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 11 read-write 0 Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1. #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 10 read-write 0 Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0. #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 9 read-write 0 Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1. #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 8 read-write 0 Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0. #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Disable counter count up on the falling edge of GTETRGD input #0 1 Enable counter count up on the falling edge of GTETRGD input. #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Disable counter count up on the rising edge of GTETRGD input #0 1 Enable counter count up on the rising edge of GTETRGD input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Disable counter count up on the falling edge of GTETRGC input #0 1 Enable counter count up on the falling edge of GTETRGC input. #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Disable counter count up on the rising edge of GTETRGC input #0 1 Enable counter count up on the rising edge of GTETRGC input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Disable counter count up on the falling edge of GTETRGB input #0 1 Enable counter count up on the falling edge of GTETRGB input. #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Disable counter count up on the rising edge of GTETRGB input #0 1 Enable counter count up on the rising edge of GTETRGB input. #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Disable counter count up on the falling edge of GTETRGA input #0 1 Enable counter count up on the falling edge of GTETRGA input. #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Disable counter count up on the rising edge of GTETRGA input #0 1 Enable counter count up on the rising edge of GTETRGA input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xFFFFFFFF DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 23 read-write 0 Disable counter count down on ELC_GPTH input #0 1 Enable counter count down on ELC_GPTH input. #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Disable counter count down on ELC_GPTG input #0 1 Enable counter count down on ELC_GPTG input. #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Disable counter count down on ELC_GPTF input #0 1 Enable counter count down on ELC_GPTF input. #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Disable counter count down on ELC_GPTE input #0 1 Enable counter count down on ELC_GPTE input. #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Disable counter count down on ELC_GPTD input #0 1 Enable counter count down on ELC_GPTD input. #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Disable counter count down on ELC_GPTC input #0 1 Enable counter count down on ELC_GPTC input. #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Disable counter count down on ELC_GPTB input #0 1 Enable counter count down on ELC_GPTB input. #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Disable counter count down on ELC_GPTA input #0 1 Enable counter count down on ELC_GPTA input. #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 15 read-write 0 Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1. #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 14 read-write 0 Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0. #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 13 read-write 0 Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1. #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 12 read-write 0 Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0. #1 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 11 read-write 0 Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1. #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 10 read-write 0 Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 9 read-write 0 Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1. #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 8 read-write 0 Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0. #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Disable counter count down on the falling edge of GTETRGD input #0 1 Enable counter count down on the falling edge of GTETRGD input. #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Disable counter count down on the rising edge of GTETRGD input #0 1 Enable counter count down on the rising edge of GTETRGD input. #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Disable counter count down on the falling edge of GTETRGC input #0 1 Enable counter count down on the falling edge of GTETRGC input. #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Disable counter count down on the rising edge of GTETRGC input #0 1 Enable counter count down on the rising edge of GTETRGC input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Disable counter count down on the falling edge of GTETRGB input #0 1 Enable counter count down on the falling edge of GTETRGB input. #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Disable counter count down on the rising edge of GTETRGB input #0 1 Enable counter count down on the rising edge of GTETRGB input. #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Disable counter count down on the falling edge of GTETRGA input #0 1 Enable counter count down on the falling edge of GTETRGA input. #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Disable counter count down on the rising edge of GTETRGA input #0 1 Enable counter count down on the rising edge of GTETRGA input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xFFFFFFFF ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 Disable GTCCRA input capture on ELC_GPTH input #0 1 Enable GTCCRA input capture on ELC_GPTH input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 Disable GTCCRA input capture on ELC_GPTG input #0 1 Enable GTCCRA input capture on ELC_GPTG input. #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 Disable GTCCRA input capture on ELC_GPTF input #0 1 Enable GTCCRA input capture on ELC_GPTF input. #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 Disable GTCCRA input capture on ELC_GPTE input #0 1 Enable GTCCRA input capture on ELC_GPTE input. #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 Disable GTCCRA input capture on ELC_GPTD input #0 1 Enable GTCCRA input capture on ELC_GPTD input. #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 Disable GTCCRA input capture on ELC_GPTC input #0 1 Enable GTCCRA input capture on ELC_GPTC input. #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 Disable GTCCRA input capture on ELC_GPTB input #0 1 Enable GTCCRA input capture on ELC_GPTB input #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 Disable GTCCRA input capture on ELC_GPTA input #0 1 Enable GTCCRA input capture on ELC_GPTA input. #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1. #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0. #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1. #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0. #1 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1. #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0. #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1. #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0. #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGD input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGD input. #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGD input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGD input. #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGC input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGC input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGC input. #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGB input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGB input. #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGB input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGB input. #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGA input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGA input. #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGA input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGA input. #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xFFFFFFFF BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 Disable GTCCRB input capture on ELC_GPTH input #0 1 Enable GTCCRB input capture on ELC_GPTH input. #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 Disable GTCCRB input capture on ELC_GPTG input #0 1 Enable GTCCRB input capture on ELC_GPTG input. #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 Disable GTCCRB input capture on ELC_GPTF input #0 1 Enable GTCCRB input capture on ELC_GPTF input. #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 Disable GTCCRB input capture on ELC_GPTE input #0 1 Enable GTCCRB input capture on ELC_GPTE input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 Disable GTCCRB input capture on ELC_GPTD input #0 1 Enable GTCCRB input capture on ELC_GPTD input. #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 Disable GTCCRB input capture on ELC_GPTC input #0 1 Enable GTCCRB input capture on ELC_GPTC input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 Disable GTCCRB input capture on ELC_GPTB input #0 1 Enable GTCCRB input capture on ELC_GPTB input. #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 Disable GTCCRB input capture on ELC_GPTA input #0 1 Enable GTCCRB input capture on ELC_GPTA input. #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1. #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0. #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1. #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0. #1 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1. #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0. #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1. #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0. #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGD input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGD input. #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGD input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGD input. #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGC input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGC input. #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGC input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGC input. #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGB input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGB input. #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGB input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGB input. #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGA input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGA input. #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGA input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGA input. #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xFFFFFFFF TPCS Timer Prescaler Select 24 26 read-write 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 others Setting prohibited true MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xFFFFFFFF OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0percent/100percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0percent/100percent duty setting. #1 OBDTYF Forcible GTIOCB Output Duty Setting 26 26 read-write 0 Do not force setting #0 1 Force setting #1 OBDTY GTIOCB Output Duty Setting 24 25 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0percent #10 11 GTIOCB pin duty 100percent #11 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OADTYF Forcible GTIOCA Output Duty Setting 18 18 read-write 0 Do not force setting #0 1 Force setting #1 OADTY GTIOCA Output Duty Setting 16 17 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 UDF Forcible Count Direction Setting 1 1 read-write 0 Do not force setting #0 1 Force setting #1 UD Count Direction Setting 0 0 read-write 0 Count down on GTCNT #0 1 Counts up on GTCNT #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xFFFFFFFF NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFBEN Noise Filter B Enable 29 29 read-write 0 Disable noise filter for GTIOCB pin #0 1 Enable noise filter for GTIOCB pin #1 OBDF GTIOCB Pin Disable Value Setting 25 26 read-write 00 Prohibit output disable #00 01 Set GTIOCB pin to Hi-Z on output disable #01 10 Set GTIOCB pin to 0 on output disable #10 11 Set GTIOCB pin to 1 on output disable. #11 OBE GTIOCB Pin Output Enable 24 24 read-write 0 Disable output #0 1 Enable output #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 Set GTIOCB pin output level on counting start and stop based on the register setting #0 1 Retain GTIOCB pin output level on counting start and stop #1 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 22 read-write 0 Output low on GTIOCB pin when counting stops #0 1 Output high on GTIOCB pin when counting stops #1 GTIOB GTIOCB Pin Function Select 16 20 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFAEN Noise Filter A Enable 13 13 read-write 0 Disable noise filter for GTIOCA pin #0 1 Enable noise filter for GTIOCA pin. #1 OADF GTIOCA Pin Disable Value Setting 9 10 read-write 00 Prohibit output disable #00 01 Set GTIOCA pin to Hi-Z on output disable #01 10 Set GTIOCA pin to 0 on output disable #10 11 Set GTIOCA pin to 1 on output disable. #11 OAE GTIOCA Pin Output Enable 8 8 read-write 0 Disable output #0 1 Enable output. #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 Set GTIOCA pin output level on counting start and stop based on the register setting. #0 1 Retain GTIOCA pin output level on counting start and stop #1 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 6 read-write 0 Output low on GTIOCA pin when counting stops #0 1 Output high on GTIOCA pin when counting stops. #1 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xFFFFFFFF GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Disable same time output level low disable request #0 1 Enable same time output level low disable request #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Disable same time output level high disable request #0 1 Enable same time output level high disable request #1 GRPDTE Dead Time Error Output Disable Request Enable 28 28 read-write 0 Disable dead time error output disable request #0 1 Enable dead time error output disable request #1 GRP Output Disable Source Select 24 25 read-write 00 Select Group A output disable request #00 01 Select Group B output disable request #01 10 Select Group C output disable request #10 11 Select Group D output disable request. #11 ADTRBDEN GTADTRB Compare Match (Down-Counting) A/D Converter Start Request Interrupt Enable 19 19 read-write 0 Disable A/D converter start request #0 1 Enable A/D converter start request. #1 ADTRBUEN GTADTRB Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable 18 18 read-write 0 Disable A/D converter start request #0 1 Enable A/D converter start request. #1 ADTRADEN GTADTRA Compare Match (Down-Counting) A/D Converter Start Request Interrupt Enable 17 17 read-write 0 Disable A/D converter start request #0 1 Enable A/D converter start request. #1 ADTRAUEN GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable 16 16 read-write 0 Disable A/D converter start request #0 1 Enable A/D converter start request. #1 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xFFFFFFFF OABLF Same Time Output Level Low Disable Request Enable 30 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 OABHF Same Time Output Level High Disable Request Enable 29 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 DTEF Dead Time Error Flag 28 28 read-only 0 No dead time error has occurred. #0 1 A dead time error has occurred. #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter is counting down #0 1 GTCNT counter is counting up. #1 ITCNT GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) 8 10 read-only TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCFPO Overflow Flag 6 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xFFFFFFFF ADTDB GTADTRB Double Buffer Operation 30 30 read-write 0 Single buffer operation (GTADTBRB --> GTADTRB) #0 1 Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) #1 ADTTB GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. 28 29 read-write 00 No transfer #00 01 Transfer at crest #01 10 Transfer at trough #10 11 Transfer at both crest and trough #11 ADTDA GTADTRA Double Buffer Operation 26 26 read-write 0 Single buffer operation (GTADTBRA --> GTADTRA) #0 1 Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) #1 ADTTA GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. 24 25 read-write 00 No transfer #00 01 Transfer at crest #01 10 Transfer at trough #10 11 Transfer at both crest and trough #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 21 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 10 Double buffer operation (GTPDBR --> GTPBR --> GTPR) #10 11 Double buffer operation (GTPDBR --> GTPBR --> GTPR) #11 CCRB GTCCRB Buffer Operation 18 19 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRA GTCCRA Buffer Operation 16 17 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 BD BD[3]: GTDV Buffer Operation DisableBD[2]: GTADTR Buffer Operation DisableBD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 3 read-write 0 Enable buffer operation #0 1 Disable buffer operation #1 GTITC General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register 0x44 32 read-write 0x00000000 0xFFFFFFFF ADTBL GTADTRB A/D Converter Start Request Link 14 14 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ADTAL GTADTRA A/D Converter Start Request Link 12 12 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function #1 IVTT GPT_OVF/GPT_UDF Interrupt Skipping Count Select 8 10 read-write 000 No skipping #000 001 Skipping count of 1 #001 010 Skipping count of 2 #010 011 Skipping count of 3 #011 100 Skipping count of 4 #100 101 Skipping count of 5 #101 110 Skipping count of 6 #110 111 Skipping count of 7. #111 IVTC GPT_OVF/GPT_UDF Interrupt Skipping Function Select 6 7 read-write 00 Do not perform skipping #00 01 Count and skip both overflow and underflow for saw waves and crest for triangle waves #01 10 Count and skip both overflow and underflow for saw waves and trough for triangle waves #10 11 Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. #11 ITLF GTCCRF Compare Match Interrupt Link 5 5 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLE GTCCRE Compare Match Interrupt Link 4 4 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLD GTCCRD Compare Match Interrupt Link 3 3 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLC GTCCRC Compare Match Interrupt Link 2 2 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLB GTCCRB Compare Match/Input Capture Interrupt Link 1 1 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 ITLA GTCCRA Compare Match/Input Capture Interrupt Link 0 0 read-write 0 Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xFFFFFFFF GTCNT Counter 0 31 read-write GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRC Compare Capture Register C 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRE Compare Capture Register E 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRD Compare Capture Register D 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRF Compare Capture Register F 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPR Cycle Setting Register 0 31 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPBR Cycle Setting Buffer Register 0 31 read-write GTPDBR General PWM Timer Cycle Setting Double-Buffer Register 0x6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPDBR Cycle Setting Double-Buffer Register 0 31 read-write GTADTRA A/D Converter Start Request Timing Register A 0x70 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTRA A/D Converter Start Request Timing Register A 0 31 read-write GTADTRB A/D Converter Start Request Timing Register B 0x7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTRB A/D Converter Start Request Timing Register B 0 31 read-write GTADTBRA A/D Converter Start Request Timing Buffer Register A 0x74 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTBRA A/D Converter Start Request Timing Buffer Register A 0 31 read-write GTADTBRB A/D Converter Start Request Timing Buffer Register B 0x80 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTBRB A/D Converter Start Request Timing Buffer Register B 0 31 read-write GTADTDBRA A/D Converter Start Request Timing Double-Buffer Register A 0x78 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTDBRA A/D Converter Start Request Timing Double-Buffer Register A 0 31 read-write GTADTDBRB A/D Converter Start Request Timing Double-Buffer Register B 0x84 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTADTDBRB A/D Converter Start Request Timing Double-Buffer Register B 0 31 read-write GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xFFFFFFFF TDFER GTDVD Setting 8 8 read-write 0 Set GTDVU and GTDVD separately #0 1 Automatically set the value written to GTDVU to GTDVD #1 TDBDE GTDVD Buffer Operation Enable 5 5 read-write 0 Disable GTDVD buffer operation #0 1 Enable GTDVD buffer operation #1 TDBUE GTDVU Buffer Operation Enable 4 4 read-write 0 Disable GTDVU buffer operation #0 1 Enable GTDVU buffer operation #1 TDE Negative-Phase Waveform Setting 0 0 read-write 0 Set GTCCRB without using GTDVU and GTDVD. #0 1 Use GTDVU and GTDVD to set the compare match value for negative-phase waveform with automatic dead time in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDVU Dead Time Value Register U 0 31 read-write GTDVD General PWM Timer Dead Time Value Register D 0x90 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDVD Dead Time Value Register D 0 31 read-write GTDBU General PWM Timer Dead Time Buffer Register U 0x94 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDVU Dead Time Buffer Register U 0 31 read-write GTDBD General PWM Timer Dead Time Buffer Register D 0x98 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDBD Dead Time Buffer Register D 0 31 read-write GTSOS General PWM Timer Output Protection Function Status Register 0x9C 32 read-only 0x00000000 0xFFFFFFFF SOS Output Protection Function Status 0 1 read-only 00 Normal operation #00 01 Protected state (GTCCRA = 0 is set during transfer at trough or crest) #01 10 Protected state (GTCCRA >= GTPR is set during transfer at trough) #10 11 Protected state (GTCCRA >= GTPR is set during transfer at crest) #11 GTSOTR General PWM Timer Output Protection Function Temporary Release Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF SOTR Output Protection Function Temporary Release 0 0 read-write 0 Do not release protected state #0 1 Release protected state #1 GPT32EH1 General PWM Timer 1 (32-bit Enhanced High Resolution) 0x40078100 GPT32EH2 General PWM Timer 2 (32-bit Enhanced High Resolution) 0x40078200 GPT32EH3 General PWM Timer 3 (32-bit Enhanced High Resolution) 0x40078300 GPT32E4 General PWM Timer 4 (32-bit Enhanced) 0x40078400 GPT32E5 General PWM Timer 5 (32-bit Enhanced) 0x40078500 GPT32E6 General PWM Timer 6 (32-bit Enhanced) 0x40078600 GPT32E7 General PWM Timer 7 (32-bit Enhanced) 0x40078700 USBHS USB 2.0 High-Speed Module 0x40060000 0x00 10 registers 0x0C 2 registers 0x14 4 registers 0x14 4 registers 0x14 8 registers 0x18 4 registers 0x18 8 registers 0x1C 4 registers 0x1C 6 registers 0x28 2 registers 0x2C 2 registers 0x22 2 registers 0x2A 2 registers 0x2E 6 registers 0x36 14 registers 0x46 12 registers 0x54 14 registers 0x64 2 registers 0x68 26 registers 0x90 20 registers 0x92 20 registers 0xD0 22 registers 0x100 4 registers 0x140 2 registers 0x144 8 registers 0x150 4 registers 0x160 12 registers SYSCFG System Configuration Control Register 0x000 16 read-write 0x0020 0x01F1 CNEN Single End Receiver Enable 8 8 read-write 0 Single end receiver operation is disabled. #0 1 Single end receiver operation is enabled. #1 HSE High-Speed Operation Enable 7 7 read-write 0 High-speed operation is disabled.(When the function controller function is selected: Full speed, When the host controller function is selected: Full/low speed) #0 1 High-speed operation is enabled (the controller detects the communication speed). #1 DCFM Controller Function Select 6 6 read-write 0 Function controller function is selected. #0 1 Host controller function is selected. #1 DRPD D+/D- Line Resistor Control 5 5 read-write 0 Pulling down the line is disabled. #0 1 Pulling down the line is enabled. #1 DPRPU D+ Line Resistor Control 4 4 read-write 0 Pulling up the line is disabled. #0 1 Pulling up the line is enabled. #1 USBE USB Operation Enable 0 0 read-write 0 USB operation is disabled. #0 1 USB operation is enabled. #1 BUSWAIT CPU Bus Wait Register 0x002 16 read-write 0x000F 0x3F3F BWAIT CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) 0 3 read-write BWAIT BWAIT wait(s) ( BWAIT + 2 access cycles ) true SYSSTS0 System Configuration Status Register 0x004 16 read-only 0x0000 0x0060 OVCMON External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. 14 15 read-only HTACT Host Sequencer Status Monitor 6 6 read-only 0 Host sequencer is stopped. #0 1 Host sequencer is operating. #1 SOFEA SOF Active Monitor While Host Controller Function is Selected. 5 5 read-only 0 SOF output is stopped. #0 1 SOF output is operating. #1 IDMON ID0 Pin Monitor 2 2 read-only 0 ID0 = Low #0 1 ID0 = High #1 LNST USB Data Line Status Monitor 0 1 read-only 00 SE0 (During Low-Speed Operation:only when the host controller function is selected or During Full-Speed Operation) /Squelch (During Hi-Speed Operation or During Chirp Operation) #00 01 K-State (During Low-Speed Operation:only when the host controller function is selected) /J-State (During Full-Speed Operation) /Unsquelch (During Hi-Speed Operation) /Chirp J (During Chirp Operation) #01 10 J-State (During Low-Speed Operation:only when the host controller function is selected) /K-State (During Full-Speed Operation) /Invalid (During Hi-Speed Operation) /Chirp K (During Chirp Operation) #10 11 SE1 (During Low-Speed Operation:only when the host controller function is selected or During Full-Speed Operation) /Invalid (During Hi-Speed Operation or During Chirp Operation) #11 PLLSTA PLL Status Register 0x006 16 read-only 0x0000 0x0001 PLLLOCK PLL Lock Flag 0 0 read-only 0 PLL is not locked. #0 1 PLL is locked. #1 DVSTCTR0 Device State Control Register 0 0x008 16 read-write 0x0000 0x0FF7 HNPBTOA Host Negotiation Protocol (HNP) Control Use this bit when switching from device B to device A in OTGmode. If the HNPBTOA bit is 1, the internal function controlremains in the Suspend state until the HNP processing endseven if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. 11 11 read-write EXICEN USBHS_EXICEN Output Pin Control 10 10 read-write 0 Output low on external USBHS_EXICEN pin #0 1 Output high on external USBHS_EXICEN pin. #1 VBUSEN USBHS_VBUSEN Output Pin Control 9 9 read-write 0 Output low on external USBHS_VBUSEN pin #0 1 Output high on external USBHS_VBUSEN pin. #1 WKUP Remote Wakeup Output for the Device Controller Operation 8 8 read-write 0 Do not output remote wakeup signal #0 1 Output remote wakeup signal. #1 RWUPE Remote Wakeup Detection Enable for the Host Controller Operation 7 7 read-write 0 Disable downstream port remote wakeup #0 1 Enable downstream port remote wakeup. #1 USBRST USB Bus Reset Output for the Host Controller Operation 6 6 read-write 0 Do not output USB bus reset signal #0 1 Output USB bus reset signal. #1 RESUME Resume Signal Output for the Host Controller Operation 5 5 read-write 0 Do not output resume signal #0 1 Output resume signal. #1 UACT USB Bus Operation Enable for the Host Controller Operation 4 4 read-write 0 Disable downstream port (disable SOF or micro-SOF transmission) #0 1 Enable downstream port (enable SOF or micro-SOF transmission). #1 RHST USB Bus Reset Status 0 2 read-only 000 Communication speed not determined #000 001 Low-speed connection(When the host controller function is selected) /USB bus reset in progress or low-speed connection(When the function controller function is selected) #001 010 Full-speed connection(When the host controller function is selected) /USB bus reset in progress or full-speed connection(When the function controller function is selected) #010 011 Setting prohibited #011 others USB bus reset in progress(When the host controller function is selected) true TESTMODE USB Test Mode Register 0x00C 16 read-write 0x0000 0x000F UTST Test Mode 0 3 read-write 0000 Normal operation #0000 0001 Test_J TestMode(When the Function Controller Function is Selected) #0001 0010 Test_K TestMode(When the Function Controller Function is Selected) #0010 0011 Test_SE0_NAK TestMode(When the Function Controller Function is Selected) #0011 0100 Test_Packet TestMode(When the Function Controller Function is Selected) #0100 0101 Reserved TestMode(When the Function Controller Function is Selected) #0101 0110 Reserved TestMode(When the Function Controller Function is Selected) #0110 0111 Reserved TestMode(When the Function Controller Function is Selected) #0111 1001 Test_J TestMode(When the Host Controller Function is Selected) #1001 1010 Test_K TestMode(When the Host Controller Function is Selected) #1010 1011 Test_SE0_NAK TestMode(When the Host Controller Function is Selected) #1011 1100 Test_Packet TestMode(When the Host Controller Function is Selected) #1100 1101 Test_Force_EnableTestMode(When the Host Controller Function is Selected) #1101 1110 Reserved TestMode(When the Host Controller Function is Selected) #1110 1111 Reserved TestMode(When the Host Controller Function is Selected) #1111 CFIFO CFIFO Port Register 0x014 32 read-write 0x00000000 0xFFFFFFFF FIFOPORT FIFO Port.Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 31 read-write CFIFOL CFIFO Port Register L CFIFO 0x014 16 read-write 0x0000 0xFFFF CFIFOH CFIFO Port Register H CFIFO 0x016 16 read-write 0x0000 0xFFFF CFIFOLL CFIFO Port Register LL CFIFOL 0x014 8 read-write 0x00 0xFF CFIFOHH CFIFO Port Register HH CFIFOH 0x017 8 read-write 0x00 0xFF D0FIFO D0FIFO Port Register 0x018 32 read-write 0x00000000 0xFFFFFFFF FIFOPORT FIFO Port Read receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 31 read-write D0FIFOL D0FIFO Port Register L D0FIFO 0x018 16 read-write 0x0000 0xFFFF D0FIFOH D0FIFO Port Register H D0FIFO 0x01A 16 read-write 0x0000 0xFFFF D0FIFOLL D0FIFO Port Register LL D0FIFOL 0x018 8 read-write 0x00 0xFF D0FIFOHH D0FIFO Port Register HH D0FIFOH 0x01B 8 read-write 0x00 0xFF D1FIFO D1FIFO Port Register 0x01C 32 read-write 0x00000000 0xFFFFFFFF FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 31 read-write D1FIFOL D1FIFO Port Register L D1FIFO 0x01C 16 read-write 0x0000 0xFFFF D1FIFOH D1FIFO Port Register H D1FIFO 0x01E 16 read-write 0x0000 0xFFFF D1FIFOLL D1FIFO Port Register LL D1FIFOL 0x01C 8 read-write 0x00 0xFF D1FIFOHH D1FIFO Port Register HH D1FIFOH 0x01F 8 read-write 0x00 0xFF CFIFOSEL CFIFO Port Select Register 0x020 16 read-write 0x0000 0xCD2F RCNT Read Count Mode 15 15 read-write 0 Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from CFIFO #0 1 Decrement DTLN[11:0] flags each time receive data is read from CFIFO. #1 REW Buffer Pointer Rewind 14 14 write-only 0 Do not rewind buffer pointer (Writing 0 has no effect.) #0 1 Rewind buffer pointer. #1 MBW CFIFO Port Access Bit Width 10 11 read-write 00 8-bit width #00 01 16-bit width #01 10 32-bit width #10 11 Setting prohibited #11 BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 ISEL FIFO Port Access Direction when DCP is Selected 5 5 read-write 0 Select reading from the FIFO buffer #0 1 Select writing to the FIFO buffer. #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP #0000 0001 PIPE1 #0001 0010 PIPE2 #0010 0011 PIPE3 #0011 0100 PIPE4 #0100 0101 PIPE5 #0101 0110 PIPE6 #0110 0111 PIPE7 #0111 1000 PIPE8 #1000 1001 PIPE9 #1001 others Setting prohibited true D0FIFOSEL D0FIFO Port Select Register 0x028 16 read-write 0x0000 0xFD0F RCNT Read Count Mode 15 15 read-write 0 The DTLN bits are cleared when all of the receive data has been read from the CFIFO #0 1 The DTLN bits are decremented each time the receive data is read from the CFIFO #1 REW Buffer Pointer Rewind 14 14 write-only 0 The buffer pointer is not rewound #0 1 The buffer pointer is rewound #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled #0 1 Auto buffer clear mode is enabled #1 DREQE UCL_Dx_DREQ Signal Output Enable 12 12 read-write 0 Disables the output #0 1 Enables the output #1 MBW FIFO Port Access Bit Width 10 11 read-write 00 8-bit width #00 01 16-bit width #01 10 32-bit width #10 11 Setting prohibited #11 BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 No pipe specified #0000 0001 Pipe1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true D1FIFOSEL D1FIFO Port Select Register 0x02C 16 read-write 0x0000 0xFD0F RCNT Read Count Mode 15 15 read-write 0 The DTLN bits are cleared when all of the receive data has been read from the CFIFO #0 1 The DTLN bits are decremented each time the receive data is read from the CFIFO #1 REW Buffer Pointer Rewind 14 14 write-only 0 The buffer pointer is not rewound #0 1 The buffer pointer is rewound #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled #0 1 Auto buffer clear mode is enabled #1 DREQE UCL_Dx_DREQ Signal Output Enable 12 12 read-write 0 Disables the output #0 1 Enables the output #1 MBW FIFO Port Access Bit Width 10 11 read-write 00 8-bit width #00 01 16-bit width #01 10 32-bit width #10 11 Setting prohibited #11 BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 No pipe specified #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true CFIFOCTR CFIFO Port Control Register 0x022 16 read-write 0x0000 0xEFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 write-only 0 No operation #0 1 Clear FIFO buffer on the CPU side. #1 FRDY FIFO Port ReadyIndicates whether the FIFO port can be accessed. 13 13 read-only 0 FIFO port access is disabled #0 1 FIFO port access is enabled #1 DTLN Receive Data Length.Indicates the length of the receive data. 0 11 read-only D0FIFOCTR D0FIFO Port Control Register 0x02A 16 read-write 0x0000 0xEFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 write-only 0 No operation #0 1 Clear FIFO buffer on the CPU side. #1 FRDY FIFO Port ReadyIndicates whether the FIFO port can be accessed. 13 13 read-only 0 FIFO port access is disabled #0 1 FIFO port access is enabled #1 DTLN Receive Data Length.Indicates the length of the receive data. 0 11 read-only D1FIFOCTR D1FIFO Port Control Register 0x02E 16 read-write 0x0000 0xEFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 write-only 0 No operation #0 1 Clear FIFO buffer on the CPU side. #1 FRDY FIFO Port ReadyIndicates whether the FIFO port can be accessed. 13 13 read-only 0 FIFO port access is disabled #0 1 FIFO port access is enabled #1 DTLN Receive Data Length.Indicates the length of the receive data. 0 11 read-only INTENB0 Interrupt Enable Register 0 0x030 16 read-write 0x0000 0xFF00 VBSE VBUS Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 RSME Resume Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFE Frame Number Update Interrupt Enable 13 13 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DVSE Device State Transition Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPE Buffer Empty Interrupt Enable 10 10 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYE Buffer Ready Interrupt Enable 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 INTENB1 Interrupt Enable Register 1 0x032 16 read-write 0x0000 0xDB71 OVRCRE OVRCRE Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BCHGE USB Bus Change Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DTCHE Disconnection Detection Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 ATTCHE Connection Detection Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 L1RSMENDE L1 Resume End Interrupt Enable 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 LPMENDE LPM Transaction End Interrupt Enable 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 EOFERRE EOF Error Detection Interrupt Enable 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SIGNE Setup Transaction Error Interrupt Enable 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SACKE Setup Transaction Normal Response Interrupt Enable 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PDDETINTE PDDETINT Detection Interrupt Enable 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYENB BRDY Interrupt Enable Register 0x036 16 read-write 0x0000 0xFFFF PIPEBRDYE BRDY Interrupt Enable for Each Pipe 0 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYENB NRDY Interrupt Enable Register 0x038 16 read-write 0x0000 0xFFFF PIPENRDYE NRDY Interrupt Enable for Each Pipe 0 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPENB BEMP Interrupt Enable Register 0x03A 16 read-write 0x0000 0xFFFF PIPEBEMPE BEMP Interrupt Enable for Each Pipe 0 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFCFG SOF Pin Configuration Register 0x03C 16 read-write 0x0000 0x017C TRNENSEL Transaction-Enabled Time Select.The transfer efficiency can be improved by setting this bit to 1 if no low-speed device is connected directly or via FS-HUB to the USB port. 8 8 read-write 0 For non-low-speed communication #0 1 For low-speed communication #1 BRDYM PIPEBRDY Interrupt Status Clear Timing.This bit can be set only in the initial setting (before communications).The setting cannot be changed once communication starts. 6 6 read-write 0 Software clears the status. #0 1 Hardware clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer. #1 INTL Interrupt Output Sense Select 5 5 read-write 0 Edge sense #0 1 Level sense #1 EDGESTS Interrupt Edge Processing Status Monitor 4 4 read-only 0 Interrupt edge processing is not run #0 1 Interrupt edge processing is running #1 PHYSET PHY Setting Register 0x03E 16 read-write 0x0033 0x0B3B HSEB CL-Only Mode 15 15 read-write 0 CL-only mode is not activated. #0 1 CL-only mode is activated. #1 REPSTART Forcibly Start Terminating Resistance Adjustment 11 11 read-write 0 Terminating resistance adjustment is forcibly started #0 1 Terminating resistance adjustment is not forcibly started #1 REPSEL Terminating Resistance Adjustment Cycle 8 9 read-write 00 No cycle is set. #00 01 Adjust terminating resistance at 16-second intervals. #01 10 Adjust terminating resistance at 64-second intervals. #10 11 Adjust terminating resistance at 128-second intervals. #11 CLKSEL Input System Clock Frequency 4 5 read-write 00 Setting Prohibited #00 01 12 MHz #01 10 20 MHz #10 11 24 MHz #11 CDPEN Charging Downstream Port Enable 3 3 read-write 0 Disable charging downstream port #0 1 Enable charging downstream port #1 PLLRESET PLL Reset Control 1 1 read-write 0 Disable PLL reset control for UTMI_PHY #0 1 Enable PLL reset control for UTMI_PHY #1 DIRPD Power-Down Control 0 0 read-write 0 Does not enter low-power consumption mode #0 1 Enter low-power consumption mode #1 INTSTS0 Interrupt Status Register 0 0x040 16 read-write 0x0000 0xFF7F VBINT VBUS Interrupt Status 15 15 read-write 0 VBUS interrupt is not generated on detecting a change in the USBHS_VBUS pin. #0 1 VBUS interrupt is generated on detecting a change in the USBHS_VBUS pin. #1 RESM Resume Interrupt Status 14 14 read-write 0 Resume interrupts are not generated #0 1 Resume interrupts are generated #1 SOFR Frame Number Refresh Interrupt Status 13 13 read-write 0 SOF interrupts are not generated #0 1 SOF interrupts are generated #1 DVST Device State Transition Interrupt Status 12 12 read-write 0 Device state transition interrupts are not generated #0 1 Device state transition interrupts are generated #1 CTRT Control Transfer Stage Transition Interrupt Status 11 11 read-write 0 Control transfer stage transition interrupts are not generated #0 1 Control transfer stage transition interrupts are generated #1 BEMP Buffer Empty Interrupt Status 10 10 read-only 0 BEMP interrupts are not generated #0 1 BEMP interrupts are not generated #1 NRDY Buffer Not Ready Interrupt Status 9 9 read-only 0 NRDY interrupts are not generated #0 1 NRDY interrupts are generated #1 BRDY Buffer Ready Interrupt Status 8 8 read-only 0 BRDY interrupts are not generated #0 1 BRDY interrupts are generated #1 VBSTS VBUS Input Status 7 7 read-only 0 The USBHS_VBUS pin is low #0 1 The USBHS_VBUS pin is high #1 DVSQ Device State 4 6 read-only 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 others Suspended state(1xx) true VALID USB Request Reception 3 3 read-write 0 Not detected #0 1 Setup packet reception #1 CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 111 Setting prohibited #111 INTSTS1 Interrupt Status Register 1 0x042 16 read-write 0x0000 0xDB71 OVRCR Overcurrent Interrupt Status 15 15 read-write zeroToClear modify 0 OVRCR interrupts are not generated #0 1 OVRCR interrupts are generated #1 BCHG USB Bus Change Interrupt Status 14 14 read-write zeroToClear modify 0 BCHG interrupts are not generated #0 1 BCHG interrupts are generated #1 DTCH USB Disconnection Detection Interrupt Status 12 12 read-write zeroToClear modify 0 DTCH interrupts are not generated #0 1 DTCH interrupts are generated #1 ATTCH USB Connection Detection Interrupt Status 11 11 read-write zeroToClear modify 0 ATTCH interrupts are not generated #0 1 ATTCH interrupts are generated #1 L1RSMEND L1 Resume End Interrupt Status 9 9 read-write zeroToClear modify 0 L1RSMEND interrupts are not generated #0 1 L1RSMEND interrupts are generated #1 LPMEND LPM Transaction End Interrupt Status 8 8 read-write zeroToClear modify 0 LPMEND interrupts are not generated #0 1 LPMEND interrupts are generated #1 EOFERR EOF Error Detection Interrupt Status 6 6 read-write zeroToClear modify 0 EOFERR interrupts are not generated #0 1 EOFERR interrupts are generated #1 SIGN Setup Transaction Error Interrupt Status 5 5 read-write zeroToClear modify 0 SIGN interrupts are not generated #0 1 SIGN interrupts are generated #1 SACK Setup Transaction Normal Response Interrupt Status 4 4 read-write zeroToClear modify 0 SACK interrupts are not generated #0 1 SACK interrupts are generated #1 PDDETINT PDDET Detection Interrupt Status 0 0 read-write zeroToClear modify 0 PDDET interrupts are not generated #0 1 PDDET interrupts are generated #1 BRDYSTS BRDY Interrupt Status Register 0x046 16 read-write 0x0000 0xFFFF PIPEBRDY BRDY Interrupt Status for Each Pipe 0 9 read-write 0 Interrupts are not generated #0 1 Interrupts are generated #1 NRDYSTS NRDY Interrupt Status Register 0x048 16 read-write 0x0000 0xFFFF PIPENRDY NRDY Interrupt Status for Each Pipe 0 9 read-write 0 Interrupts are not generated #0 1 Interrupts are generated #1 BEMPSTS BEMP Interrupt Status Register 0x04A 16 read-write 0x0000 0xFFFF PIPEBEMP BEMP Interrupt Status for Each Pipe 0 9 read-write 0 Interrupts are not generated #0 1 Interrupts are generated #1 FRMNUM Frame Number Register 0x04C 16 read-write 0x0000 0xC7FF OVRN Overrun/Underrun Detection Status 15 15 read-write 0 No error #0 1 An error occurred #1 CRCE CRC Error Detection Status 14 14 read-write 0 No error #0 1 An error occurred #1 FRNM Frame Number.Indicate the latest frame number. 0 10 read-only UFRMNUM uFrame Number Register 0x04E 16 read-write 0x0000 0x8007 DVCHG Device State Change 15 15 read-write 0 Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. #0 1 Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. #1 UFRNM MicroframeIndicate the microframe number. 0 2 read-only USBADDR USB Address Register 0x050 16 read-write 0x0000 0x077F STSRECOV0 Status Recovery 8 10 read-write 001 Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) #001 010 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected) #010 011 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) #011 100 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected) #100 101 Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) #101 110 Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected) #110 111 Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) #111 others Setting prohibited. true USBADDR USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully. 0 6 read-only USBREQ USB Request Type Register 0x054 16 read-write 0x0000 0xFFFF BREQUEST USB request bRequest value Finction controller selected : read-only Host controller selected : read-write 8 15 read-write BMREQUESTTYPE USB request bmRequestType value Finction controller selected : read-only Host controller selected : read-write 0 7 read-write USBVAL USB Request Value Register 0x056 16 read-write 0x0000 0xFFFF WVALUE Value of USB request wValue Finction controller selected : read-only Host controller selected : read-write 0 15 read-write USBINDX USB Request Index Register 0x058 16 read-write 0x0000 0xFFFF WINDEX Value of USB request wIndex Finction controller selected : read-only Host controller selected : read-write 0 15 read-write USBLENG USB Request Length Register 0x05A 16 read-write 0x0000 0xFFFF WLENGTH Value of USB request wLength Finction controller selected : read-only Host controller selected : read-write 0 15 read-write DCPCFG DCP Configuration Register 0x05C 16 read-write 0x0000 0x0190 CNTMD Continuous Transfer Mode 8 8 read-write 0 Non-continuous transfer mode #0 1 Continuous transfer mode #1 SHTNAK Pipe Blocking on End of Transfer 7 7 read-write 0 The pipe remains open after transfer ends. #0 1 The pipe is blocked after transfer ends. #1 DIR Transfer Direction 4 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 DCPMAXP DCP Maximum Packet Size Register 0x05E 16 read-write 0x0040 0xF07F DEVSEL Device SelectThese bits specify the address of the destination function device for control transfer when the host controller function is selected. 12 15 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 others setting prohibited true MXPS Maximum Packet SizeThese bits specify the maximum data payload (maximum packet size) for the DCP. 0 6 read-write DCPCTR DCP Control Register 0x060 16 read-write 0x0040 0xF1F7 BSTS Buffer Status 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 SUREQ SETUP Token Transmission 14 14 read-write 0 Writing is ignored. #0 1 Transmits the setup packet. #1 CSCLR Split Transaction CSPLIT Status Clear 13 13 read-write 0 Writing is ignored. #0 1 Clears the CSSTS bit to 0. #1 CSSTS Split Transaction COMPLETE SPLIT(CSPLIT) Status 12 12 read-only 0 START-SPLIT(SSPLIT) transaction processing is in progress or processing for devices that do not use Split Transaction is in progress. #0 1 The CSPLIT transaction processing is in progress. #1 SUREQCLR SUREQ Bit Clear 11 11 read-write 0 Writing is ignored. #0 1 Clears the SUREQ bit to 0. #1 SQCLR Toggle Bit Clear 8 8 read-write 0 Writing is ignored. #0 1 Specifies DATA0. #1 SQSET Toggle Bit Set 7 7 read-write 0 Writing is ignored. #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Monitor 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 The relevant pipe is not used for the USB bus. #0 1 The relevant pipe is in use for the USB bus. #1 PINGE PING Token Issue Enable 4 4 read-write 0 Issuing PING token is disabled. #0 1 Normal PING operation #1 CCPL Control Transfer End Enable 2 2 read-write 0 Completion of control transfer is disabled. #0 1 Completion of control transfer is enabled. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on buffer state) #01 10 STALL response #10 11 STALL response #11 PIPESEL Pipe Window Select Register 0x064 16 read-write 0x0000 0x000F PIPESEL Pipe Window SelectThese bits specify the pipe for registers at addresses 68H to 6EH. 0 3 read-write 0000 No pipe selected #0000 0001 PIPE1 #0001 0010 PIPE2 #0010 0011 PIPE3 #0011 0100 PIPE4 #0100 0101 PIPE5 #0101 0110 PIPE6 #0110 0111 PIPE7 #0111 1000 PIPE8 #1000 1001 PIPE9 #1001 others setting prohibited true PIPECFG Pipe Configuration Register 0x068 16 read-write 0x0000 0xC79F TYPE Transfer Type 14 15 read-write 00 Pipe not used #00 01 Bulk transfer #01 10 Interrupt transfer #10 11 Isochronous transfer #11 BFRE BRDY Interrupt Operation Specification 10 10 read-write 0 BRDY interrupt upon transmitting or receiving data #0 1 BRDY interrupt upon completion of reading data #1 DBLB Double Buffer Mode 9 9 read-write 0 Single buffer #0 1 Double buffer #1 CNTMD Continuous Transfer Mode 8 8 read-write 0 Discontinuous transfer mode #0 1 Continuous transfer mode #1 SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 The pipe is continued at the end of transfer. #0 1 The pipe is disabled at the end of transfer. #1 DIR Transfer Direction 4 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 EPNUM Endpoint Number 0 3 read-write 000 the selected pipe is not used #000 others specify the endpoint number for the selected pipe. true PIPEBUF Pipe Buffer Register 0x06A 16 read-write 0x0000 0x7CFF BUFSIZE Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes 10 14 read-write BUFSIZE ( BUFSIZE + 1 ) x 64 kbytes true BUFNMB Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h). 0 7 read-write 0x04 0x87 BUFNMB specify the FIFO buffer number of the selected pipe (04h to 87h). true PIPEMAXP Pipe Maximum Packet Size Register 0x06C 16 read-write 0x0000 0xF7FF DEVSEL Device SelectThese bits specify the address of the peripheral device when the host controller function is selected. 12 15 read-write 0x0 0xA DEVSEL Address=DEVSEL true MXPS Maximum Packet SizeThese bits specify the maximum data payload (maximum packet size) for the selected pipe.A size of 1h to 40h bytes can be set for PIPE6 to PIPE9. 0 10 read-write 0x01 0x40 MXPS Maximum packet size true PIPEPERI Pipe Cycle Control Register 0x06E 16 read-write 0x0000 0x1007 IFIS Isochronous IN Buffer Flush 12 12 read-write 0 The buffer is not flushed. #0 1 The buffer is flushed. #1 IITV Interval Error Detection IntervalThese bits specify the transfer interval timing for the selected pipe as n-th power of 2 of the frame timing. 0 2 read-write 9 0x002 1-9 PIPE%sCTR PIPE Control Register 0x070 16 read-write 0x0000 0xF7E3 BSTS Buffer StatusThis bit indicates the FIFO buffer status for the relevant pipe. 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 INBUFM Transmit Buffer MonitorThis bit indicates the FIFO buffer status for the relevant pipe in the transmitting direction. 14 14 read-only 0 No transmittable data is present in the FIFO buffer. #0 1 Transmittable data is present in the FIFO buffer. #1 CSCLR CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe 13 13 read-write 0 Writing is disabled. #0 1 The CSSTS bit is cleared. #1 CSSTS CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe 12 12 read-only 0 SSplit Transaction processing is in progress or transfer without Split Transaction is in progress. #0 1 CSplit Transaction processing is in progress. #1 ATREPM Auto Response ModeThis bit enables or disables auto response mode for the relevant pipe. 10 10 read-write 0 Auto response mode is disabled. #0 1 Auto response mode is enabled (Transmission: zero-length packet response, Reception: NAK response and NRDY interrupt) #1 ACLRM Auto Buffer Clear ModeThis bit enables or disables auto buffer clear mode for the relevant pipe 9 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 SQCLR Toggle Bit ClearThis bit is set to 1 when the expected value of the sequence toggle bit for the next transaction of the relevant pipe is cleared to DATA0 8 8 read-write 0 Writing is ignored. #0 1 Specifies DATA0. #1 SQSET Toggle Bit SetThis bit is set to 1 when the expected value of the sequence toggle bit for the next transaction of the relevant pipe is set for DATA1 7 7 read-write 0 Writing is ignored. #0 1 Specifies DATA1. #1 SQMON Toggle Bit ConfirmationThis bit indicates the expected value of the sequence toggle bit for the next transaction of the relevant pipe 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe BusyThis bit indicates whether the relevant pipe is being used for the USB bus 5 5 read-only 0 The relevant pipe is not used for the USB bus. #0 1 The relevant pipe is in use for the USB bus. #1 PID Response PIDThese bits specify the response type for the next transaction of the relevant pipe. 0 1 read-write 00 NAK response #00 01 BUF response (depending on buffer state) #01 10 STALL response #10 11 STALL response #11 5 0x004 1-5 PIPE%sTRE PIPE Transaction Counter Enable Register 0x090 16 read-write 0x0000 0x0300 TRENB Transaction Counter EnableEnables or disables the transaction counter function. 9 9 read-write 0 The transaction counter function is disabled. #0 1 The transaction counter function is enabled. #1 TRCLR Transaction Counter ClearSetting this bit to 1 allows clearing the transaction counter to 0. 8 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 5 0x004 1-5 PIPE%sTRN PIPE Transaction Counter Register 0x092 16 read-write 0x0000 0xFFFF TRNCNT Transaction CounterWhen writing to: Specify the number of total packets (number of transactions) to be received by the relevant PIPE.When read from: When TRENB = 0: Indicate the specified number of transactions.When TRENB = 1: Indicate the number of currently counted transactions. 0 15 read-write 10 0x002 0-9 DEVADD%s Device Address Configuration Register 0x0D0 16 read-write 0x0000 0x7FC0 UPPHUB Communication Target Connecting Hub Register 11 14 read-write 0x0000 0x1010 0000 Directly connected to the port of the USBHS. #0000 UPPHUB USB address of the hub true HUBPORT Communication Target Connecting Hub Port 8 10 read-write 000 Directly connected to the port of the USBHS. #000 others Port number of the hub true USBSPD Transfer Speed of Communication Target Device 6 7 read-write 00 DEVADDx is not used. #00 01 Low speed #01 10 Full speed #10 11 High speed #11 DEVADDA Device Address Configuration Register A 0x0E4 16 read-write 0x0000 0x7FC0 UPPHUB Communication Target Connecting Hub Register 11 14 read-write 0x0000 0x1010 0000 Directly connected to the port of the USBHS. #0000 UPPHUB USB address of the hub true HUBPORT Communication Target Connecting Hub Port 8 10 read-write 000 Directly connected to the port of the USBHS. #000 others Port number of the hub true USBSPD Transfer Speed of Communication Target Device 6 7 read-write 00 DEVADDA is not used. #00 01 Low speed #01 10 Full speed #10 11 High speed #11 LPCTRL Low Power Control Register 0x100 16 read-write 0x0000 0x0181 HWUPM Resume Return Mode Setting 7 7 read-write 0 Hardware does not recover while CPU clock inactive #0 1 Hardware recovers while CPU clock inactive. #1 LPSTS Low Power Status Register 0x102 16 read-write 0x0000 0x510B SUSPENDM UTMI SuspendM Control 14 14 read-write 0 UTMI suspension mode #0 1 UTMI normal mode #1 BCCTRL Battery Charging Control Register 0x140 16 read-write 0x0000 0x033F PDDETSTS PDDET Status 9 9 read-only 0 The PDDET pin is at low level. #0 1 The PDDET pin is at high level. #1 CHGDETSTS CHGDET Status 8 8 read-only 0 The CHGDET pin is at low level. #0 1 The CHGDET pin is at high level. #1 DCPMODE DCP Mode Control 5 5 read-write 0 The RDCP_DAT resistor is disabled #0 1 The RDCP_DAT resistor is enabled. #1 VDMSRCE VDMSRC Control 4 4 read-write 0 The VDM_SRC circuit is disabled. (Initial value) #0 1 The VDM_SRC circuit is enabled. #1 IDPSINKE IDPSINK Control 3 3 read-write 0 The IDP_SINK circuit is disabled. (Initial value) #0 1 The IDP_SINK circuit is enabled. #1 VDPSRCE VDPSRC Control 2 2 read-write 0 The VDP_SRC circuit is disabled. (Initial value) #0 1 The VDP_SRC circuit is enabled. #1 IDMSINKE IDMSINK Control 1 1 read-write 0 The IDM_SINK circuit is disabled. (Initial value) #0 1 The IDM_SINK circuit is enabled. #1 IDPSRCE IDPSRC Control 0 0 read-write 0 The IDP_SRC circuit is disabled. (Initial value) #0 1 The IDP_SRC circuit is enabled. #1 PL1CTRL1 Function L1 Control Register 1 0x144 16 read-write 0x0000 0x4FFF L1EXTMD PHY Control Mode at L1 Return 14 14 read-write 0 SUSPENDM is not set by hardware when Host K is received. #0 1 SUSPENDM is set by hardware when Host K is received. #1 HIRDTHR L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL. 8 11 read-write DVSQ DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0]. 4 7 read-only 0000 Powered state #0000 0001 Default state #0001 0010 Address state #0010 0011 Configured state #0011 0100 Suspended state #0100 0101 Suspended state #0101 0110 Suspended state #0110 0111 Suspended state #0111 1000 L1 state #1000 1001 L1 state #1001 1010 L1 state #1010 1011 L1 state #1011 others setting prohibited true L1NEGOMD L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11. 3 3 read-write 0 When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. #0 1 When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. #1 L1RESPMD L1 Response Mode 1 2 read-write 00 NYET #00 01 ACK #01 10 STALL #10 11 According to the L1NEGOMD bit #11 L1RESPEN L1 Response Enable 0 0 read-write 0 LPM is not supported. #0 1 LPM is supported. #1 PL1CTRL2 Function L1 Control Register 2 0x146 16 read-write 0x0000 0x1F00 RWEMON RWE Value Monitor 12 12 read-write 0 The RWE bit value of the LPM token received last is reflected. #0 1 The RWE bit value of the LPM token received last is reflected. #1 HIRDMON HIRD Value Monitor 8 11 read-write 0 The HIRD field value of the LPM token received last is reflected. #0 1 The HIRD field value of the LPM token received last is reflected. #1 HL1CTRL1 Host L1 Control Register 1 0x148 16 read-write 0x0000 0x0007 L1STATUS L1 Request Completion Status 1 2 read-only 00 ACK received #00 01 NYET received #01 10 STALL received #10 11 Transaction error #11 L1REQ L1 Transition Request 0 0 read-write 0 This bit is cleared to 0 by hardware when the LPM transaction is completed. #0 1 Set this bit to 1 when requesting a transition to the L1 state. #1 HL1CTRL2 Host L1 Control Register 2 0x14A 16 read-write 0x0000 0x9F0F BESL BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume. 15 15 read-write L1RWE LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token. 12 12 read-write HIRD LPM Token HIRD 8 11 read-write 0000 50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1) #0000 0001 125 us(BESL = 0) / 100 us(BESL = 1) #0001 0010 200 us(BESL = 0) / 150 us(BESL = 1) #0010 0011 275 us(BESL = 0) / 250 us(BESL = 1) #0011 0100 350 us(BESL = 0) / 350 us(BESL = 1) #0100 0101 425 us(BESL = 0) / 450 us(BESL = 1) #0101 0110 500 us(BESL = 0) / 950 us(BESL = 1) #0110 0111 575 us(BESL = 0) / 1950 us(BESL = 1) #0111 1000 650 us(BESL = 0) / 2950 us(BESL = 1) #1000 1001 725 us(BESL = 0) / 3950 us(BESL = 1) #1001 1010 800 us(BESL = 0) / 4950 us(BESL = 1) #1010 1011 875 us(BESL = 0) / 5950 us(BESL = 1) #1011 1100 950 us(BESL = 0) / 6950 us(BESL = 1) #1100 1101 1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1) #1101 1110 1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1) #1110 1111 1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1) #1111 L1ADDR LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token. 0 3 read-write DPUSR0R Deep Standby USB Transceiver Control/Pin Monitor Register 0x160 32 read-only 0x00000000 0xFF4FFFFF DVBSTSHM VBUS InputIndicates VBUS input signal on the HS side of USB port. 23 23 read-only DOVCBHM OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. 21 21 read-only DOVCAHM OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. 20 20 read-only DPUSR1R Deep Standby USB Suspend/Resume Interrupt Register 0x164 32 read-write 0x00000000 0xFFFFFFFF DVBSTSH Indication of Return from VBUS Interrupt Source 23 23 read-only 0 Indicates deep software standby mode #0 1 Indicates return from deep software standby mode #1 DOVCBH Indication of Return from OVRCURB Interrupt Source 21 21 read-only 0 Indicates deep software standby mode #0 1 Indicates return from deep software standby mode #1 DOVCAH Indication of Return from OVRCURA Interrupt Source 20 20 read-only 0 Indicates deep software standby mode #0 1 Indicates return from deep software standby mode #1 DVBSTSHE VBUS Interrupt Enable/Clear 7 7 read-write 0 Disables return from deep software standby mode #0 1 Enables return from deep software standby mode #1 DOVCBHE OVRCURB Interrupt Enable Clear 5 5 read-write 0 Disables return from deep software standby mode #0 1 Enables return from deep software standby mode #1 DOVCAHE OVRCURA Interrupt Enable Clear 4 4 read-write 0 Disables return from deep software standby mode #0 1 Enables return from deep software standby mode #1 DPUSR2R Deep Standby USB Suspend/Resume Interrupt Register 0x168 16 read-write 0x0000 0xFFFF DMINTE DM Interrupt Enable Clear 9 9 read-write 0 Disables return from deep software standby mode #0 1 Enables return from deep software standby mode #1 DPINTE DP Interrupt Enable Clear 8 8 read-write 0 Disables return from deep software standby mode #0 1 Enables return from deep software standby mode #1 DMVAL DM InputIndicates DM input signal on the HS side of USB port. 5 5 read-only DPVAL DP InputIndicates DP input signal on the HS side of USB port. 4 4 read-only DMINT Indication of Return from DM Interrupt Source 1 1 read-only 0 Indicates deep software standby mode #0 1 Indicates return from deep software standby mode #1 DPINT Indication of Return from DP Interrupt Source 0 0 read-only 0 Indicates deep software standby mode #0 1 Indicates return from deep software standby mode #1 DPUSRCR Deep Standby USB Suspend/Resume Command Register 0x16A 16 read-write 0x0000 0xFFFF FIXPHYPD USB Transceiver Control Fix for PLL 1 1 read-write 0 Normal mode #0 1 Go to/Return from deep software standby mode #1 FIXPHY USB Transceiver Control Fix 0 0 read-write 0 Normal mode #0 1 Go to/Return from deep software standby mode #1 SCI0 Serial Communication Interface 0 0x40070000 0x00 1 registers 0x00 3 registers 0x02 3 registers 0x04 1 registers 0x04 12 registers 0x0E 2 registers 0x0E 4 registers 0x10 2 registers 0x10 6 registers 0x14 4 registers 0x16 4 registers 0x18 4 registers 0x1A 3 registers SMR Serial Mode Register (SCMR.SMIF = 0) 0x00 8 read-write 0x00 0xFF CM Communications Mode 7 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 CHR Character Length(Valid only in asynchronous mode) 6 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 PE Parity Enable(Valid only in asynchronous mode) 5 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 3 read-write 0 1 stop bit #0 1 2 stop bits #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x00 8 read-write 0x00 0xFF GM GSM Mode 7 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 BLK Block Transfer Mode 6 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 BCP Stop Bit Length(Valid only in asynchronous mode) 2 3 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 BRR Bit Rate Register 0x01 8 read-write 0xFF 0xFF BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write SCR Serial Control Register (SCMR.SMIF = 0) 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 TXI interrupt request is disabled #0 1 TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 RXI and ERI interrupt requests are disabled #0 1 RXI and ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 TEIE Transmit End Interrupt Enable 2 2 read-write 0 TEI interrupt request is disabled #0 1 TEI interrupt request is enabled #1 CKE Clock Enable 0 1 read-write 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) true SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x02 8 read-write 0x00 0xFF TIE Transmit Interrupt Enable 7 7 read-write 0 A TXI interrupt request is disabled #0 1 A TXI interrupt request is enabled #1 RIE Receive Interrupt Enable 6 6 read-write 0 RXI and ERI interrupt requests are disabled #0 1 RXI and ERI interrupt requests are enabled #1 TE Transmit Enable 5 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 RE Receive Enable 4 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 MPIE Multi-Processor Interrupt EnableSet this bit to 0 in smart card interface mode. 3 3 read-write TEIE Transmit End Interrupt EnableSet this bit to 0 in smart card interface mode. 2 2 read-write CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 TDR Transmit Data Register 0x03 8 read-write 0xFF 0xFF TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB Multi-Processor Bit. Value of the multi-processor bit in the reception frame 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer. Sets the multi-processor bit for adding to the transmission frame 0 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 SSR_FIFO Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) SSR 0x04 8 read-write 0x80 0xFD TDFE Transmit FIFO data empty flag 7 7 read-write zeroToClear modify 0 The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. #0 1 The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number #1 RDF Receive FIFO data full flag 6 6 read-write zeroToClear modify 0 The quantity of receive data written in FRDR falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred. #0 1 A framing error has occurred. #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred. #0 1 A parity error has occurred. #1 TEND Transmit End Flag 2 2 read-write zeroToClear modify 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 DR Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) 0 0 read-write zeroToClear modify 0 Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) #0 1 Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x04 8 read-write 0x84 0xFF TDRE Transmit Data Empty Flag 7 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 RDRF Receive Data Full Flag 6 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 ORER Overrun Error Flag 5 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 ERS Error Signal Status Flag 4 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 PER Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 TEND Transmit End Flag 2 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 MPB This bit should be 0 in smart card interface mode. 1 1 read-only MPBT This bit should be 0 in smart card interface mode. 0 0 read-write RDR Receive Data Register 0x05 8 read-only 0x00 0xFF RDR RDR is an 8-bit register that stores receive data. 0 7 read-only SCMR Smart Card Mode Register 0x06 8 read-write 0xF2 0xFF BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SEMR Serial Extended Mode Register 0x07 8 read-write 0x00 0xFF RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 5 read-write 0 Noise cancellation function for the RXDn/TXDn input signal is disabled. #0 1 Noise cancellation function for the RXDn/TXDn input signal is enabled. #1 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BRME Bit Modulation Enable 2 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 SNFR Noise Filter Setting Register 0x08 8 read-write 0x00 0xFF NFCS Noise Filter Clock Select 0 2 read-write 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 others Settings prohibited. true SIMR1 I2C Mode Register 1 0x09 8 read-write 0x00 0xFF IICDL SSDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 7 read-write 00000 No output delay #00000 others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. true IICM Simple I2C Mode Select 0 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 SIMR2 I2C Mode Register 2 0x0A 8 read-write 0x00 0xFF IICACKT ACK Transmission Data 5 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 SIMR3 I2C Mode Register 3 0x0B 8 read-write 0x00 0xFF IICSCLS SCL Output Select 6 7 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 5 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 IICRSTAREQ Restart Condition Generation 1 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSTAREQ Start Condition Generation 0 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 SISR I2C Status Register 0x0C 8 read-only 0x00 0xCB IICACKR ACK Reception Data Flag 0 0 read-only 0 ACK received #0 1 NACK received #1 SPMR SPI Mode Register 0x0D 8 read-write 0x00 0xFF CKPH Clock Phase Select 7 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 MFF Mode Fault Flag 4 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master or slave mode selection 2 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 CTSE CTS Enable 1 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 SSE SSn# Pin Function Enable 0 0 read-write 0 SSn# pin function is disabled. #0 1 SSn# pin function is enabled. #1 TDRHL Transmit 9-bit Data Register 0x0E 16 read-write 0xFFFF 0xFFFF TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 read-write FTDRHL Transmit FIFO Data Register HL TDRHL 0x0E 16 write-only 0xFFFF 0xFFFF MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 9 9 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TDAT Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 write-only FTDRH Transmit FIFO Data Register H TDRHL 0x0E 8 write-only 0xFF 0xFF MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 1 1 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 TDATH Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 write-only FTDRL Transmit FIFO Data Register L TDRHL 0x0F 8 write-only 0xFF 0xFF TDATL Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 7 write-only RDRHL Receive 9-bit Data Register 0x10 16 read-only 0x0000 0xFFFF RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only FRDRHL Receive FIFO Data Register HL RDRHL 0x10 16 read-only 0x0000 0xFFFF RDF Receive FIFO data full flag(It is same as SSR.RDF) 14 14 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 ORER Overrun error flag(It is same as SSR.ORER) 13 13 read-only 0 No overrun error occurred. #0 1 An overrun error has occurred. #1 FER Framing error flag 12 12 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL. #0 1 A framing error has occurred at the first data of FRDRH and FRDRL. #1 PER Parity error flag 11 11 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL. #0 1 A parity error has occurred at the first data of FRDRH and FRDRL. #1 DR Receive data ready flag(It is same as SSR.DR) 10 10 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 9 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RDAT Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 read-only FRDRH Receive FIFO Data Register H RDRHL 0x10 8 read-only 0x00 0xFF RDF Receive FIFO data full flag(It is same as SSR.RDF) 6 6 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 ORER Overrun error flag(It is same as SSR.ORER) 5 5 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 FER Framing error flag 4 4 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL #0 1 A framing error has occurred at the first data of FRDRH and FRDRL #1 PER Parity error flag 3 3 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL #0 1 A parity error has occurred at the first data of FRDRH and FRDRL #1 DR Receive data ready flag(It is same as SSR.DR) 2 2 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 1 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 RDATH Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 read-only FRDRL Receive FIFO Data Register L RDRHL 0x11 8 read-only 0x00 0xFF RDATL Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. 0 7 read-only MDDR Modulation Duty Register 0x12 8 read-write 0xFF 0xFF MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write DCCR Data Compare Match Control Register 0x13 8 read-write 0x40 0xFF DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 IDSEL ID frame select Bit(Valid only in asynchronous mode(including multi-processor) 6 6 read-write 0 It's always compared data in spite of the value of the MPB bit. #0 1 It's compared data when the MPB bit is 1 ( ID frame ) only. #1 DFER Data Compare Match Framing Error Flag 4 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 DCMF Data Compare Match Flag 0 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 FCR FIFO Control Register 0x14 16 read-write 0xF800 0xFFFF RSTRG RTS# Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 12 15 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true RTRG Receive FIFO data trigger number 8 11 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true TTRG Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 4 7 read-write 0000 Trigger number 0 #0000 others Triger number n (n= 0-15) true DRES Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) 3 3 read-write 0 reception data full interrupt (RXI) #0 1 receive error interrupt (ERI) #1 TFRST Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) 2 2 read-write 0 The number of data stored in FTDRH and FTDRL register are NOT made 0 #0 1 The number of data stored in FTDRH and FTDRL register are made 0 #1 RFRST Receive FIFO Data Register Reset(Valid only in FCR.FM=1) 1 1 read-write 0 The number of data stored in FRDRH and FRDRL register are NOT made 0 #0 1 The number of data stored in FRDRH and FRDRL register are made 0 #1 FM FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 0 read-write 0 Non-FIFO mode #0 1 FIFO mode #1 FDR FIFO Data Count Register 0x16 16 read-only 0x0000 0xFFFF T Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 8 12 read-only R Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 0 4 read-only LSR Line Status Register 0x18 16 read-only 0x0000 0xFFFF PNUM Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 8 12 read-only FNUM Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 2 6 read-only ORER Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 0 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 CDR Compare Match Data Register 0x1A 16 read-write 0x0000 0xFFFF CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write SPTR Serial Port Register 0x1C 8 read-write 0x03 0xFF SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 2 read-write 0 The value of SPB2DT bit isn't output in TxD terminal. #0 1 The value of SPB2DT bit is output in TxD terminal. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 1 read-write 0 Low level is output in TxD terminal. #0 1 High level is output in TxD terminal. #1 RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 0 read-only 0 RXD terminal is the Low level. #0 1 RXD terminal is the High level. #1 SCI1 Serial Communication Interface 1 0x40070020 SCI2 Serial Communication Interface 2 0x40070040 SCI3 Serial Communication Interface 3 0x40070060 SCI4 Serial Communication Interface 4 0x40070080 SCI5 Serial Communication Interface 5 0x400700A0 SCI6 Serial Communication Interface 6 0x400700C0 SCI7 Serial Communication Interface 7 0x400700E0 SCI8 Serial Communication Interface 8 0x40070100 SCI9 Serial Communication Interface 9 0x40070120 IIC0 Inter-Integrated Circuit 0 0x40053000 0x00 16 registers 0x0B 6 registers 0x10 4 registers 0x15 3 registers ICCR1 I2C Bus Control Register 1 0x00 8 read-write 0x1F 0xFF ICE I2C Bus Interface Enable 7 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 CLO Extra SCL Clock Cycle Output 5 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 SOWP SCLO/SDAO Write Protect 4 4 write-only 0 Enables a value to be written in SCLO bit and SDAO bit. #0 1 Disables a value to be written in SCLO bit and SDAO bit. #1 SCLO SCL Output Control/Monitor 3 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAO SDA Output Control/Monitor 2 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SCLI SCL Line Monitor 1 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SDAI SDA Line Monitor 0 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 ICCR2 I2C Bus Control Register 2 0x01 8 read-write 0x00 0xFF BBSY Bus Busy Detection Flag 7 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 6 read-write 0 Slave mode #0 1 Master mode #1 TRS Transmit/Receive Mode 5 5 read-write 0 Receive mode #0 1 Transmit mode #1 SP Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 RS Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. 2 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 ST Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 ICMR1 I2C Bus Mode Register 1 0x02 8 read-write 0x08 0xFF MTWP MST/TRS Write Protect 7 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 6 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 BCWP BC Write Protect(This bit is read as 1.) 3 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 ICMR2 I2C Bus Mode Register 2 0x03 8 read-write 0x06 0xFF DLCS SDA Output Delay Clock Source Selection 7 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 SDDL SDA Output Delay Counter 4 6 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 TMOH Timeout H Count Control 2 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Selection 0 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x04 8 read-write 0x00 0xFF SMBS SMBus/I2C Bus Selection 7 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 RDRFS RDRF Flag Set Timing Selection 5 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 ACKWP ACKBT Write Protect 4 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 ACKBT Transmit Acknowledge 3 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKBR Receive Acknowledge 2 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 ICFER I2C Bus Function Enable Register 0x05 8 read-write 0x72 0xFF FMPE Fast-mode Plus Enable 7 7 read-write 0 No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #0 1 An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #1 SCLE SCL Synchronous Circuit Enable 6 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 NFE Digital Noise Filter Circuit Enable 5 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 NACKE NACK Reception Transfer Suspension Enable 4 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 SALE Slave Arbitration-Lost Detection Enable 3 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 MALE Master Arbitration-Lost Detection Enable 1 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 TMOE Timeout Function Enable 0 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICSER I2C Bus Status Enable Register 0x06 8 read-write 0x09 0xFF HOAE Host Address Enable 7 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 DIDE Device-ID Address Detection Enable 5 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 GCAE General Call Address Enable 3 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 SAR2E Slave Address Register 2 Enable 2 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 SAR1E Slave Address Register 1 Enable 1 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR0E Slave Address Register 0 Enable 0 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x07 8 read-write 0x00 0xFF TIE Transmit Data Empty Interrupt Request Enable 7 7 read-write 0 Transmit data empty interrupt request (TXI) is disabled. #0 1 Transmit data empty interrupt request (TXI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 6 read-write 0 Transmit end interrupt request (TEI) is disabled. #0 1 Transmit end interrupt request (TEI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 5 read-write 0 Receive data full interrupt request (RXI) is disabled. #0 1 Receive data full interrupt request (RXI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 ALIE Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICSR1 I2C Bus Status Register 1 0x08 8 read-write 0x00 0xFF HOA Host Address Detection Flag 7 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 DID Device-ID Address Detection Flag 5 5 read-write zeroToClear modify 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 GCA General Call Address Detection Flag 3 3 read-write zeroToClear modify 0 General call address is not detected. #0 1 General call address is detected. #1 AAS2 Slave Address 2 Detection Flag 2 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 AAS1 Slave Address 1 Detection Flag 1 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS0 Slave Address 0 Detection Flag 0 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 ICSR2 I2C Bus Status Register 2 0x09 8 read-write 0x00 0xFF TDRE Transmit Data Empty Flag 7 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 RDRF Receive Data Full Flag 5 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 NACKF NACK Detection Flag 4 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 STOP Stop Condition Detection Flag 3 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 START Start Condition Detection Flag 2 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 AL Arbitration-Lost Flag 1 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 TMOF Timeout Detection Flag 0 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 3 0x2 0-2 SARL%s Slave Address Register L%s 0x0A 8 read-write 0x00 0xFF SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write 3 0x2 0-2 SARU%s Slave Address Register U%s 0x0B 8 read-write 0x00 0xFF SVA9 10-Bit Address(bit9) 2 2 read-write SVA8 10-Bit Address(bit8) 1 1 read-write FS 7-Bit/10-Bit Address Format Selection 0 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write 0xFF 0xFF BRL Bit Rate Low-Level Period(Low-level period of SCL clock) 0 4 read-write ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write 0xFF 0xFF BRH Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write ICDRT I2C Bus Transmit Data Register 0x12 8 read-write 0xFF 0xFF ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICDRR I2C Bus Receive Data Register 0x13 8 read-only 0x00 0xFF ICDRR 8-bit register that stores the received data 0 7 read-only ICWUR I2C Bus Wake Up Unit Register 0x16 8 read-write 0x00 0xFF WUE Wake Up function Enable 7 7 read-write 0 Wake-up function is disabled #0 1 Wake-up function is enabled. #1 WUIE Wake Up Interrupt Request Enable 6 6 read-write 0 Wake Up Interrupt Request (WUI) is disabled. #0 1 Wake Up Interrupt Request (WUI) is enabled. #1 WUF Wake-Up Event Occurrence Flag 5 5 read-write 0 Slave address match during Wake-Up function. #0 1 Slave address not match during Wake-Up function. #1 WUACK Asynchronous/Synchronous Operation State Flag 4 4 read-write 0 State of synchronous operation #0 1 State of asynchronous operation #1 WUAFA Wake-Up Analog Filter Additional Selection 0 0 read-write 0 Do not add the Wake Up analog filter. #0 1 Add the Wake Up analog filter. #1 ICWUR2 I2C Bus Wake Up Unit Register 2 0x17 8 read-only 0x03 0xFF WUSYF Wake-Up function synchronous operation status flag 2 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition #1 WUASYF Wake-Up function asynchronous operation status flag 1 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition #1 WUSEN Wake-Up function synchronous enable 0 0 read-write 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 IIC1 Inter-Integrated Circuit 1 0x40053100 0x00 16 registers 0x0B 6 registers 0x10 4 registers 0x15 1 registers ICCR1 I2C Bus Control Register 1 0x00 8 read-write 0x1F 0xFF ICE I2C Bus Interface Enable 7 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 CLO Extra SCL Clock Cycle Output 5 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 SOWP SCLO/SDAO Write Protect 4 4 write-only 0 Enables a value to be written in SCLO bit and SDAO bit. #0 1 Disables a value to be written in SCLO bit and SDAO bit. #1 SCLO SCL Output Control/Monitor 3 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAO SDA Output Control/Monitor 2 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SCLI SCL Line Monitor 1 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SDAI SDA Line Monitor 0 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 ICCR2 I2C Bus Control Register 2 0x01 8 read-write 0x00 0xFF BBSY Bus Busy Detection Flag 7 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 6 read-write 0 Slave mode #0 1 Master mode #1 TRS Transmit/Receive Mode 5 5 read-write 0 Receive mode #0 1 Transmit mode #1 SP Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 RS Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. 2 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 ST Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 ICMR1 I2C Bus Mode Register 1 0x02 8 read-write 0x08 0xFF MTWP MST/TRS Write Protect 7 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 6 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 BCWP BC Write Protect(This bit is read as 1.) 3 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 ICMR2 I2C Bus Mode Register 2 0x03 8 read-write 0x06 0xFF DLCS SDA Output Delay Clock Source Selection 7 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 SDDL SDA Output Delay Counter 4 6 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 TMOH Timeout H Count Control 2 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Selection 0 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x04 8 read-write 0x00 0xFF SMBS SMBus/I2C Bus Selection 7 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 RDRFS RDRF Flag Set Timing Selection 5 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 ACKWP ACKBT Write Protect 4 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 ACKBT Transmit Acknowledge 3 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKBR Receive Acknowledge 2 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 ICFER I2C Bus Function Enable Register 0x05 8 read-write 0x72 0xFF FMPE Fast-mode Plus Enable 7 7 read-write 0 No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #0 1 An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #1 SCLE SCL Synchronous Circuit Enable 6 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 NFE Digital Noise Filter Circuit Enable 5 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 NACKE NACK Reception Transfer Suspension Enable 4 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 SALE Slave Arbitration-Lost Detection Enable 3 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 MALE Master Arbitration-Lost Detection Enable 1 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 TMOE Timeout Function Enable 0 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICSER I2C Bus Status Enable Register 0x06 8 read-write 0x09 0xFF HOAE Host Address Enable 7 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 DIDE Device-ID Address Detection Enable 5 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 GCAE General Call Address Enable 3 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 SAR2E Slave Address Register 2 Enable 2 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 SAR1E Slave Address Register 1 Enable 1 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR0E Slave Address Register 0 Enable 0 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x07 8 read-write 0x00 0xFF TIE Transmit Data Empty Interrupt Request Enable 7 7 read-write 0 Transmit data empty interrupt request (TXI) is disabled. #0 1 Transmit data empty interrupt request (TXI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 6 read-write 0 Transmit end interrupt request (TEI) is disabled. #0 1 Transmit end interrupt request (TEI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 5 read-write 0 Receive data full interrupt request (RXI) is disabled. #0 1 Receive data full interrupt request (RXI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 ALIE Arbitration-Lost Interrupt Request Enable 1 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICSR1 I2C Bus Status Register 1 0x08 8 read-write 0x00 0xFF HOA Host Address Detection Flag 7 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 DID Device-ID Address Detection Flag 5 5 read-write zeroToClear modify 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 GCA General Call Address Detection Flag 3 3 read-write zeroToClear modify 0 General call address is not detected. #0 1 General call address is detected. #1 AAS2 Slave Address 2 Detection Flag 2 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 AAS1 Slave Address 1 Detection Flag 1 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS0 Slave Address 0 Detection Flag 0 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 ICSR2 I2C Bus Status Register 2 0x09 8 read-write 0x00 0xFF TDRE Transmit Data Empty Flag 7 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 RDRF Receive Data Full Flag 5 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 NACKF NACK Detection Flag 4 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 STOP Stop Condition Detection Flag 3 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 START Start Condition Detection Flag 2 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 AL Arbitration-Lost Flag 1 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 TMOF Timeout Detection Flag 0 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 3 0x2 0-2 SARL%s Slave Address Register L%s 0x0A 8 read-write 0x00 0xFF SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write 3 0x2 0-2 SARU%s Slave Address Register U%s 0x0B 8 read-write 0x00 0xFF SVA9 10-Bit Address(bit9) 2 2 read-write SVA8 10-Bit Address(bit8) 1 1 read-write FS 7-Bit/10-Bit Address Format Selection 0 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write 0xFF 0xFF BRL Bit Rate Low-Level Period(Low-level period of SCL clock) 0 4 read-write ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write 0xFF 0xFF BRH Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write ICDRT I2C Bus Transmit Data Register 0x12 8 read-write 0xFF 0xFF ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICDRR I2C Bus Receive Data Register 0x13 8 read-only 0x00 0xFF ICDRR 8-bit register that stores the received data 0 7 read-only IIC2 Inter-Integrated Circuit 2 0x40053200 SYSTEM System Control 0x4001E000 0x20 5 registers 0x26 1 registers 0x28 3 registers 0x30 1 registers 0x32 1 registers 0x36 7 registers 0x3E 4 registers 0x52 2 registers 0x61 2 registers 0x413 1 registers 0x480 2 registers 0x490 1 registers 0x492 1 registers 0xA2 1 registers 0xA5 1 registers 0x0C 2 registers 0x1C 4 registers 0x92 1 registers 0x94 1 registers 0x98 4 registers 0xA0 1 registers 0xAA 1 registers 0x400 13 registers 0x40E 2 registers 0x0C 2 registers 0x1C 4 registers 0x92 1 registers 0x94 1 registers 0x98 4 registers 0xA0 1 registers 0xAA 1 registers 0x400 13 registers 0x40E 2 registers 0xE0 4 registers 0xE1 4 registers 0x417 5 registers 0xE0 4 registers 0xE1 4 registers 0x417 5 registers 0x41D 3 registers 0x4B0 3 registers 0x4B4 1 registers 0x4B6 1 registers 0x4B8 8 registers 0x500 512 registers 0x41D 3 registers 0x4B0 3 registers 0x4B4 1 registers 0x4B6 1 registers 0x4B8 8 registers 0x500 512 registers 0x3FE 2 registers 0x3FE 2 registers 0x410 2 registers 0xC0 2 registers 0x49A 1 registers 0x410 2 registers 0xC0 2 registers 0x49A 1 registers 0x416 1 registers 0x416 1 registers SCKDIVCR System Clock Division Control Register 0x020 32 read-write 0x22022222 0xFFFFFFFF FCK Flash IF Clock (FCLK) Select 28 30 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true ICK System Clock (ICLK) Select 24 26 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true BCK External Bus Clock (BCLK) Select 16 18 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true PCKA Peripheral Module Clock A (PCLKA) Select 12 14 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true PCKB Peripheral Module Clock B (PCLKB) Select 8 10 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true PCKC Peripheral Module Clock C (PCLKC) Select 4 6 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 others Setting prohibited true SCKDIVCR2 System Clock Division Control Register 2 0x024 8 read-write 0x40 0xFF UCK USB Clock (UCLK) Select 4 6 read-write 010 /3 #010 011 /4 #011 100 /5 #100 others Setting prohibited true SCKSCR System Clock Source Control Register 0x026 8 read-write 0x01 0xFF CKSEL Clock Source Select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator #011 100 Sub-clock oscillator #100 101 PLL #101 others Setting prohibited true PLLCCR PLL Clock Control Register 0x028 16 read-write 0x1300 0xFFFF PLLMUL PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0 8 13 read-write #010011 #111011 others Setting prohibited true PLSRCSEL PLL Clock Source Select 4 4 read-write 0 Main clock oscillator #0 1 HOCO #1 PLIDIV PLL Input Frequency Division Ratio Select 0 1 read-write 00 /1 #00 01 /2 #01 10 /3 #10 11 Setting prohibited #11 PLLCR PLL Control Register 0x02A 8 read-write 0x01 0xFF PLLSTP PLL Stop Control 0 0 read-write 0 Operate the PLL #0 1 Stop the PLL. #1 BCKCR External Bus Clock Control Register 0x030 8 read-write 0x00 0xFF BCLKDIV BCLK Pin Output Select 0 0 read-write 0 BCLK #0 1 BCLK/2 #1 MOSCCR Main Clock Oscillator Control Register 0x032 8 read-write 0x01 0xFF MOSTP Main Clock Oscillator Stop 0 0 read-write 0 Main clock oscillator is operating. #0 1 Main clock oscillator is stopped. #1 HOCOCR High-Speed On-Chip Oscillator Control Register 0x036 8 read-write 0x00 0xFE HCSTP HOCO Stop 0 0 read-write 0 Operate the HOCO clock #0 1 Stop the HOCO clock #1 MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x038 8 read-write 0x00 0xFF MCSTP MOCO Stop 0 0 read-write 0 Operate the MOCO clock #0 1 Stop the MOCO clock #1 FLLCR1 FLL Control Register 1 0x039 8 read-write 0x00 0xFF FLLEN FLL Enable 0 0 read-write 0 FLL function is disabled. #0 1 FLL function is enabled. #1 FLLCR2 FLL Control Register 2 0x03A 16 read-write 0x0000 0xFFFF FLLCNTL FLL Multiplication ControlMultiplication ratio of the FLL reference clock select 0 10 read-write OSCSF Oscillation Stabilization Flag Register 0x03C 8 read-only 0x00 0xFE PLLSF PLL Clock Oscillation Stabilization Flag 5 5 read-only 0 PLL clock is stopped or is not yet stable #0 1 PLL clock is stable, so is available for use as the system clock #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 3 read-only 0 Main clock oscillator is stopped (MOSTP = 1) or is not yet stable #0 1 Main clock oscillator is stable, so is available for use as the system clock #1 HOCOSF HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. 0 0 read-only 0 HOCO clock is stopped or is not yet stable #0 1 HOCO clock is stable, so is available for use as the system clock #1 CKOCR Clock Out Control Register 0x03E 8 read-write 0x00 0xFF CKOEN Clock out enable 7 7 read-write 0 Disable clock out #0 1 Enable clock out #1 CKODIV Clock out input frequency Division Select 4 6 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 111 /128 #111 CKOSEL Clock out source select 0 2 read-write 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 others Setting prohibited true TRCKCR Trace Clock Control Register 0x03F 8 read-write 0x01 0xFF TRCKEN Trace Clock operating Enable 7 7 read-write 0 Disable operation #0 1 Enable operation #1 TRCK Trace Clock operating frequency select 0 3 read-write 0000 /1 #0000 0001 /2 #0001 0010 /4 #0010 others Setting prohibited true OSTDCR Oscillation Stop Detection Control Register 0x040 8 read-write 0x00 0xFF OSTDE Oscillation Stop Detection Function Enable 7 7 read-write 0 Disable oscillation stop detection function #0 1 Enable oscillation stop detection function #1 OSTDIE Oscillation Stop Detection Interrupt Enable 0 0 read-write 0 Disable oscillation stop detection interrupt (do not notify the POEG) #0 1 Enable oscillation stop detection interrupt (notify the POEG) #1 OSTDSR Oscillation Stop Detection Status Register 0x041 8 read-write 0x00 0xFF OSTDF Oscillation Stop Detection Flag 0 0 read-write zeroToClear modify 0 Main clock oscillation stop not detected #0 1 Main clock oscillation stop detected #1 EBCKOCR External Bus Clock Output Control Register 0x052 8 read-write 0x00 0xFF EBCKOEN BCLK Pin Output Control 0 0 read-write 0 Disable EBCLK pin output (fixed high) #0 1 Enable EBCLK pin output #1 SDCKOCR SDRAM Clock Output Control Register 0x053 8 read-write 0x00 0xFF SDCKOEN SDCLK Pin Output Control 0 0 read-write 0 Disable SDCLK pin output (fixed high) #0 1 Enable SDCLK pin output #1 MOCOUTCR MOCO User Trimming Control Register 0x061 8 read-write 0x00 0xFF MOCOUTRM MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits 0 7 read-write HOCOUTCR HOCO User Trimming Control Register 0x062 8 read-write 0x00 0xFF HOCOUTRM HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits 0 7 read-write MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write 0x00 0xFF AUTODRVEN Main Clock Oscillator Drive Capability Auto Switching Enable 7 7 read-write 0 Disable #0 1 Enable. #1 MOSEL Main Clock Oscillator Switching 6 6 read-write 0 Resonator #0 1 External clock input #1 MODRV0 Main Clock Oscillator Drive Capability 0 Switching 4 5 read-write 00 20MHz to 24MHz #00 01 16MHz to 20MHz #01 10 8MHz to 16MHz #10 11 8MHz #11 SOSCCR Sub-clock oscillator control register 0x480 8 read-write 0x00 0xFF SOSTP Sub-Clock Oscillator Stop 0 0 read-write 0 Operate the sub-clock oscillator #0 1 Stop the sub-clock oscillator #1 SOMCR Sub Clock Oscillator Mode Control Register 0x481 8 read-write 0x00 0xFD SODRV1 Sub Clock Oscillator Drive Capability Switching 1 1 read-write 0 Standard #0 1 Middle #1 LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write 0x00 0xFF LCSTP LOCO Stop 0 0 read-write 0 Operate the LOCO clock #0 1 Stop the LOCO clock #1 LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write 0x00 0xFF LOCOUTRM LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits 0 7 read-write MOSCWTCR Main Clock Oscillator Wait Control Register 0x0A2 8 read-write 0x05 0xFF MSTS Main clock oscillator wait time setting 0 3 read-write 0001 Wait time = 35 cycles (133.5 μs) #0001 0010 Wait time = 67 cycles (255.6 μs) #0010 0011 Wait time = 131 cycles (499.7 μs) #0011 0100 Wait time = 259 cycles (988.0 μs) #0100 0101 Wait time = 547 cycles (2086.6 μs) (value after reset) #0101 0110 Wait time = 1059 cycles (4039.8 μs) #0110 0111 Wait time = 2147 cycles (8190.2 μs) #0111 1000 Wait time = 4291 cycles (16368.9 μs) #1000 1001 Wait time = 8163 cycles (31139.4 μs). #1001 others settings prohibited. true HOCOWTCR High-speed on-chip oscillator wait control register 0x0A5 8 read-write 0x02 0xFF HSTS HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) 0 2 read-write SBYCR Standby Control Register 0x00C 16 read-write 0x4000 0xFFFF SSBY Software Standby 15 15 read-write 0 Sleep mode #0 1 Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1) #1 OPE Output Port Enable 14 14 read-write 0 In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state. #0 1 In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state.. #1 MSTPCRA Module Stop Control Register A 0x01C 32 read-write 0xFFBFFF1C 0xFFFFFFFF MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA7 Standny RAM Module Stop 7 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA6 ECCRAM Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA5 High-Speed RAM Module Stop 5 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA1 RAM1 Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA0 RAM0 Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 SNZCR Snooze Control Register 0x092 8 read-write 0x00 0xFF SNZE Snooze Mode Enable 7 7 read-write 0 Disable Snooze Mode #0 1 Enable Snooze Mode #1 SNZDTCEN DTC Enable in Snooze Mode 1 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 RXDREQEN RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. 0 0 read-write 0 Ignore RXD0 falling edge in Standby mode. #0 1 Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. #1 SNZEDCR Snooze End Control Register 0x094 8 read-write 0x00 0xFF SCI0UMTED SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode. 7 7 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD1UMTED AD compare mismatch 1 Snooze End Enable 6 6 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD1MATED AD compare match 1 Snooze End Enable 5 5 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD0UMTED AD compare mismatch 0 Snooze End Enable 4 4 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD0MATED AD compare match 0 Snooze End Enable 3 3 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCNZRED Not Last DTC transmission completion Snooze End Enable 2 2 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCZRED Last DTC transmission completion Snooze End Enable 1 1 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AGT1UNFED AGT1 underflow Snooze End Enable 0 0 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 SNZREQCR Snooze Request Control Register 0x098 32 read-write 0x00000000 0xFFFFFFFF SNZREQEN30 Snooze Request Enable 30Enable AGT1 compare match B snooze request 30 30 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN29 Snooze Request Enable 29Enable AGT1 compare match A snooze request 29 29 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN28 Snooze Request Enable 28Enable AGT1 underflow snooze request 28 28 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN25 Snooze Request Enable 25Enable RTC period snooze request 25 25 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN24 Snooze Request Enable 24Enable RTC alarm snooze request 24 24 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN22 Snooze Request Enable 22Enable Comparator-OC0 snooze request 22 22 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN17 Snooze Request Enable 17Enable KR snooze request 17 17 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN15 Snooze Request Enable 15Enable IRQ15 pin snooze request 15 15 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN14 Snooze Request Enable 14Enable IRQ14 pin snooze request 14 14 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN13 Snooze Request Enable 13Enable IRQ13 pin snooze request 13 13 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN12 Snooze Request Enable 12Enable IRQ12 pin snooze request 12 12 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN11 Snooze Request Enable 11Enable IRQ11 pin snooze request 11 11 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN10 Snooze Request Enable 10Enable IRQ10 pin snooze request 10 10 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN9 Snooze Request Enable 9Enable IRQ9 pin snooze request 9 9 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN8 Snooze Request Enable 8Enable IRQ8 pin snooze request 8 8 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN7 Snooze Request Enable 7Enable IRQ7 pin snooze request 7 7 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN6 Snooze Request Enable 6Enable IRQ6 pin snooze request 6 6 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN5 Snooze Request Enable 5Enable IRQ5 pin snooze request 5 5 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN4 Snooze Request Enable 4Enable IRQ4 pin snooze request 4 4 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN3 Snooze Request Enable 3Enable IRQ3 pin snooze request 3 3 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN2 Snooze Request Enable 2Enable IRQ2 pin snooze request 2 2 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN1 Snooze Request Enable 1Enable IRQ1 pin snooze request 1 1 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN0 Snooze Request Enable 0Enable IRQ0 pin snooze request 0 0 read-write 0 Disable snooze request #0 1 Enable snooze request #1 OPCCR Operating Power Control Register 0x0A0 8 read-write 0x00 0xFF OPCMTSF Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Prohibited #01 10 Prohibited #10 11 Low-speed mode #11 others Setting prohibited true SOPCCR Sub Operating Power Control Register 0x0AA 8 read-write 0x00 0xFF SOPCMTSF Sub Operating Power Control Mode Transition Status Flag 4 4 read-only 0 Transition completed #0 1 During transition #1 SOPCM Sub Operating Power Control Mode Select 0 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 DPSBYCR Deep Standby Control Register 0x400 8 read-write 0x01 0xFF DPSBY Deep Software Standby 7 7 read-write 0 Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) #0 1 Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) #1 IOKEEP I/O Port Retention 6 6 read-write 0 When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. #0 1 When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. #1 DEEPCUT Power-Supply Control 0 1 read-write 00 Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. #00 01 Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode. #01 10 Setting prohibited. #10 11 Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. #11 DPSIER0 Deep Standby Interrupt Enable Register 0 0x402 8 read-write 0x00 0xFF DIRQ7E IRQ7-DS Pin Enable 7 7 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ6E IRQ6-DS Pin Enable 6 6 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ5E IRQ5-DS Pin Enable 5 5 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ4E IRQ4-DS Pin Enable 4 4 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ3E IRQ3-DS Pin Enable 3 3 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ2E IRQ2-DS Pin Enable 2 2 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ1E IRQ1-DS Pin Enable 1 1 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ0E IRQ0-DS Pin Enable 0 0 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DPSIER1 Deep Standby Interrupt Enable Register 1 0x403 8 read-write 0x00 0xFF DIRQ14E IRQ14-DS Pin Enable 6 6 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ13E IRQ13-DS Pin Enable 5 5 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ12E IRQ12-DS Pin Enable 4 4 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ11E IRQ11-DS Pin Enable 3 3 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ10E IRQ10-DS Pin Enable 2 2 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ9E IRQ9-DS Pin Enable 1 1 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DIRQ8E IRQ8-DS Pin Enable 0 0 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DPSIER2 Deep Standby Interrupt Enable Register 2 0x404 8 read-write 0x00 0xFF DNMIE NMI Pin Enable 4 4 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DRTCAIE RTC Alarm interrupt Deep Standby Cancel Signal Enable 3 3 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DTRTCIIE RTC Interval interrupt Deep Standby Cancel Signal Enable 2 2 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DLVD2IE LVD2 Deep Standby Cancel Signal Enable 1 1 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DLVD1IE LVD1 Deep Standby Cancel Signal Enable 0 0 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DPSIER3 Deep Standby Interrupt Enable Register 3 0x405 8 read-write 0x00 0xFF DAGT1IE AGT1 Underflow Deep Standby Cancel Signal Enable 2 2 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DUSBHSIE USBHS Suspend/Resume Deep Standby Cancel Signal Enable 1 1 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DUSBFSIE USBFS Suspend/Resume Deep Standby Cancel Signal Enable 0 0 read-write 0 Canceling deep software standby mode is disabled #0 1 Canceling deep software standby mode is enabled #1 DPSIFR0 Deep Standby Interrupt Flag Register 0 0x406 8 read-write 0x00 0xFF DIRQ7F IRQ7-DS Pin Deep Standby Cancel Flag 7 7 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ6F IRQ6-DS Pin Deep Standby Cancel Flag 6 6 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ5F IRQ5-DS Pin Deep Standby Cancel Flag 5 5 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ4F IRQ4-DS Pin Deep Standby Cancel Flag 4 4 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ3F IRQ3-DS Pin Deep Standby Cancel Flag 3 3 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ2F IRQ2-DS Pin Deep Standby Cancel Flag 2 2 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ1F IRQ1-DS Pin Deep Standby Cancel Flag 1 1 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ0F IRQ0-DS Pin Deep Standby Cancel Flag 0 0 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR1 Deep Standby Interrupt Flag Register 1 0x407 8 read-write 0x00 0xFF DIRQ14F IRQ14-DS Pin Deep Standby Cancel Flag 6 6 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ13F IRQ13-DS Pin Deep Standby Cancel Flag 5 5 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ12F IRQ12-DS Pin Deep Standby Cancel Flag 4 4 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ11F IRQ11-DS Pin Deep Standby Cancel Flag 3 3 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ10F IRQ10-DS Pin Deep Standby Cancel Flag 2 2 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ9F IRQ9-DS Pin Deep Standby Cancel Flag 1 1 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DIRQ8F IRQ8-DS Pin Deep Standby Cancel Flag 0 0 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR2 Deep Standby Interrupt Flag Register 2 0x408 8 read-write 0x00 0xFF DNMIF NMI Pin Deep Standby Cancel Flag 4 4 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DRTCAIF RTC Alarm interrupt Deep Standby Cancel Flag 3 3 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DTRTCIIF RTC Interval interrupt Deep Standby Cancel Flag 2 2 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD2IF LVD2 Deep Standby Cancel Flag 1 1 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DLVD1IF LVD1 Deep Standby Cancel Flag 0 0 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIFR3 Deep Standby Interrupt Flag Register 3 0x409 8 read-write 0x00 0xFF DAGT1IF AGT1 Underflow Deep Standby Cancel Flag 2 2 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DUSBHSIF USBHS Suspend/Resume Deep Standby Cancel Flag 1 1 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DUSBFSIF USBFS Suspend/Resume Deep Standby Cancel Flag 0 0 read-write zeroToClear modify 0 The cancel request is not generated #0 1 The cancel request is generated #1 DPSIEGR0 Deep Standby Interrupt Edge Register 0 0x40A 8 read-write 0x00 0xFF DIRQ7EG IRQ7-DS Pin Edge Select 7 7 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ6EG IRQ6-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ5EG IRQ5-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ4EG IRQ4-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ3EG IRQ3-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ2EG IRQ2-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ1EG IRQ1-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ0EG IRQ0-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR1 Deep Standby Interrupt Edge Register 1 0x40B 8 read-write 0x00 0xFF DIRQ14EG IRQ14-DS Pin Edge Select 6 6 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ13EG IRQ13-DS Pin Edge Select 5 5 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ12EG IRQ12-DS Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ11EG IRQ11-DS Pin Edge Select 3 3 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ10EG IRQ10-DS Pin Edge Select 2 2 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ9EG IRQ9-DS Pin Edge Select 1 1 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DIRQ8EG IRQ8-DS Pin Edge Select 0 0 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DPSIEGR2 Deep Standby Interrupt Edge Register 2 0x40C 8 read-write 0x00 0xFF DNMIEG NMI Pin Edge Select 4 4 read-write 0 A cancel request is generated at a falling edge #0 1 A cancel request is generated at a rising edge #1 DLVD2IEG LVD2 Edge Select 1 1 read-write 0 A cancel request is generated when VCC<Vdet2 (fall) is detected #0 1 A cancel request is generated when VCC>=Vdet2 (rise) is detected #1 DLVD1IEG LVD1 Edge Select 0 0 read-write 0 A cancel request is generated when VCC<Vdet1 (fall) is detected #0 1 A cancel request is generated when VCC>=Vdet1 (rise) is detected #1 SYOCDCR System Control OCD Control Register 0x40E 8 read-write 0x00 0xFE DBGEN Debugger Enable bit 7 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 DOCDF Deep Standby OCD flag 0 0 read-write zeroToClear modify 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 STCONR Standby Condition Register 0x40F 8 read-write 0xC3 0xFF STCON SSTBY condition bit 0 1 read-write 00 set this value in case of transferring to Software Standby Mode in using HOCO. #00 11 set this value in case of transferring to Software Standby Mode in using expect for HOCO. #11 2 0x2 1,2 LVD%sCR1 Voltage Monitor %s Circuit Control Register 1 0x0E0 8 read-write 0x01 0xFF IRQSEL Voltage Monitor Interrupt Type Select 2 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 IDTSEL Voltage Monitor Interrupt Generation Condition Select 0 1 read-write 00 Generate when VCC>=Vdet (rise) is detected #00 01 Generate when VCC<Vdet (drop) is detected #01 10 Generate when drop and rise are detected #10 11 Settings prohibited #11 2 0x2 1,2 LVD%sSR Voltage Monitor %s Circuit Status Register 0x0E1 8 read-write 0x02 0xFF MON Voltage Monitor 1 Signal Monitor Flag 1 1 read-only 0 VCC < Vdet #0 1 VCC >= Vdet or MON bit is disabled #1 DET Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. 0 0 read-write zeroToClear modify 0 Not detected #0 1 Vdet1 passage detection #1 LVCMPCR Voltage Monitor Circuit Control Register 0x417 8 read-write 0x00 0xFF LVD2E Voltage Detection 2 Enable 6 6 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 LVD1E Voltage Detection 1 Enable 5 5 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVDLVLR Voltage Detection Level Select Register 0x418 8 read-write 0xF3 0xFF LVD2LVL Voltage Detection 2 Level Select (Standard voltage during fall in voltage) 5 7 read-write 101 2.99V (Vdet2_1) #101 110 2.92V (Vdet2_2) #110 111 2.85V (Vdet2_3) #111 others Settings other than above are prohibited. true LVD1LVL Voltage Detection 1 Level Select (Standard voltage during fall in voltage) 0 4 read-write 10001 2.99V (Vdet1_1) #10001 10010 2.92V (Vdet1_2) #10010 10011 2.85V (Vdet1_3) #10011 others Settings other than above are prohibited. true 2 0x1 1,2 LVD%sCR0 Voltage Monitor %s Circuit Control Register 0 0x41A 8 read-write 0x8A 0xF7 RN Voltage Monitor Reset Negate Select 7 7 read-write 0 Negation follows a stabilization time (tLVD) after VCC > Vdet is detected. #0 1 Negation follows a stabilization time (tLVD) after assertion of the LVD reset. #1 RI Voltage Monitor Circuit Mode Select 6 6 read-write 0 Voltage Monitor interrupt during Vdet1 passage #0 1 Voltage Monitor reset enabled when the voltage falls to and below Vdet1 #1 FSAMP Sampling Clock Select 4 5 read-write 00 1/2 LOCO frequency #00 01 1/4 LOCO frequency #01 10 1/8 LOCO frequency #10 11 1/16 LOCO frequency #11 CMPE Voltage Monitor Circuit Comparison Result Output Enable 2 2 read-write 0 Disable voltage monitor 1 circuit comparison result output #0 1 Enable voltage monitor 1 circuit comparison result output. #1 DFDIS Voltage Monitor Digital Filter Disable Mode Select 1 1 read-write 0 Enable digital filter #0 1 Disable digital filter #1 RIE Voltage Monitor Interrupt/Reset Enable 0 0 read-write 0 Disable #0 1 Enable #1 VBTICTLR VBATT Input Control Register 0x4BB 8 read-write 0x00 0xF8 VCH2INEN RTCIC2 Input Enable 2 2 read-write 0 Disabled #0 1 Enabled #1 VCH1INEN RTCIC1 Input Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 VCH0INEN RTCIC0 Input Enable 0 0 read-write 0 Disabled #0 1 Enabled #1 512 0x1 0-511 VBTBKR[%s] VBATT Backup Register [%s] 0x500 8 read-write 0x00 0x00 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write PRCR Protect Register 0x3FE 16 read-write 0x0000 0xFFFF PRKEY PRKEY Key Code 8 15 write-only 0x5A Enables writing to the PRCR register. 0x5A others Disables writing to the PRCR register. true PRC3 Enables writing to the registers related to the LVD. 3 3 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRC1 Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function. 1 1 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRC0 Enables writing to the registers related to the clock generation circuit. 0 0 read-write 0 Writes protected. #0 1 Writes not protected. #1 RSTSR0 Reset Status Register 0 0x410 8 read-write 0x00 0x70 DPSRSTF Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 7 7 read-write zeroToClear modify 0 Deep software standby mode cancelation not requested by an interrupt. #0 1 Deep software standby mode cancelation requested by an interrupt. #1 LVD2RF Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 3 3 read-write zeroToClear modify 0 Voltage Monitor 2 reset not detected. #0 1 Voltage Monitor 2 reset detected. #1 LVD1RF Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 2 2 read-write zeroToClear modify 0 Voltage Monitor 1 reset not detected. #0 1 Voltage Monitor 1 reset detected. #1 LVD0RF Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 1 1 read-write zeroToClear modify 0 Voltage Monitor 0 reset not detected. #0 1 Voltage Monitor 0 reset detected. #1 PORF Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 0 0 read-write zeroToClear modify 0 Power-on reset not detected. #0 1 Power-on reset detected. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write 0x00 0xFE CWSF Cold/Warm Start Determination Flag 0 0 read-write oneToSet modify 0 Cold start #0 1 Warm start #1 RSTSR1 Reset Status Register 1 0x0C0 16 read-write 0x0000 0xE0F8 SPERF SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 12 12 read-write zeroToClear modify 0 SP error reset not detected. #0 1 SP error reset detected. #1 BUSMRF Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 11 11 read-write zeroToClear modify 0 Bus Master MPU reset not detected. #0 1 Bus Master MPU reset detected. #1 BUSSRF Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 10 10 read-write zeroToClear modify 0 Bus Slave MPU reset not detected. #0 1 Bus Slave MPU reset detected. #1 REERF RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 9 9 read-write zeroToClear modify 0 RAM ECC error reset not detected. #0 1 RAM ECC error reset detected. #1 RPERF RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 8 8 read-write zeroToClear modify 0 RAM parity error reset not detected. #0 1 RAM parity error reset detected. #1 SWRF Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 2 2 read-write zeroToClear modify 0 Software reset not detected. #0 1 Software reset detected. #1 WDTRF Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 1 1 read-write zeroToClear modify 0 Watchdog timer reset not detected. #0 1 Watchdog timer reset detected. #1 IWDTRF Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 0 0 read-write zeroToClear modify 0 Independent watchdog timer reset not detected. #0 1 Independent watchdog timer reset detected. #1 FWEPROR Flash P/E Protect Register 0x416 8 read-write 0x02 0xFF FLWE Flash Programming and Erasure 0 1 read-write 00 Prohibits programming and erasure of the code flash, data flash or blank checking. #00 01 Permits programming and erasure of the code flash, data flash or blank checking. #01 10 Prohibits programming and erasure of the code flash, data flash or blank checking. #10 11 Prohibits programming and erasure of the code flash, data flash or blank checking. #11 EDMAC0 DMA Controller for the Ethernet Controller Channel 0 0x40064000 0x00 4 registers 0x08 4 registers 0x10 4 registers 0x18 4 registers 0x20 4 registers 0x28 4 registers 0x30 4 registers 0x38 4 registers 0x40 4 registers 0x48 4 registers 0x50 4 registers 0x58 4 registers 0x64 16 registers 0x78 8 registers 0xC8 8 registers 0xD4 8 registers EDMR EDMAC Mode Register 0x00 32 read-write 0x00000000 0xFFFFFFFF DE Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers. 6 6 read-write 0 Big endian mode #0 1 Little endian mode #1 DL Transmit/Receive DescriptorLength 4 5 read-write 00 16 bytes #00 01 32 bytes #01 10 64 bytes #10 11 16 bytes #11 SWR Software Reset 0 0 write-only 0 no effect. #0 1 the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset. #1 EDTRR EDMAC Transmit Request Register 0x08 32 read-write 0x00000000 0xFFFFFFFF TR Transmit Request 0 0 write-only 0 no effect. #0 1 When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. #1 EDRRR EDMAC Receive Request Register 0x10 32 read-write 0x00000000 0xFFFFFFFF RR Receive Request 0 0 read-write 0 Receive function is disabled. #0 1 Receive descriptor is read, and the receive function is enabled. #1 TDLAR Transmit Descriptor List Start Address Register 0x18 32 read-write 0x00000000 0xFFFFFFFF TDLAR The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b 0 31 read-write RDLAR Receive Descriptor List Start Address Register 0x20 32 read-write 0x00000000 0xFFFFFFFF RDLAR The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b 0 31 read-write EESR ETHERC/EDMAC Status Register 0x28 32 read-write 0x00000000 0xFFFFFFFF TWB Write-Back Complete Flag 30 30 read-write oneToClear modify 0 Write-back has not been completed, or no transmission has been requested. #0 1 Write-back to the transmit descriptor has been completed. #1 TABT Transmit Abort Detect Flag 26 26 read-write oneToClear modify 0 Frame transmission has not been aborted or no transmission has been requested. #0 1 Frame transmission has been aborted. #1 RABT Receive Abort Detect Flag 25 25 read-write oneToClear modify 0 Frame reception has not been aborted or no reception has been requested. #0 1 Frame reception has been aborted. #1 RFCOF Receive Frame Counter Overflow Flag 24 24 read-write oneToClear modify 0 Receive frame counter has not overflowed. #0 1 Receive frame counter has overflowed. #1 ADE Address Error Flag 23 23 read-write oneToClear modify 0 Invalid memory address has not been detected (normal operation). #0 1 Invalid memory address has been detected. #1 ECI ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared. 22 22 read-only 0 ETHERC status interrupt source has not been detected. #0 1 ETHERC status interrupt source has been detected. #1 TC Frame Transfer Complete Flag 21 21 read-write oneToClear modify 0 Transfer have not been completed, or no transfer has been requested. #0 1 All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO. #1 TDE Transmit Descriptor Empty Flag 20 20 read-write oneToClear modify 0 The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1. #0 1 The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0. #1 TFUF Transmit FIFO Underflow Flag 19 19 read-write oneToClear modify 0 Underflow has not occurred. #0 1 Underflow has occurred. #1 FR Frame Receive Flag 18 18 read-write oneToClear modify 0 Frame has not been received. #0 1 Frame has been received. Update of the receive descriptor is complete. #1 RDE Receive Descriptor Empty Flag 17 17 read-write oneToClear modify 0 The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1. #0 1 The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0. #1 RFOF Receive FIFO Overflow Flag 16 16 read-write oneToClear modify 0 Overflow has not occurred. #0 1 Overflow has occurred. #1 CND Carrier Not Detect Flag 11 11 read-write oneToClear modify 0 A carrier has been detected when transmission starts. #0 1 A carrier has not been detected during preamble transmission. #1 DLC Loss of Carrier Detect Flag 10 10 read-write oneToClear modify 0 Loss of carrier has not been detected. #0 1 Loss of carrier has been detected during frame transmission. #1 CD Late Collision Detect Flag 9 9 read-write oneToClear modify 0 Late collision has not been detected. #0 1 Late collision has been detected during frame transmission. #1 TRO Transmit Retry Over Flag 8 8 read-write oneToClear modify 0 Transmit retry-over condition has not been detected. #0 1 Transmit retry-over condition has been detected. #1 RMAF Multicast Address Frame Receive Flag 7 7 read-write oneToClear modify 0 Multicast address frame has not been received. #0 1 Multicast address frame has been received. #1 RRF Alignment Error Flag 4 4 read-write oneToClear modify 0 Alignment error has not been detected. #0 1 Alignment error has been detected. #1 RTLF Frame-Too-Long Error Flag 3 3 read-write oneToClear modify 0 Frame-too-long error has not been detected. #0 1 Frame-too-long error has been detected. #1 RTSF Frame-Too-Short Error Flag 2 2 read-write oneToClear modify 0 Frame-too-short error has not been detected. #0 1 Frame-too-short error has been detected. #1 PRE PHY-LSI Receive Error Flag 1 1 read-write oneToClear modify 0 PHY-LSI receive error has not been detected. #0 1 PHY-LSI receive error has been detected. #1 CERF CRC Error Flag 0 0 read-write oneToClear modify 0 CRC error has not been detected. #0 1 CRC error has been detected. #1 EESIPR ETHERC/EDMAC Status Interrupt Enable Register 0x30 32 read-write 0x00000000 0xFFFFFFFF TWBIP Write-Back Complete Interrupt Request Enable 30 30 read-write 0 Write-back complete interrupt request is disabled. #0 1 Write-back complete interrupt request is enabled. #1 TABTIP Transmit Abort Detect Interrupt Request Enable 26 26 read-write 0 Transmit abort detect interrupt request is disabled. #0 1 Transmit abort detect interrupt request is enabled. #1 RABTIP Receive Abort Detect Interrupt Request Enable 25 25 read-write 0 Receive abort detect interrupt request is disabled. #0 1 Receive abort detect interrupt request is enabled. #1 RFCOFIP Receive Frame Counter Overflow Interrupt Request Enable 24 24 read-write 0 Receive frame counter overflow interrupt request is disabled. #0 1 Receive frame counter overflow interrupt request is enabled. #1 ADEIP Address Error Interrupt Request Enable 23 23 read-write 0 Address error interrupt request is disabled. #0 1 Address error interrupt request is enabled. #1 ECIIP ETHERC Status Register Source Interrupt Request Enable 22 22 read-write 0 ETHERC status interrupt request is disabled. #0 1 ETHERC status interrupt request is enabled. #1 TCIP Frame Transfer Complete Interrupt Request Enable 21 21 read-write 0 Frame transmission complete interrupt request is disabled. #0 1 Frame transmission complete interrupt request is enabled. #1 TDEIP Transmit Descriptor Empty Interrupt Request Enable 20 20 read-write 0 Transmit descriptor empty interrupt request is disabled. #0 1 Transmit descriptor empty interrupt request is enabled. #1 TFUFIP Transmit FIFO Underflow Interrupt Request Enable 19 19 read-write 0 Underflow interrupt request is disabled. #0 1 Underflow interrupt request is enabled. #1 FRIP Frame Receive Interrupt Request Enable 18 18 read-write 0 Frame reception interrupt request is disabled. #0 1 Frame reception interrupt request is enabled. #1 RDEIP Receive Descriptor Empty Interrupt Request Enable 17 17 read-write 0 Receive descriptor empty interrupt request is disabled. #0 1 Receive descriptor empty interrupt request is enabled. #1 RFOFIP Receive FIFO Overflow Interrupt Request Enable 16 16 read-write 0 Overflow interrupt request is disabled. #0 1 Overflow interrupt request is enabled. #1 CNDIP Carrier Not Detect Interrupt Request Enable 11 11 read-write 0 Carrier not detect interrupt request is disabled. #0 1 Carrier not detect interrupt request is enabled. #1 DLCIP Loss of Carrier Detect Interrupt Request Enable 10 10 read-write 0 Loss of carrier detect interrupt request is disabled. #0 1 Loss of carrier detect interrupt request is enabled. #1 CDIP Late Collision Detect Interrupt Request Enable 9 9 read-write 0 Late collision detect interrupt request is disabled. #0 1 Late collision detect interrupt request is enabled. #1 TROIP Transmit Retry Over Interrupt Request Enable 8 8 read-write 0 Transmit retry over interrupt request is disabled. #0 1 Transmit retry over interrupt request is enabled. #1 RMAFIP Multicast Address Frame Receive Interrupt Request Enable 7 7 read-write 0 Multicast address frame receive interrupt request is disabled. #0 1 Multicast address frame receive interrupt request is enabled. #1 RRFIP Alignment Error Interrupt Request Enable 4 4 read-write 0 Alignment error interrupt request is disabled. #0 1 Alignment error interrupt request is enabled. #1 RTLFIP Frame-Too-Long Error Interrupt Request Enable 3 3 read-write 0 Frame-too-long error interrupt request is disabled. #0 1 Frame-too-long error interrupt request is enabled. #1 RTSFIP Frame-Too-Short Error Interrupt Request Enable 2 2 read-write 0 Frame-too-short error interrupt request is disabled. #0 1 Frame-too-short error interrupt request is enabled. #1 PREIP PHY-LSI Receive Error Interrupt Request Enable 1 1 read-write 0 PHY-LSI receive error interrupt request is disabled. #0 1 PHY-LSI receive error interrupt request is enabled. #1 CERFIP CRC Error Interrupt Request Enable 0 0 read-write 0 CRC error interrupt request is disabled. #0 1 CRC error interrupt request is enabled. #1 TRSCER ETHERC/EDMAC Transmit/Receive Status Copy Enable Register 0x38 32 read-write 0x00000000 0xFFFFFFFF RMAFCE RMAF Flag Copy Enable 7 7 read-write 0 The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor. #0 1 The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor. #1 RRFCE RRF Flag Copy Enable 4 4 read-write 0 The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor. #0 1 The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor. #1 RMFCR Missed-Frame Counter Register 0x40 32 read-write 0x00000000 0xFFFFFFFF MFC Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception. 0 15 read-write clear TFTR Transmit FIFO Threshold Register 0x48 32 read-write 0x00000000 0xFFFFFFFF TFT Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes 0 10 read-write 0x000 0x200 0x000 Store and forward mode 0x000 others The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited) true FDR Transmit FIFO Threshold Register 0x50 32 read-write 0x00000000 0xFFFFFFFF TFD Receive FIFO Depth 8 12 read-write 01111 4096 bytes #01111 others Settings other than above are prohibited. true RFD Transmit FIFO Depth 0 4 read-write 00111 2048 bytes #00111 others Settings other than above are prohibited. true RMCR Receive Method Control Register 0x58 32 read-write 0x00000000 0xFFFFFFFF RNR Receive Request Reset 0 0 read-write 0 EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received. #0 1 EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received. #1 TFUCR Transmit FIFO Underflow Counter 0x64 32 read-write 0x00000000 0xFFFFFFFF UNDER Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh. 0 15 read-write RFOCR Receive FIFO Overflow Counter 0x68 32 read-write 0x00000000 0xFFFFFFFF OVER Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh. 0 15 read-write IOSR Independent Output Signal Setting Register 0x6C 32 read-write 0x00000000 0xFFFFFFFF ELB External Loopback Mode 0 0 read-write 0 The ETn_EXOUT pin outputs low. #0 1 The ETn_EXOUT pin outputs high. #1 FCFTR Flow Control Start FIFO Threshold Setting Register 0x70 32 read-write 0x00070007 0xFFFFFFFF RFFO Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.) 16 18 read-write 000 When 2 receive frames have been stored in the receive FIFO. #000 001 When 4 receive frames have been stored in the receive FIFO. #001 010 When 6 receive frames have been stored in the receive FIFO. #010 011 When 8 receive frames have been stored in the receive FIFO. #011 100 When 10 receive frames have been stored in the receive FIFO. #100 101 When 12 receive frames have been stored in the receive FIFO. #101 110 When 14 receive frames have been stored in the receive FIFO. #110 111 When 16 receive frames have been stored in the receive FIFO. #111 RFDO Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.) 0 2 read-write 000 When 224 ( 256 - 32) bytes of data is stored in the receive FIFO. #000 001 When 480 ( 512 - 32) bytes of data is stored in the receive FIFO. #001 010 When 736 ( 768 - 32) bytes of data is stored in the receive FIFO. #010 011 When 992 (1024 - 32) bytes of data is stored in the receive FIFO. #011 100 When 1248 (1280 - 32) bytes of data is stored in the receive FIFO. #100 101 When 1504 (1536 - 32) bytes of data is stored in the receive FIFO. #101 110 When 1760 (1792 - 32) bytes of data is stored in the receive FIFO. #110 111 When 2016 (2048 - 32) bytes of data is stored in the receive FIFO. #111 RPADIR Receive Data Padding Insert Register 0x78 32 read-write 0x00000000 0xFFFFFFFF PADS Padding Size 16 17 read-write 00 No padding is inserted. #00 01 1 byte is inserted. #01 10 2 bytes are inserted. #10 11 3 bytes are inserted. #11 PADR Padding Slot 0 5 read-write 00h Padding is inserted at the head of received data. 0x00 others Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data. true TRIMD Transmit Interrupt Setting Register 0x07C 32 read-write 0x00000000 0xFFFFFFFF TIM Transmit Interrupt Mode 4 4 read-write 0 Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. #0 1 Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed. #1 TIS Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt. 0 0 read-write 0 Transmit Interrupt is disabled. #0 1 Transmit Interrupt is enabled. #1 RBWAR Receive Buffer Write Address Register 0xC8 32 read-only 0x00000000 0xFFFFFFFF RBWAR Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception. 0 31 read-only RDFAR Receive Descriptor Fetch Address Register 0xCC 32 read-only 0x00000000 0xFFFFFFFF RDFAR Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception. 0 31 read-only TBRAR Transmit Buffer Read Address Register 0x0D4 32 read-only 0x00000000 0xFFFFFFFF TBRAR Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register. 0 31 read-only TDFAR Transmit Descriptor Fetch Address Register 0xD8 32 read-only 0x00000000 0xFFFFFFFF TDFAR Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register. 0 31 read-only ETHERC0 Ethernet Controller Channel 0 0x40064100 0x00 4 registers 0x08 4 registers 0x10 4 registers 0x18 4 registers 0x20 4 registers 0x28 4 registers 0x40 4 registers 0x50 12 registers 0x60 16 registers 0xC0 4 registers 0xC8 4 registers 0xD0 16 registers 0xE4 24 registers ECMR ETHERC Mode Register 0x00 32 read-write 0x00000000 0xFFFFFFFF TPC PAUSE Frame Transmit 20 20 read-write 0 PAUSE frame is transmitted even during a PAUSE period. #0 1 PAUSE frame is not transmitted during a PAUSE period. #1 ZPF 0 Time PAUSE Frame Enable 19 19 read-write 0 PAUSE frame that contains the pause_time parameter of 0 is not used. #0 1 PAUSE frame that contains the pause_time parameter of 0 is used. #1 PFR PAUSE Frame Receive Mode 18 18 read-write 0 PAUSE frame is not transferred to the EDMAC. #0 1 PAUSE frame is transferred to the EDMAC. #1 RXF Receive Flow Control Operating Mode 17 17 read-write 0 PAUSE frame detection is disabled. #0 1 PAUSE frame detection is enabled. #1 TXF Transmit Flow Control Operating Mode 16 16 read-write 0 Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.) #0 1 Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.) #1 PRCEF CRC Error Frame Receive Mode 12 12 read-write 0 EDMAC is notified of a CRC error. #0 1 EDMAC is not notified of a CRC error. #1 MPDE Magic Packet Detection Enable 9 9 read-write 0 Magic Packet detection is disabled. #0 1 Magic Packet detection is enabled. #1 RE Reception Enable 6 6 read-write 0 Receive function is disabled. #0 1 Receive function is enabled. #1 TE Transmission Enable 5 5 read-write 0 Transmit function is disabled. #0 1 Transmit function is enabled. #1 ILB Internal Loopback Mode 3 3 read-write 0 Normal data transmission or reception is performed. #0 1 Data is looped back in the ETHERC when full-duplex mode is selected. #1 RTM Bit Rate 2 2 read-write 0 10 Mbps #0 1 100 Mbps #1 DM Duplex Mode 1 1 read-write 0 Half-duplex mode #0 1 Full-duplex mode #1 PRM Promiscuous Mode 0 0 read-write 0 Promiscuous mode is disabled. #0 1 Promiscuous mode is enabled. #1 RFLR Receive Frame Maximum Length Register 0x08 32 read-write 0x00000000 0xFFFFFFFF RFL Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes. 0 11 read-write ECSR ETHERC Status Register 0x10 32 read-write 0x00000000 0xFFFFFFFF BFR Continuous Broadcast Frame Reception Flag 5 5 read-write oneToClear modify 0 Continuous reception of broadcast frames has not been detected. #0 1 Continuous reception of broadcast frames has been detected. #1 PSRTO PAUSE Frame Retransmit Over Flag 4 4 read-write oneToClear modify 0 PAUSE frame retransmit count has not reached the upper limit. #0 1 PAUSE frame retransmit count has reached the upper limit. #1 LCHNG LCHNG Link Signal Change Flag 2 2 read-write oneToClear modify 0 Change in the ETn_LINKSTA signal has not been detected. #0 1 Change in the ETn_LINKSTA signal has been detected (high to low, or low to high). #1 MPD Magic Packet Detect Flag 1 1 read-write oneToClear modify 0 Magic Packet has not been detected. #0 1 Magic Packet has been detected. #1 ICD False Carrier Detect Flag 0 0 read-write oneToClear modify 0 PHY-LSI has not detected a false carrier on the line. #0 1 PHY-LSI has detected a false carrier on the line. #1 ECSIPR ETHERC Interrupt Enable Register 0x18 32 read-write 0x00000000 0xFFFFFFFF BFSIPR Continuous Broadcast Frame Reception Interrupt Enable 5 5 read-write 0 Notification of continuous broadcast frame reception interrupt is disabled. #0 1 Notification of continuous broadcast frame reception interrupt is enabled. #1 PSRTOIP PAUSE Frame Retransmit Over Interrupt Enable 4 4 read-write 0 Notification of PAUSE frame retransmit over interrupt is disabled. #0 1 Notification of PAUSE frame retransmit over interrupt is enabled. #1 LCHNGIP LINK Signal Change Interrupt Enable 2 2 read-write 0 Notification of ETn_LINKSTA signal change interrupt is disabled. #0 1 Notification of ETn_LINKSTA signal change interrupt is enabled. #1 MPDIP Magic Packet Detect Interrupt Enable 1 1 read-write 0 Notification of the Magic Packet detect interrupt is disabled. #0 1 Notification of the Magic Packet detect interrupt is enabled. #1 ICDIP False Carrier Detect Interrupt Enable 0 0 read-write 0 Notification of the false carrier detect interrupt is disabled. #0 1 Notification of the false carrier detect interrupt is enabled. #1 PIR PHY Interface Register 0x20 32 read-write 0x00000000 0xFFFFFFF7 MDI MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0. 3 3 read-only MDO MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read). 2 2 read-write MMD MII/RMII Management Mode 1 1 read-write 0 Read #0 1 Write #1 MDC MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII. 0 0 read-write PSR PHY Status Register 0x28 32 read-only 0x00000000 0xFFFFFFFE LMON ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI. 0 0 read-only RDMLR Random Number Generation Counter Upper Limit Setting Register 0x40 32 read-write 0x00000000 0xFFFFFFFF RMD Random Number Generation Counter 0 19 read-write 00000h Normal operation 0x00000 others Setting prohibited true IPGR IPG Register 0x50 32 read-write 0x00000014 0xFFFFFFFF IPG Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" 0 4 read-write 14h 96 bit time (initial value) 0x14 others (IPGx4+16) bit time true APR Automatic PAUSE Frame Register 0x54 32 read-write 0x00000000 0xFFFFFFFF AP Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. 0 15 read-write MPR Manual PAUSE Frame Register 0x58 32 write-only 0x00000000 0xFFFF0000 MP Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined. 0 15 write-only RFCF Received PAUSE Frame Counter 0x60 32 read-only 0x00000000 0xFFFFFFFF RPAUSE Received PAUSE Frame CountNumber of received PAUSE frames 0 7 read-only TPAUSER PAUSE Frame Retransmit Count Setting Register 0x64 32 read-write 0x00000000 0xFFFFFFFF TPAUSE Automatic PAUSE Frame Retransmit Setting 0 15 read-write 0x0000 Number of retransmissions is unlimited 0x0000 others Maximum number of retransmissions is (TPAUSE) true TPAUSECR PAUSE Frame Retransmit Counter 0x68 32 read-only 0x00000000 0xFFFFFFFF BCFRR Broadcast Frame Receive Count Setting Register 0x6C 32 read-write 0x00000000 0xFFFFFFFF BCF Broadcast Frame Continuous Receive Count Setting 0 15 read-write 0000h Number of receptions is unlimited. 0x0000 others Receive (BFC) frame. true MAHR MAC Address Upper Bit Register 0xC0 32 read-write 0x00000000 0xFFFFFFFF MAHR MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address. 0 31 read-write MALR MAC Address Lower Bit Register 0xC8 32 read-write 0x00000000 0xFFFFFFFF MALR MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address. 0 15 read-write TROCR Transmit Retry Over Counter Register 0xD0 32 read-write 0x00000000 0xFFFFFFFF TROCR Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted. 0 31 read-write clear CDCR Late Collision Detect Counter Register 0xD4 32 read-write 0x00000000 0xFFFFFFFF LCCR Lost Carrier Counter Register 0xD8 32 read-write 0x00000000 0xFFFFFFFF LCCR Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission. 0 31 read-write clear CNDCR Carrier Not Detect Counter Register 0xDC 32 read-write 0x00000000 0xFFFFFFFF CNDCR Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission. 0 31 read-write clear CEFCR CRC Error Frame Receive Counter Register 0xE4 32 read-write 0x00000000 0xFFFFFFFF CEFCR CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected. 0 31 read-write clear FRECR Frame Receive Error Counter Register 0xE8 32 read-write 0x00000000 0xFFFFFFFF FRECR Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred. 0 31 read-write clear TSFRCR Too-Short Frame Receive Counter Register 0xEC 32 read-write 0x00000000 0xFFFFFFFF TSFRCR Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received. 0 31 read-write clear TLFRCR Too-Long Frame Receive Counter Register 0xF0 32 read-write 0x00000000 0xFFFFFFFF TLFRCR Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received. 0 31 read-write clear RFCR Received Alignment Error Frame Counter Register 0xF4 32 read-write 0x00000000 0xFFFFFFFF RFCR Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets). 0 31 read-write clear MAFCR Multicast Address Frame Receive Counter Register 0xF8 32 read-write 0x00000000 0xFFFFFFFF MAFCR Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received. 0 31 read-write clear SDHI0 SD Host Interface 0 0x40062000 0x00 84 registers 0x58 12 registers 0x68 12 registers 0x1B0 4 registers 0x1C0 16 registers 0x1E0 32 registers SD_CMD Command Type Register 0x000 32 read-write 0x00000000 0xFFFFFFFF CMD12AT Multiple Block Transfer Mode (enabled at multiple block transfer) 14 15 read-write 00 CMD12 is automatically issued at multiple block transfer. #00 01 CMD12 is not automatically issued at multiple block transfer. #01 10 Setting prohibited #10 11 Setting prohibited #11 TRSTP Single/Multiple Block Transfer (enabled when the command with data is handled) 13 13 read-write 0 Single block transfer #0 1 Multiple block transfer #1 CMDRW Write/Read Mode (enabled when the command with data is handled) 12 12 read-write 0 Write (SD/MMC host interface -> SD card/MMC) #0 1 Read (SD/MMC host interface <- SD card/MMC) #1 CMDTP Data Mode (Command Type) 11 11 read-write 0 Command does not include data transfer (bc, bcr, or ac) #0 1 Command includes data transfer (adtc) #1 RSPTP Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type. 8 10 read-write 000 Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. #000 011 Expansion mode and no response #011 100 Expansion mode and R1, R5, R6, or R7 response #100 101 Expansion mode and R1b response #101 110 Expansion mode and R2 response #110 111 Expansion mode and R3 or R4 response #111 others Settings prohibited. true ACMD Command Type Select 6 7 read-write 00 CMD #00 01 ACMD #01 others Setting prohibited true CMDIDX Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 0 5 read-write SD_ARG SD Command Argument Register 0x008 32 read-write 0x00000000 0xFFFFFFFF SD_ARG Argument RegisterSet command format[39:8] (argument) 0 31 read-write SD_ARG1 SD Command Argument Register 1 0x00C 32 read-write 0x00000000 0xFFFFFFFF SD_ARG1 Argument Register 1Set command format[39:24] (argument) 0 15 read-write SD_STOP Data Stop Register 0x010 32 read-write 0x00000000 0xFFFFFFFF SEC Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. 8 8 read-write 0 Disables SD_SECCNT setting value. #0 1 Enables SD_SECCNT setting value. #1 STP Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set. 0 0 read-write SD_SECCNT Block Count Register 0x014 32 read-write 0x00000000 0xFFFFFFFF SD_SECCNT Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. 0 31 read-write SD_RSP10 SD Card Response Register 10 0x018 32 read-only 0x00000000 0xFFFFFFFF SD_RSP10 Store the response from the SD card/MMC 0 31 read-only SD_RSP1 SD Card Response Register 1 0x01C 32 read-only 0x00000000 0xFFFFFFFF SD_RSP1 Store the response from the SD card/MMC 0 15 read-only SD_RSP32 SD Card Response Register 32 0x020 32 read-only 0x00000000 0xFFFFFFFF SD_RSP32 Store the response from the SD card/MMC 0 31 read-only SD_RSP3 SD Card Response Register 3 0x024 32 read-only 0x00000000 0xFFFFFFFF SD_RSP3 Store the response from the SD card/MMC 0 15 read-only SD_RSP54 SD Card Response Register 54 0x028 32 read-only 0x00000000 0xFFFFFFFF SD_RSP54 Store the response from the SD card/MMC 0 31 read-only SD_RSP5 SD Card Response Register 5 0x02C 32 read-only 0x00000000 0xFFFFFFFF SD_RSP5 Store the response from the SD card/MMC 0 15 read-only SD_RSP76 SD Card Response Register 76 0x030 32 read-only 0x00000000 0xFFFFFFFF SD_RSP76 Store the response from the SD card/MMC 0 23 read-only SD_RSP7 SD Card Response Register 7 0x034 32 read-only 0x00000000 0xFFFFFFFF SD_RSP7 Store the response from the SD card/MMC 0 7 read-only SD_INFO1 SD Card Interrupt Flag Register 1 0x038 32 read-write 0x00000000 0xFFFFFB5F SDD3MON Inticates the SDnDAT3 State 10 10 read-only 0 SDnDAT3 is set to 0. #0 1 SDnDAT3 is set to 1. #1 SDD3IN SDnDAT3 Card Insertion 9 9 read-write zeroToClear modify 0 SD card insertion not detected #0 1 SD card insertion detected #1 SDD3RM SDnDAT3 Card Removal 8 8 read-write zeroToClear modify 0 SD card removal not detected #0 1 SD card removal detected #1 SDWPMON Indicates the SDnWP state 7 7 read-only 0 SDnWP is set to 1. #0 1 SDnWP is set to 0. #1 SDCDMON Indicates the SDnCD state 5 5 read-only 0 Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.) #0 1 Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.) #1 SDCDIN SDnCD Card Insertion 4 4 read-write zeroToClear modify 0 Card insertion not detected #0 1 Card insertion detected #1 SDCDRM SDnCD Card Removal 3 3 read-write zeroToClear modify 0 Card removal not detected #0 1 Card removal detected #1 ACEND Access End 2 2 read-write zeroToClear modify 0 Access end is not detected #0 1 Access end is detected #1 RSPEND Response End Detection 0 0 read-write 0 Response end is not detected #0 1 Response end is detected #1 SD_INFO2 SD Card Interrupt Flag Register 2 0x03C 32 read-write 0x00002000 0xFFFFFF7F ILA Illegal Access Error 15 15 read-write zeroToClear modify 0 Illegal access error not detected #0 1 Illegal access error detected #1 CBSY Command Type Register Busy 14 14 read-only 0 A command sequence is being executed. #0 1 A command sequence has been completed. #1 SD_CLK_CTRLEN When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. 13 13 read-only 0 The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. #0 1 The SD/MMC bus (CMD, DAT) is not busy. #1 BWE SD_BUF Write Enable 9 9 read-write zeroToClear modify 1 Data can be written in SD_BUF0. #1 0 Data cannot be written in SD_BUF0. #0 BRE SD_BUF Read Enable 8 8 read-write zeroToClear modify 1 Data can be read from SD_BUF0. #1 0 Data cannot be read from SD_BUF0. #0 SDD0MON SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. 7 7 read-only 1 SDDAT0 is set to 1. #1 0 SDDAT0 is set to 0. #0 RSPTO Response Timeout 6 6 read-write zeroToClear modify 0 Response timeout not detected #0 1 Response timeout detected #1 ILR SD_BUF Illegal Read Access 5 5 read-write zeroToClear modify 0 Illegal read access to the SD_BUF register not detected #0 1 Illegal read access to the SD_BUF register detected #1 ILW SD_BUF Illegal Write Access 4 4 read-write zeroToClear modify 0 Illegal write access to the SD_BUF register not detected #0 1 Illegal write access to the SD_BUF register detected #1 DTO Data Timeout 3 3 read-write zeroToClear modify 0 Data timeout not detected #0 1 Data timeout detected #1 ENDE END Error 2 2 read-write zeroToClear modify 0 End bit error not detected #0 1 End bit error detected #1 CRCE CRC Error 1 1 read-write zeroToClear modify 0 CRC error not detected #0 1 CRC error detected #1 CMDE Command Error 0 0 read-write zeroToClear modify 0 Command error not detected #0 1 Command error detected #1 SD_INFO1_MASK SD_INFO1 Interrupt Mask Register 0x040 32 read-write 0x0000031D 0xFFFFFFFF SDD3INM SDnDAT3 Card Insertion Interrupt Request Mask 9 9 read-write 0 SD card insertion interrupt request by the SDnDAT3 is not masked #0 1 SD card insertion interrupt request by the SDnDAT3 is masked #1 SDD3RMM SDnDAT3 Card Removal Interrupt Request Mask 8 8 read-write 0 SD card removal interrupt request by the SDnDAT3 is not masked #0 1 SD card removal interrupt request by the SDnDAT3 is masked #1 SDCDINM SDnCD card Insertion Interrupt Request Mask 4 4 read-write 0 Card insertion interrupt request by the SDnCD is not masked #0 1 Card insertion interrupt request by the SDnCD is masked #1 SDCDRMM SDnCD card Removal Interrupt Request Mask 3 3 read-write 0 Card removal interrupt request by the by the SDnCD is not masked #0 1 Card removal interrupt request by the by the SDnCD is masked #1 ACENDM Access End Interrupt Request Mask 2 2 read-write 0 Access end interrupt request is not masked #0 1 Access end interrupt request is masked #1 RSPENDM Response End Interrupt Request Mask 0 0 read-write 0 Response end interrupt request is not masked #0 1 Response end interrupt request is masked #1 SD_INFO2_MASK SD_INFO2 Interrupt Mask Register 0x044 32 read-write 0x00008B7F 0xFFFFFFFF ILAM Illegal Access Error Interrupt Request Mask 15 15 read-write 0 Illegal access error interrupt request not masked #0 1 Illegal access error interrupt request masked #1 BWEM BWE Interrupt Request Mask 9 9 read-write 0 Write enable interrupt request for the SD_BUF register not masked #0 1 Write enable interrupt request for the SD_BUF register masked #1 BREM BRE Interrupt Request Mask 8 8 read-write 0 Read enable interrupt request for the SD buffer not masked #0 1 Read enable interrupt request for the SD buffer masked #1 RSPTOM Response Timeout Interrupt Request Mask 6 6 read-write 0 Response timeout interrupt request not masked #0 1 Response timeout interrupt request masked #1 ILRM SD_BUF Register Illegal Read Interrupt Request Mask 5 5 read-write 0 Illegal read detection interrupt request for the SD_BUF register not masked #0 1 Illegal read detection interrupt request for the SD_BUF register masked #1 ILWM SD_BUF Register Illegal Write Interrupt Request Mask 4 4 read-write 0 Illegal write detection interrupt request for the SD_BUF register not masked #0 1 Illegal write detection interrupt request for the SD_BUF register masked #1 DTOM Data Timeout Interrupt Request Mask 3 3 read-write 0 Data timeout interrupt request not masked #0 1 Data timeout interrupt request masked #1 ENDEM End Bit Error Interrupt Request Mask 2 2 read-write 0 End bit detection error interrupt request not masked #0 1 End bit detection error interrupt request masked #1 CRCEM CRC Error Interrupt Request Mask 1 1 read-write 0 CRC error interrupt request not masked #0 1 CRC error interrupt request masked #1 CMDEM Command Error Interrupt Request Mask 0 0 read-write 0 Command error interrupt request not masked #0 1 Command error interrupt request masked #1 SD_CLK_CTRL SD Clock Control Register 0x048 32 read-write 0x00000020 0xFFFFFFFF CLKCTRLEN SD/MMC Clock Output Automatic Control Enable 9 9 read-write 0 Automatic control for SD/MMC Clock output is disabled. #0 1 Automatic control for SD/MMC Clock output is enabled. #1 CLKEN SD/MMC Clock Output Control Enable 8 8 read-write 0 SD/MMC Clock output is disabled. The SDCLK signal is fixed 0. #0 1 SD/MMC Clock output is enabled. #1 CLKSEL SDHI Clock Frequency Select 0 7 read-write 0x00 PCLKA divided by 2 0x00 0x01 PCLKA divided by 4 0x01 0x02 PCLKA divided by 8 0x02 0x04 PCLKA divided by 16 0x04 0x08 PCLKA divided by 32 0x08 0x10 PCLKA divided by 64 0x10 0x20 PCLKA divided by 128 0x20 0x40 PCLKA divided by 256 0x40 0x80 PCLKA divided by 512 0x80 others Settings prohibited. true SD_SIZE Transfer Data Length Register 0x04C 32 read-write 0x00000200 0xFFFFFFFF LEN Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0. 0 9 read-write SD_OPTION SD Card Access Control Option Register 0x050 32 read-write 0x000040EE 0xFFFFFFFF WIDTH Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0. 15 15 read-write 0 4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) #0 1 1-bit width (WIDTH8=0 or 1 ) #1 WIDTH8 Bus Widthsee b15, WIDTH bit 13 13 read-write TOUTMASK Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence. 8 8 read-write 0 Activate Timeout #0 1 Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set) #1 TOP Timeout Counter 4 7 read-write 1111 Setting prohibited #1111 others SDHI clock x 2^(TOP+13) true CTOP Card Detect Time Counter 0 3 read-write 1111 Setting prohibited #1111 others IMCLK x 2^(CTOP+10) true SD_ERR_STS1 SD Error Status Register 1 0x058 32 read-only 0x00002000 0xFFFFFFFF CRCTK CRC Status TokenStore the CRC status token value (normal value is 010b) 12 14 read-only CRCTKE CRC Status Token Error 11 11 read-only 0 An error has not occured in the CRC status. #0 1 An error has occured in the CRC status. #1 RDCRCE Read Data CRC Error 10 10 read-only 0 CRC error has detected in read data #0 1 CRC error has not detected in read data #1 RSPCRCE1 Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0. 9 9 read-only 0 CRC error has not occured. #0 1 CRC error has occured in the response to a command issued within a command sequence. #1 RSPCRCE0 Response CRC Error 0NOTE: other than a response to a command issued within a command sequence 8 8 read-only 0 A CRC error has not occur in a response #0 1 A CRC error has occured in a response #1 CRCLENE CRC Status Token Length Error 5 5 read-only 0 An error has not occured in the CRC status length. #0 1 An error has occured in the CRC status length (and the end bit has not been detected) #1 RDLENE Read Data Length Error 4 4 read-only 0 An error has occurred not in the read data length. #0 1 An error has occured in the read data length (and the end bit has not been detected among the valid bits). #1 RSPLENE1 Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0. 3 3 read-only 0 An error has not occurred in the response length to a command issued within a command sequence. #0 1 An error has occured in the response length to a command issued within a command sequence. #1 RSPLENE0 Response Length Error 0NOTE: other than a response to a command issued within a command sequence 2 2 read-only 0 An error has not occured in the response length #0 1 An error has occured in the response length #1 CMDE1 Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0. 1 1 read-only 0 An error has not occurs in the command index of the response to a command issued within a command sequence. #0 1 An error has occured in the command index of the response to a command issued within a command sequence. #1 CMDE0 Command Error 0NOTE: other than a response to a command issued within a command sequence 0 0 read-only 0 An error has not occured in the command index of a response. #0 1 An error has occured in the command index of a response. #1 SD_ERR_STS2 SD Error Status Register 2 0x05C 32 read-only 0x00000000 0xFFFFFFFF CRCBSYTO CRC Status Token Busy Timeout 6 6 read-only 0 Not timeout #0 1 The busy state continues for longer than N-cycle after the CRC status #1 CRCTO CRC Status Token Timeout 5 5 read-only 0 Not timeout #0 1 The CRC status is not received though a longer time than N-cycle has elapsed after data writing. #1 RDTO Read Data Timeout 4 4 read-only 0 Not timeout #0 1 The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state. #1 BSYTO1 Busy Timeout 1 3 3 read-only 0 Not timeout. #0 1 The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0. #1 BSYTO0 Busy Timeout 0 2 2 read-only 0 Not timeout. #0 1 The busy state for longer than N-cycle continues after R1b response. #1 RSPTO1 Response Timeout 1 1 1 read-only 0 Not timeout. #0 1 The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0. #1 RSPTO0 Response Timeout 0 0 0 read-only 0 Not timeout. #0 1 The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. #1 SD_BUF0 SD Buffer Register 0x060 32 read-write 0x00000000 0x00000000 SD_BUF SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. 0 31 read-write SDIO_MODE SDIO Mode Control Register 0x068 32 read-write 0x00000000 0xFFFFFFFF C52PUB SDIO None AbortNOTE: See manual 9 9 read-write IOABT SDIO AbortNOTE: See manual 8 8 read-write RWREQ Read Wait Request 2 2 read-write 0 Allow SD/MMC to exit read wait state #0 1 Request for SD/MMC to enter read wait state. #1 INTEN SDIO Mode 0 0 read-write 1 Enables the SD host interface to receive SDIO interrupt from the SDIO card #1 0 Disables the SD host interface to receive SDIO interrupt from the SDIO card #0 SDIO_INFO1 SDIO Interrupt Flag Register 1 0x06C 32 read-write 0x00000000 0xFFFFFFF9 EXWT EXWT Status FlagNOTE: See manual 15 15 read-write zeroToClear modify EXPUB52 EXPUB52 Status FlagNOTE: See manual 14 14 read-write zeroToClear modify IOIRQ SDIO Interrupt Status 0 0 read-write zeroToClear modify 0 SDIO interrupt not accepted #0 1 SDIO interrupt accepted #1 SDIO_INFO1_MASK SDIO_INFO1 Interrupt Mask Register 0x070 32 read-write 0x0000C007 0xFFFFFFFF EXWTM EXWT Interrupt Request Mask Control 15 15 read-write 0 EXWT interrupt request not masked #0 1 EXWT interrupt request masked #1 EXPUB52M EXPUB52 Interrupt Request Mask Control 14 14 read-write 0 EXPUB52 interrupt request not masked #0 1 EXPUB52 interrupt request masked #1 IOIRQM IOIRQ Interrupt Mask Control 0 0 read-write 0 IOIRQ interrupt not masked #0 1 IOIRQ interrupt masked #1 SD_DMAEN DMA Mode Enable Register 0x1B0 32 read-write 0x00001010 0xFFFFFFFF DMAEN SD_BUF Read/Write DMA Transfer 1 1 read-write 0 The SD_BUF read/write DMA transfer is disabled. #0 1 The SD_BUF read/write DMA transfer is enabled. #1 SOFT_RST Software Reset Register 0x1C0 32 read-write 0x00000007 0xFFFFFFFF SDRST Software Reset of SD I/F Unit 0 0 read-write 0 Reset #0 1 Reset released #1 SDIF_MODE SD Interface Mode Setting Register 0x1CC 32 read-write 0x00000000 0xFFFFFFFF NOCHKCR CRC Check Mask (for MMC test commands) 8 8 read-write 0 CRC check is valid #0 1 CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write) #1 EXT_SWAP Swap Control Register 0x1E0 32 read-write 0x00000000 0xFFFFFFFF BRSWP SD_BUF0 Swap Read 7 7 read-write 0 The current data are read without swapping. #0 1 Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds. #1 BWSWP SD_BUF0 Swap Write 6 6 read-write 0 The current data are written without swapping. #0 1 Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds. #1 SDHI1 SD Host Interface 1 0x40062400 CRC CRC Calculator 0x40074000 0x00 2 registers 0x04 4 registers 0x04 1 registers 0x08 4 registers 0x08 2 registers 0x08 1 registers 0x0C 2 registers CRCCR0 CRC Control Register0 0x00 8 read-write 0x00 0xFF DORCLR CRCDOR Register Clear 7 7 write-only 0 No effect. #0 1 Clears the CRCDOR register. #1 LMS CRC Calculation Switching 6 6 read-write 0 Generates CRC for LSB first communication. #0 1 Generates CRC for MSB first communication. #1 GPS CRC Generating Polynomial Switching 0 2 read-write 000 No calculation is executed. #000 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) #100 101 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) #101 others No calculation is executed. true CRCCR1 CRC Control Register1 0x01 8 read-write 0x00 0xFF CRCSEN Snoop enable bit 7 7 read-write 0 Disabled #0 1 Enabled #1 CRCSWR Snoop-on-write/read switch bit 6 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 CRCDIR CRC Data Input Register 0x04 32 read-write 0x00000000 0xFFFFFFFF CRCDIR Calculation input Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDIR_BY CRC Data Input Register (byte access) CRCDIR 0x04 8 read-write 0x00 0xFF CRCDIR_BY Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) 0 7 read-write CRCDOR CRC Data Output Register 0x08 32 read-write 0x00000000 0xFFFFFFFF CRCDOR Calculation output Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDOR_HA CRC Data Output Register (halfword access) CRCDOR 0x08 16 read-write 0x0000 0xFFFF CRCDOR_HA Calculation output Data (Case of CRC-16 or CRC-CCITT ) 0 15 read-write CRCDOR_BY CRC Data Output Register(byte access) CRCDOR 0x08 8 read-write 0x00 0xFF CRCDOR_BY Calculation output Data (Case of CRC-8 ) 0 7 read-write CRCSAR Snoop Address Register 0x0C 16 read-write 0x0000 0xFFFF CRCSA snoop address bitSet the I/O register address to snoop 0 13 read-write 0x0003 SCI0.TDR 0x0003 0x0005 SCI0.RDR 0x0005 0x0023 SCI1.TDR 0x0023 0x0025 SCI1.RDR 0x0025 0x0043 SCI2.TDR 0x0043 0x0045 SCI2.RDR 0x0045 0x0063 SCI3.TDR 0x0063 0x0065 SCI3.RDR 0x0065 0x0083 SCI4.TDR 0x0083 0x0085 SCI4.RDR 0x0085 0x00A3 SCI5.TDR 0x00A3 0x00A5 SCI5.RDR 0x00A5 0x00C3 SCI6.TDR 0x00C3 0x00C5 SCI6.RDR 0x00C5 0x00E3 SCI7.TDR 0x00E3 0x00E5 SCI7.RDR 0x00E5 0x0103 SCI8.TDR 0x0103 0x0105 SCI8.RDR 0x0105 0x0123 SCI9.TDR 0x0123 0x0125 SCI9.RDR 0x0125 others Settings other than above are prohibited. true CTSU Capacitive Touch Sensing Unit 0x40081000 0x00 9 registers 0x0B 3 registers 0x10 14 registers CTSUCR0 CTSU Control Register 0 0x00 8 read-write 0x00 0xFF CTSUTXVSEL CTSU Transmission power supply selection 7 7 read-write 0 Select Vcc #0 1 Select internal logic power supply #1 CTSUINIT CTSU Control Block Initialization 4 4 read-write 0 Writing a 0 has no effect, this bit is read as 0. #0 1 initializes the CTSU control block and registers. #1 CTSUSNZ CTSU Wait State Power-Saving Enable 2 2 read-write 0 Power-saving function during wait state is disabled. #0 1 Power-saving function during wait state is enabled. #1 CTSUCAP CTSU Measurement Operation Start Trigger Select 1 1 read-write 0 Software trigger. #0 1 External trigger. #1 CTSUSTRT CTSU Measurement Operation Start 0 0 read-write 0 Measurement operation stops. #0 1 Measurement operation starts. #1 CTSUCR1 CTSU Control Register 1 0x01 8 read-write 0x00 0xFF CTSUMD CTSU Measurement Mode Select 6 7 read-write 00 Self-capacitance single scan mode #00 01 Self-capacitance multi-scan mode #01 10 Mutual capacitance simple scan mode #10 11 Mutual capacitance full scan mode #11 CTSUCLK CTSU Operating Clock Select 4 5 read-write 00 PCLK #00 01 PCLK/2 (PCLK divided by 2) #01 10 PCLK/2 (PCLK divided by 4) #10 11 Setting prohibited #11 CTSUATUNE1 CTSU Power Supply Capacity Adjustment 3 3 read-write 0 Normal output #0 1 High-current output #1 CTSUCSW CTSU LPF Capacitance Charging Control 1 1 read-write 0 Turned off capacitance switch #0 1 Turned on capacitance switch #1 CTSUPON CTSU Power Supply Enable 0 0 read-write 0 Powered off the CTSU #0 1 Powered on the CTSU #1 CTSUSDPRS CTSU Synchronous Noise Reduction Setting Register 0x02 8 read-write 0x00 0xFF CTSUSOFF CTSU High-Pass Noise Reduction Function Off Setting 6 6 read-write 0 High-pass noise reduction function turned on #0 1 High-pass noise reduction function turned off #1 CTSUPRMODE CTSU Base Period and Pulse Count Setting 4 5 read-write 00 510 pulses #00 01 126 pulses #01 10 62 pulses (recommended setting value) #10 11 Setting prohibited #11 CTSUPRRATIO CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b) 0 3 read-write CTSUSST CTSU Sensor Stabilization Wait Control Register 0x03 8 read-write 0x00 0xFF CTSUSST CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b. 0 7 read-write CTSUMCH0 CTSU Measurement Channel Register 0 0x04 8 read-write 0x1F 0xFF CTSUMCH0 CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'11111 in mode other than self-capacitor single scan mode, the measurement is stopped. 0 4 read-write CTSUMCH0 The value of CTSUMCH0 indicate to channel to be measured. true CTSUMCH1 CTSU Measurement Channel Register 1 0x05 8 read-only 0x1F 0xFF CTSUMCH1 CTSU Measurement Channel 1 Note1: If the value of CTSUMCH1 was set to b'11111, the measurement is stopped. 0 4 read-only CTSUMCH1 The value of CTSUMCH1 indicate to channel to be measured. true CTSUCHAC0 CTSU Channel Enable Control Register 0 0x06 8 read-write 0x00 0xFF CTSUCHAC0 CTSU Channel Enable Control 0.0: Not measurement target1: Measurement targetNote: CTSUCHAC0[0] corresponds to TS00 and CTSUCHAC0[7] corresponds to TS07. 0 7 read-write CTSUCHAC0 TS pin which correspond to the bit number of CTSUCHAC0 register set whether the measurement target. true CTSUCHAC1 CTSU Channel Enable Control Register 1 0x07 8 read-write 0x00 0xFF CTSUCHAC1 CTSU Channel Enable Control 1.0: Not measurement target1: Measurement targetNote: CTSUCHAC1[0] corresponds to TS08 and CTSUCHAC1[7] corresponds to TS15. 0 7 read-write CTSUCHAC1 TS pin which correspond to the bit number of CTSUCHAC1 register set whether the measurement target. true CTSUCHAC2 CTSU Channel Enable Control Register 2 0x08 8 read-write 0x00 0xFF CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register 0 0x0B 8 read-write 0x00 0xFF CTSUCHTRC0 CTSU Channel Transmit/Receive Control 0CTSUCHTRC0[0] corresponds to TS00 and CTSUCHTRC0[7] corresponds to TS07. ( 0: Reception / 1: Transmission ) 0 7 read-write CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register 1 0x0C 8 read-write 0x00 0xFF CTSUCHTRC1 CTSU Channel Transmit/Receive Control 1CTSUCHTRC1[0] corresponds to TS08 and CTSUCHTRC1[7] corresponds to TS15. ( 0: Reception / 1: Transmission ) 0 7 read-write CTSUCHTRC2 CTSU Channel Transmit/Receive Control Register 2 0x0D 8 read-write 0x00 0xFF CTSUDCLKC CTSU High-Pass Noise Reduction Control Register 0x10 8 read-write 0x00 0xFF CTSUSSCNT CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b. 4 5 read-write CTSUSSMOD CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b. 0 1 read-write CTSUST CTSU Status Register 0x11 8 read-write 0x00 0xFF CTSUPS CTSU Mutual Capacitance Status Flag 7 7 read-only 0 First measurement #0 1 Second measurement #1 CTSUROVF CTSU Reference Counter Overflow Flag 6 6 read-write 0 No overflow #0 1 An overflow #1 CTSUSOVF CTSU Sensor Counter Overflow Flag 5 5 read-write 0 No overflow #0 1 An overflow #1 CTSUDTSR CTSU Data Transfer Status Flag 4 4 read-only 0 Measurement result has been read #0 1 Measurement result has not been read #1 CTSUSTC CTSU Measurement Status Counter 0 2 read-only 000 Status 0 #000 001 Status 1 #001 010 Status 2 #010 011 Status 3 #011 100 Status 4 #100 101 Status 5 #101 CTSUSSC CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 0x12 16 read-write 0x0000 0xFFFF CTSUSSDIV CTSU Spectrum Diffusion Frequency Division Setting 8 11 read-write 0000 4.00 <= fb #0000 0001 2.00 <= fb < 4.00 #0001 0010 1.33 <= fb < 2.00 #0010 0011 1.00 <= fb < 1.33 #0011 0100 0.80 <= fb < 1.00 #0100 0101 0.67 <= fb < 0.80 #0101 0110 0.57 <= fb < 0.67 #0110 0111 0.50 <= fb < 0.57 #0111 1000 0.44 <= fb < 0.50 #1000 1001 0.40 <= fb < 0.44 #1001 1010 0.36 <= fb < 0.40 #1010 1011 0.33 <= fb < 0.36 #1011 1100 0.31 <= fb < 0.33 #1100 1101 0.29 <= fb < 0.31 #1101 1110 0.27 <= fb < 0.29 #1110 1111 fb < 0.27 #1111 CTSUSO0 CTSU Sensor Offset Register 0 0x14 16 read-write 0x0000 0xFFFF CTSUSNUM CTSU Measurement Count Setting 10 15 read-write CTSUSO CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 ) 0 9 read-write CTSUSO1 CTSU Sensor Offset Register 1 0x16 16 read-write 0x0000 0xFFFF CTSUICOG CTSU ICO Gain Adjustment 13 14 read-write 00 100% gain #00 01 66% gain #01 10 50% gain #10 11 40% gain #11 CTSUSDPA CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2 8 12 read-write CTSURICOA CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 ) 0 7 read-write CTSUSC CTSU Sensor Counter 0x18 16 read-only 0x0000 0xFFFF CTSUSC CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. 0 15 read-only CTSURC CTSU Reference Counter 0x1A 16 read-only 0x0000 0xFFFF CTSURC CTSU Reference Counter 0 15 read-only CTSUERRS CTSU Error Status Register 0x1C 16 read-only 0x0000 0x7FFF CTSUICOMP TSCAP Voltage Error Monitor 15 15 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 MMPU Bus Master MPU 0x40000000 0x00 3072 registers 0x200 512 registers 0x600 128 registers 0xA00 128 registers 0x204 512 registers 0x604 128 registers 0xA04 128 registers 0x208 512 registers 0x608 128 registers 0xA08 128 registers 0x102 2 registers 0x502 2 registers 0x902 2 registers 3 0x400 A,B,C MMPUCTL%s Bus Master MPU Control Register 0x000 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the OAD and ENABLE bit is invalid. true OAD Operation after detection 1 1 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 ENABLE Master Group enable 0 0 read-write 0 Master Group is disabled. Permission of all regions. #0 1 Master Group is enabled. Protection of all regions. #1 32 0x010 0-31 MMPUACA%s Group A Region %s Access Control Register 0x200 16 read-write 0x0000 0xFFFF WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 ENABLE Region enable 0 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 8 0x010 0-7 MMPUACB%s Group B Region %s Access Control Register 0x600 16 read-write 0x0000 0xFFFF WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 ENABLE Region enable 0 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 8 0x010 0-7 MMPUACC%s Group C Region %s Access Control Register 0xA00 16 read-write 0x0000 0xFFFF WP Write protection 2 2 read-write 0 Write permission #0 1 Write protection #1 RP Read protection 1 1 read-write 0 Read permission #0 1 Read protection #1 ENABLE Region enable 0 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 32 0x010 0-31 MMPUSA%s Group A Region %s Start Address Register 0x204 32 read-write 0x00000000 0x00000003 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write 8 0x010 0-7 MMPUSB%s Group B Region %s Start Address Register 0x604 32 read-write 0x00000000 0x00000003 MMPUSB Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write 8 0x010 0-7 MMPUSC%s Group C Region %s Start Address Register 0xA04 32 read-write 0x00000000 0x00000003 MMPUSC Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write 32 0x010 0-31 MMPUEA%s Group A Region %s End Address Register 0x208 32 read-write 0x00000003 0x00000003 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write 8 0x010 0-7 MMPUEB%s Group B Region %s End Address Register 0x608 32 read-write 0x00000003 0x00000003 MMPUEB Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write 8 0x010 0-7 MMPUEC%s Group C Region %s End Address Register 0xA08 32 read-write 0x00000003 0x00000003 MMPUEC Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUPTA Group A Protection of Register 0x102 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true PROTECT Protection of register(MMPUSAn, MMPUEAn and MMPUACAn) 0 0 read-write 0 All Bus Master MPU Group A register writing is possible. #0 1 All Bus Master MPU Group A register writing is protected. Read is possible. #1 MMPUPTB Group B Protection of Register 0x502 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true PROTECT Protection of register(MMPUSBn, MMPUEBn and MMPUACBn) 0 0 read-write 0 All Bus Master MPU Group B register writing is possible. #0 1 All Bus Master MPU Group B register writing is protected. Read is possible. #1 MMPUPTC Group C protection of register 0x902 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true PROTECT Protection of register (MMPUSCn, MMPUECn and MMPUACCn) 0 0 read-write 0 All Bus Master MPU Group C register writing is possible. #0 1 All Bus Master MPU Group C register writing is protected. Read is possible. #1 SMPU Bus Slave MPU 0x40000C00 0x00 2 registers 0x10 2 registers 0x14 2 registers 0x18 26 registers 0x34 2 registers 0x38 2 registers SMPUCTL Slave MPU Control Register 0x00 16 read-write 0x0000 0xFFFF KEY Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. 8 15 write-only 0xA5 Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT and OAD bit is invalid. true PROTECT Protection of register 1 1 read-write 0 All Bus Slave register writing is possible. #0 1 All Bus Slave register writing is protected. Read is possible. #1 OAD Master Group enable 0 0 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 SMPUMBIU Access Control Register for MBIU 0x10 16 read-write 0x2000 0xFFFF WPSRAMHS SRAMHS Write Protection 15 15 read-write 0 Memory protection for SRAMHS writes from master group A, B, and C disabled #0 1 Memory protection for SRAMHS writes from master group A, B, and C enabled. #1 RPSRAMHS SRAMHS Read Protection 14 14 read-write 0 Memory protection for SRAMHS reads from master group A, B, and C disabled #0 1 Memory protection for SRAMHS reads from master group A, B, and C enabled. #1 WPFLI Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.) 13 13 read-write 0 Setting prohibited #0 1 Memory protection for code flash memory writes from master group A, B, and C enabled. #1 RPFLI Code Flash Memory Read Protection 12 12 read-write 0 Memory protection for code flash memory reads from master group A, B, and C disabled #0 1 Memory protection for code flash memory reads from master group A, B, and C enabled. #1 WPGRPC Master Group C Write protection 7 7 read-write 0 Memory protection for master group C writes disabled #0 1 Memory protection for master group C writes enabled. #1 RPGRPC Master Group C Read protection 6 6 read-write 0 Memory protection for master group C reads disabled #0 1 Memory protection for master group C reads enabled. #1 WPGRPB Master Group B Write protection 5 5 read-write 0 Memory protection for master group B writes disabled #0 1 Memory protection for master group B writes enabled. #1 RPGRPB Master Group B Read protection 4 4 read-write 0 Memory protection for master group B reads disabled #0 1 Memory protection for master group B reads enabled. #1 WPGRPA Master Group A Write protection 3 3 read-write 0 Memory protection for master group A writes disabled #0 1 Memory protection for master group A writes enabled. #1 RPGRPA Master Group A Read protection 2 2 read-write 0 Memory protection for master group A reads disabled #0 1 Memory protection for master group A reads enabled. #1 SMPUFBIU Access Control Register for FBIU 0x14 16 read-write 0x00C0 0xFFFF WP_GRPC Master Group C Write protection 7 7 read-write 0 Setting prohibited #0 1 Master group C write of memory protection is enabled. The write value should always be 1. #1 RP_GRPC Master Group C Read protection 6 6 read-write 0 Setting prohibited #0 1 Master group C read of memory protection is enabled. The write value should always be 1. #1 WP_GRPB Master Group B Write protection 5 5 read-write 0 Master group B write of memory protection is disabled. #0 1 Master group B write of memory protection is enabled. #1 RP_GRPB Master Group B Read protection 4 4 read-write 0 Master group B read of memory protection is disabled. #0 1 Master group B read of memory protection is enabled. #1 WP_GRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection is disabled. #0 1 Master group A write of memory protection is enabled. #1 RP_GRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection is disabled. #0 1 Master group A read of memory protection is enabled. #1 WP_CPU CPU Write protection 1 1 read-write 0 CPU write of memory protection is disabled. #0 1 CPU write of memory protection is enabled. #1 RP_CPU CPU Read protection 0 0 read-write 0 CPU read of memory protection is disabled. #0 1 CPU read of memory protection is enabled. #1 2 0x4 0,1 SMPUSRAM%s Access Control Register for SRAM%s 0x18 16 read-write 0x0000 0xFFFF WP_GRPC Master Group C Write protection 7 7 read-write 0 Master group C write of memory protection is disabled. #0 1 Master group C write of memory protection is enabled. #1 RP_GRPC Master Group C Read protection 6 6 read-write 0 Master group C read of memory protection is disabled. #0 1 Master group C read of memory protection is enabled. #1 WP_GRPB Master Group B Write protection 5 5 read-write 0 Master group B write of memory protection is disabled. #0 1 Master group B write of memory protection is enabled. #1 RP_GRPB Master Group B Read protection 4 4 read-write 0 Master group B read of memory protection is disabled. #0 1 Master group B read of memory protection is enabled. #1 WP_GRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection is disabled. #0 1 Master group A write of memory protection is enabled. #1 RP_GRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection is disabled. #0 1 Master group A read of memory protection is enabled. #1 WP_CPU CPU Write protection 1 1 read-write 0 CPU write of memory protection is disabled. #0 1 CPU write of memory protection is enabled. #1 RP_CPU CPU Read protection 0 0 read-write 0 CPU read of memory protection is disabled. #0 1 CPU read of memory protection is enabled. #1 4 0x4 0,2,6,7 SMPUP%sBIU Access Control Register for P%sBIU 0x20 16 read-write 0x00F0 0xFFFF WP_GRPC Master Group C Write protection 7 7 read-write 0 Setting prohibited #0 1 Master group C write of memory protection is enabled. The write value should always be 1. #1 RP_GRPC Master Group C Read protection 6 6 read-write 0 Setting prohibited #0 1 Master group C read of memory protection is enabled. The write value should always be 1. #1 WP_GRPB Master Group B Write protection 5 5 read-write 0 Setting prohibited #0 1 Master group B write of memory protection is enabled. The write value should always be 1. #1 RP_GRPB Master Group B Read protection 4 4 read-write 0 Setting prohibited #0 1 Master group B read of memory protection is enabled. The write value should always be 1. #1 WP_GRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection is disabled. #0 1 Master group A write of memory protection is enabled. #1 RP_GRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection is disabled. #0 1 Master group A read of memory protection is enabled. #1 WP_CPU CPU Write protection 1 1 read-write 0 CPU write of memory protection is disabled. #0 1 CPU write of memory protection is enabled. #1 RP_CPU CPU Read protection 0 0 read-write 0 CPU read of memory protection is disabled. #0 1 CPU read of memory protection is enabled. #1 SMPUEXBIU Access Control Register for EXBIU 0x30 16 read-write 0x0000 0xFFFF WP_GRPC Master Group C Write protection 7 7 read-write 0 Master group C write of memory protection is disabled. #0 1 Master group C write of memory protection is enabled. #1 RP_GRPC Master Group C Read protection 6 6 read-write 0 Master group C read of memory protection is disabled. #0 1 Master group C read of memory protection is enabled. #1 WP_GRPB Master Group B Write protection 5 5 read-write 0 Master group B write of memory protection is disabled. #0 1 Master group B write of memory protection is enabled. #1 RP_GRPB Master Group B Read protection 4 4 read-write 0 Master group B read of memory protection is disabled. #0 1 Master group B read of memory protection is enabled. #1 WP_GRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection is disabled. #0 1 Master group A write of memory protection is enabled. #1 RP_GRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection is disabled. #0 1 Master group A read of memory protection is enabled. #1 WP_CPU CPU Write protection 1 1 read-write 0 CPU write of memory protection is disabled. #0 1 CPU write of memory protection is enabled. #1 RP_CPU CPU Read protection 0 0 read-write 0 CPU read of memory protection is disabled. #0 1 CPU read of memory protection is enabled. #1 SMPUEXBIU2 Access Control Register for EXBIU2 0x34 16 read-write 0x0000 0xFFFF WP_GRPC Master Group C Write protection 7 7 read-write 0 Master group C write of memory protection is disabled. #0 1 Master group C write of memory protection is enabled. #1 RP_GRPC Master Group C Read protection 6 6 read-write 0 Master group C read of memory protection is disabled. #0 1 Master group C read of memory protection is enabled. #1 WP_GRPB Master Group B Write protection 5 5 read-write 0 Master group B write of memory protection is disabled. #0 1 Master group B write of memory protection is enabled. #1 RP_GRPB Master Group B Read protection 4 4 read-write 0 Master group B read of memory protection is disabled. #0 1 Master group B read of memory protection is enabled. #1 WP_GRPA Master Group A Write protection 3 3 read-write 0 Master group A write of memory protection is disabled. #0 1 Master group A write of memory protection is enabled. #1 RP_GRPA Master Group A Read protection 2 2 read-write 0 Master group A read of memory protection is disabled. #0 1 Master group A read of memory protection is enabled. #1 WP_CPU CPU Write protection 1 1 read-write 0 CPU write of memory protection is disabled. #0 1 CPU write of memory protection is enabled. #1 RP_CPU CPU Read protection 0 0 read-write 0 CPU read of memory protection is disabled. #0 1 CPU read of memory protection is enabled. #1 SPMON CPU Stack Pointer Monitor 0x40000D00 0x00 2 registers 0x04 14 registers 0x14 12 registers MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x00 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the OAD bit is invalid. true OAD Operation after detection 0 0 read-write 1 Internal reset. #1 0 Non-maskable interrupt. #0 MSPMPUCTL Stack Pointer Monitor Access Control Register 0x04 16 read-write 0x0000 0xFFFF ERROR SP_main monitor error flag 8 8 read-only 0 SP_main has not overflowed or underflowed. #0 1 SP_main has overflowed or underflowed. #1 ENABLE SP_main monitor enable 0 0 read-write 0 SP_main monitor is disabled. #0 1 SP_main monitor is enabled. #1 MSPMPUPT Stack Pointer Monitor Protection Register 0x06 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true PROTECT Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) 0 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 MSPMPUSA Main Stack Pointer Monitor Start Address Register 0x08 32 read-write 0x00000000 0x00000003 MSPMPUSA Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 2 31 read-write 0x1FF00000 0x200FFFFC MSPMPUEA Main Stack Pointer Monitor End Address Register 0x0C 32 read-write 0x00000003 0x00000003 MSPMPUEA Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 2 31 read-write 0x1FF00003 0x200FFFFF PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x10 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the OAD bit is invalid. true OAD Operation after detection 0 0 read-write 1 Internal reset. #1 0 Non-maskable interrupt. #0 PSPMPUCTL Stack Pointer Monitor Access Control Register 0x14 16 read-write 0x0000 0xFEFF ERROR SP_process monitor error flag 8 8 read-only 0 SP_process has not overflowed or underflowed. #0 1 SP_process has overflowed or underflowed. #1 ENABLE SP_process monitor enable 0 0 read-write 0 SP_process monitor is disabled. #0 1 SP_process monitor is enabled. #1 PSPMPUPT Stack Pointer Monitor Protection Register 0x16 16 read-write 0x0000 0xFFFF KEY Write Keyword The data written to these bits are not stored. 8 15 write-only 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 others Writing to the PROTECT bit is invalid. true PROTECT Protection of register (PSPMPUAC, PSPMPUSA and PSPMPUSE) 0 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 PSPMPUSA Process Stack Pointer Monitor Start Address Register 0x18 32 read-write 0x00000000 0x00000003 PSPMPUSA Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 2 31 read-write 0x1FF00000 0x200FFFFC PSPMPUEA Process Stack Pointer Monitor End Address Register 0x1C 32 read-write 0x00000003 0x00000003 PSPMPUEA Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 2 31 read-write 0x1FF00003 0x200FFFFF ADC120 12bit A/D Converter 0 0x4005C000 0x00 13 registers 0x0E 34 registers 0x40 10 registers 0x62 22 registers 0x7A 4 registers 0x80 9 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xB0 33 registers 0xD2 1 registers 0xDD 11 registers 0xEA 6 registers 0x1A0 4 registers 0x1B0 2 registers 0x1B4 2 registers 0x1E0 1 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xFFFF ADST A/D Conversion Start 15 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 TRGE Trigger Start Enable 9 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 EXTRG Trigger Select 8 8 read-write 0 A/D conversion is started by the synchronous trigger (ELCTRG0). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG0#). #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 GBADIE Group B Scan End Interrupt Enable 6 6 read-write 0 Disables S12GBADI0 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI0 interrupt generation upon group B scan completion. #1 DBLANS Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xFFFF ANSA07 AN007 Select 7 7 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSA06 AN006 Select 6 6 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSA05 AN005 Select 5 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSA04 AN004 Select 4 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSA03 AN003 Select 3 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSA02 AN002 Select 2 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSA01 AN001 Select 1 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSA00 AN000 Select 0 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xFFFF ANSA20 AN020 Select 4 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSA19 AN019 Select 3 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSA18 AN018 Select 2 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSA17 AN017 Select 1 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSA16 AN016 Select 0 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xFFFF ADS07 A/D-Converted Value Addition/Average Channel AN007 Select 7 7 read-write 0 AN007 is not selected. #0 1 AN007 is selected. #1 ADS06 A/D-Converted Value Addition/Average Channel AN006 Select 6 6 read-write 0 AN006 is not selected. #0 1 AN006 is selected. #1 ADS05 A/D-Converted Value Addition/Average Channel AN005 Select 5 5 read-write 0 AN005 is not selected. #0 1 AN005 is selected. #1 ADS04 A/D-Converted Value Addition/Average Channel AN004 Select 4 4 read-write 0 AN004 is not selected. #0 1 AN004 is selected. #1 ADS03 A/D-Converted Value Addition/Average Channel AN003 Select 3 3 read-write 0 AN003 is not selected. #0 1 AN003 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN002 Select 2 2 read-write 0 AN002 is not selected. #0 1 AN002 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN001 Select 1 1 read-write 0 AN001 is not selected. #0 1 AN001 is selected. #1 ADS00 A/D-Converted Value Addition/Average Channel AN000 Select 0 0 read-write 0 AN000 is not selected. #0 1 AN000 is selected. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xFFFF ADS20 A/D-Converted Value Addition/Average Channel AN020 Select 4 4 read-write 0 AN020 is not selected. #0 1 AN020 is selected. #1 ADS19 A/D-Converted Value Addition/Average Channel AN019 Select 3 3 read-write 0 AN019 is not selected. #0 1 AN019 is selected. #1 ADS18 A/D-Converted Value Addition/Average Channel AN018 Select 2 2 read-write 0 AN018 is not selected. #0 1 AN018 is selected. #1 ADS17 A/D-Converted Value Addition/Average Channel AN017 Select 1 1 read-write 0 AN017 is not selected. #0 1 AN017 is selected. #1 ADS16 A/D-Converted Value Addition/Average Channel AN016 Select 0 0 read-write 0 AN016 is not selected. #0 1 AN016 is selected. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xFF AVEE Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 7 read-write 0 Disabled #0 1 Enabled #1 ADC Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write 000 1-time conversion (no addition; same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 others Setting prohibited true ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xFFFF ADRFMT A/D Data Register Format Select 15 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disables self-diagnosis of ADC12. #0 1 Enables self-diagnosis of ADC12. #1 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 ADPRC A/D Conversion Accuracy Specify 1 2 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 01 A/D conversion is performed with 10-bit accuracy. #01 10 A/D conversion is performed with 8-bit accuracy. #10 11 Setting prohibited #11 ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xFFFF TRSA A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 13 read-write TRSB A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADEXICR A/D Conversion Extended Input Control Register 0x012 16 read-write 0x0000 0xFFFF OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 11 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group B in group scan mode. #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 10 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is not selected for group B in group scan mode. #1 OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xFFFF ANSB07 AN007 Select 7 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSB06 AN006 Select 6 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSB05 AN005 Select 5 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSB04 AN004 Select 4 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSB03 AN003 Select 3 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSB02 AN002 Select 2 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSB01 AN001 Select 1 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSB00 AN000 Select 0 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xFFFF ANSB20 AN020 Select 4 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSB19 AN019 Select 3 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSB18 AN018 Select 2 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSB17 AN017 Select 1 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSB16 AN016 Select 0 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ADDBLDR A/D Data Duplication Register 0x018 16 read-only 0x0000 0xFFFF ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xFFFF ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xFFFF ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xFFFF DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 AD A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed "0" 0 11 read-only 8 0x2 0-7 ADDR%s A/D Data Register %s 0x020 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only 5 0x2 16-20 ADDR%s A/D Data Register %s 0x040 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADSHCR A/D Sample and Hold Circuit Control Register 0x066 16 read-write 0x0018 0xFFFF SHANS2 AN002 sample-and-hold circuit Select 10 10 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS1 AN001 sample-and-hold circuit Select 9 9 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS0 AN000 sample-and-hold circuit Select 8 8 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SSTSH Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states) 0 7 read-write 0x04 0xFF ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xFF CHARGE Selection of Precharge or Discharge 4 4 read-write 0 Discharge #0 1 Precharge #1 ADNDIS The charging time 0 3 read-write 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 others ( 1 / ADCLK ) x ADNDIS true ADSHMSR A/D Sample and Hold Operation Mode Select Register 0x07C 8 read-write 0x00 0xFF SHMD Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select 0 0 read-write 0 Sampling by channel-dedicated sample-and-hold circuit is disable. #0 1 Sampling by channel-dedicated sample-and-hold circuit is enable. #1 ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xFFFF GBRP Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 GBRSCN Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) 1 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 ADDBLDRA A/D Data Duplication Register A 0x084 16 read-only 0x0000 0xFFFF ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplication Register B 0x086 16 read-only 0x0000 0xFFFF ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xFF MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCOMB Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. 0 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xFFFF CMPAIE Compare A Interrupt Enable 15 15 read-write 0 S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met. #0 1 S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met. #0 1 S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met. #1 CMPAE Compare Window A Operation Enable 11 11 read-write 0 Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window A operation is enabled. #1 CMPBE Compare Window B Operation Enable 9 9 read-write 0 Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window B operation is enabled. #1 CMPAB Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases. #00 01 S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases. #01 10 S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases. #10 11 Setting prohibited. #11 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xFF CMPOCA Internal reference voltage Compare selection bit. 1 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xFF CMPLOCA Compare Window A Internal Reference Voltage ComparisonCondition Select 1 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xFFFF CMPCHA07 Compare Window A Channel AN007 Select 7 7 read-write 0 Disable compare function for AN007 #0 1 Enable compare function for AN007 #1 CMPCHA06 Compare Window A Channel AN006 Select 6 6 read-write 0 Disable compare function for AN006 #0 1 Enable compare function for AN006 #1 CMPCHA05 Compare Window A Channel AN005 Select 5 5 read-write 0 Disable compare function for AN005 #0 1 Enable compare function for AN005 #1 CMPCHA04 Compare Window A Channel AN004 Select 4 4 read-write 0 Disable compare function for AN004 #0 1 Enable compare function for AN004 #1 CMPCHA03 Compare Window A Channel AN003 Select 3 3 read-write 0 Disable compare function for AN003 #0 1 Enable compare function for AN003 #1 CMPCHA02 Compare Window A Channel AN002 Select 2 2 read-write 0 Disable compare function for AN002 #0 1 Enable compare function for AN002 #1 CMPCHA01 Compare Window A Channel AN001 Select 1 1 read-write 0 Disable compare function for AN001 #0 1 Enable compare function for AN001 #1 CMPCHA00 Compare Window A Channel AN000 Select 0 0 read-write 0 Disable compare function for AN000 #0 1 Enable compare function for AN000 #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xFFFF CMPCHA20 AN020 Select 4 4 read-write 0 Excludes AN020 from the compare window A target range. #0 1 Includes AN020 from the compare window A target range. #1 CMPCHA19 AN019 Select 3 3 read-write 0 Excludes AN019 from the compare window A target range. #0 1 Includes AN019 from the compare window A target range. #1 CMPCHA18 AN018 Select 2 2 read-write 0 Excludes AN018 from the compare window A target range. #0 1 Includes AN018 from the compare window A target range. #1 CMPCHA17 AN017 Select 1 1 read-write 0 Excludes AN017 from the compare window A target range. #0 1 Includes AN017 from the compare window A target range. #1 CMPCHA16 AN016 Select 0 0 read-write 0 Excludes AN016 from the compare window A target range. #0 1 Includes AN016 from the compare window A target range. #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xFFFF CMPLCHA07 Comparison condition of AN007 7 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN006 6 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN005 5 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA04 Comparison condition of AN004 4 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN003 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN002 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN001 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA00 Comparison condition of AN000 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xFFFF CMPLCHA20 Comparison condition of AN020 4 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA19 Comparison condition of AN019 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN018 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN017 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA16 Comparison condition of AN016 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x09C 16 read-write 0x0000 0xFFFF ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x09E 16 read-write 0x0000 0xFFFF ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xFFFF CMPSTCHA07 Compare window A flag of AN007 7 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare window A flag of AN004 4 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA00 Compare window A flag of AN000 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0x0A2 16 read-write 0x0000 0xFFFF CMPSTCHA20 Compare window A flag of AN020 4 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare window A flag of AN019 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA16 Compare window A flag of AN016 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xFF CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0x0A6 8 read-write 0x00 0xFF CMPLB Compare window B Compare condition setting bit. 7 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 CMPCHB Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. 0 5 read-write 0x00 AN000 0x00 0x01 AN001 0x01 0x02 AN002 0x02 0x03 AN003 0x03 0x04 AN004 0x04 0x05 AN005 0x05 0x06 AN006 0x06 0x07 AN007 0x07 0x10 AN016 0x10 0x11 AN017 0x11 0x12 AN018 0x12 0x13 AN019 0x13 0x14 AN020 0x14 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F others Setting prohibited true ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xFFFF ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xFFFF ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xFF CMPSTB Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN007,AN016-AN020, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADSSTRL A/D Sampling State Register L 0x0DD 8 read-write 0x0B 0xFF SST Sampling Time Setting (AN016-AN020) 0 7 read-write 0x05 0xFF ADSSTRT A/D Sampling State Register T 0x0DE 8 read-write 0x0B 0xFF SST Sampling Time Setting (temperature sensor output) 0 7 read-write 0x05 0xFF ADSSTRO A/D Sampling State Register O 0x0DF 8 read-write 0x0B 0xFF SST Sampling Time Setting (Internal reference voltage) 0 7 read-write 0x05 0xFF 8 0x1 0-7 ADSSTR0%s A/D Sampling State Register %s (Corresponding Channel is AN00%s ) 0x0E0 8 read-write 0x0B 0xFF SST Sampling time setting 0 7 read-write 0x05 0xFF ADPGACR A/D Programmable Gain Amplifier Control Register 0x1A0 16 read-write 0x9999 0xFFFF P002GEN PGA P002 gain setting and enable bit 11 11 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P002ENAMP Amplifier enable bit for PGA P002 10 10 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P002SEL1 The amplifier passing is enable for PGA P002 9 9 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P002SEL0 A through amplifier is enable for PGA P002 8 8 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P001GEN PGA P001 gain setting and enable bit 7 7 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P001ENAMP Amplifier enable bit for PGA P001 6 6 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P001SEL1 The amplifier passing is enable for PGA P001 5 5 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P001SEL0 A through amplifier is enable for PGA P001 4 4 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P000GEN PGA P000 gain setting and enable bit 3 3 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P000ENAMP Amplifier enable bit for PGA P000 2 2 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P000SEL1 The amplifier passing is enable for PGA P000 1 1 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P000SEL0 A through amplifier is enable for PGA P000 0 0 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 ADPGAGS0 A/D Programmable Gain Amplifier Gain Setting Register 0 0x1A2 16 read-write 0x0000 0xFFFF P002GAIN PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0. 8 11 read-write 0000 x 2.000 (ADPGADDCR0.P002DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P002DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P002DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P002DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P002DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P002DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P002DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P002DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P002DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P002DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P002DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0) #1111 P001GAIN PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0. 4 7 read-write 0000 x 2.000 (ADPGADDCR0.P001DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P001DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P001DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P001DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P001DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P001DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P001DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P001DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P001DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P001DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P001DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0) #1111 P000GAIN PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0. 0 3 read-write 0000 x 2.000 (ADPGADDCR0.P000DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P000DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P000DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P000DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P000DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P000DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P000DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P000DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P000DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P000DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P000DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0) #1111 ADPGADCR0 A/D Programmable Gain Amplifier Differential Input Control Register 0x1B0 16 read-write 0x0000 0xFFFF P003DG P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. 12 13 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P002DEN P002 Differential Input Enable 11 11 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P002DG P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. 8 9 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P001DEN P001 Differential Input Enable 7 7 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P001DG P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b. 4 5 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P000DEN P000 Differential Input Enable 3 3 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P000DG P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b. 0 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 ADC121 12bit A/D Converter 1 0x4005C200 0x00 13 registers 0x0E 26 registers 0x2A 6 registers 0x40 8 registers 0x62 22 registers 0x7A 4 registers 0x80 9 registers 0x8C 1 registers 0x90 21 registers 0xA6 1 registers 0xA8 5 registers 0xB0 33 registers 0xD2 1 registers 0xDD 7 registers 0xE5 3 registers 0xEA 6 registers 0x1A0 4 registers 0x1B0 2 registers 0x1B4 2 registers 0x1E0 1 registers ADCSR A/D Control Register 0x000 16 read-write 0x0000 0xFFFF ADST A/D Conversion Start 15 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 ADCS Scan Mode Select 13 14 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 TRGE Trigger Start Enable 9 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 EXTRG Trigger Select 8 8 read-write 0 A/D conversion is started by the synchronous trigger (ELCTRG1). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG1#). #1 DBLE Double Trigger Mode Select 7 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 GBADIE Group B Scan End Interrupt Enable 6 6 read-write 0 Disables S12GBADI1 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI1 interrupt generation upon group B scan completion. #1 DBLANS Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write ADANSA0 A/D Channel Select Register A0 0x004 16 read-write 0x0000 0xFFFF ANSA07 AN107 Select 7 7 read-write 0 AN107 is not subjected to conversion. #0 1 AN107 is subjected to conversion. #1 ANSA06 AN106 Select 6 6 read-write 0 AN106 is not subjected to conversion. #0 1 AN106 is subjected to conversion. #1 ANSA05 AN105 Select 5 5 read-write 0 AN105 is not subjected to conversion. #0 1 AN105 is subjected to conversion. #1 ANSA03 AN103 Select 3 3 read-write 0 AN103 is not subjected to conversion. #0 1 AN103 is subjected to conversion. #1 ANSA02 AN102 Select 2 2 read-write 0 AN102 is not subjected to conversion. #0 1 AN102 is subjected to conversion. #1 ANSA01 AN101 Select 1 1 read-write 0 AN101 is not subjected to conversion. #0 1 AN101 is subjected to conversion. #1 ANSA00 AN100 Select 0 0 read-write 0 AN100 is not subjected to conversion. #0 1 AN100 is subjected to conversion. #1 ADANSA1 A/D Channel Select Register A1 0x006 16 read-write 0x0000 0xFFFF ANSA19 AN119 Select 3 3 read-write 0 AN119 is not subjected to conversion. #0 1 AN119 is subjected to conversion. #1 ANSA18 AN118 Select 2 2 read-write 0 AN118 is not subjected to conversion. #0 1 AN118 is subjected to conversion. #1 ANSA17 AN117 Select 1 1 read-write 0 AN117 is not subjected to conversion. #0 1 AN117 is subjected to conversion. #1 ANSA16 AN116 Select 0 0 read-write 0 AN116 is not subjected to conversion. #0 1 AN116 is subjected to conversion. #1 ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x008 16 read-write 0x0000 0xFFFF ADS07 A/D-Converted Value Addition/Average Channel AN107 Select 7 7 read-write 0 AN107 is not selected. #0 1 AN107 is selected. #1 ADS06 A/D-Converted Value Addition/Average Channel AN106 Select 6 6 read-write 0 AN106 is not selected. #0 1 AN106 is selected. #1 ADS05 A/D-Converted Value Addition/Average Channel AN105 Select 5 5 read-write 0 AN105 is not selected. #0 1 AN105 is selected. #1 ADS03 A/D-Converted Value Addition/Average Channel AN103 Select 3 3 read-write 0 AN103 is not selected. #0 1 AN103 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN102 Select 2 2 read-write 0 AN102 is not selected. #0 1 AN102 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN101 Select 1 1 read-write 0 AN101 is not selected. #0 1 AN101 is selected. #1 ADS00 A/D-Converted Value Addition/Average Channel AN100 Select 0 0 read-write 0 AN100 is not selected. #0 1 AN100 is selected. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0x00A 16 read-write 0x0000 0xFFFF ADS19 A/D-Converted Value Addition/Average Channel AN119 Select 3 3 read-write 0 AN119 is not selected. #0 1 AN119 is selected. #1 ADS18 A/D-Converted Value Addition/Average Channel AN118 Select 2 2 read-write 0 AN118 is not selected. #0 1 AN118 is selected. #1 ADS17 A/D-Converted Value Addition/Average Channel AN117 Select 1 1 read-write 0 AN117 is not selected. #0 1 AN117 is selected. #1 ADS16 A/D-Converted Value Addition/Average Channel AN116 Select 0 0 read-write 0 AN116 is not selected. #0 1 AN116 is selected. #1 ADADC A/D-Converted Value Addition/Average Count Select Register 0x00C 8 read-write 0x00 0xFF AVEE Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 7 read-write 0 Disabled #0 1 Enabled #1 ADC Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write 000 1-time conversion (no addition; same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 others Setting prohibited true ADCER A/D Control Extended Register 0x00E 16 read-write 0x0000 0xFFFF ADRFMT A/D Data Register Format Select 15 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 DIAGM Self-Diagnosis Enable 11 11 read-write 0 Disables self-diagnosis of ADC12. #0 1 Enables self-diagnosis of ADC12. #1 DIAGLD Self-Diagnosis Mode Select 10 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 9 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 ACE A/D Data Register Automatic Clearing Enable 5 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 ADPRC A/D Conversion Accuracy Specify 1 2 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 01 A/D conversion is performed with 10-bit accuracy. #01 10 A/D conversion is performed with 8-bit accuracy. #10 11 Setting prohibited #11 ADSTRGR A/D Conversion Start Trigger Select Register 0x010 16 read-write 0x0000 0xFFFF TRSA A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 13 read-write TRSB A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADEXICR A/D Conversion Extended Input Control Register 0x012 16 read-write 0x0000 0xFFFF OCSB Internal Reference Voltage A/D Conversion Select for Group B 11 11 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group B in group scan mode. #1 TSSB Temperature Sensor Output A/D Conversion Select for Group B 10 10 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is not selected for group B in group scan mode. #1 OCSA Internal Reference Voltage A/D Conversion Select 9 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 TSSA Temperature Sensor Output A/D Conversion Select 8 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 ADANSB0 A/D Channel Select Register B0 0x014 16 read-write 0x0000 0xFFFF ANSB07 AN107 Select 7 7 read-write 0 AN107 is not subjected to conversion. #0 1 AN107 is subjected to conversion. #1 ANSB06 AN106 Select 6 6 read-write 0 AN106 is not subjected to conversion. #0 1 AN106 is subjected to conversion. #1 ANSB05 AN105 Select 5 5 read-write 0 AN105 is not subjected to conversion. #0 1 AN105 is subjected to conversion. #1 ANSB03 AN103 Select 3 3 read-write 0 AN103 is not subjected to conversion. #0 1 AN103 is subjected to conversion. #1 ANSB02 AN102 Select 2 2 read-write 0 AN102 is not subjected to conversion. #0 1 AN102 is subjected to conversion. #1 ANSB01 AN101 Select 1 1 read-write 0 AN101 is not subjected to conversion. #0 1 AN101 is subjected to conversion. #1 ANSB00 AN100 Select 0 0 read-write 0 AN100 is not subjected to conversion. #0 1 AN100 is subjected to conversion. #1 ADANSB1 A/D Channel Select Register B1 0x016 16 read-write 0x0000 0xFFFF ANSB19 AN119 Select 3 3 read-write 0 AN119 is not subjected to conversion. #0 1 AN119 is subjected to conversion. #1 ANSB18 AN118 Select 2 2 read-write 0 AN118 is not subjected to conversion. #0 1 AN118 is subjected to conversion. #1 ANSB17 AN117 Select 1 1 read-write 0 AN117 is not subjected to conversion. #0 1 AN117 is subjected to conversion. #1 ANSB16 AN116 Select 0 0 read-write 0 AN116 is not subjected to conversion. #0 1 AN116 is subjected to conversion. #1 ADDBLDR A/D Data Duplication Register 0x018 16 read-only 0x0000 0xFFFF ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADTSDR A/D Temperature Sensor Data Register 0x01A 16 read-only 0x0000 0xFFFF ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADOCDR A/D Internal Reference Voltage Data Register 0x01C 16 read-only 0x0000 0xFFFF ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x01E 16 read-only 0x0000 0xFFFF DIAGST Self-Diagnosis Status 14 15 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 AD A/D-converted value (right-justified)NOTE: Unused bits in the AD bit field are fixed "0" 0 11 read-only 4 0x2 0-3 ADDR%s A/D Data Register %s 0x020 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only 3 0x2 5-7 ADDR%s A/D Data Register %s 0x02A 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only 4 0x2 16-19 ADDR%s A/D Data Register %s 0x040 16 read-only 0x0000 0xFFFF ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADSHCR A/D Sample and Hold Circuit Control Register 0x066 16 read-write 0x0018 0xFFFF SHANS2 AN102 sample-and-hold circuit Select 10 10 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS1 AN101 sample-and-hold circuit Select 9 9 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SHANS0 AN100 sample-and-hold circuit Select 8 8 read-write 0 Bypass the sample-and-hold circuit. #0 1 Use the sample-and-hold circuit. #1 SSTSH Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states) 0 7 read-write 0x04 0xFF ADDISCR A/D Disconnection Detection Control Register 0x07A 8 read-write 0x00 0xFF CHARGE Selection of Precharge or Discharge 4 4 read-write 0 Discharge #0 1 Precharge #1 ADNDIS The charging time 0 3 read-write 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 others ( 1 / ADCLK ) x ADNDIS true ADSHMSR A/D Sample and Hold Operation Mode Select Register 0x07C 8 read-write 0x00 0xFF SHMD Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select 0 0 read-write 0 Sampling by channel-dedicated sample-and-hold circuit is disable. #0 1 Sampling by channel-dedicated sample-and-hold circuit is enable. #1 ADGSPCR A/D Group Scan Priority Control Register 0x080 16 read-write 0x0000 0xFFFF GBRP Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 GBRSCN Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) 1 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 ADDBLDRA A/D Data Duplication Register A 0x084 16 read-only 0x0000 0xFFFF ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplication Register B 0x086 16 read-only 0x0000 0xFFFF ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x08C 8 read-only 0x00 0xFF MONCMPB Comparison Result Monitor B 5 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCMPA Comparison Result Monitor A 4 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCOMB Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. 0 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 ADCMPCR A/D Compare Function Control Register 0x090 16 read-write 0x0000 0xFFFF CMPAIE Compare A Interrupt Enable 15 15 read-write 0 S12ADCMPAIi interrupt is disabled when comparison conditions (window A) are met. #0 1 S12ADCMPAIi interrupt is enabled when comparison conditions (window A) are met. #1 WCMPE Window Function Setting 14 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 CMPBIE Compare B Interrupt Enable 13 13 read-write 0 S12ADCMPBIi interrupt is disabled when comparison conditions (window B) are met. #0 1 S12ADCMPBIi interrupt is enabled when comparison conditions (window B) are met. #1 CMPAE Compare Window A Operation Enable 11 11 read-write 0 Compare window A operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window A operation is enabled. #1 CMPBE Compare Window B Operation Enable 9 9 read-write 0 Compare window B operation is disabled. S12ADWMELC and S12ADWUMELC outputs are disabled. #0 1 Compare window B operation is enabled. #1 CMPAB Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 S12ADWMELC is output when window A comparison conditions are met OR window B comparison conditions are met. S12ADWUMELC is output in other cases. #00 01 S12ADWMELC is output when window A comparison conditions are met EXOR window B comparison conditions are met. S12ADWUMELC is output in other cases. #01 10 S12ADWMELC is output when window A comparison conditions are met and window B comparison conditions are met. S12ADWUMELC is output in other cases. #10 11 Setting prohibited. #11 ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 read-write 0x00 0xFF CMPOCA Internal reference voltage Compare selection bit. 1 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 read-write 0x00 0xFF CMPLOCA Compare Window A Internal Reference Voltage ComparisonCondition Select 1 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 read-write 0x0000 0xFFFF CMPCHA05 Compare Window A Channel AN105 Select 5 5 read-write 0 Disable compare function for AN105 #0 1 Enable compare function for AN105 #1 CMPCHA03 Compare Window A Channel AN103 Select 3 3 read-write 0 Disable compare function for AN103 #0 1 Enable compare function for AN103 #1 CMPCHA02 Compare Window A Channel AN102 Select 2 2 read-write 0 Disable compare function for AN102 #0 1 Enable compare function for AN102 #1 CMPCHA01 Compare Window A Channel AN101 Select 1 1 read-write 0 Disable compare function for AN101 #0 1 Enable compare function for AN101 #1 CMPCHA00 Compare Window A Channel AN100 Select 0 0 read-write 0 Disable compare function for AN100 #0 1 Enable compare function for AN100 #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 read-write 0x0000 0xFFFF CMPCHA20 AN120 Select 4 4 read-write 0 Excludes AN120 from the compare window A target range. #0 1 Includes AN120 from the compare window A target range. #1 CMPCHA19 AN119 Select 3 3 read-write 0 Excludes AN119 from the compare window A target range. #0 1 Includes AN119 from the compare window A target range. #1 CMPCHA18 AN118 Select 2 2 read-write 0 Excludes AN118 from the compare window A target range. #0 1 Includes AN118 from the compare window A target range. #1 CMPCHA17 AN117 Select 1 1 read-write 0 Excludes AN117 from the compare window A target range. #0 1 Includes AN117 from the compare window A target range. #1 CMPCHA16 AN116 Select 0 0 read-write 0 Excludes AN116 from the compare window A target range. #0 1 Includes AN116 from the compare window A target range. #1 ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 read-write 0x0000 0xFFFF CMPLCHA07 Comparison condition of AN107 7 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN106 6 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN105 5 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN103 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN102 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN101 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA00 Comparison condition of AN100 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 read-write 0x0000 0xFFFF CMPLCHA19 Comparison condition of AN119 3 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN118 2 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN117 1 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA16 Comparison condition of AN116 0 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x09C 16 read-write 0x0000 0xFFFF ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x09E 16 read-write 0x0000 0xFFFF ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 read-write 0x0000 0xFFFF CMPSTCHA07 Compare window A flag of AN007 7 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA00 Compare window A flag of AN000 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0x0A2 16 read-write 0x0000 0xFFFF CMPSTCHA19 Compare window A flag of AN019 3 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA16 Compare window A flag of AN016 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 read-write 0x00 0xFF CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0x0A6 8 read-write 0x00 0xFF CMPLB Compare window B Compare condition setting bit. 7 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 CMPCHB Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. 0 5 read-write 0x00 AN100 0x00 0x01 AN101 0x01 0x02 AN102 0x02 0x03 AN103 0x03 0x05 AN105 0x05 0x06 AN106 0x06 0x07 AN107 0x07 0x10 AN116 0x10 0x11 AN117 0x11 0x12 AN118 0x12 0x13 AN119 0x13 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F others Setting prohibited true ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0x0A8 16 read-write 0x0000 0xFFFF ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0x0AA 16 read-write 0x0000 0xFFFF ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 read-write 0x00 0xFF CMPSTB Compare window B flag.It is a status flag that shows the comparative result of CH (AN100-AN103, AN105-AN107, AN116-AN119, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADSSTRL A/D Sampling State Register L 0x0DD 8 read-write 0x0B 0xFF SST Sampling Time Setting (AN116-AN119) 0 7 read-write 0x05 0xFF ADSSTRT A/D Sampling State Register T 0x0DE 8 read-write 0x0B 0xFF SST Sampling Time Setting (temperature sensor output) 0 7 read-write 0x05 0xFF ADSSTRO A/D Sampling State Register O 0x0DF 8 read-write 0x0B 0xFF SST Sampling Time Setting (Internal reference voltage) 0 7 read-write 0x05 0xFF 4 0x1 0-3 ADSSTR0%s A/D Sampling State Register %s (Corresponding Channel is AN10%s ) 0x0E0 8 read-write 0x0B 0xFF SST Sampling time setting 0 7 read-write 0x05 0xFF 3 0x1 5-7 ADSSTR0%s A/D Sampling State Register %s (Corresponding Channel is AN10%s ) 0x0E5 8 read-write 0x0B 0xFF SST Sampling time setting 0 7 read-write 0x05 0xFF ADPGACR A/D Programmable Gain Amplifier Control Register 0x1A0 16 read-write 0x9999 0xFFFF P002GEN PGA P002 gain setting and enable bit 11 11 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P002ENAMP Amplifier enable bit for PGA P002 10 10 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P002SEL1 The amplifier passing is enable for PGA P002 9 9 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P002SEL0 A through amplifier is enable for PGA P002 8 8 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P001GEN PGA P001 gain setting and enable bit 7 7 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P001ENAMP Amplifier enable bit for PGA P001 6 6 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P001SEL1 The amplifier passing is enable for PGA P001 5 5 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P001SEL0 A through amplifier is enable for PGA P001 4 4 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 P000GEN PGA P000 gain setting and enable bit 3 3 read-write 0 The gain setting is invalidated (AIN is not input in PGA). #0 1 The gain setting is effectively done (AIN is input in PGA). #1 P000ENAMP Amplifier enable bit for PGA P000 2 2 read-write 0 The amplifier in PGA is not used. #0 1 The amplifier in PGA is used. #1 P000SEL1 The amplifier passing is enable for PGA P000 1 1 read-write 0 By way of the amplifier in PGA. #0 1 Note 1 that by way of amplifier in PGA #1 P000SEL0 A through amplifier is enable for PGA P000 0 0 read-write 0 Not through the PGA in amplifier #0 1 I will through in the PGA amplifier. #1 ADPGAGS0 A/D Programmable Gain Amplifier Gain Setting Register 0 0x1A2 16 read-write 0x0000 0xFFFF P002GAIN PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0. 8 11 read-write 0000 x 2.000 (ADPGADDCR0.P002DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P002DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P002DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P002DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P002DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P002DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P002DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P002DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P002DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P002DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P002DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0) #1111 P001GAIN PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0. 4 7 read-write 0000 x 2.000 (ADPGADDCR0.P001DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P001DEN=0) / x 1.500 (ADPGADDCR0.P001DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P001DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P001DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P001DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P001DEN=0) / x 2.333 (ADPGADDCR0.P001DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P001DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P001DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P001DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P001DEN=0) / x 4.00 (ADPGADDCR0.P001DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P001DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P001DEN=0) / x 5.667 (ADPGADDCR0.P001DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P001DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P001DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P001DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P001DEN=0) #1111 P000GAIN PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0. 0 3 read-write 0000 x 2.000 (ADPGADDCR0.P000DEN=0) #0000 0001 x 2.500 (ADPGADDCR0.P000DEN=0) / x 1.500 (ADPGADDCR0.P000DEN=1) #0001 0010 x 2.667 (ADPGADDCR0.P000DEN=0) #0010 0011 x 2.857 (ADPGADDCR0.P000DEN=0) #0011 0100 x 3.077 (ADPGADDCR0.P000DEN=0) #0100 0101 x 3.333 (ADPGADDCR0.P000DEN=0) / x 2.333 (ADPGADDCR0.P000DEN=1) #0101 0110 x 3.636 (ADPGADDCR0.P000DEN=0) #0110 0111 x 4.000 (ADPGADDCR0.P000DEN=0) #0111 1000 x 4.444 (ADPGADDCR0.P000DEN=0) #1000 1001 x 5.000 (ADPGADDCR0.P000DEN=0) / x 4.00 (ADPGADDCR0.P000DEN=1) #1001 1010 x 5.714 (ADPGADDCR0.P000DEN=0) #1010 1011 x 6.667 (ADPGADDCR0.P000DEN=0) / x 5.667 (ADPGADDCR0.P000DEN=1) #1011 1100 x 8.000 (ADPGADDCR0.P000DEN=0) #1100 1101 x 10.000 (ADPGADDCR0.P000DEN=0) #1101 1110 x 13.333 (ADPGADDCR0.P000DEN=0) #1110 1111 x 1.000 (for offset measurement) (ADPGADDCR0.P000DEN=0) #1111 ADPGADCR0 A/D Programmable Gain Amplifier Differential Input Control Register 0x1B0 16 read-write 0x0000 0xFFFF P003DG P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. 12 13 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P002DEN P002 Differential Input Enable 11 11 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P002DG P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. 8 9 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P001DEN P001 Differential Input Enable 7 7 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P001DG P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b. 4 5 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 P000DEN P000 Differential Input Enable 3 3 read-write 0 Differential input is disabled. #0 1 Differential input is enabled. #1 P000DG P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b. 0 1 read-write 00 x 1.5 #00 01 x 2.333 #01 10 x 4.0 #10 11 x 5.667 #11 MSTP Module Stop Control B,C,D 0x40047000 0x00 12 registers MSTPCRB Module Stop Control Register B 0x00 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPB31 Serial Communication Interface 0 Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB28 Serial Communication Interface 3 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB27 Serial Communication Interface 4 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB26 Serial Communication Interface 5 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB25 Serial Communication Interface 6 Module Stop 25 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB24 Serial Communication Interface 7 Module Stop 24 24 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB23 Serial Communication Interface 8 Module Stop 23 23 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface Module Stop 18 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB15 ETHERC0 and EDMAC0 Module Stop 15 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB13 EPTPC and PTPEDMAC Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB12 Universal Serial Bus 2.0 HS Interface Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB11 Universal Serial Bus 2.0 FS Interface Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB8 I2C Bus Interface 1 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB7 I2C Bus Interface 2 Module Stop 7 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB6 Queued Serial Peripheral Interface Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB5 IrDA Module Stop 5 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB2 RCAN0 Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB1 RCAN1 Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRC Module Stop Control Register C 0x04 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPC31 TSIP Module Stop 31 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC12 Synchronous Digital Hierarchy/ Multi Media Card 0 Module Stop 12 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC11 Synchronous Digital Hierarchy/ Multi Media Card 1 Module Stop 11 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC9 Sampling Rate Converter Module Stop 9 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC8 Synchronous Serial Interface 0 Module Stop 8 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC7 Synchronous Serial Interface 1 Module Stop 7 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC6 2DG engine Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC5 JPEG codec engine Module Stop 5 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC4 Grafic LCD Controler Module Stop 4 4 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC2 Parallel Data Capture Module Stop 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 CRC Calculator Module Stop 1 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC0 CAC Module Stop 0 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPCRD Module Stop Control Register D 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF MSTPD28 Comparator-OC0 Module Stop 28 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD27 Comparator-OC1 Module Stop 27 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD26 Comparator-OC2 Module Stop 26 26 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD25 Comparator-OC3 Module Stop 25 25 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD24 Comparator-OC4 Module Stop 24 24 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD23 Comparator-OC5 Module Stop 23 23 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD22 Temperature Sensor Module Stop 22 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 D/A Converter 0 Module Stop 20 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 12-bit A/D Converter 0 Module Stop 16 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD15 12-bit A/D Converter 1 Module Stop 15 15 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD14 PGI Module Stop 14 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD6 GPT ch13-ch8 Module Stop 6 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD5 GPT ch7-ch0 Module Stop 5 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0. 3 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1. 2 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 GPT328 General PWM Timer 8 (32-bit Enhanced) 0x40078800 0x00 116 registers 0x7C 4 registers 0x74 4 registers 0x80 4 registers 0x78 4 registers 0x84 32 registers GTWP General PWM Timer Write-Protection Register 0x00 32 read-write 0x00000000 0xFFFFFFFF PRKEY GTWP Key Code 8 15 write-only 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 others The WP bits write is not permitted. true WP Register Write Disable 0 0 read-write 0 Enable writes to the register #0 1 Disable writes to the register #1 GTSTR General PWM Timer Software Start Register 0x04 32 read-write 0x00000000 0xFFFFFFFF CSTRT13 Channel 13 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 13 13 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3213.GTCNT counter starts (write) / Counter running (read) #1 CSTRT12 Channel 12 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 12 12 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3212.GTCNT counter starts (write) / Counter running (read) #1 CSTRT11 Channel 11 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 11 11 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3211.GTCNT counter starts (write) / Counter running (read) #1 CSTRT10 Channel 10 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 10 10 read-write 0 No effect (write) / counter stop (read) #0 1 GPT3210.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT329.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT328.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E7.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E6.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E5.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32E4.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH3.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH2.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH1.GTCNT counter starts (write) / Counter running (read) #1 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT32EH0.GTCNT counter starts (write) / Counter running (read) #1 GTSTP General PWM Timer Software Stop Register 0x08 32 read-write 0xFFFFFFFF 0xFFFFFFFF CSTOP13 Channel 13 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 13 13 read-write 0 No effect (write) / counter running (read) #0 1 GPT3213.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP12 Channel 12 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 12 12 read-write 0 No effect (write) / counter running (read) #0 1 GPT3212.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP11 Channel 11 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 11 11 read-write 0 No effect (write) / counter running (read) #0 1 GPT3211.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP10 Channel 10 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 10 10 read-write 0 No effect (write) / counter running (read) #0 1 GPT3210.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT329.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT328.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E7.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E6.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E5.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT32E4.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH3.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH2.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH1.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT32EH0.GTCNT counter stops (write) / Counter stop (read) #1 GTCLR General PWM Timer Software Clear Register 0x0C 32 write-only 0x00000000 0xFFFFFFFF CCLR13 Channel 13 GTCNT Count Clear 13 13 write-only 0 No effect #0 1 GPT3213.GTCNT counter clears #1 CCLR12 Channel 12 GTCNT Count Clear 12 12 write-only 0 No effect #0 1 GPT3212.GTCNT counter clears #1 CCLR11 Channel 11 GTCNT Count Clear 11 11 write-only 0 No effect #0 1 GPT3211.GTCNT counter clears #1 CCLR10 Channel 10 GTCNT Count Clear 10 10 write-only 0 No effect #0 1 GPT3210.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 9 write-only 0 No effect #0 1 GPT329.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 8 write-only 0 No effect #0 1 GPT328.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 7 write-only 0 No effect #0 1 GPT32E7.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 6 write-only 0 No effect #0 1 GPT32E6.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 5 write-only 0 No effect #0 1 GPT32E5.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 4 write-only 0 No effect #0 1 GPT32E4.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 3 write-only 0 No effect #0 1 GPT32EH3.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 2 write-only 0 No effect #0 1 GPT32EH2.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 1 write-only 0 No effect #0 1 GPT32EH1.GTCNT counter clears #1 CCLR0 Channel 0 GTCNT Count Clear 0 0 write-only 0 No effect #0 1 GPT32EH0.GTCNT counter clears #1 GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write 0x00000000 0xFFFFFFFF CSTRT Software Source Counter Start Enable 31 31 read-write 0 Disable counter start by the GTSTR register #0 1 Enable counter start by the GTSTR register #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 23 read-write 0 Disable counter start on ELC_GPTH input #0 1 Enable counter start on ELC_GPTH input. #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 22 read-write 0 Disable counter start on ELC_GPTG input #0 1 Enable counter start on ELC_GPTG input. #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 21 read-write 0 Disable counter start on ELC_GPTF input #0 1 Enable counter start on ELC_GPTF input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 20 read-write 0 Disable counter start on ELC_GPTE input #0 1 Enable counter start on ELC_GPTE input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 19 read-write 0 Disable counter start on ELC_GPTD input #0 1 Enable counter start on ELC_GPTD input. #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 18 read-write 0 Disable counter start on ELC_GPTC input #0 1 Enable counter start on ELC_GPTC input. #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 17 read-write 0 Disable counter start on ELC_GPTB input #0 1 Enable counter start on ELC_GPTB input. #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 16 read-write 0 Disable counter start on ELC_GPTA input #0 1 Enable counter start on ELC_GPTA input. #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 15 read-write 0 Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 1. #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 14 read-write 0 Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 0. #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 13 read-write 0 Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 1. #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 12 read-write 0 Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 0. #1 SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 11 read-write 0 Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 1. #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 10 read-write 0 Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 0. #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 9 read-write 0 Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 8 read-write 0 Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 0. #1 SSGTRGDF GTETRGD Pin Falling Input Source Counter Start Enable 7 7 read-write 0 Disable counter start on the falling edge of GTETRGD input #0 1 Enable counter start on the falling edge of GTETRGD input. #1 SSGTRGDR GTETRGD Pin Rising Input Source Counter Start Enable 6 6 read-write 0 Disable counter start on the rising edge of GTETRGD input #0 1 Enable counter start on the rising edge of GTETRGD input #1 SSGTRGCF GTETRGC Pin Falling Input Source Counter Start Enable 5 5 read-write 0 Disable counter start on the falling edge of GTETRGC input #0 1 Enable counter start on the falling edge of GTETRGC input #1 SSGTRGCR GTETRGC Pin Rising Input Source Counter Start Enable 4 4 read-write 0 Disable counter start on the rising edge of GTETRGC input #0 1 Enable counter start on the rising edge of GTETRGC input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 3 read-write 0 Disable counter start on the falling edge of GTETRGB input #0 1 Enable counter start on the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 2 read-write 0 Disable counter start on the rising edge of GTETRGB input #0 1 Enable counter start on the rising edge of GTETRGB input. #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 1 read-write 0 Disable counter start on the falling edge of GTETRGA input #0 1 Enable counter start on the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 0 read-write 0 Disable counter start on the rising edge of GTETRGA input #0 1 Enable counter start on the rising edge of GTETRGA input. #1 GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write 0x00000000 0xFFFFFFFF CSTOP Software Source Counter Stop Enable 31 31 read-write 0 Disable counter stop by the GTSTP register #0 1 Enable counter stop by the GTSTP register #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 23 read-write 0 Disable counter stop on ELC_GPTH input #0 1 Enable counter stop on ELCH event inpu #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 22 read-write 0 Disable counter stop on ELC_GPTG input #0 1 Enable counter stop on ELC_GPTG input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 21 read-write 0 Disable counter stop on ELC_GPTF input #0 1 Enable counter stop on ELC_GPTF input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 20 read-write 0 Disable counter stop on ELC_GPTE input #0 1 Enable counter stop on ELC_GPTE input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 19 read-write 0 Disable counter stop on ELC_GPTD input #0 1 Enable counter stop on ELC_GPTD input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 18 read-write 0 Disable counter stop on ELC_GPTC input #0 1 Enable counter stop on ELC_GPTC input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 17 read-write 0 Disable counter stop on ELC_GPTB input #0 1 Enable counter stop on ELC_GPTB input #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 16 read-write 0 Disable counter stop on ELC_GPTA input #0 1 Enable counter stop on ELC_GPTA input #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 15 read-write 0 Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 14 read-write 0 Disable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter stop on the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 13 read-write 0 Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 12 read-write 0 Disable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter stop on the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 11 read-write 0 Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 10 read-write 0 Disable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter stop on the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 9 read-write 0 Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 8 read-write 0 Disable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter stop on the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSGTRGDF GTETRGD Pin Falling Input Source Counter Stop Enable 7 7 read-write 0 Disable counter stop on the falling edge of GTETRGD input #0 1 Enable counter stop on the falling edge of GTETRGD input #1 PSGTRGDR GTETRGD Pin Rising Input Source Counter Stop Enable 6 6 read-write 0 Disable counter stop on the rising edge of GTETRGD input #0 1 Enable counter stop on the rising edge of GTETRGD input #1 PSGTRGCF GTETRGC Pin Falling Input Source Counter Stop Enable 5 5 read-write 0 Disable counter stop on the falling edge of GTETRGC input #0 1 Enable counter stop on the falling edge of GTETRGC input #1 PSGTRGCR GTETRGC Pin Rising Input Source Counter Stop Enable 4 4 read-write 0 Disable counter stop on the rising edge of GTETRGC input #0 1 Enable counter stop on the rising edge of GTETRGC input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 3 read-write 0 Disable counter stop on the falling edge of GTETRGB input #0 1 Enable counter stop on the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 2 read-write 0 Disable counter stop on the rising edge of GTETRGB input #0 1 Enable counter stop on the rising edge of GTETRGB input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 1 read-write 0 Disable counter stop on the falling edge of GTETRGA input #0 1 Enable counter stop on the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 0 read-write 0 Disable counter stop on the rising edge of GTETRGA input #0 1 Enable counter stop on the rising edge of GTETRGA input #1 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write 0x00000000 0xFFFFFFFF CCLR Software Source Counter Clear Enable 31 31 read-write 0 Disable counter clear by the GTCLR register #0 1 Enable counter clear by the GTCLR register #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 23 read-write 0 Disable counter clear on ELC_GPTH input #0 1 Enable counter clear on ELC_GPTH input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 22 read-write 0 Disable counter clear on ELC_GPTG input #0 1 Enable counter clear on ELC_GPTG input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 21 read-write 0 Disable counter clear on ELC_GPTF input #0 1 Enable counter clear on ELC_GPTF input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 20 read-write 0 Disable counter clear on ELC_GPTE input #0 1 Enable counter clear on ELC_GPTE input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 19 read-write 0 Disable counter clear on ELC_GPTD input #0 1 Enable counter clear on ELC_GPTD input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 18 read-write 0 Disable counter clear on ELC_GPTC input #0 1 Enable counter clear on ELC_GPTC input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 17 read-write 0 Disable counter clear on ELC_GPTB input #0 1 Enable counter clear on ELC_GPTB input #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 16 read-write 0 Disable counter clear on ELC_GPTA input #0 1 Enable counter clear on ELC_GPTA input #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 15 read-write 0 Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 14 read-write 0 Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 13 read-write 0 Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 12 read-write 0 Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 11 read-write 0 Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 10 read-write 0 Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 9 read-write 0 Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 8 read-write 0 Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSGTRGDF GTETRGD Pin Falling Input Source Counter Clear Enable 7 7 read-write 0 Disable counter clear on the falling edge of GTETRGD input #0 1 Enable counter clear on the falling edge of GTETRGD input #1 CSGTRGDR GTETRGD Pin Rising Input Source Counter Clear Enable 6 6 read-write 0 Disable counter clear on the rising edge of GTETRGD input #0 1 Enable counter clear on the rising edge of GTETRGD input #1 CSGTRGCF GTETRGC Pin Falling Input Source Counter Clear Enable 5 5 read-write 0 Disable counter clear on the falling edge of GTETRGC input #0 1 Enable counter clear on the falling edge of GTETRGC input #1 CSGTRGCR GTETRGC Pin Rising Input Source Counter Clear Enable 4 4 read-write 0 Disable counter clear on the rising edge of GTETRGC input #0 1 Enable counter clear on the rising edge of GTETRGC input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 3 read-write 0 Disable counter clear on the falling edge of GTETRGB input #0 1 Enable counter clear on the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 2 read-write 0 Disable counter clear on the rising edge of GTETRGB input #0 1 Enable counter clear on the rising edge of GTETRGB input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 1 read-write 0 Disable counter clear on the falling edge of GTETRGA input #0 1 Enable counter clear on the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 0 read-write 0 Disable counter clear on the rising edge of GTETRGA input #0 1 Enable counter clear on the rising edge of GTETRGA input #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write 0x00000000 0xFFFFFFFF USELCH ELC_GPTH Event Source Counter Count Up Enable 23 23 read-write 0 Disable counter count up on ELC_GPTH input #0 1 Enable counter count up on ELC_GPTH input. #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 22 read-write 0 Disable counter count up on ELC_GPTG input #0 1 Enable counter count up on ELC_GPTG input. #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 21 read-write 0 Disable counter count up on ELC_GPTF input #0 1 Enable counter count up on ELC_GPTF input. #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 20 read-write 0 Disable counter count up on ELC_GPTE input #0 1 Enable counter count up on ELC_GPTE input.put #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 19 read-write 0 Disable counter count up on ELC_GPTD input #0 1 Enable counter count up on ELC_GPTD input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 18 read-write 0 Disable counter count up on ELC_GPTC input #0 1 Enable counter count up on ELC_GPTC input. #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 17 read-write 0 Disable counter count up on ELC_GPTB input #0 1 Enable counter count up on ELC_GPTB input. #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 16 read-write 0 Disable counter count up on ELC_GPTA input #0 1 Enable counter count up on ELC_GPTA input. #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 15 read-write 0 Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 1. #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 14 read-write 0 Disable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count up on the falling edge of GTIOCB input when GTIOCA input is 0. #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 13 read-write 0 Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 1. #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 12 read-write 0 Disable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count up on the rising edge of GTIOCB input when GTIOCA input is 0. #1 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 11 read-write 0 Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 1. #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 10 read-write 0 Disable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count up on the falling edge of GTIOCA input when GTIOCB input is 0. #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 9 read-write 0 Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 1. #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 8 read-write 0 Disable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count up on the rising edge of GTIOCA input when GTIOCB input is 0. #1 USGTRGDF GTETRGD Pin Falling Input Source Counter Count Up Enable 7 7 read-write 0 Disable counter count up on the falling edge of GTETRGD input #0 1 Enable counter count up on the falling edge of GTETRGD input. #1 USGTRGDR GTETRGD Pin Rising Input Source Counter Count Up Enable 6 6 read-write 0 Disable counter count up on the rising edge of GTETRGD input #0 1 Enable counter count up on the rising edge of GTETRGD input #1 USGTRGCF GTETRGC Pin Falling Input Source Counter Count Up Enable 5 5 read-write 0 Disable counter count up on the falling edge of GTETRGC input #0 1 Enable counter count up on the falling edge of GTETRGC input. #1 USGTRGCR GTETRGC Pin Rising Input Source Counter Count Up Enable 4 4 read-write 0 Disable counter count up on the rising edge of GTETRGC input #0 1 Enable counter count up on the rising edge of GTETRGC input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 3 read-write 0 Disable counter count up on the falling edge of GTETRGB input #0 1 Enable counter count up on the falling edge of GTETRGB input. #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 2 read-write 0 Disable counter count up on the rising edge of GTETRGB input #0 1 Enable counter count up on the rising edge of GTETRGB input. #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 1 read-write 0 Disable counter count up on the falling edge of GTETRGA input #0 1 Enable counter count up on the falling edge of GTETRGA input. #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 0 read-write 0 Disable counter count up on the rising edge of GTETRGA input #0 1 Enable counter count up on the rising edge of GTETRGA input #1 GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write 0x00000000 0xFFFFFFFF DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 23 read-write 0 Disable counter count down on ELC_GPTH input #0 1 Enable counter count down on ELC_GPTH input. #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 22 read-write 0 Disable counter count down on ELC_GPTG input #0 1 Enable counter count down on ELC_GPTG input. #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 21 read-write 0 Disable counter count down on ELC_GPTF input #0 1 Enable counter count down on ELC_GPTF input. #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 20 read-write 0 Disable counter count down on ELC_GPTE input #0 1 Enable counter count down on ELC_GPTE input. #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 19 read-write 0 Disable counter count down on ELC_GPTD input #0 1 Enable counter count down on ELC_GPTD input. #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 18 read-write 0 Disable counter count down on ELC_GPTC input #0 1 Enable counter count down on ELC_GPTC input. #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 17 read-write 0 Disable counter count down on ELC_GPTB input #0 1 Enable counter count down on ELC_GPTB input. #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 16 read-write 0 Disable counter count down on ELC_GPTA input #0 1 Enable counter count down on ELC_GPTA input. #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 15 read-write 0 Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 1. #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 14 read-write 0 Disable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count down on the falling edge of GTIOCB input when GTIOCA input is 0. #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 13 read-write 0 Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 1. #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 12 read-write 0 Disable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable counter count down on the rising edge of GTIOCB input when GTIOCA input is 0. #1 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 11 read-write 0 Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 1. #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 10 read-write 0 Disable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count down on the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 9 read-write 0 Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 1. #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 8 read-write 0 Disable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable counter count down on the rising edge of GTIOCA input when GTIOCB input is 0. #1 DSGTRGDF GTETRGD Pin Falling Input Source Counter Count Down Enable 7 7 read-write 0 Disable counter count down on the falling edge of GTETRGD input #0 1 Enable counter count down on the falling edge of GTETRGD input. #1 DSGTRGDR GTETRGD Pin Rising Input Source Counter Count Down Enable 6 6 read-write 0 Disable counter count down on the rising edge of GTETRGD input #0 1 Enable counter count down on the rising edge of GTETRGD input. #1 DSGTRGCF GTETRGC Pin Falling Input Source Counter Count Down Enable 5 5 read-write 0 Disable counter count down on the falling edge of GTETRGC input #0 1 Enable counter count down on the falling edge of GTETRGC input. #1 DSGTRGCR GTETRGC Pin Rising Input Source Counter Count Down Enable 4 4 read-write 0 Disable counter count down on the rising edge of GTETRGC input #0 1 Enable counter count down on the rising edge of GTETRGC input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 3 read-write 0 Disable counter count down on the falling edge of GTETRGB input #0 1 Enable counter count down on the falling edge of GTETRGB input. #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 2 read-write 0 Disable counter count down on the rising edge of GTETRGB input #0 1 Enable counter count down on the rising edge of GTETRGB input. #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 1 read-write 0 Disable counter count down on the falling edge of GTETRGA input #0 1 Enable counter count down on the falling edge of GTETRGA input. #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 0 read-write 0 Disable counter count down on the rising edge of GTETRGA input #0 1 Enable counter count down on the rising edge of GTETRGA input #1 GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write 0x00000000 0xFFFFFFFF ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 23 read-write 0 Disable GTCCRA input capture on ELC_GPTH input #0 1 Enable GTCCRA input capture on ELC_GPTH input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 22 read-write 0 Disable GTCCRA input capture on ELC_GPTG input #0 1 Enable GTCCRA input capture on ELC_GPTG input. #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 21 read-write 0 Disable GTCCRA input capture on ELC_GPTF input #0 1 Enable GTCCRA input capture on ELC_GPTF input. #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 20 read-write 0 Disable GTCCRA input capture on ELC_GPTE input #0 1 Enable GTCCRA input capture on ELC_GPTE input. #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 19 read-write 0 Disable GTCCRA input capture on ELC_GPTD input #0 1 Enable GTCCRA input capture on ELC_GPTD input. #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 18 read-write 0 Disable GTCCRA input capture on ELC_GPTC input #0 1 Enable GTCCRA input capture on ELC_GPTC input. #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 17 read-write 0 Disable GTCCRA input capture on ELC_GPTB input #0 1 Enable GTCCRA input capture on ELC_GPTB input #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 16 read-write 0 Disable GTCCRA input capture on ELC_GPTA input #0 1 Enable GTCCRA input capture on ELC_GPTA input. #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 15 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 1. #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 14 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCB input when GTIOCA input is 0. #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 13 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 1. #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 12 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCB input when GTIOCA input is 0. #1 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 11 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 1. #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 10 read-write 0 Disable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRA input capture on the falling edge of GTIOCA input when GTIOCB input is 0. #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 9 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 1. #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 8 read-write 0 Disable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRA input capture on the rising edge of GTIOCA input when GTIOCB input is 0. #1 ASGTRGDF GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable 7 7 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGD input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGD input. #1 ASGTRGDR GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable 6 6 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGD input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGD input. #1 ASGTRGCF GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable 5 5 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGC input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGC input #1 ASGTRGCR GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable 4 4 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGC input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGC input. #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 3 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGB input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGB input. #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 2 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGB input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGB input. #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 1 read-write 0 Disable GTCCRA input capture on the falling edge of GTETRGA input #0 1 Enable GTCCRA input capture on the falling edge of GTETRGA input. #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 0 read-write 0 Disable GTCCRA input capture on the rising edge of GTETRGA input #0 1 Enable GTCCRA input capture on the rising edge of GTETRGA input. #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write 0x00000000 0xFFFFFFFF BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 23 read-write 0 Disable GTCCRB input capture on ELC_GPTH input #0 1 Enable GTCCRB input capture on ELC_GPTH input. #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 22 read-write 0 Disable GTCCRB input capture on ELC_GPTG input #0 1 Enable GTCCRB input capture on ELC_GPTG input. #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 21 read-write 0 Disable GTCCRB input capture on ELC_GPTF input #0 1 Enable GTCCRB input capture on ELC_GPTF input. #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 20 read-write 0 Disable GTCCRB input capture on ELC_GPTE input #0 1 Enable GTCCRB input capture on ELC_GPTE input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 19 read-write 0 Disable GTCCRB input capture on ELC_GPTD input #0 1 Enable GTCCRB input capture on ELC_GPTD input. #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 18 read-write 0 Disable GTCCRB input capture on ELC_GPTC input #0 1 Enable GTCCRB input capture on ELC_GPTC input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 17 read-write 0 Disable GTCCRB input capture on ELC_GPTB input #0 1 Enable GTCCRB input capture on ELC_GPTB input. #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 16 read-write 0 Disable GTCCRB input capture on ELC_GPTA input #0 1 Enable GTCCRB input capture on ELC_GPTA input. #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 15 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 1. #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 14 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCB input when GTIOCA input is 0. #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 13 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 1. #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 12 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCB input when GTIOCA input is 0. #1 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 11 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 1. #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 10 read-write 0 Disable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRB input capture on the falling edge of GTIOCA input when GTIOCB input is 0. #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 9 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 1. #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 8 read-write 0 Disable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Enable GTCCRB input capture on the rising edge of GTIOCA input when GTIOCB input is 0. #1 BSGTRGDF GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable 7 7 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGD input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGD input. #1 BSGTRGDR GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable 6 6 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGD input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGD input. #1 BSGTRGCF GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable 5 5 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGC input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGC input. #1 BSGTRGCR GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable 4 4 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGC input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGC input. #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 3 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGB input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGB input. #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 2 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGB input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGB input. #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 1 read-write 0 Disable GTCCRB input capture on the falling edge of GTETRGA input #0 1 Enable GTCCRB input capture on the falling edge of GTETRGA input. #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 0 read-write 0 Disable GTCCRB input capture on the rising edge of GTETRGA input #0 1 Enable GTCCRB input capture on the rising edge of GTETRGA input. #1 GTCR General PWM Timer Control Register 0x2C 32 read-write 0x00000000 0xFFFFFFFF TPCS Timer Prescaler Select 24 26 read-write 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 others Setting prohibited true MD Mode Select 16 18 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (32-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (64-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 CST Count Start 0 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write 0x00000001 0xFFFFFFFF OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0percent/100percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0percent/100percent duty setting. #1 OBDTYF Forcible GTIOCB Output Duty Setting 26 26 read-write 0 Do not force setting #0 1 Force setting #1 OBDTY GTIOCB Output Duty Setting 24 25 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0percent #10 11 GTIOCB pin duty 100percent #11 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OADTYF Forcible GTIOCA Output Duty Setting 18 18 read-write 0 Do not force setting #0 1 Force setting #1 OADTY GTIOCA Output Duty Setting 16 17 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 UDF Forcible Count Direction Setting 1 1 read-write 0 Do not force setting #0 1 Force setting #1 UD Count Direction Setting 0 0 read-write 0 Count down on GTCNT #0 1 Counts up on GTCNT #1 GTIOR General PWM Timer I/O Control Register 0x34 32 read-write 0x00000000 0xFFFFFFFF NFCSB Noise Filter B Sampling Clock Select 30 31 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFBEN Noise Filter B Enable 29 29 read-write 0 Disable noise filter for GTIOCB pin #0 1 Enable noise filter for GTIOCB pin #1 OBDF GTIOCB Pin Disable Value Setting 25 26 read-write 00 Prohibit output disable #00 01 Set GTIOCB pin to Hi-Z on output disable #01 10 Set GTIOCB pin to 0 on output disable #10 11 Set GTIOCB pin to 1 on output disable. #11 OBE GTIOCB Pin Output Enable 24 24 read-write 0 Disable output #0 1 Enable output #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 23 read-write 0 Set GTIOCB pin output level on counting start and stop based on the register setting #0 1 Retain GTIOCB pin output level on counting start and stop #1 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 22 read-write 0 Output low on GTIOCB pin when counting stops #0 1 Output high on GTIOCB pin when counting stops #1 GTIOB GTIOCB Pin Function Select 16 20 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFCSA Noise Filter A Sampling Clock Select 14 15 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFAEN Noise Filter A Enable 13 13 read-write 0 Disable noise filter for GTIOCA pin #0 1 Enable noise filter for GTIOCA pin. #1 OADF GTIOCA Pin Disable Value Setting 9 10 read-write 00 Prohibit output disable #00 01 Set GTIOCA pin to Hi-Z on output disable #01 10 Set GTIOCA pin to 0 on output disable #10 11 Set GTIOCA pin to 1 on output disable. #11 OAE GTIOCA Pin Output Enable 8 8 read-write 0 Disable output #0 1 Enable output. #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 Set GTIOCA pin output level on counting start and stop based on the register setting. #0 1 Retain GTIOCA pin output level on counting start and stop #1 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 6 read-write 0 Output low on GTIOCA pin when counting stops #0 1 Output high on GTIOCA pin when counting stops. #1 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write 0x00000000 0xFFFFFFFF GRPABL Same Time Output Level Low Disable Request Enable 30 30 read-write 0 Disable same time output level low disable request #0 1 Enable same time output level low disable request #1 GRPABH Same Time Output Level High Disable Request Enable 29 29 read-write 0 Disable same time output level high disable request #0 1 Enable same time output level high disable request #1 GRP Output Disable Source Select 24 25 read-write 00 Select Group A output disable request #00 01 Select Group B output disable request #01 10 Select Group C output disable request #10 11 Select Group D output disable request. #11 GTST General PWM Timer Status Register 0x3C 32 read-write 0x00008000 0xFFFFFFFF OABLF Same Time Output Level Low Disable Request Enable 30 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 OABHF Same Time Output Level High Disable Request Enable 29 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 ODF Output Disable Flag 24 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 TUCF Count Direction Flag 15 15 read-only 0 GTCNT counter is counting down #0 1 GTCNT counter is counting up. #1 TCFPU Underflow Flag 7 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TCFF Input Compare Match Flag F 5 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFE Input Compare Match Flag E 4 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFD Input Compare Match Flag D 3 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFC Input Compare Match Flag C 2 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFB Input Capture/Compare Match Flag B 1 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFA Input Capture/Compare Match Flag A 0 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write 0x00000000 0xFFFFFFFF CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 21 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 others Setting prohibited true CCRB GTCCRB Buffer Operation 18 19 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRA GTCCRA Buffer Operation 16 17 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 BD1 GTPR Buffer Operation Disable 1 1 read-write 0 Enable buffer operation #0 1 Disable buffer operation. #1 BD2 GTCCR Buffer Operation Disable 0 0 read-write 0 Enable buffer operation #0 1 Disable buffer operation. #1 GTCNT General PWM Timer Counter 0x48 32 read-write 0x00000000 0xFFFFFFFF GTCNT Counter 0 31 read-write GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRC Compare Capture Register C 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRE Compare Capture Register E 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRD Compare Capture Register D 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTCCRF Compare Capture Register F 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPR Cycle Setting Register 0 31 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTPBR Cycle Setting Buffer Register 0 31 read-write GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write 0x00000000 0xFFFFFFFF TDE Negative-Phase Waveform Setting 0 0 read-write 0 Set GTCCRB without using GTDVU and GTDVD. #0 1 Use GTDVU and GTDVD to set the compare match value for negative-phase waveform with automatic dead time in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write 0xFFFFFFFF 0xFFFFFFFF GTDVU Dead Time Value Register U 0 31 read-write GPT329 General PWM Timer 9 (32-bit Enhanced) 0x40078900 GPT3210 General PWM Timer 10 (32-bit Enhanced) 0x40078A00 GPT3211 General PWM Timer 11 (32-bit Enhanced) 0x40078B00 GPT3212 General PWM Timer 12 (32-bit Enhanced) 0x40078C00 GPT3213 General PWM Timer 13 (32-bit Enhanced) 0x40078D00 RTC Realtime Clock 0x40044000 0x00 1 registers 0x02 1 registers 0x02 1 registers 0x04 1 registers 0x04 1 registers 0x06 1 registers 0x06 1 registers 0x08 1 registers 0x08 1 registers 0x0A 1 registers 0x0C 1 registers 0x0E 3 registers 0x10 1 registers 0x12 1 registers 0x12 1 registers 0x14 1 registers 0x14 1 registers 0x16 1 registers 0x16 1 registers 0x18 1 registers 0x18 1 registers 0x1A 1 registers 0x1A 1 registers 0x1C 2 registers 0x1C 3 registers 0x1E 1 registers 0x22 1 registers 0x24 1 registers 0x28 1 registers 0x2A 5 registers 0x40 6 registers 0x52 48 registers 0x52 48 registers 0x54 48 registers 0x54 48 registers 0x56 48 registers 0x56 48 registers 0x5A 48 registers 0x5A 48 registers 0x5C 48 registers R64CNT 64-Hz Counter 0x00 8 read-only 0x00 0x80 F1HZ 1Hz 6 6 read-only F2HZ 2Hz 5 5 read-only F4HZ 4Hz 4 4 read-only F8HZ 8Hz 3 3 read-only F16HZ 16Hz 2 2 read-only F32HZ 32Hz 1 1 read-only F64HZ 64Hz 0 0 read-only RSECCNT Second Counter 0x02 8 read-write 0x00 0x00 SEC10 10-Second Count Counts from 0 to 5 for 60-second counting. 4 6 read-write SEC1 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT0 Binary Counter 0 RSECCNT 0x02 8 read-write 0x00 0x00 BCNT0 The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. 0 7 read-write RMINCNT Minute Counter 0x04 8 read-write 0x00 0x00 MIN10 10-Minute Count Counts from 0 to 5 for 60-minute counting. 4 6 read-write MIN1 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT1 Binary Counter 1 RMINCNT 0x04 8 read-write 0x00 0x00 BCNT1 The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. 0 7 read-write RHRCNT Hour Counter 0x06 8 read-write 0x00 0x00 PM Time Counter Setting for a.m./p.m. 6 6 read-write 0 a.m. #0 1 p.m. #1 HR10 10-Hour Count Counts from 0 to 2 once per carry from the ones place. 4 5 read-write HR1 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. 0 3 read-write BCNT2 Binary Counter 2 RHRCNT 0x06 8 read-write 0x00 0x00 BCNT2 The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write RWKCNT Day-of-Week Counter 0x08 8 read-write 0x00 0x00 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 BCNT3 Binary Counter 3 RWKCNT 0x08 8 read-write 0x00 0x00 BCNT3 The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write RDAYCNT Day Counter 0x0A 8 read-write 0x00 0xC0 DATE10 10-Day Count Counts from 0 to 3 once per carry from the ones place. 4 5 read-write DATE1 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. 0 3 read-write RMONCNT Month Counter 0x0C 8 read-write 0x00 0xE0 MON10 10-Month Count Counts from 0 to 1 once per carry from the ones place. 4 4 read-write MON1 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. 0 3 read-write RYRCNT Year Counter 0x0E 16 read-write 0x0000 0xFF00 YR10 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. 4 7 read-write YR1 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. 0 3 read-write RSECAR Second Alarm Register 0x10 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RSECCNT counter value. #0 1 The register value is compared with the RSECCNT counter value. #1 SEC10 10-Seconds Value for the tens place of seconds 4 6 read-write SEC1 1-Second Value for the ones place of seconds 0 3 read-write BCNT0AR Binary Counter 0 Alarm Register RSECAR 0x10 8 read-write 0x00 0x00 BCNT0AR he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. 0 7 read-write RMINAR Minute Alarm Register 0x12 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RMINCNT counter value. #0 1 The register value is compared with the RMINCNT counter value. #1 MIN10 10-Minute Count Value for the tens place of minutes 4 6 read-write MIN1 1-Minute Count Value for the ones place of minutes 0 3 read-write BCNT1AR Binary Counter 1 Alarm Register RMINAR 0x12 8 read-write 0x00 0x00 BCNT1AR he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. 0 7 read-write RHRAR Hour Alarm Register 0x14 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RHRCNT counter value. #0 1 The register value is compared with the RHRCNT counter value. #1 PM Time Counter Setting for a.m./p.m. 6 6 read-write 0 a.m. #0 1 p.m. #1 HR10 10-Hour Count Value for the tens place of hours 4 5 read-write HR1 1-Hour Count Value for the ones place of hours 0 3 read-write BCNT2AR Binary Counter 2 Alarm Register RHRAR 0x14 8 read-write 0x00 0x00 BCNT2AR The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write RWKAR Day-of-Week Alarm Register 0x16 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RWKCNT counter value. #0 1 The register value is compared with the RWKCNT counter value. #1 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 BCNT3AR Binary Counter 3 Alarm Register RWKAR 0x16 8 read-write 0x00 0x00 BCNT3AR The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write RDAYAR Date Alarm Register 0x18 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RDAYCNT counter value. #0 1 The register value is compared with the RDAYCNT counter value. #1 DATE10 10 Days Value for the tens place of days 4 5 read-write DATE1 1 Day Value for the ones place of days 0 3 read-write BCNT0AER Binary Counter 0 Alarm Enable Register RDAYAR 0x18 8 read-write 0x00 0x00 ENB The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. 0 7 read-write RMONAR Month Alarm Register 0x1A 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RMONCNT counter value. #0 1 The register value is compared with the RMONCNT counter value. #1 MON10 10 Months Value for the tens place of months 4 4 read-write MON1 1 Month Value for the ones place of months 0 3 read-write BCNT1AER Binary Counter 1 Alarm Enable Register RMONAR 0x1A 8 read-write 0x00 0x00 ENB The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. 0 7 read-write RYRAR Year Alarm Register 0x1C 16 read-write 0x0000 0xFF00 YR10 10 Years Value for the tens place of years 4 7 read-write YR1 1 Year Value for the ones place of years 0 3 read-write BCNT2AER Binary Counter 2 Alarm Enable Register RYRAR 0x1C 16 read-write 0x0000 0xFF00 ENB The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. 0 7 read-write RYRAREN Year Alarm Enable Register 0x1E 8 read-write 0x00 0x00 ENB Compare enable 7 7 read-write 0 The register value is not compared with the RYRCNT counter value. #0 1 The register value is compared with the RYRCNT counter value. #1 BCNT3AER Binary Counter 3 Alarm Enable Register RYRAREN 0x1E 8 read-write 0x00 0x00 ENB The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. 0 7 read-write RCR1 RTC Control Register 1 0x22 8 read-write 0x00 0x0A PES Periodic Interrupt Select 4 7 read-write 0110 A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). #0110 0111 A periodic interrupt is generated every 1/128 second. #0111 1000 A periodic interrupt is generated every 1/64 second. #1000 1001 A periodic interrupt is generated every 1/32 second. #1001 1010 A periodic interrupt is generated every 1/16 second. #1010 1011 A periodic interrupt is generated every 1/8 second. #1011 1100 A periodic interrupt is generated every 1/4 second. #1100 1101 A periodic interrupt is generated every 1/2 second. #1101 1110 A periodic interrupt is generated every 1 second. #1110 1111 A periodic interrupt is generated every 2 seconds. #1111 others No periodic interrupts are generated. true RTCOS RTCOUT Output Select 3 3 read-write 0 RTCOUT outputs 1 Hz. #0 1 RTCOUT outputs 64 Hz. #1 PIE Periodic Interrupt Enable 2 2 read-write 0 A periodic interrupt request is disabled. #0 1 A periodic interrupt request is enabled. #1 CIE Carry Interrupt Enable 1 1 read-write 0 A carry interrupt request is disabled. #0 1 A carry interrupt request is enabled. #1 AIE Alarm Interrupt Enable 0 0 read-write 0 An alarm interrupt request is disabled. #0 1 An alarm interrupt request is enabled. #1 RCR2 RTC Control Register 2 0x24 8 read-write 0x00 0x0E CNTMD Count Mode Select 7 7 read-write 0 The calendar count mode. #0 1 The binary count mode. #1 HR24 Hours Mode 6 6 read-write 0 The RTC operates in 12-hour mode. #0 1 The RTC operates in 24-hour mode. #1 AADJP Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) 5 5 read-write 0 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. #0 1 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. #1 AADJE Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) 4 4 read-write 0 Automatic adjustment is disabled. #0 1 Automatic adjustment is enabled. #1 RTCOE RTCOUT Output Enable 3 3 read-write 0 RTCOUT output disabled. #0 1 RTCOUT output enabled. #1 ADJ30 30-Second Adjustment 2 2 read-write 0 Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) #0 1 30-second adjustment is executed.(write) / During 30-second adjustment.(read) #1 RESET RTC Software Reset 1 1 read-write 0 Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) #0 1 The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) #1 START Start 0 0 read-write 0 Prescaler and time counter are stopped. #0 1 Prescaler and time counter operate normally. #1 RCR4 RTC Control Register 4 0x28 8 read-write 0x00 0xFE RCKSEL Count Source Select 0 0 read-write 0 Sub-clock oscillator is selected. #0 1 LOCO clock oscillator is selected. #1 RFRH Frequency Register H 0x2A 16 read-write 0x0000 0xFFFE RFC16 Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. 0 0 read-write RFRL Frequency Register L 0x2C 16 read-write 0x0000 0x0000 RFC Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. 0 15 read-write RADJ Time Error Adjustment Register 0x2E 8 read-write 0x00 0x00 PMADJ Plus-Minus 6 7 read-write 00 Adjustment is not performed. #00 01 Adjustment is performed by the addition to the prescaler. #01 10 Adjustment is performed by the subtraction from the prescaler. #10 11 Setting prohibited #11 ADJ Adjustment Value These bits specify the adjustment value from the prescaler. 0 5 read-write 3 0x2 0-2 RTCCR%s Time Capture Control Register %s 0x40 8 read-write 0x00 0x00 TCNF Time Capture Noise Filter Control 4 5 read-write 00 The noise filter is off. #00 01 Setting prohibited #01 10 The noise filter is on (count source). #10 11 The noise filter is on (count source by divided by 32). #11 TCST Time Capture Status 2 2 read-only 0 No event is detected. #0 1 An event is detected. #1 TCCT Time Capture Control 0 1 read-write 00 No event is detected. #00 01 Rising edge is detected. #01 10 Falling edge is detected. #10 11 Both edges are detected. #11 3 0x10 0-2 RSECCP%s Second Capture Register %s 0x52 8 read-only 0x00 0x00 SEC10 10-Second Capture Capture value for the tens place of seconds 4 6 read-only SEC1 1-Second Capture Capture value for the ones place of seconds 0 3 read-only 3 0x10 0-2 BCNT0CP%s BCNT0 Capture Register %s RSECCP%s 0x52 8 read-only 0x00 0x00 BCNT0CP BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RMINCP%s Minute Capture Register %s 0x54 8 read-only 0x00 0x00 MIN10 10-Minute Capture Capture value for the tens place of minutes 4 6 read-only MIN1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT1CP%s BCNT1 Capture Register %s RMINCP%s 0x54 8 read-only 0x00 0x00 BCNT1CP BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RHRCP%s Hour Capture Register %s 0x56 8 read-only 0x00 0x00 PM A.m./p.m. select for time counter setting. 6 6 read-only 0 a.m. #0 1 p.m. #1 HR10 10-Minute Capture Capture value for the tens place of minutes 4 5 read-only HR1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT2CP%s BCNT2 Capture Register %s RHRCP%s 0x56 8 read-only 0x00 0x00 BCNT2CP BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RDAYCP%s Date Capture Register %s 0x5A 8 read-only 0x00 0x00 DATE10 10-Day Capture Capture value for the tens place of minutes 4 5 read-only DATE1 1-Day Capture Capture value for the ones place of minutes 0 3 read-only 3 0x10 0-2 BCNT3CP%s BCNT3 Capture Register %s RDAYCP%s 0x5A 8 read-only 0x00 0x00 BCNT3CP BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. 0 7 read-only 3 0x10 0-2 RMONCP%s Month Capture Register %s 0x5C 8 read-only 0x00 0x00 MON10 10-Month Capture Capture value for the tens place of months 4 4 read-only MON1 1-Month Capture Capture value for the ones place of months 0 3 read-only SSIE0 Serial Sound Interface Enhanced (SSIE) 0x4004E000 0x00 8 registers 0x10 24 registers SSICR Control Register 0x00 32 read-write 0x00000000 0xFFFFFFFF CKS Oversampling Clock Select 30 30 read-write 0 AUDIO_CLK input #0 1 Setting prohibited #1 TUIEN Transmit Underflow Interrupt Enable 29 29 read-write 0 Disables an underflow interrupt. #0 1 Enables an underflow interrupt. #1 TOIEN Transmit Overflow Interrupt Enable 28 28 read-write 0 Disables an overflow interrupt. #0 1 Enables an overflow interrupt. #1 RUIEN Receive Underflow Interrupt Enable 27 27 read-write 0 Disables an underflow interrupt. #0 1 Enables an underflow interrupt. #1 ROIEN Receive Overflow Interrupt Enable 26 26 read-write 0 Disables an overflow interrupt. #0 1 Enables an overflow interrupt. #1 IIEN Idle Mode Interrupt Enable 25 25 read-write 0 Disables an idle mode interrupt. #0 1 Enables an idle mode interrupt. #1 CHNL Channels 22 23 read-write 00 One channel #00 others Settings other than above are prohibited. true DWL Data Word Length 19 21 read-write 000 8 bits #000 001 16 bits #001 010 18 bits #010 011 20 bits #011 100 22 bits #100 101 24 bits #101 others Settings other than above are prohibited. true SWL System Word LengthSet the system word length to the bit clock frequency/2 fs. 16 18 read-write 000 8 bits (serial bit clock frequency = 16fs ) #000 001 16 bits (serial bit clock frequency = 32fs ) #001 010 24 bits (serial bit clock frequency = 48fs ) #010 011 32 bits (serial bit clock frequency = 64fs ) #011 others Settings other than above are prohibited. true SWSD Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited. 14 14 read-write 0 Serial word select is input, slave mode. #0 1 Serial word select is output, master mode. #1 SCKP Serial Bit Clock Polarity 13 13 read-write 0 SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). #0 1 SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge). #1 SWSP Serial WS Polarity 12 12 read-write 0 SSIWS is low for 1st channel, high for 2nd channel. #0 1 SSIWS is high for 1st channel, low for 2nd channel. #1 SPDP Serial Padding Polarity 11 11 read-write 0 Padding bits are low. #0 1 Padding bits are high. #1 SDTA Serial Data Alignment 10 10 read-write 0 Transmitting and receiving in the order of serial data and padding bits #0 1 Transmitting and receiving in the order of padding bits and serial data #1 PDTA Parallel Data Alignment 9 9 read-write 0 The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits) #0 1 The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits) #1 DEL Serial Data Delay 8 8 read-write 0 1 clock cycle delay between SSIWS and SSIDATA #0 1 No delay between SSIWS and SSIDATA #1 CKDV Serial Oversampling Clock Division Ratio 4 7 read-write 0x0 CLK 0x0 0x1 CLK/2 0x1 0x2 CLK/4 0x2 0x3 CLK/8 0x3 0x4 CLK/16 0x4 0x5 CLK/32 0x5 0x6 CLK/64 0x6 0x7 CLK/128 0x7 0x8 CLK/6 0x8 0x9 CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) 0x9 0xA CLK/24 0xA 0xB CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) 0xB 0xC CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) 0xC others Settings other than above are prohibited. true MUEN Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing. 3 3 read-write 0 This module is not muted. #0 1 This module is muted. #1 TEN Transmit Enable 1 1 read-write 0 Disables the transmit operation. #0 1 Enables the transmit operation. #1 REN Receive Enable 0 0 read-write 0 Disables the receive operation. #0 1 Enables the receive operation. #1 SSISR Status Register 0x04 32 read-write 0x02000013 0x3E00007F TUIRQ Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 29 29 read-write zeroToClear modify 0 No transmit underflow has occurred. #0 1 A transmit underflow has occurred. #1 TOIRQ Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 28 28 read-write zeroToClear modify 0 No transmit overflow has occurred. #0 1 A transmit overflow has occurred. #1 RUIRQ Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 27 27 read-write zeroToClear modify 0 No receive underflow has occurred. #0 1 A receive underflow has occurred. #1 ROIRQ Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. 26 26 read-write zeroToClear modify 0 No receive overflow has occurred. #0 1 A receive overflow has occurred. #1 IIRQ Idle Mode Interrupt Status Flag 25 25 read-only 0 This module is not in idle state. #0 1 This module is in idle state. #1 TCHNO Transmit Channel Number 5 6 read-only TSWNO Transmit Serial Word Number 4 4 read-only RCHNO Receive Channel Number.These bits are read as 00b. 2 3 read-only RSWNO Receive Serial Word Number 1 1 read-only IDST Idle Mode Status Flag 0 0 read-only 0 Serial bus is operating. #0 1 The current communication is stopped. #1 SSIFCR FIFO Control Register 0x10 32 read-write 0x00000000 0xFFFFFFFF AUCKE Oversampling Clock Enable 31 31 read-write 0 The oversampling clock is disabled. #0 1 The oversampling clock is enabled. #1 SSIRST SSI soft ware reset 16 16 read-write 0 Clears the SSI software reset. #0 1 initiates the SSI software reset. #1 TTRG Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. 6 7 read-write 00 7 (1) #00 01 6 (2) #01 10 4 (4) #10 11 2 (6) #11 RTRG Receive Data Trigger Number 4 5 read-write 00 1 #00 01 2 #01 10 4 #10 11 6 #11 TIE Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. 3 3 read-write 0 Transmit data empty interrupt (TXI) request is disabled #0 1 Transmit data empty interrupt (TXI) request is enabled #1 RIE Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. 2 2 read-write 0 Receive data full interrupt (RXI) request is disabled #0 1 Receive data full interrupt (RXI) request is enabled #1 TFRST Transmit FIFO Data Register Reset 1 1 read-write 0 Clears the transmit data FIFO reset. #0 1 Initiates the transmit data FIFO reset. #1 RFRST Receive FIFO Data Register Reset 0 0 read-write 0 Clears the receive data FIFO reset. #0 1 Initiates the receive data FIFO reset. #1 SSIFSR FIFO Status Register 0x14 32 read-write 0x00010000 0xFFFFFFFF TDC Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR) 24 27 read-only TDE Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs. 16 16 read-write zeroToClear modify 0 Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number. #0 1 Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number. #1 RDC Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR) 8 11 read-only RDF Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read. 0 0 read-write zeroToClear modify 0 Number of received data bytes in SSIFRDR is less than the set receive trigger number. #0 1 Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number. #1 SSIFTDR Transmit FIFO Data Register 0x18 32 write-only 0x00000000 0x00000000 SSIFTDR SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs. 0 31 write-only SSIFRDR Receive FIFO Data Register 0x1C 32 read-only 0x00000000 0x00000000 SSIFRDR SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data. 0 31 read-only SSIOFR Audio Format Register 0x20 32 read-write 0x00000000 0xFFFFFFFF BCKASTP Whether to Enable Stopping BCK Output When SSIE is in Idle Status 9 9 read-write 0 Always outputs BCK to the SSIBCK pin. #0 1 Automatically controls output of BCK to the SSIBCK pin. #1 LRCONT Whether to Enable LRCK/FS Continuation 8 8 read-write 0 Disables LRCK/FS continuation. #0 1 Enables LRCK/FS continuation. #1 OMOD Audio Format Select 0 1 read-write 00 I2S format #00 01 TDM format #01 10 Monaural format #10 11 Setting prohibited. #11 SSISCR Status Control Register 0x24 32 read-write 0x00000000 0xFFFFFFFF TDES TDE Setting Condition Select 8 12 read-write 00000 SSIFTDR has one stage or more free space #00000 00001 SSIFTDR has two stages or more free space (snip) #00001 11110 SSIFTDR has thirty-one stages or more free space #11110 11111 SSIFTDR has thirty-two stages or more free space. #11111 RDFS RDF Setting Condition Select 0 4 read-write 00000 SSIFRDR has one stage or more data size #00000 00001 SSIFRDR has two stages or more data size (snip) #00001 11110 SSIFRDR has thirty-one stages or more data size #11110 11111 SSIFRDR has thirty-two stages or more data size. #11111 SSIE1 Serial Sound Interface Enhanced (SSIE) 0x4004E100 USBFS USB 2.0 FS Module 0x40090000 0x00 2 registers 0x04 2 registers 0x08 2 registers 0x14 2 registers 0x14 2 registers 0x18 2 registers 0x18 2 registers 0x1C 2 registers 0x1C 2 registers 0x20 4 registers 0x28 12 registers 0x36 8 registers 0x40 4 registers 0x46 12 registers 0x54 14 registers 0x64 2 registers 0x68 2 registers 0x6C 22 registers 0x90 20 registers 0x92 20 registers 0xD0 12 registers 0xF0 4 registers 0x400 8 registers SYSCFG System Configuration Control Register 0x000 16 read-write 0x0000 0xFFFF SCKE USB Clock Enable 10 10 read-write 0 Stops supplying the clock signal to the USB. #0 1 Enables supplying the clock signal to the USB. #1 DCFM Controller Function Select 6 6 read-write 0 Function controller is selected. #0 1 Host controller is selected. #1 DRPD D+/D- Line Resistor Control 5 5 read-write 0 Pulling down the lines is disabled. #0 1 Pulling down the lines is enabled. #1 DPRPU D+ Line Resistor Control 4 4 read-write 0 Pulling up the line is disabled. #0 1 Pulling up the line is enabled. #1 USBE USB Operation Enable 0 0 read-write 0 USB operation is disabled. #0 1 USB operation is enabled. #1 SYSSTS0 System Configuration Status Register 0 0x004 16 read-only 0x0000 0x0000 OVCMON External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. 14 15 read-only HTACT USB Host Sequencer Status Monitor 6 6 read-only 0 Host sequencer of the USB is completely stopped. #0 1 Host sequencer of the USB is not completely stopped. #1 SOFEA Active Monitor When the Host Controller is Selected. 5 5 read-only 0 SOF output is stopped. #0 1 SOF output is operating. #1 IDMON External ID0 Input Pin Monitor 2 2 read-only 0 USB0_ID pin is low #0 1 USB0_ID pin is high #1 LNST USB Data Line Status Monitor 0 1 read-only 00 SE0 #00 01 J-State #01 10 K-State #10 11 SE1 #11 DVSTCTR0 Device State Control Register 0 0x008 16 read-write 0x0000 0xFFFF HNPBTOA Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. 11 11 read-write 0 Normal Operation #0 1 Switching from device B to device A is enabled #1 EXICEN USB0_EXICEN Output Pin Control 10 10 read-write 0 External USB0_EXICEN pin outputs low #0 1 External USB0_EXICEN pin outputs high #1 VBUSEN USB0_VBUSEN Output Pin Control 9 9 read-write 0 External USB0_VBUSEN pin outputs low #0 1 External USB0_VBUSEN pin outputs high #1 WKUP Wakeup Output 8 8 read-write 0 Remote wakeup signal is not output. #0 1 Remote wakeup signal is output. #1 RWUPE Wakeup Detection Enable 7 7 read-write 0 Downstream port wakeup is disabled. #0 1 Downstream port wakeup is enabled. #1 USBRST USB Bus Reset Output 6 6 read-write 0 USB bus reset signal is not output. #0 1 USB bus reset signal is output. #1 RESUME Resume Output 5 5 read-write 0 Resume signal is not output. #0 1 Resume signal is output. #1 UACT USB Bus Enable 4 4 read-write 0 Downstream port is disabled (SOF transmission is disabled). #0 1 Downstream port is enabled (SOF transmission is enabled). #1 RHST USB Bus Reset Status 0 2 read-only 000 Communication speed not determined #000 001 Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) #001 010 Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) #010 011 Setting prohibited #011 others USB bus reset in progress(When the host controller function is selected) true CFIFO CFIFO Port Register 0x014 16 read-write 0x0000 0xFFFF FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write CFIFOL CFIFO Port Register L CFIFO 0x014 8 read-write 0x00 0xFF D0FIFO D0FIFO Port Register 0x018 16 read-write 0x0000 0xFFFF FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D0FIFOL D0FIFO Port Register L D0FIFO 0x018 8 read-write 0x00 0xFF D1FIFO D1FIFO Port Register 0x01C 16 read-write 0x0000 0xFFFF FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D1FIFOL D1FIFO Port Register L D1FIFO 0x01C 8 read-write 0x00 0xFF CFIFOSEL CFIFO Port Select Register 0x020 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 REW Buffer Pointer Rewind 14 14 read-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 MBW CFIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 BIGEND CFIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 ISEL CFIFO Port Access Direction When DCP is Selected 5 5 read-write 0 Reading from the buffer memory is selected #0 1 Writing to the buffer memory is selected #1 CURPIPE CFIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true CFIFOCTR CFIFO Port Control Register 0x022 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 read-only 0 Invalid #0 1 Clears the buffer memory on the CPU side #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only D0FIFOSEL D0FIFO Port Select Register 0x028 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 REW Buffer Pointer Rewind 14 14 read-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 MBW FIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true D0FIFOCTR D0FIFO Port Control Register 0x02A 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 read-only 0 Invalid #0 1 Clears the buffer memory on the CPU side #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only D1FIFOSEL D1FIFO Port Select Register 0x02C 16 read-write 0x0000 0xFFFF RCNT Read Count Mode 15 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 REW Buffer Pointer Rewind 14 14 read-only 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 MBW FIFO Port Access Bit Width 10 10 read-write 0 8-bit width #0 1 16-bit width #1 BIGEND FIFO Port Endian Control 8 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 others Setting prohibited true D1FIFOCTR D1FIFO Port Control Register 0x02E 16 read-write 0x0000 0xFFFF BVAL Buffer Memory Valid Flag 15 15 read-write 0 Invalid #0 1 Writing ended #1 BCLR CPU Buffer Clear 14 14 read-only 0 Invalid #0 1 Clears the buffer memory on the CPU side #1 FRDY FIFO Port Ready 13 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only INTENB0 Interrupt Enable Register 0 0x030 16 read-write 0x0000 0xFFFF VBSE VBUS Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 RSME Resume Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFE Frame Number Update Interrupt Enable 13 13 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DVSE Device State Transition Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPE Buffer Empty Interrupt Enable 10 10 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYE Buffer Ready Interrupt Enable 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 INTENB1 Interrupt Enable Register 1 0x032 16 read-write 0x0000 0xFFFF OVRCRE Overcurrent Input Change Interrupt Enable 15 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BCHGE USB Bus Change Interrupt Enable 14 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DTCHE Disconnection Detection Interrupt Enable 12 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 ATTCHE Connection Detection Interrupt Enable 11 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 EOFERRE EOF Error Detection Interrupt Enable 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SIGNE Setup Transaction Error Interrupt Enable 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SACKE Setup Transaction Normal Response Interrupt Enable 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYENB BRDY Interrupt Enable Register 0x036 16 read-write 0x0000 0xFFFF PIPE9BRDYE BRDY Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BRDYE BRDY Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BRDYE BRDY Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BRDYE BRDY Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BRDYE BRDY Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BRDYE BRDY Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BRDYE BRDY Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BRDYE BRDY Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BRDYE BRDY Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0BRDYE BRDY Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYENB NRDY Interrupt Enable Register 0x038 16 read-write 0x0000 0xFFFF PIPE9NRDYE NRDY Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8NRDYE NRDY Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7NRDYE NRDY Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6NRDYE NRDY Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5NRDYE NRDY Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4NRDYE NRDY Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3NRDYE NRDY Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2NRDYE NRDY Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1NRDYE NRDY Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0NRDYE NRDY Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BEMPENB BEMP Interrupt Enable Register 0x03A 16 read-write 0x0000 0xFFFF PIPE9BEMPE BEMP Interrupt Enable for PIPE9 9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BEMPE BEMP Interrupt Enable for PIPE8 8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BEMPE BEMP Interrupt Enable for PIPE7 7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BEMPE BEMP Interrupt Enable for PIPE6 6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BEMPE BEMP Interrupt Enable for PIPE5 5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BEMPE BEMP Interrupt Enable for PIPE4 4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BEMPE BEMP Interrupt Enable for PIPE3 3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BEMPE BEMP Interrupt Enable for PIPE2 2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BEMPE BEMP Interrupt Enable for PIPE1 1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE0BEMPE BEMP Interrupt Enable for PIPE0 0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFCFG SOF Output Configuration Register 0x03C 16 read-write 0x0000 0xFFFF TRNENSEL Transaction-Enabled Time Select 8 8 read-write 0 For non-low-speed communication #0 1 For low-speed communication #1 BRDYM BRDY Interrupt Status Clear Timing 6 6 read-write 0 Software clears the status. #0 1 The USB clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer. #1 EDGESTS Edge Interrupt Output Status Monitor 4 4 read-only 0 before stopping the clock supply to the USB module #0 1 the edge interrupt output signal is in the middle of the edge processing #1 INTSTS0 Interrupt Status Register 0 0x040 16 read-write 0x0000 0xFF7F VBINT VBUS Interrupt Status 15 15 read-write zeroToClear modify 0 VBUS interrupts are not generated. #0 1 VBUS interrupts are generated. #1 RESM Resume Interrupt Status 14 14 read-write zeroToClear modify 0 Resume interrupts are not generated. #0 1 Resume interrupts are generated. #1 SOFR Frame Number Refresh Interrupt Status 13 13 read-write zeroToClear modify 0 SOF interrupts are not generated. #0 1 SOF interrupts are generated. #1 DVST Device State Transition Interrupt Status 12 12 read-write zeroToClear modify 0 Device state transition interrupts are not generated. #0 1 Device state transition interrupts are generated. #1 CTRT Control Transfer Stage Transition Interrupt Status 11 11 read-write zeroToClear modify 0 Control transfer stage transition interrupts are not generated. #0 1 Control transfer stage transition interrupts are generated. #1 BEMP Buffer Empty Interrupt Status 10 10 read-only 0 BEMP interrupts are not generated. #0 1 BEMP interrupts are generated. #1 NRDY Buffer Not Ready Interrupt Status 9 9 read-only 0 NRDY interrupts are not generated. #0 1 NRDY interrupts are generated. #1 BRDY Buffer Ready Interrupt Status 8 8 read-only 0 BRDY interrupts are not generated. #0 1 BRDY interrupts are generated. #1 VBSTS VBUS Input Status 7 7 read-only 0 USB0_VBUS pin is low. #0 1 USB0_VBUS pin is high. #1 DVSQ Device State 4 6 read-only 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 others Suspended state true VALID USB Request Reception 3 3 read-write 0 Setup packet is not received #0 1 Setup packet is received #1 CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 others Setting prohibited true INTSTS1 Interrupt Status Register 1 0x042 16 read-write 0x0000 0xFFFF OVRCR Overcurrent Input Change Interrupt Status 15 15 read-write zeroToClear modify 0 OVRCR interrupts are not generated. #0 1 OVRCR interrupts are generated. #1 BCHG USB Bus Change Interrupt Status 14 14 read-write zeroToClear modify 0 BCHG interrupts are not generated. #0 1 BCHG interrupts are generated. #1 DTCH USB Disconnection Detection Interrupt Status 12 12 read-write zeroToClear modify 0 DTCH interrupts are not generated. #0 1 DTCH interrupts are generated. #1 ATTCH ATTCH Interrupt Status 11 11 read-write zeroToClear modify 0 ATTCH interrupts are not generated. #0 1 ATTCH interrupts are generated. #1 EOFERR EOF Error Detection Interrupt Status 6 6 read-write zeroToClear modify 0 EOFERR interrupts are not generated. #0 1 EOFERR interrupts are generated. #1 SIGN Setup Transaction Error Interrupt Status 5 5 read-write zeroToClear modify 0 SIGN interrupts are not generated. #0 1 SIGN interrupts are generated. #1 SACK Setup Transaction Normal Response Interrupt Status 4 4 read-write zeroToClear modify 0 SACK interrupts are not generated. #0 1 SACK interrupts are generated. #1 BRDYSTS BRDY Interrupt Status Register 0x046 16 read-write 0x0000 0xFFFF PIPE9BRDY BRDY Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BRDY BRDY Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BRDY BRDY Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BRDY BRDY Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BRDY BRDY Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BRDY BRDY Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BRDY BRDY Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BRDY BRDY Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BRDY BRDY Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0BRDY BRDY Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 NRDYSTS NRDY Interrupt Status Register 0x048 16 read-write 0x0000 0xFFFF PIPE9NRDY NRDY Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8NRDY NRDY Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7NRDY NRDY Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6NRDY NRDY Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5NRDY NRDY Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4NRDY NRDY Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3NRDY NRDY Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2NRDY NRDY Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1NRDY NRDY Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0NRDY NRDY Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 BEMPSTS BEMP Interrupt Status Register 0x04A 16 read-write 0x0000 0xFFFF PIPE9BEMP BEMP Interrupt Status for PIPE9 9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BEMP BEMP Interrupt Status for PIPE8 8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BEMP BEMP Interrupt Status for PIPE7 7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BEMP BEMP Interrupt Status for PIPE6 6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BEMP BEMP Interrupt Status for PIPE5 5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BEMP BEMP Interrupt Status for PIPE4 4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BEMP BEMP Interrupt Status for PIPE3 3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BEMP BEMP Interrupt Status for PIPE2 2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BEMP BEMP Interrupt Status for PIPE1 1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE0BEMP BEMP Interrupt Status for PIPE0 0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 FRMNUM Frame Number Register 0x04C 16 read-write 0x0000 0xFFFF OVRN Overrun/Underrun Detection Status 15 15 read-write 0 No error #0 1 An error occurred #1 CRCE Receive Data Error 14 14 read-write 0 No error #0 1 An error occurred #1 FRNM Frame NumberLatest frame number 0 10 read-only DVCHGR Device State Change Register 0x04E 16 read-write 0x0000 0xFFFF DVCHG Device State Change 15 15 read-write 0 Disables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0]. #0 1 Enables the writing to the USBADDR.STSRECOV[3:0] bits and USBADDR.USBADDR[6:0]. #1 USBADDR USB Address Register 0x050 16 read-write 0x0000 0xFFFF STSRECOV Status Recovery 8 11 read-write 0100 Return to the low-speed state (bits DVSTCTR0.RHST[2:0] = 001b;(Recovery when the host controller is selected)) #0100 1000 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b;(Recovery when the host controller is selected)) #1000 1001 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state);(Recovery when the function controller is selected) #1001 1010 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state);(Recovery when the function controller is selected) #1010 1011 Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state);(Recovery when the function controller is selected) #1011 others Settings other than above are prohibited. true USBADDR USB AddressWhen the function controller is selected, these bits indicate the USB address assigned by the host when the SET_ADDRESS request is successfully processed. 0 6 read-write USBREQ USB Request Type Register 0x054 16 read-write 0x0000 0xFFFF BREQUEST RequestThese bits store the USB request bRequest value. 8 15 read-write BMREQUESTTYPE Request TypeThese bits store the USB request bmRequestType value. 0 7 read-write USBVAL USB Request Value Register 0x056 16 read-write 0x0000 0xFFFF WVALUE ValueThese bits store the USB request wValue value. 0 15 read-write USBINDX USB Request Index Register 0x058 16 read-write 0x0000 0xFFFF WINDEX IndexThese bits store the USB request wIndex value. 0 15 read-write USBLENG USB Request Length Register 0x05A 16 read-write 0x0000 0xFFFF WLENGTH LengthThese bits store the USB request wLength value. 0 15 read-write DCPCFG DCP Configuration Register 0x05C 16 read-write 0x0000 0xFFFF SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Pipe continued at the end of transfer #0 1 Pipe disabled at the end of transfer #1 DIR Transfer Direction 4 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 DCPMAXP DCP Maximum Packet Size Register 0x05E 16 read-write 0x0040 0xFFFF DEVSEL Device Select 12 15 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 others Settings prohibited. true MXPS Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP. 0 6 read-write DCPCTR DCP Control Register 0x060 16 read-write 0x0040 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 SUREQ Setup Token Transmission 14 14 read-write 0 Invalid #0 1 Transmits the setup packet. #1 SUREQCLR SUREQ Bit Clear 11 11 read-write 0 Invalid #0 1 Clears the SUREQ bit to 0. #1 SQCLR Sequence Toggle Bit Clear 8 8 read-write 0 Invalid #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 read-write 0 Invalid #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Monitor 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 DCP is not used for the transaction. #0 1 DCP is used for the transaction. #1 CCPL Control Transfer End Enable 2 2 read-write 0 Invalid #0 1 Completion of control transfer is enabled. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 PIPESEL Pipe Window Select Register 0x064 16 read-write 0x0000 0xFFFF PIPESEL Pipe Window Select 0 3 read-write 0000 No pipe selected #0000 0001 PIPE1 #0001 0010 PIPE2 #0010 0011 PIPE3 #0011 0100 PIPE4 #0100 0101 PIPE5 #0101 0110 PIPE6 #0110 0111 PIPE7 #0111 1000 PIPE8 #1000 1001 PIPE9 #1001 others Settings prohibited. true PIPECFG Pipe Configuration Register 0x068 16 read-write 0x0000 0xFFFF TYPE Transfer Type 14 15 read-write 00 Pipe not used #00 01 Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) #01 10 Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) #10 11 Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) #11 BFRE BRDY Interrupt Operation Specification 10 10 read-write 0 BRDY interrupt upon transmitting or receiving data #0 1 BRDY interrupt upon completion of reading data #1 DBLB Double Buffer Mode 9 9 read-write 0 Single buffer #0 1 Double buffer #1 SHTNAK Pipe Disabled at End of Transfer 7 7 read-write 0 Pipe assignment continued at the end of transfer #0 1 Pipe assignment disabled at the end of transfer #1 DIR Transfer Direction 4 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 EPNUM Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. 0 3 read-write PIPEMAXP Pipe Maximum Packet Size Register 0x06C 16 read-write 0x0000 0xFFBF DEVSEL Device Select 12 15 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 others Settings prohibited. true MXPS Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) 0 8 read-write PIPEPERI Pipe Cycle Control Register 0x06E 16 read-write 0x0000 0xFFFF IFIS Isochronous IN Buffer Flush 12 12 read-write 0 The buffer is not flushed. #0 1 The buffer is flushed. #1 IITV Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. 0 2 read-write 5 0x002 1-5 PIPE%sCTR Pipe %s Control Register 0x070 16 read-write 0x0000 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 ATREPM Auto Response Mode 10 10 read-write 0 Auto response is disabled. #0 1 Auto response is enabled. #1 ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 SQCLR Sequence Toggle Bit Clear 8 8 write-only 0 Write disabled #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 write-only 0 Write disabled #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 The relevant pipe is not used for the transaction. #0 1 The relevant pipe is used for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 4 0x002 6-9 PIPE%sCTR Pipe %s Control Register 0x07A 16 read-write 0x0000 0xFFFF BSTS Buffer Status 15 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 ACLRM Auto Buffer Clear Mode 9 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 SQCLR Sequence Toggle Bit Clear 8 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQSET Sequence Toggle Bit Set 7 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 SQMON Sequence Toggle Bit Confirmation 6 6 read-only 0 DATA0 #0 1 DATA1 #1 PBUSY Pipe Busy 5 5 read-only 0 The relevant pipe is not used at the USB bus. #0 1 The relevant pipe is used at the USB bus. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 5 0x004 1-5 PIPE%sTRE Pipe %s Transaction Counter Enable Register 0x090 16 read-write 0x0000 0xFFFF TRENB Transaction Counter Enable 9 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 TRCLR Transaction Counter Clear 8 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 5 0x004 1-5 PIPE%sTRN Pipe %s Transaction Counter Register 0x092 16 read-write 0x0000 0xFFFF TRNCNT Transaction Counter 0 15 read-write 6 0x002 0-5 DEVADD%s Device Address %s Configuration Register 0x0D0 16 read-write 0x0000 0xFFFF USBSPD Transfer Speed of Communication Target Device 6 7 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 PHYSLEW PHY Cross Point Adjustment Register 0x0F0 32 read-write 0x0000000E 0xFF4CFFFF SLEWF01 Receiver Cross Point Adjustment 01 3 3 read-write 0 Reserved #0 1 Host or device controller mode. #1 SLEWF00 Receiver Cross Point Adjustment 00 2 2 read-write 0 Reserved #0 1 Host or device controller mode. #1 SLEWR01 Receiver Cross Point Adjustment 01 1 1 read-write 0 Reserved #0 1 Host or device controller mode. #1 SLEWR00 Receiver Cross Point Adjustment 00 0 0 read-write 0 Reserved #0 1 Host or device controller mode. #1 DPUSR0R Deep Software Standby USB Transceiver Control/Pin Monitor Register 0x400 32 read-write 0x00000000 0xFF4CFFFF DVBSTS0 USB VBUS InputIndicates the VBUS input signal of the USB. 23 23 read-only DOVCB0 USB OVRCURB InputIndicates the OVRCURB input signal of the USB. 21 21 read-only DOVCA0 USB OVRCURA InputIndicates the OVRCURA input signal of the USB. 20 20 read-only DM0 USB D-InputIndicates the D- input signal of the USB. 17 17 read-only DP0 USB0 D+ InputIndicates the D+ input signal of the USB. 16 16 read-only FIXPHY0 USB Transceiver Output Fix 4 4 read-write 0 The outputs are fixed in normal mode and on return from deep software standby mode. #0 1 The outputs are fixed on transitions to deep software standby mode. #1 DRPD0 D+/D- Pull-Down Resistor Control 3 3 read-write 0 Disables DP/DM pull-down resistor. #0 1 Enables DP/DM pull-down resistor. #1 RPUE0 DP Pull-Up Resistor Control 1 1 read-write 0 Disables DP pull-up resistor. #0 1 Enables DP pull-up resistor. #1 SRPC0 USB Single End Receiver Control 0 0 read-write 0 Input through the DP and DM inputs is disabled. #0 1 Input through the DP and DM inputs is enabled. #1 DPUSR1R Deep Software Standby USB Suspend/Resume Interrupt Register 0x404 32 read-write 0x00000000 0xFFFFFFFF DVBINT0 USB VBUS Interrupt Source Recovery 23 23 read-only 0 The system has not returned from deep software standby mode. #0 1 The system has returned from deep software standby mode. #1 DOVRCRB0 USB OVRCURB Interrupt Source Recovery 21 21 read-only 0 The system has not returned from deep software standby mode. #0 1 The system has returned from deep software standby mode. #1 DOVRCRA0 USB OVRCURA Interrupt Source Recovery 20 20 read-only 0 The system has not returned from deep software standby mode. #0 1 The system has returned from deep software standby mode. #1 DMINT0 USB DM Interrupt Source Recovery 17 17 read-only 0 The system has not returned from deep software standby mode. #0 1 The system has returned from deep software standby mode. #1 DPINT0 USB DP Interrupt Source Recovery 16 16 read-only 0 The system has not returned from deep software standby mode. #0 1 The system has returned from deep software standby mode. #1 DVBSE0 USB VBUS Interrupt Enable/Clear 7 7 read-write 0 Recovery from deep software standby mode is disabled. #0 1 Recovery from deep software standby mode is enabled. #1 DOVRCRBE0 USB OVRCURB Interrupt Enable/Clear 5 5 read-write 0 Recovery from deep software standby mode is disabled. #0 1 Recovery from deep software standby mode is enabled. #1 DOVRCRAE0 USB OVRCURA Interrupt Enable/Clear 4 4 read-write 0 Recovery from deep software standby mode is disabled. #0 1 Recovery from deep software standby mode is enabled. #1 DMINTE0 USB DM Interrupt Enable/Clear 1 1 read-write 0 Recovery from deep software standby mode is disabled. #0 1 Recovery from deep software standby mode is enabled. #1 DPINTE0 USB DP Interrupt Enable/Clear 0 0 read-write 0 Recovery from deep software standby mode is disabled. #0 1 Recovery from deep software standby mode is enabled. #1 SRCRAM Sampling Rate Converter RAM 0x40048000 0x00 22208 registers 5552 0x4 0-5551 SRCFCTR[%s] Filter Coefficient Table [%s] 0x00 32 read-write 0x00000000 0xFFC00000 SRCFCOE Stores a filter coefficient value. 0 21 read-write SRC Sampling Rate Converter 0x4004DFF0 0x00 16 registers SRCID Input Data Register 0x00 32 write-only 0x00000000 0xFFFFFFFF SRCID SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0. 0 31 write-only SRCOD Output Data Register 0x04 32 read-only 0x00000000 0xFFFFFFFF SRCOD SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again. 0 31 read-only SRCIDCTRL Input Data Control Register 0x08 16 read-write 0x0000 0xFFFF IED Input Data Endian 9 9 read-write 0 Endian formats 1 are the same between the CPU and input data. #0 1 Endian formats 1 are different between the CPU and input data. #1 IEN Input FIFO Empty Interrupt Enable 8 8 read-write 0 Input FIFO empty interrupt is disabled. #0 1 Input FIFO empty interrupt is enabled. #1 IFTRG Input FIFO Data Triggering Number 0 1 read-write 00 0 #00 01 2 #01 10 4 #10 11 6 #11 SRCODCTRL Output Data Control Register 0x0A 16 read-write 0x0000 0xFFFF OCH Output Data Channel Exchange 10 10 read-write 0 Does not exchange the channels (the same order as data input) #0 1 Exchanges the channels (the opposite order from data input) #1 OED Output Data Endian 9 9 read-write 0 Endian formats are the same between the chip and input data. #0 1 Endian formats are different between the chip and input data. #1 OEN Output Data FIFO Full Interrupt Enable 8 8 read-write 0 Output data FIFO full interrupt is disabled. #0 1 Output data FIFO full interrupt is enabled. #1 OFTRG Output FIFO Data Trigger Number 0 1 read-write 00 1 #00 01 4 #01 10 8 #10 11 12 #11 SRCCTRL Control Register 0x0C 16 read-write 0x0000 0xFFFF FICRAE Filter Coefficient Table Access Enable 15 15 read-write 0 Reading/writing to filter coefficient table RAM is disabled. #0 1 Reading/writing to filter coefficient table RAM is enabled. #1 CEEN Conversion End Interrupt Enable 13 13 read-write 0 Disables conversion end interrupt requests. #0 1 Enables conversion end interrupt requests. #1 SRCEN Module Enable 12 12 read-write 0 Disables this module operation. #0 1 Enables this module operation. #1 UDEN Output Data FIFO Underflow Interrupt Enable 11 11 read-write 0 Disables output data FIFO underflow interrupt requests. #0 1 Enables output data FIFO underflow interrupt requests. #1 OVEN Output Data FIFO Overwrite Interrupt Enable 10 10 read-write 0 Output data FIFO overwrite interrupt is disabled. #0 1 Output data FIFO overwrite interrupt is enabled. #1 FL Internal Work Memory Flush 9 9 write-only 0 no effect #0 1 starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing). #1 CL Internal Work Memory Clear 8 8 write-only 0 no effect #0 1 Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator. #1 IFS Input Sampling Rate 4 7 read-write 0000 8.0 kHz #0000 0001 11.025 kHz #0001 0010 12.0 kHz #0010 0011 Setting prohibited #0011 0100 16.0 kHz #0100 0101 22.05 kHz #0101 0110 24.0 kHz #0110 0111 Setting prohibited #0111 1000 32.0 kHz #1000 1001 44.1 kHz #1001 1010 48.0 kHz #1010 others Settings prohibited. true OFS Output Sampling Rate 0 2 read-write 000 44.1 kHz #000 001 48.0 kHz #001 010 32.0 kHz #010 011 Setting prohibited #011 100 8.0 kHz ( Valid only when IFS[3:0] =1001b ) #100 101 16.0 kHz ( Valid only when IFS[3:0] =1001b ) #101 others Settings other than above are prohibited. true SRCSTAT Status Register 0x0E 16 read-write 0x0002 0xFFFF OFDN Output FIFO Data Count 11 15 read-only OFDN The value of OFDN indicatethe number of data units in the output FIFO. true IFDN Input FIFO Data Count 7 10 read-only IFDN The value of IFDN indicatethe number of data units in the input FIFO. true CEF Conversion End Flag 5 5 read-write zeroToClear modify 0 All of the output data has not been read out. #0 1 All of the output data has been read out. #1 FLF Flush Processing Status Flag 4 4 read-only 0 Flash processing is completed. #0 1 Flash processing is in progress. #1 UDF Output FIFO Underflow Interrupt Request Flag 3 3 read-write zeroToClear modify 0 Output data FIFO has not been read out. #0 1 Output data FIFO has been read out. #1 OVF Output Data FIFO Overwrite Interrupt Request Flag 2 2 read-write zeroToClear modify 0 Next data conversion processing is not completed. #0 1 Next data conversion processing is completed. #1 IINT Input Data FIFO Empty Interrupt Request Flag 1 1 read-write zeroToClear modify 0 Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number. #0 1 Number of data units in the input FIFO has become equal to or smaller than the specified triggering number. #1 OINT Output Data FIFO Full Interrupt Request Flag 0 0 read-write zeroToClear modify 0 Number of data units in the output FIFO has not become equal to or greater than the specified triggering number. #0 1 Number of data units in the output FIFO has become equal to or greater than the specified triggering number. #1 ICU Interrupt Controller 0x40006000 0x00 16 registers 0x140 2 registers 0x120 2 registers 0x130 2 registers 0x100 1 registers 0x300 384 registers 0x280 32 registers 0x200 2 registers 0x1A0 4 registers IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 IEL32 ICU Interrupt 32 32 IEL33 ICU Interrupt 33 33 IEL34 ICU Interrupt 34 34 IEL35 ICU Interrupt 35 35 IEL36 ICU Interrupt 36 36 IEL37 ICU Interrupt 37 37 IEL38 ICU Interrupt 38 38 IEL39 ICU Interrupt 39 39 IEL40 ICU Interrupt 40 40 IEL41 ICU Interrupt 41 41 IEL42 ICU Interrupt 42 42 IEL43 ICU Interrupt 43 43 IEL44 ICU Interrupt 44 44 IEL45 ICU Interrupt 45 45 IEL46 ICU Interrupt 46 46 IEL47 ICU Interrupt 47 47 IEL48 ICU Interrupt 48 48 IEL49 ICU Interrupt 49 49 IEL50 ICU Interrupt 50 50 IEL51 ICU Interrupt 51 51 IEL52 ICU Interrupt 52 52 IEL53 ICU Interrupt 53 53 IEL54 ICU Interrupt 54 54 IEL55 ICU Interrupt 55 55 IEL56 ICU Interrupt 56 56 IEL57 ICU Interrupt 57 57 IEL58 ICU Interrupt 58 58 IEL59 ICU Interrupt 59 59 IEL60 ICU Interrupt 60 60 IEL61 ICU Interrupt 61 61 IEL62 ICU Interrupt 62 62 IEL63 ICU Interrupt 63 63 IEL64 ICU Interrupt 64 64 IEL65 ICU Interrupt 65 65 IEL66 ICU Interrupt 66 66 IEL67 ICU Interrupt 67 67 IEL68 ICU Interrupt 68 68 IEL69 ICU Interrupt 69 69 IEL70 ICU Interrupt 70 70 IEL71 ICU Interrupt 71 71 IEL72 ICU Interrupt 72 72 IEL73 ICU Interrupt 73 73 IEL74 ICU Interrupt 74 74 IEL75 ICU Interrupt 75 75 IEL76 ICU Interrupt 76 76 IEL77 ICU Interrupt 77 77 IEL78 ICU Interrupt 78 78 IEL79 ICU Interrupt 79 79 IEL80 ICU Interrupt 80 80 IEL81 ICU Interrupt 81 81 IEL82 ICU Interrupt 82 82 IEL83 ICU Interrupt 83 83 IEL84 ICU Interrupt 84 84 IEL85 ICU Interrupt 85 85 IEL86 ICU Interrupt 86 86 IEL87 ICU Interrupt 87 87 IEL88 ICU Interrupt 88 88 IEL89 ICU Interrupt 89 89 IEL90 ICU Interrupt 90 90 IEL91 ICU Interrupt 91 91 IEL92 ICU Interrupt 92 92 IEL93 ICU Interrupt 93 93 IEL94 ICU Interrupt 94 94 IEL95 ICU Interrupt 95 95 16 0x1 0-15 IRQCR%s IRQ Control Register %s 0x000 8 read-write 0x00 0xFF FLTEN IRQ Digital Filter Enable 7 7 read-write 0 Digital filter is disabled. #0 1 Digital filter is enabled. #1 FCLKSEL IRQ Digital Filter Sampling Clock 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only 0x0000 0xFFFF SPEST MPU Stack Error Interrupt Status Flag 12 12 read-only 0 MPU Stack Error interrupt is not requested. #0 1 MPU Stack Error interrupt is requested. #1 BUSMST MPU Bus Master Error Interrupt Status Flag 11 11 read-only 0 MPU Bus Master Error interrupt is not requested. #0 1 MPU Bus Master Error interrupt is requested. #1 BUSSST MPU Bus Slave Error Interrupt Status Flag 10 10 read-only 0 MPU Bus Slave Error interrupt is not requested. #0 1 MPU Bus Slave Error interrupt is requested. #1 RECCST RAM ECC Error Interrupt Status Flag 9 9 read-only 0 RAM ECC Error interrupt is not requested. #0 1 RAM ECC Error interrupt is requested. #1 RPEST RAM Parity Error Interrupt Status Flag 8 8 read-only 0 RAM Parity Error interrupt is not requested. #0 1 RAM Parity Error interrupt is requested. #1 NMIST NMI Status Flag 7 7 read-only 0 NMI pin interrupt is not requested. #0 1 NMI pin interrupt is requested. #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 6 read-only 0 Oscillation stop detection interrupt is not requested. #0 1 Oscillation stop detection interrupt is requested. #1 LVD2ST Voltage-Monitoring 2 Interrupt Status Flag 3 3 read-only 0 Voltage-monitoring 2 interrupt is not requested. #0 1 Voltage-monitoring 2 interrupt is requested. #1 LVD1ST Voltage-Monitoring 1 Interrupt Status Flag 2 2 read-only 0 Voltage-monitoring 1 interrupt is not requested. #0 1 Voltage-monitoring 1 interrupt is requested. #1 WDTST WDT Underflow/Refresh Error Status Flag 1 1 read-only 0 WDT underflow/refresh error interrupt is not requested. #0 1 WDT underflow/refresh error interrupt is requested. #1 IWDTST IWDT Underflow/Refresh Error Status Flag 0 0 read-only 0 IWDT underflow/refresh error interrupt is not requested. #0 1 IWDT underflow/refresh error interrupt is requested. #1 NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write 0x0000 0xFFFF SPEEN MPU Stack Error Interrupt Enable 12 12 read-write 0 MPU Stack Error interrupt is disabled. #0 1 MPU Stack Error interrupt is enabled. #1 BUSMEN MPU Bus Master Error Interrupt Enable 11 11 read-write 0 MPU Bus Master Error interrupt is disabled. #0 1 MPU Bus Master Error interrupt is enabled. #1 BUSSEN MPU Bus Slave Error Interrupt Enable 10 10 read-write 0 MPU Bus Slave Error interrupt is disabled. #0 1 MPU Bus Slave Error interrupt is enabled. #1 RECCEN RAM ECC Error Interrupt Enable 9 9 read-write 0 RAM ECC Error interrupt is disabled. #0 1 RAM ECC Error interrupt is enabled. #1 RPEEN RAM Parity Error Interrupt Enable 8 8 read-write 0 RAM Parity Error interrupt is disabled. #0 1 RAM Parity Error interrupt is enabled. #1 NMIEN NMI Pin Interrupt Enable 7 7 read-write 0 NMI pin interrupt is disabled. #0 1 NMI pin interrupt is enabled. #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 6 read-write 0 Oscillation stop detection interrupt is disabled. #0 1 Oscillation stop detection interrupt is enabled. #1 LVD2EN Voltage-Monitoring 2 Interrupt Enable 3 3 read-write 0 Voltage-monitoring 2 interrupt is disabled. #0 1 Voltage-monitoring 2 interrupt is enabled. #1 LVD1EN Voltage-Monitoring 1 Interrupt Enable 2 2 read-write 0 Voltage-monitoring 1 interrupt is disabled. #0 1 Voltage-monitoring 1 interrupt is enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 1 read-write 0 WDT underflow/refresh error interrupt is disabled. #0 1 WDT underflow/refresh error interrupt is enabled. #1 IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 0 read-write 0 IWDT underflow/refresh error interrupt is disabled. #0 1 IWDT underflow/refresh error interrupt is enabled. #1 NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 write-only 0x0000 0xFFFF SPECLR SPEST Clear 12 12 write-only 0 No effect. #0 1 Clear the NMISR.SPEST flag. #1 BUSMCLR BUSMST Clear 11 11 write-only 0 No effect. #0 1 Clear the NMISR.BUSMST flag. #1 BUSSCLR BUSSST Clear 10 10 write-only 0 No effect. #0 1 Clear the NMISR.BUSSST flag. #1 RECCCLR RECCST Clear 9 9 write-only 0 No effect. #0 1 Clear the NMISR.RECCST flag. #1 RPECLR RPEST Clear 8 8 write-only 0 No effect. #0 1 Clear the NMISR.RPEST flag. #1 NMICLR NMIST Clear 7 7 write-only 0 No effect. #0 1 Clear the NMISR.NMIST flag. #1 OSTCLR OSTST Clear 6 6 write-only 0 No effect. #0 1 Clear the NMISR.OSTST flag. #1 LVD2CLR LVD2ST Clear 3 3 write-only 0 No effect. #0 1 Clear the NMISR.LVD2ST flag. #1 LVD1CLR LVD1ST Clear 2 2 write-only 0 No effect. #0 1 Clear the NMISR.LVD1ST flag. #1 WDTCLR WDTST Clear 1 1 write-only 0 No effect. #0 1 Clear the NMISR.WDTST flag. #1 IWDTCLR IWDTST Clear 0 0 write-only 0 No effect. #0 1 Clear the NMISR.IWDTST flag. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write 0x00 0xFF NFLTEN NMI Digital Filter Enable 7 7 read-write 0 Digital filter is disabled. #0 1 Digital filter is enabled. #1 NFCLKSEL NMI Digital Filter Sampling Clock 4 5 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NMIMD NMI Detection Set 0 0 read-write 0 Falling edge #0 1 Rising edge #1 96 0x4 0-95 IELSR%s INT Event Link Setting Register %s 0x300 32 read-write 0x00000000 0xFFFFFFFF DTCE DTC Activation Enable 24 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IR Interrupt Status Flag 16 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( "1" write to the IR bit is prohibited. ) #1 IELS Event selection to NVIC 0 8 read-write 0x000 Nothing is selected 0x000 others See Event Table true 8 0x4 0-7 DELSR%s DMAC Event Link Setting Register %s 0x280 32 read-write 0x00000000 0xFFFFFFFF IR Interrupt Status Flag for DMAC 16 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( "1" write to the IR bit is prohibited. ) #1 DELS DMAC Event Link Select 0 8 read-write 0x000 Nothing is selected. 0x000 others See Event Table true SELSR0 SYS Event Link Setting Register 0x200 16 read-write 0x0000 0xFFFF SELS SYS Event Link Select 0 8 read-write 000000000 Disable event output to the associated low-power mode module #000000000 others Event signal number to be linked. true WUPEN Wake Up interrupt enable register 0x1A0 32 read-write 0x00000000 0xFFFFFFFF IIC0WUPEN IIC0 address match interrupt S/W standby returns enable bit 31 31 read-write 0 S/W standby returns by IIC0 address match interrupt is disabled #0 1 S/W standby returns by IIC0 address match interrupt is enabled #1 AGT1CBWUPEN AGT1 compare match B interrupt S/W standby returns enable bit 30 30 read-write 0 S/W standby returns by AGT1 compare match B interrupt is disabled #0 1 S/W standby returns by AGT1 compare match B interrupt is enabled #1 AGT1CAWUPEN AGT1 compare match A interrupt S/W standby returns enable bit 29 29 read-write 0 S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 S/W standby returns by AGT1 compare match A interrupt is enabled #1 AGT1UDWUPEN AGT1 underflow interrupt S/W standby returns enable bit 28 28 read-write 0 S/W standby returns by AGT1 underflow interrupt is disabled #0 1 S/W standby returns by AGT1 underflow interrupt is enabled #1 USBFSWUPEN USBFS interrupt S/W standby returns enable bit 27 27 read-write 0 S/W standby returns by USBFS interrupt is disabled #0 1 S/W standby returns by USBFS interrupt is enabled #1 USBHSWUPEN USBHS interrupt S/W standby returns enable bit 26 26 read-write 0 S/W standby returns by USBHS interrupt is disabled #0 1 S/W standby returns by USBHS interrupt is enabled #1 RTCPRDWUPEN RCT period interrupt S/W standby returns enable bit 25 25 read-write 0 S/W standby returns by RTC period interrupt is disabled #0 1 S/W standby returns by RTC period interrupt is enabled #1 RTCALMWUPEN RTC alarm interrupt S/W standby returns enable bit 24 24 read-write 0 S/W standby returns by RTC alarm interrupt is disabled #0 1 S/W standby returns by RTC alarm interrupt is enabled #1 ACMPHS0WUPEN ACMPHS0 interrupt S/W standby returns enable bit 22 22 read-write 0 S/W standby returns by ACMPHS0 interrupt is disabled #0 1 S/W standby returns by ACMPHS0 interrupt is enabled #1 LVD2WUPEN LVD2 interrupt S/W standby returns enable bit 19 19 read-write 0 S/W standby returns by LVD2 interrupt is disabled #0 1 S/W standby returns by LVD2 interrupt is enabled #1 LVD1WUPEN LVD1 interrupt S/W standby returns enable bit 18 18 read-write 0 S/W standby returns by LVD1 interrupt is disabled #0 1 S/W standby returns by LVD1 interrupt is enabled #1 KEYWUPEN Key interrupt S/W standby returns enable bit 17 17 read-write 0 S/W standby returns by KEY interrupt is disabled #0 1 S/W standby returns by KEY interrupt is enabled #1 IWDTWUPEN IWDT interrupt S/W standby returns enable bit 16 16 read-write 0 S/W standby returns by IWDT interrupt is disabled #0 1 S/W standby returns by IWDT interrupt is enabled #1 IRQWUPEN15 IRQ15 interrupt S/W standby returns enable bit 15 15 read-write 0 S/W standby returns by IRQ15 interrupt is disabled #0 1 S/W standby returns by IRQ15 interrupt is enabled #1 IRQWUPEN14 IRQ14 interrupt S/W standby returns enable bit 14 14 read-write 0 S/W standby returns by IRQ14 interrupt is disabled #0 1 S/W standby returns by IRQ14 interrupt is enabled #1 IRQWUPEN13 IRQ13 interrupt S/W standby returns enable bit 13 13 read-write 0 S/W standby returns by IRQ13 interrupt is disabled #0 1 S/W standby returns by IRQ13 interrupt is enabled #1 IRQWUPEN12 IRQ12 interrupt S/W standby returns enable bit 12 12 read-write 0 S/W standby returns by IRQ12 interrupt is disabled #0 1 S/W standby returns by IRQ12 interrupt is enabled #1 IRQWUPEN11 IRQ11 interrupt S/W standby returns enable bit 11 11 read-write 0 S/W standby returns by IRQ11 interrupt is disabled #0 1 S/W standby returns by IRQ11 interrupt is enabled #1 IRQWUPEN10 IRQ10 interrupt S/W standby returns enable bit 10 10 read-write 0 S/W standby returns by IRQ10 interrupt is disabled #0 1 S/W standby returns by IRQ10 interrupt is enabled #1 IRQWUPEN9 IRQ9 interrupt S/W standby returns enable bit 9 9 read-write 0 S/W standby returns by IRQ9 interrupt is disabled #0 1 S/W standby returns by IRQ9 interrupt is enabled #1 IRQWUPEN8 IRQ8 interrupt S/W standby returns enable bit 8 8 read-write 0 S/W standby returns by IRQ8 interrupt is disabled #0 1 S/W standby returns by IRQ8 interrupt is enabled #1 IRQWUPEN7 IRQ7 interrupt S/W standby returns enable bit 7 7 read-write 0 S/W standby returns by IRQ7 interrupt is disabled #0 1 S/W standby returns by IRQ7 interrupt is enabled #1 IRQWUPEN6 IRQ6 interrupt S/W standby returns enable bit 6 6 read-write 0 S/W standby returns by IRQ6 interrupt is disabled #0 1 S/W standby returns by IRQ6 interrupt is enabled #1 IRQWUPEN5 IRQ5 interrupt S/W standby returns enable bit 5 5 read-write 0 S/W standby returns by IRQ5 interrupt is disabled #0 1 S/W standby returns by IRQ5 interrupt is enabled #1 IRQWUPEN4 IRQ4 interrupt S/W standby returns enable bit 4 4 read-write 0 S/W standby returns by IRQ4 interrupt is disabled #0 1 S/W standby returns by IRQ4 interrupt is enabled #1 IRQWUPEN3 IRQ3 interrupt S/W standby returns enable bit 3 3 read-write 0 S/W standby returns by IRQ3 interrupt is disabled #0 1 S/W standby returns by IRQ3 interrupt is enabled #1 IRQWUPEN2 IRQ2 interrupt S/W standby returns enable bit 2 2 read-write 0 S/W standby returns by IRQ2 interrupt is disabled #0 1 S/W standby returns by IRQ2 interrupt is enabled #1 IRQWUPEN1 IRQ1 interrupt S/W standby returns enable bit 1 1 read-write 0 S/W standby returns by IRQ1 interrupt is disabled #0 1 S/W standby returns by IRQ1 interrupt is enabled #1 IRQWUPEN0 IRQ0 interrupt S/W standby returns enable bit 0 0 read-write 0 S/W standby returns by IRQ0 interrupt is disabled #0 1 S/W standby returns by IRQ0 interrupt is enabled #1 SRAM SRAM Control 0x40002000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0xC0 5 registers 0xD0 1 registers 0xD4 1 registers 0xD8 1 registers PARIOAD SRAM Parity Error Operation After Detection Register 0x00 8 read-write 0x00 0xFF OAD Operation after Detection 0 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 SRAMPRCR SRAM Protection Register 0x04 8 read-write 0x00 0xFF KW Write Key Code 1 7 write-only 1111000 Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 others Writing to the RAMPRCR bit is invalid. true SRAMPRCR Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 SRAMWTSC RAM Wait State Control Register 0x08 8 read-write 0x0E 0xFF SRAM1WTEN SRAM1 Wait Enable 3 3 read-write 0 Not add wait state in read access cycle to SRAM1 #0 1 Add wait state in read access cycle to SRAM1 #1 SRAM0WTEN SRAM0 Wait Enable 2 2 read-write 0 Not add wait state in read access cycle to SRAM0 #0 1 Add wait state in read access cycle to SRAM0 #1 ECCRAMRDWTEN ECCRAM Read wait enable 1 1 read-write 0 Not add wait state in read access cycle to SRAM0 (ECC area) #0 1 Add wait state in read access cycle to SRAM0 (ECC area) #1 ECCMODE ECCRAM Operating Mode Control Register 0xC0 8 read-write 0x00 0xFF ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking. #11 ECC2STS ECCRAM 2-Bit Error Status Register 0xC1 8 read-write 0x00 0xFF ECC2ERR ECC 2-Bit Error Status 0 0 read-write zeroToClear modify 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred #1 ECC1STSEN ECCRAM 1-Bit Error Information Update Enable Register 0xC2 8 read-write 0x00 0xFF E1STSEN ECC 1-Bit Error Information Update Enable 0 0 read-write 0 Disables updating of the 1-bit ECC error information. #0 1 Enables updating of the 1-bit ECC error information. #1 ECC1STS ECCRAM 1-Bit Error Status Register 0xC3 8 read-write 0x00 0xFF ECC1ERR ECC 1-Bit Error Status 0 0 read-write zeroToClear modify 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 ECCPRCR ECCRAM Protection Register 0xC4 8 read-write 0x00 0xFF KW Write Key Code 1 7 write-only 1111000 Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 others Writing to the ECCRAMPRCR bit is invalid. true ECCPRCR ECCRAMETST Register Write Control 0 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers #1 ECCETST ECC Test Control Register 0xD4 8 read-write 0x00 0xFF TSTBYP ECC Bypass Select 0 0 read-write 0 ECC bypass disabled #0 1 ECC bypass enabled. #1 ECCOAD RAM ECC Error Operation After Detection Register 0xD8 8 read-write 0x00 0xFF OAD Operation after Detection 0 0 read-write 0 Non maskable interrupt. #0 1 Internal reset. #1 GPT_ODC PWM Delay Generation Circuit 0x4007B000 0x00 4 registers 0x18 16 registers 0x18 16 registers 0x1A 16 registers 0x28 16 registers 0x28 16 registers 0x2A 16 registers GTDLYCR PWM Output Delay Control Register 0x00 16 read-write 0x0000 0xFFFF DLYRST PWM Delay Generation Circuit Reset 1 1 read-write 0 Normal operation #0 1 Reset #1 DLLEN DLL Operation Enable 0 0 read-write 0 Disable DLL operation #0 1 Enable DLL operation #1 GTDLYCR2 PWM Output Delay Control Register2 0x02 16 read-write 0x0000 0xFFFF DLYEN3 PWM Delay Generation Circuit enable for channel 3 11 11 read-write 0 Enable delay generation circuit of channel 3 #0 1 Disable delay generation circuit of channel 3 #1 DLYEN2 PWM Delay Generation Circuit enable for channel 2 10 10 read-write 0 Enable delay generation circuit of channel 2 #0 1 Disable delay generation circuit of channel 2. #1 DLYEN1 PWM Delay Generation Circuit enable for channel 1 9 9 read-write 0 Enable delay generation circuit of channel 1 #0 1 Disable delay generation circuit of channel 1. #1 DLYEN0 PWM Delay Generation Circuit enable for channel 0 8 8 read-write 0 Enable delay generation circuit of channel 0 #0 1 Disable delay generation circuit of channel 0. #1 DLYBS3 PWM Delay Generation Circuit bypass for channel 3 3 3 read-write 0 Bypass delay generation circuit of channel 3 #0 1 Do not bypass delay generation circuit of channel 3. #1 DLYBS2 PWM Delay Generation Circuit bypass for channel 2 2 2 read-write 0 Bypass delay generation circuit of channel 2 #0 1 Do not bypass delay generation circuit of channel 2. #1 DLYBS1 PWM Delay Generation Circuit bypass for channel 1 1 1 read-write 0 Bypass delay generation circuit of channel 1 #0 1 Do not bypass delay generation circuit of channel 1. #1 DLYBS0 PWM Delay Generation Circuit bypass for channel 0 0 0 read-write 0 Bypass delay generation circuit of channel 0 #0 1 Do not bypass delay generation circuit of channel 0. #1 4 0x4 0-3 GTDLYR%sA GTIOC%sA Rising Output Delay Register GTDLYR%s 0x18 16 read-write 0x0000 0xFFFF DLY GTIOCnA Output Rising Edge Delay Setting 0 4 read-write 00000 No delay on rising edges #00000 others Delay of DLY/32 times the PCLKD period is applied. true 4 0x4 0-3 GTDLYR%sB GTIOC%sB Rising Output Delay Register GTDLYR%s 0x1A 16 read-write 0x0000 0xFFFF DLY GTIOCnB Output Rising Edge Delay Setting 0 4 read-write 00000 No delay on rising edges #00000 others Delay of DLY/32 times the PCLKD period is applied. true 4 0x4 0-3 GTDLYF%sA GTIOC%sA Falling Output Delay Register GTDLYF%s 0x28 16 read-write 0x0000 0xFFFF DLY GTIOCnA Output Falling Edge Delay Setting 0 4 read-write 00000 No delay on rising edges #00000 others Delay of DLY/32 times the PCLKD period is applied. true 4 0x4 0-3 GTDLYF%sB GTIOC%sB Falling Output Delay Register GTDLYF%s 0x2A 16 read-write 0x0000 0xFFFF DLY GTIOCnB Output Falling Edge Delay Setting 0 4 read-write 00000 No delay on rising edges #00000 others Delay of DLY/32 times the PCLKD period is applied. true AGT0 Asynchronous General purpose Timer 0 0x40084000 0x00 6 registers 0x08 3 registers 0x0C 4 registers AGT AGT Counter Register 0x00 16 read-write 0xFFFF 0xFFFF AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x02 16 read-write 0xFFFF 0xFFFF AGTCMA AGT Compare Match A RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x04 16 read-write 0xFFFF 0xFFFF AGTCMB AGT Compare Match B RegisterNOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCR AGT Control Register 0x08 8 read-write 0x00 0xFF TCMBF AGT compare match B flag 7 7 read-write zeroToClear modify 0 No Match #0 1 Match #1 TCMAF AGT compare match A flag 6 6 read-write zeroToClear modify 0 No Match #0 1 Match #1 TUNDF AGT underflow flag 5 5 read-write zeroToClear modify 0 No underflow #0 1 Underflow #1 TEDGF Active edge judgement flag 4 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received #1 TSTOP AGT count forced stop 2 2 write-only 0 no effect #0 1 The count is forcibly stopped. #1 TCSTF AGT count status flag 1 1 read-only 0 Count stops #0 1 Count starts #1 TSTART AGT count start 0 0 read-write 0 Count stops #0 1 Count starts #1 AGTMR1 AGT Mode Register 1 0x09 8 read-write 0x00 0xFF TCK AGT count source select 4 6 read-write 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock LOCO specified by AGTMR2.CKS bit. #100 101 Underflow event signal from AGT #101 110 Divided clock fSUB specified by AGTMR2.CKS bit. #110 others Setting prohibited true TEDGPL AGTIO edge polarity select 3 3 read-write 0 One edge #0 1 Both edges #1 TMOD AGT operating mode select 0 2 read-write 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode #100 others Setting prohibited true AGTMR2 AGT Mode Register 2 0x0A 8 read-write 0x00 0xFF LPM AGT Low Power Mode 7 7 read-write 0 Normal mode #0 1 Low Power mode #1 CKS fsub/LOCO count source clock frequency division ratio select 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128 #111 AGTIOC AGT I/O Control Register 0x0C 8 read-write 0x00 0xFF TIOGT AGTIO count control 6 7 read-write 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEE #01 others Setting prohibited true TIPF AGTIO input filter select 4 5 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTO output enable 2 2 read-write 0 AGTO output disabled (port) #0 1 AGTO output enabled #1 TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 0 read-write AGTISR AGT Event Pin Select Register 0x0D 8 read-write 0x00 0xFF EEPS AGTEE polarty selection 2 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 AGTCMSR AGT Compare Match Function Select Register 0x0E 8 read-write 0x00 0xFF TOPOLB AGTOB polarity select 6 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 TOEB AGTOB output enable 5 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TCMEB Compare match B register enable 4 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOPOLA AGTOA polarity select 2 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOEA AGTOA output enable 1 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TCMEA Compare match A register enable 0 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 AGTIOSEL AGT Pin Select Register 0x0F 8 read-write 0x00 0xFF TIES AGTIO input enable 4 4 read-write 0 external event input disable during software standby mode #0 1 external event input enable during software standby mode #1 SEL AGTIO pin select 0 1 read-write 00 AGTIO_A can not be used as AGTIO input pin in deep software standby mode #00 01 Setting prohibited #01 10 AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. #10 11 AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. #11 AGT1 Asynchronous General purpose Timer 1 0x40084100 FCACHE Flash Cache 0x4001C000 0x00 1 registers 0x30 1 registers 0x32 2 registers 0x100 2 registers 0x104 2 registers 0x11C 1 registers 0x120 1 registers 0x124 1 registers 0x127 1 registers 0x130 4 registers 0x138 8 registers FCACHEE Flash Cache Enable Register 0x100 16 read-write 0x0000 0xFFFF FCACHEEN FCACHE Enable 0 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 FCACHEIV Flash Cache Invalidate Register 0x104 16 read-write 0x0000 0xFFFF FCACHEIV FCACHE Invalidation 0 0 read-write oneToSet modify 0 (Read)not in progress / (Write) no effect. #0 1 (Read)in progress /(Write) Starting Cache Invalidation #1 FLWT Flash Wait Cycle Register 0x11C 8 read-write 0x00 0xFF FLWT Flash Wait Cycle 0 2 read-write 000 0 wait (ICLK<=80MHz) #000 001 1 wait (80MHz < ICLK <=160MHz) #001 010 2 waits (160MHz < ICLK <=240MHz) #010 others Setting prohibited true BUS BUS Control 0x40003000 0x802 2 registers 0x812 112 registers 0x80A 128 registers 0x880 2 registers 0x02 128 registers 0x04 128 registers 0x08 128 registers 0xC00 3 registers 0xC10 1 registers 0xC14 3 registers 0xC20 1 registers 0xC24 2 registers 0xC40 1 registers 0xC44 6 registers 0xC50 1 registers 0x1800 176 registers 0x1804 176 registers 0x1000 10 registers 0x100C 2 registers 0x1010 8 registers 0x1100 10 registers 0x110C 24 registers 0x1128 24 registers CS0CR CS0 Control Register 0x0802 16 read-write 0x0021 0xFFFF MPXEN Address/Data Multiplexed I/O Interface Select 12 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 EMODE Endian Mode 8 8 read-write 0 Little Endian #0 1 Big Endian #1 BSIZE External Bus Width Select 4 5 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EXENB Operation Enable 0 0 read-write 0 Disable operation #0 1 Enable operation #1 7 0x10 1-7 CS%sCR CS%s Control Register 0x0812 16 read-write 0x0000 0xFFFF MPXEN Address/Data Multiplexed I/O Interface Select 12 12 read-write 0 Separate bus interface is selected for area n #0 1 Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 EMODE Endian Mode 8 8 read-write 0 Little Endian #0 1 Big Endian #1 BSIZE External Bus Width Select 4 5 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EXENB Operation Enable 0 0 read-write 0 Disable operation #0 1 Enable operation #1 8 0x10 0-7 CS%sREC CS%s Recovery Cycle Register 0x080A 16 read-write 0x0000 0xFFFF WRCV Write Recovery 8 11 read-write 0x0 No recovery cycle is inserted. 0x0 others WRCV recovery cycle is inserted. true RRCV Read Recovery 0 3 read-write 0x0 No recovery cycle is inserted. 0x0 others RRCV recovery cycle is inserted. true CSRECEN CS Recovery Cycle Insertion Enable Register 0x0880 16 read-write 0x3E3E 0xFFFF RCVENM7 Multiplexed Bus Recovery Cycle Insertion Enable 7 15 15 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM6 Multiplexed Bus Recovery Cycle Insertion Enable 6 14 14 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM5 Multiplexed Bus Recovery Cycle Insertion Enable 5 13 13 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM4 Multiplexed Bus Recovery Cycle Insertion Enable 4 12 12 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM3 Multiplexed Bus Recovery Cycle Insertion Enable 3 11 11 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM2 Multiplexed Bus Recovery Cycle Insertion Enable 2 10 10 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM1 Multiplexed Bus Recovery Cycle Insertion Enable 1 9 9 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVENM0 Multiplexed Bus Recovery Cycle Insertion Enable 0 8 8 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN7 Separate Bus Recovery Cycle Insertion Enable 7 7 7 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN6 Separate Bus Recovery Cycle Insertion Enable 6 6 6 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN5 Separate Bus Recovery Cycle Insertion Enable 5 5 5 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN4 Separate Bus Recovery Cycle Insertion Enable 4 4 4 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN3 Separate Bus Recovery Cycle Insertion Enable 3 3 3 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN2 Separate Bus Recovery Cycle Insertion Enable 2 2 2 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN1 Separate Bus Recovery Cycle Insertion Enable 1 1 1 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RCVEN0 Separate Bus Recovery Cycle Insertion Enable 0 0 0 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 8 0x10 0-7 CS%sMOD CS%s Mode Register 0x0002 16 read-write 0x0000 0xFFFF PRMOD Page Read Access Mode Select 15 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PWENB Page Write Access Enable 9 9 read-write 0 Disable #0 1 Enable #1 PRENB Page Read Access Enable 8 8 read-write 0 Disable #0 1 Enable #1 EWENB External Wait Enable 3 3 read-write 0 Disable #0 1 Enable #1 WRMOD Write Access Mode Select 0 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 8 0x10 0-7 CS%sWCR1 CS%s Wait Control Register 1 0x0004 32 read-write 0x07070707 0xFFFFFFFF CSRWAIT Normal Read Cycle Wait Select 24 28 read-write 0x00 No wait is inserted. 0x00 others Wait with a length of CSRWAIT clock cycle is inserted. true CSWWAIT Normal Write Cycle Wait Select 16 20 read-write 0x00 No wait is inserted. 0x00 others Wait with a length of CSWWAIT clock cycle is inserted. true CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 10 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of CSPRWAIT clock cycle is inserted. true CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of CSPWWAIT clock cycle is inserted. true 8 0x10 0-7 CS%sWCR2 CS%s Wait Control Register 2 0x0008 32 read-write 0x00000007 0xFFFFFFFF CSON CS Assert Wait Select 28 30 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of CSON clock cycle is inserted. true WDON Write Data Output Wait Select 24 26 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of WDON clock cycle is inserted. true WRON WR Assert Wait Select 20 22 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of WRON clock cycle is inserted. true RDON RD Assert Wait Select 16 18 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of RDON clock cycle is inserted. true AWAIT Address Cycle Wait Select 12 13 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of AWAIT clock cycle is inserted. true WDOFF Write Data Output Extension Cycle Select 8 10 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of WDOFF clock cycle is inserted. true CSWOFF Write-Access CS Extension Cycle Select 4 6 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of CSWOFF clock cycle is inserted. true CSROFF Read-Access CS Extension Cycle Select 0 2 read-write 0x0 No wait is inserted. 0x0 others Wait with a length of CSROFF clock cycle is inserted. true SDCCR SDC Control Register 0x0C00 8 read-write 0x00 0xFF BSIZE SDRAM Bus Width Select 4 5 read-write 00 A 16-bit bus space #00 01 Setting prohibited #01 10 An 8-bit bus space #10 11 Setting prohibited #11 EXENB Operation Enable 0 0 read-write 0 Disable #0 1 Enable #1 SDCMOD SDC Mode Register 0x0C01 8 read-write 0x00 0xFF EMODE Endian Mode 0 0 read-write 0 Endian order of SDRAM address space is the same as the endian order of the operating mode #0 1 Endian order of SDRAM address space is not the endian order of the operating mode. #1 SDAMOD SDRAM Access Mode Register 0x0C02 8 read-write 0x00 0xFF BE Continuous Access Enable 0 0 read-write 0 Disable #0 1 Enable. #1 SDSELF SDRAM Self-Refresh Control Register 0x0C10 8 read-write 0x00 0xFF SFEN SDRAM Self-Refresh Enable 0 0 read-write 0 Disable #0 1 Enable #1 SDRFCR SDRAM Refresh Control Register 0x0C14 16 read-write 0x0001 0xFFFF REFW Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) 12 15 read-write RFC Auto-Refresh Request Interval Setting 0 11 read-write 0x0 Setting prohibited 0x0 others RFC+1 cycles inserted true SDRFEN SDRAM Auto-Refresh Control Register 0x0C16 8 read-write 0x00 0xFF RFEN Auto-Refresh Operation Enable 0 0 read-write 0 Disable #0 1 Enable #1 SDICR SDRAM Initialization Sequence Control Register 0x0C20 8 read-write 0x00 0xFF INIRQ Initialization Sequence Start 0 0 read-write 0 Invalid #0 1 Initialization sequence starts #1 SDIR SDRAM Initialization Register 0x0C24 16 read-write 0x0010 0xFFFF PRC Initialization Precharge Cycle Count (PRC+3 cycles) 8 10 read-write ARFC Initialization Auto-Refresh Count 4 7 read-write 0x0 Setting prohibited 0x0 others ARFC times true ARFI Initialization Auto-Refresh Interval (ARFI+3 cycles ) 0 3 read-write SDADR SDRAM Address Register 0x0C40 8 read-write 0x00 0xFF MXC Address Multiplex Select 0 1 read-write 00 8-bit shift #00 01 9-bit shift #01 10 10-bit shift #10 11 11-bit shift #11 SDTR SDRAM Timing Register 0x0C44 32 read-write 0x00000002 0xFFFFFFFF RAS Row Active Interval 16 18 read-write 000 1 cycle #000 001 2 cycles #001 010 3 cycles #010 011 4 cycles #011 100 5 cycles #100 101 6 cycles #101 110 7 cycles #110 111 Setting prohibited #111 RCD Row Column Latency ( RCD+1 cycles ) 12 13 read-write RP Row Precharge Interval ( RP+1 cycles ) 9 11 read-write WR Write Recovery Interval 8 8 read-write 0 1 cycle #0 1 2 cycles #1 CL SDRAMC Column Latency 0 2 read-write 001 1 cycle #001 010 2 cycles #010 011 3 cycles #011 others Setting prohibited true SDMOD SDRAM Mode Register 0x0C48 16 read-write 0x0000 0xFFFF MR Mode Register SettingWriting to these bits: Mode register set command is issued. 0 14 read-write SDSR SDRAM Status Register 0x0C50 8 read-only 0x00 0xFF SRFST Self-Refresh Transition/Recovery Status 4 4 read-only 0 Transition/recovery not in progress #0 1 Transition/recovery in progress #1 INIST Initialization Status 3 3 read-only 0 Initialization sequence not in progress #0 1 Initialization sequence in progress #1 MRSST Mode Register Setting Status 0 0 read-only 0 Mode register setting not in progress #0 1 Mode register setting in progress #1 11 0x10 1-11 BUS%sERRADD Bus Error Address Register %s 0x1800 32 read-only 0x00000000 0x00000000 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only 11 0x10 1-11 BUS%sERRSTAT Bus Error Status Register %s 0x1804 8 read-only 0x00 0xFE ERRSTAT Bus Error StatusWhen bus error assert, error flag occurs. 7 7 read-only 0 No bus error occurred #0 1 Bus error occurred #1 ACCSTAT Error access statusThe status at the time of the error 0 0 read-only 0 Read access #0 1 Write Access #1 2 0x4 M4I,M4D BUSMCNT%s Master Bus Control Register %s 0x1000 16 read-write 0x0000 0xFFFF IERES Ignore Error Responses 15 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 BUSMCNTSYS Master Bus Control Register SYS 0x1008 16 read-write 0x0000 0xFFFF IERES Ignore Error Responses 15 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 BUSMCNTDMA Master Bus Control Register DMA 0x100C 16 read-write 0x0000 0xFFFF IERES Ignore Error Responses 15 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 2 0x4 EDM,GPX BUSMCNT%s Master Bus Control Register %s 0x1010 16 read-write 0x0000 0xFFFF IERES Ignore Error Responses 15 15 read-write 0 Bus error will be reported. #0 1 Bus error will not be reported. #1 2 0x4 FLI,RAMH BUSSCNT%s Slave Bus Control Register %s 0x1100 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true BUSSCNTMBIU Slave Bus Control Register MBIU 0x1108 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true 2 0x4 RAM0,RAM1 BUSSCNT%s Slave Bus Control Register %s 0x110C 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true 4 0x4 P0B,P2B,P3B,P4B BUSSCNT%s Slave Bus Control Register %s 0x1114 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true 2 0x4 P6B,P7B BUSSCNT%s Slave Bus Control Register %s 0x1128 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true 4 0x4 FBU,EXT,EXT2,GPX BUSSCNT%s Slave Bus Control Register %s 0x1130 16 read-write 0x0000 0xFFFF EWRES Early Write ResponseWhether the next write request is accepted or not until a response for the write transaction comes back. 8 8 read-write 0 Not accepted. #0 1 Accepted but error response is ignored. #1 ARBMET Arbitration MethodSpecify the priority between groups 4 5 read-write 00 fixed priority #00 01 round-robin #01 others Setting prohibited true DAC12 12-bit D/A converter 0x4005E000 0x00 7 registers 0x08 1 registers 0x101C 1 registers 2 0x2 0,1 DADR%s D/A Data Register %s 0x00 16 read-write 0x0000 0xFFFF DADR D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. 0 15 read-write DACR D/A Control Register 0x0004 8 read-write 0x1F 0xFF DAOE1 D/A Output Enable 1 7 7 read-write 0 Analog output of channel 1 (DA1) is disabled. #0 1 D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled. #1 DAOE0 D/A Output Enable 0 6 6 read-write 0 Analog output of channel 0 (DA0) is disabled. #0 1 D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. #1 DAE D/A Enable 5 5 read-write 0 D/A conversion is independently controlled on channels 0 and 1. #0 1 D/A conversion on channels 0 and 1 is controlled as a single whole. #1 DADPR DADRm Format Select Register 0x0005 8 read-write 0x00 0xFF DPSEL DADRm Format Select 7 7 read-write 0 Right justified format. #0 1 Left justified format. #1 DAADSCR D/A-A/D Synchronous Start Control Register 0x0006 8 read-write 0x00 0xFF DAADST D/A-A/D Synchronous Conversion 7 7 read-write 0 D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). #0 1 D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). #1 DAAMPCR D/A Output Amplifier Control Register 0x0008 8 read-write 0x00 0xFF DAAMP1 Amplifier Control 1 7 7 read-write 0 Output amplifier of channel 1 is not used. #0 1 Output amplifier of channel 1 is used. #1 DAAMP0 Amplifier Control 0 6 6 read-write 0 Output amplifier of channel 0 is not used. #0 1 Output amplifier of channel 0 is used. #1 DAASWCR D/A Amplifier Stabilization Wait Control Register 0x101C 8 read-write 0x00 0xFF DAASW1 D/A Amplifier Stabilization Wait 1 7 7 read-write 0 Amplifier stabilization wait off (output) for channel 1 #0 1 Amplifier stabilization wait on (high-Z) for channel 1. #1 DAASW0 D/A Amplifier Stabilization Wait 0 6 6 read-write 0 Amplifier stabilization wait off (output) for channel 0 #0 1 Amplifier stabilization wait on (high-Z) for channel 0. #1 AMI ADC-DAC Interface 0x4005F000 0xC0 1 registers DAADUSR D/A A/D Synchronous Unit Select Register 0xC0 8 read-write 0x00 0xFF AMADSEL1 A/D Unit 1 Select 1 1 read-write 0 Unit 1 is not selected. #0 1 Unit 1 is selected. #1 POEG Port Output Enable Module for GPT 0x40042000 0x00 1024 registers 4 0x100 A,B,C,D POEGG%s POEG Group %s Setting Register 0x00 32 read-write 0x00000000 0xFFFFFFFF NFCS Noise Filter Clock Select 30 31 read-write 00 Sampling GTETRG pin input level for three times in every PCLKB. #00 01 Sampling GTETRG pin input level for three times in every PCLKB /8. #01 10 Sampling GTETRG pin input level for three times in every PCLKB /32. #10 11 Sampling GTETRG pin input level for three times in every PCLKB /128. #11 NFEN Noise Filter Enable 29 29 read-write 0 Filtering noise disabled #0 1 Filtering noise enabled #1 INV GTETRG Input Reverse 28 28 read-write 0 GTETRG Input #0 1 GTETRG Input Reversed. #1 ST GTETRG Input Status Flag 16 16 read-only 0 GTETRG input after filtering is 0. #0 1 GTETRG input after filtering is 1. #1 CDRE5 Comparator Disable Request Enable 5Note: Can be modified only once after a reset. 13 13 read-write 0 A disable request of comparator 5 disabled. #0 1 A disable request of comparator 5 enabled. #1 CDRE4 Comparator Disable Request Enable 4Note: Can be modified only once after a reset. 12 12 read-write 0 A disable request of comparator 4 disabled. #0 1 A disable request of comparator 4 enabled. #1 CDRE3 Comparator Disable Request Enable 3Note: Can be modified only once after a reset. 11 11 read-write 0 A disable request of comparator 3 disabled. #0 1 A disable request of comparator 3 enabled. #1 CDRE2 Comparator Disable Request Enable 2Note: Can be modified only once after a reset. 10 10 read-write 0 A disable request of comparator 2 disabled. #0 1 A disable request of comparator 2 enabled. #1 CDRE1 Comparator Disable Request Enable 1Note: Can be modified only once after a reset. 9 9 read-write 0 A disable request of comparator 1 disabled. #0 1 A disable request of comparator 1 enabled. #1 CDRE0 Comparator Disable Request Enable 0Note: Can be modified only once after a reset. 8 8 read-write 0 A disable request of comparator 0 disabled. #0 1 A disable request of comparator 0 enabled. #1 OSTPE Oscillation Stop Detection EnableNote: Can be modified only once after a reset. 6 6 read-write 0 A output-disable request from the oscillation stop detection disabled. #0 1 A output-disable request from the oscillation stop detection enabled. #1 IOCE Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. 5 5 read-write 0 Disable output-disable requests from GPT disable request #0 1 Enable output-disable requests from GPT disable request #1 PIDE Port Input Detection EnableNote: Can be modified only once after a reset. 4 4 read-write 0 A output-disable request from the GTETRG pins disabled. #0 1 A output-disable request from the GTETRG pins enabled. #1 SSF Software Stop Flag 3 3 read-write 0 A output-disable request from software has not been generated. #0 1 A output-disable request from software has been generated. #1 OSTPF Oscillation Stop Detection Flag 2 2 read-write zeroToClear modify 0 A output-disable request from the oscillation stop detection has not been generated. #0 1 A output-disable request from the oscillation stop detection has been generated. #1 IOCF Real Time Overcurrent Detection Flag 1 1 read-write zeroToClear modify 0 A output-disable request from GPT disable request or comparator interrupt has not been generated. #0 1 A output-disable request from GPT disable request or comparator interrupt has been generated. #1 PIDF Port Input Detection Flag 0 0 read-write zeroToClear modify 0 A output-disable request from the GTETRG pin has not been generated. #0 1 A output-disable request from the GTETRG pin has been generated. #1 IRDA Infrared Data Association 0x40070F00 0x00 1 registers IRCR IrDA Control Register 0x00 8 read-write 0x00 0xFF IRE IrDA Enable 7 7 read-write 0 Serial I/O pins are used for normal serial communication. #0 1 Serial I/O pins are used for IrDA data communication. #1 IRTXINV IRTXD Polarity Switching 3 3 read-write 0 Data to be transmitted is output to IRTXD as is. #0 1 Data to be transmitted is output to IRTXD after the polarity is inverted. #1 IRRXINV IRRXD Polarity Switching 2 2 read-write 0 IRRXD input is used as received data as is. #0 1 IRRXD input is used as received data after the polarity is inverted. #1 CAN0 CAN0 Module 0x40050000 0x200 512 registers 0x204 512 registers 0x206 512 registers 0x207 512 registers 0x208 512 registers 0x209 512 registers 0x20A 512 registers 0x20B 512 registers 0x20C 512 registers 0x20D 512 registers 0x20E 512 registers 0x400 48 registers 0x42C 4 registers 0x820 32 registers 0x820 57 registers 32 0x10 0-31 MB%s_ID Mailbox Register 0x200 32 read-write 0x00000000 0x00000000 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write 32 0x10 0-31 MB%s_DL Mailbox Register 0x204 16 read-write 0x0000 0x0000 DLC Data Length Code 0 3 read-write 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 others Data length = 8 bytes true 32 0x10 0-31 MB%s_D0 Mailbox Register 0x206 8 read-write 0x00 0x00 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D1 Mailbox Register 0x207 8 read-write 0x00 0x00 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D2 Mailbox Register 0x208 8 read-write 0x00 0x00 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D3 Mailbox Register 0x209 8 read-write 0x00 0x00 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D4 Mailbox Register 0x20A 8 read-write 0x00 0x00 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D5 Mailbox Register 0x20B 8 read-write 0x00 0x00 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D6 Mailbox Register 0x20C 8 read-write 0x00 0x00 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_D7 Mailbox Register 0x20D 8 read-write 0x00 0x00 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write 32 0x10 0-31 MB%s_TS Mailbox Register 0x20E 16 read-write 0x0000 0x0000 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 15 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write 8 0x4 0-7 MKR[%s] Mask Register 0x400 32 read-write 0x00000000 0x00000000 SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write 2 0x4 0,1 FIDCR%s FIFO Received ID Compare Registers 0x420 32 read-write 0x00000000 0x00000000 IDE ID Extension 31 31 read-write 0 Standard ID #0 1 Extended ID #1 RTR Remote Transmission Request 30 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 28 read-write EID Extended ID 0 17 read-write MKIVLR Mask Invalid Register 0x428 32 read-write 0x00000000 0x00000000 MB31 mailbox 31 Mask Invalid 31 31 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 mailbox 30 Mask Invalid 30 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 mailbox 29 Mask Invalid 29 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 mailbox 28 Mask Invalid 28 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 mailbox 27 Mask Invalid 27 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 mailbox 26 Mask Invalid 26 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 mailbox 25 Mask Invalid 25 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 mailbox 24 Mask Invalid 24 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 mailbox 23 Mask Invalid 23 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 mailbox 22 Mask Invalid 22 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 mailbox 21 Mask Invalid 21 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 mailbox 20 Mask Invalid 20 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 mailbox 19 Mask Invalid 19 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 mailbox 18 Mask Invalid 18 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 mailbox 17 Mask Invalid 17 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 mailbox 16 Mask Invalid 16 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 mailbox 15 Mask Invalid 15 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 mailbox 14 Mask Invalid 14 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 mailbox 13 Mask Invalid 13 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 mailbox 12 Mask Invalid 12 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 mailbox 11 Mask Invalid 11 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 mailbox 10 Mask Invalid 10 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB9 mailbox 9 Mask Invalid 9 9 read-write 0 Mask valid #0 1 Mask invalid #1 MB8 mailbox 8 Mask Invalid 8 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB7 mailbox 7 Mask Invalid 7 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB6 mailbox 6 Mask Invalid 6 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB5 mailbox 5 Mask Invalid 5 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB4 mailbox 4 Mask Invalid 4 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB3 mailbox 3 Mask Invalid 3 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB2 mailbox 2 Mask Invalid 2 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB1 mailbox 1 Mask Invalid 1 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB0 mailbox 0 Mask Invalid 0 0 read-write 0 Mask valid #0 1 Mask invalid #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write 0x00000000 0x00000000 MB31 mailbox 31 Interrupt Enable 31 31 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB30 mailbox 30 Interrupt Enable 30 30 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB29 mailbox 29 Interrupt Enable 29 29 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB28 mailbox 28 Interrupt Enable 28 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB27 mailbox 27 Interrupt Enable 27 27 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB26 mailbox 26 Interrupt Enable 26 26 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB25 mailbox 25 Interrupt Enable 25 25 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB24 mailbox 24 Interrupt Enable 24 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB3 mailbox 3 Interrupt Enable 3 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB0 mailbox 0 Interrupt Enable 0 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write 0x00000000 0x00000000 MB29 Receive FIFO Interrupt Generation Timing Control 29 29 read-write 0 Every time reception is completed #0 1 When the receive FIFO becomes buffer warning by completion of reception #1 MB28 Receive FIFO Interrupt Enable 28 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB25 Transmit FIFO Interrupt Generation Timing Control 25 25 read-write 0 Every time transmission is completed #0 1 When the transmit FIFO becomes empty due to completion of transmission #1 MB24 Transmit FIFO Interrupt Enable 24 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB3 mailbox 3 Interrupt Enable 3 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB0 mailbox 0 Interrupt Enable 0 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 32 0x1 0-31 MCTL_TX[%s] Message Control Register for Transmit 0x820 8 read-write 0x00 0xFF TRMREQ Transmit Mailbox Request 7 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 ONESHOT One-Shot Enable 4 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 SENTDATA Transmission Complete Flag 0 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 32 0x1 0-31 MCTL_RX[%s] Message Control Register for Receive MCTL_TX[%s] 0x820 8 read-write 0x00 0xFF TRMREQ Transmit Mailbox Request 7 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 RECREQ Receive Mailbox Request 6 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 ONESHOT One-Shot Enable 4 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 1 read-only 0 Message valid #0 1 Message being updated #1 NEWDATA Reception Complete Flag 0 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 CTLR Control Register 0x840 16 read-write 0x0500 0xFFFF RBOC Forcible Return From Bus-Off 13 13 read-write 0 Nothing occurred #0 1 Forcible return from bus-off #1 BOM Bus-Off Recovery Mode by a program request 11 12 read-write 00 Normal mode (ISO11898-1 compliant) #00 01 Entry to CAN halt mode automatically at bus-off entry #01 10 Entry to CAN halt mode automatically at bus-off end #10 11 Entry to CAN halt mode (during bus-off recovery period) #11 SLPM CAN Sleep Mode 10 10 read-write 0 Other than CAN sleep mode #0 1 CAN sleep mode #1 CANM CAN Operating Mode Select 8 9 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forcible transition) #11 TSPS Time Stamp Prescaler Select 6 7 read-write 00 Every bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 TSRC Time Stamp Counter Reset Command 5 5 read-write 0 Nothing occurred #0 1 Reset #1 TPM Transmission Priority Mode Select 4 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 MLM Message Lost Mode Select 3 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 IDFM ID Format Mode Select 1 2 read-write 00 Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. #00 01 Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. #01 10 Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. #10 11 Do not use this combination #11 MBM CAN Mailbox Mode Select 0 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 STR Status Register 0x842 16 read-only 0x0500 0xFFFF RECST Receive Status Flag (receiver) 14 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 TRMST Transmit Status Flag (transmitter) 13 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or in bus-off state #1 BOST Bus-Off Status Flag 12 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 EPST Error-Passive Status Flag 11 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 SLPST CAN Sleep Status Flag 10 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 HLTST CAN Halt Status Flag 9 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 RSTST CAN Reset Status Flag 8 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 EST Error Status Flag 7 7 read-only 0 No error occurred #0 1 Error occurred #1 TABST Transmission Abort Status Flag 6 6 read-only 0 No mailbox with TRMABT bit = 1 #0 1 Mailbox(es) with TRMABT bit = 1 #1 FMLST FIFO Mailbox Message Lost Status Flag 5 5 read-only 0 RFMLF bit = 0 #0 1 RFMLF bit = 1 #1 NMLST Normal Mailbox Message Lost Status Flag 4 4 read-only 0 No mailbox with MSGLOST bit = 1 #0 1 Mailbox(es) with MSGLOST bit = 1 #1 TFST Transmit FIFO Status Flag 3 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 RFST Receive FIFO Status Flag 2 2 read-only 0 No message in receive FIFO (empty) #0 1 Message in receive FIFO #1 SDST SENTDATA Status Flag 1 1 read-only 0 No mailbox with SENTDATA bit = 1 #0 1 Mailbox(es) with SENTDATA bit = 1 #1 NDST NEWDATA Status Flag 0 0 read-only 0 No mailbox with NEWDATA bit = 1 #0 1 Mailbox(es) with NEWDATA bit = 1 #1 BCR Bit Configuration Register 0x844 32 read-write 0x00000000 0xFFFFFFFF TSEG1 Time Segment 1 Control 28 31 read-write 0000 Setting prohibited #0000 0001 Setting prohibited #0001 0010 Setting prohibited #0010 0011 4 Tq #0011 0100 5 Tq #0100 0101 6 Tq #0101 0110 7 Tq #0110 0111 8 Tq #0111 1000 9 Tq #1000 1001 10 Tq #1001 1010 11 Tq #1010 1011 12 Tq #1011 1100 13 Tq #1100 1101 14 Tq #1101 1110 15 Tq #1110 1111 16 Tq #1111 BRP Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). 16 25 read-write SJW Resynchronization Jump Width Control 12 13 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 TSEG2 Time Segment 2 Control 8 10 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 CCLKS CAN Clock Source Selection 0 0 read-write 0 PCLK (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock) #1 RFCR Receive FIFO Control Register 0x848 8 read-write 0x80 0xFF RFEST Receive FIFO Empty Status Flag 7 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFWST Receive FIFO Buffer Warning Status Flag 6 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFFST Receive FIFO Full Status Flag 5 5 read-only 0 Receive FIFO is not full #0 1 Receive FIFO is full (4 unread messages) #1 RFMLF Receive FIFO Message Lost Flag 4 4 read-write 0 No receive FIFO message lost has occurred #0 1 Receive FIFO message lost has occurred #1 RFUST Receive FIFO Unread Message Number Status 1 3 read-only 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 others Setting prohibited true RFE Receive FIFO Enable 0 0 read-write 0 Receive FIFO disabled #0 1 Receive FIFO enabled #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only 0x00 0x00 RFPCR The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. 0 7 write-only TFCR Transmit FIFO Control Register 0x84A 8 read-write 0x80 0xFF TFEST Transmit FIFO Empty Status 7 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFFST Transmit FIFO Full Status 6 6 read-only 0 Transmit FIFO is not full #0 1 Transmit FIFO is full (4 unsent messages) #1 TFUST Transmit FIFO Unsent Message Number Status 1 3 read-only 000 No unsent message #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unsent messages #011 100 4 unsent messages #100 others Setting prohibited true TFE Transmit FIFO Enable 0 0 read-write 0 Transmit FIFO disabled #0 1 Transmit FIFO enabled #1 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only 0x00 0x00 TFPCR The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. 0 7 write-only EIER Error Interrupt Enable Register 0x84C 8 read-write 0x00 0xFF BLIE Bus Lock Interrupt Enable 7 7 read-write 0 Bus lock interrupt disabled #0 1 Bus lock interrupt enabled #1 OLIE Overload Frame Transmit Interrupt Enable 6 6 read-write 0 Overload frame transmit interrupt disabled #0 1 Overload frame transmit interrupt enabled #1 ORIE Overrun Interrupt Enable 5 5 read-write 0 Receive overrun interrupt disabled #0 1 Receive overrun interrupt enabled #1 BORIE Bus-Off Recovery Interrupt Enable 4 4 read-write 0 Bus-off recovery interrupt disabled #0 1 Bus-off recovery interrupt enabled #1 BOEIE Bus-Off Entry Interrupt Enable 3 3 read-write 0 Bus-off entry interrupt disabled #0 1 Bus-off entry interrupt enabled #1 EPIE Error-Passive Interrupt Enable 2 2 read-write 0 Error-passive interrupt disabled #0 1 Error-passive interrupt enabled #1 EWIE Error-Warning Interrupt Enable 1 1 read-write 0 Error-warning interrupt disabled #0 1 Error-warning interrupt enabled #1 BEIE Bus Error Interrupt Enable 0 0 read-write 0 Bus error interrupt disabled #0 1 Bus error interrupt enabled #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write 0x00 0xFF BLIF Bus Lock Detect Flag 7 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 OLIF Overload Frame Transmission Detect Flag 6 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 ORIF Receive Overrun Detect Flag 5 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 BORIF Bus-Off Recovery Detect Flag 4 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 BOEIF Bus-Off Entry Detect Flag 3 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 EPIF Error-Passive Detect Flag 2 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 EWIF Error-Warning Detect Flag 1 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 BEIF Bus Error Detect Flag 0 0 read-write 0 No bus error detected #0 1 Bus error detected #1 RECR Receive Error Count Register 0x84E 8 read-only 0x00 0xFF RECR Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception. 0 7 read-only TECR Transmit Error Count Register 0x84F 8 read-only 0x00 0xFF TECR Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission. 0 7 read-only ECSR Error Code Store Register 0x850 8 read-write 0x00 0xFF EDPM Error Display Mode Select 7 7 read-write 0 Output of first detected error code #0 1 Output of accumulated error code #1 ADEF ACK Delimiter Error Flag 6 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 BE0F Bit Error (dominant) Flag 5 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 BE1F Bit Error (recessive) Flag 4 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 CEF CRC Error Flag 3 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 AEF ACK Error Flag 2 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 FEF Form Error Flag 1 1 read-write 0 No form error detected #0 1 Form error detected #1 SEF Stuff Error Flag 0 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 CSSR Channel Search Support Register 0x851 8 read-write 0x00 0x00 CSSR When the value for the channel search is input, the channel number is output to MSSR. 0 7 read-write MSSR Mailbox Search Status Register 0x852 8 read-only 0x80 0xFF SEST Search Result Status 7 7 read-only 0 Search result found #0 1 No search result #1 MBNST Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. 0 4 read-only MSMR Mailbox Search Mode Register 0x853 8 read-write 0x00 0xFF MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 TSR Time Stamp Register 0x854 16 read-only 0x0000 0xFFFF TSR Free-running counter value for the time stamp function 0 15 read-only AFSR Acceptance Filter Support Register 0x856 16 read-write 0x0000 0x0000 AFSR After the standard ID of a received message is written, the value converted for data table search can be read. 0 15 read-write TCR Test Control Register 0x858 8 read-write 0x00 0xFF TSTM CAN Test Mode Select 1 2 read-write 00 Other than CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 TSTE CAN Test Mode Enable 0 0 read-write 0 CAN test mode disabled #0 1 CAN test mode enabled #1 CAN1 CAN1 Module 0x40051000 PDC Parallel Data Capture Unit 0x40094000 0x00 28 registers PCCR0 PDC Control Register 0 0x000 32 read-write 0x00000000 0xFFFFFFFF EDS Endian Select 14 14 read-write 0 Little endian #0 1 Big endian #1 PCKDIV PCKO Frequency Division Ratio Select 11 13 read-write 000 PCKO/2 #000 001 PCKO/4 #001 010 PCKO/6 #010 011 PCKO/8 #011 100 PCKO/10 #100 101 PCKO/12 #101 110 PCKO/14 #110 111 PCKO/16 #111 PCKOE PCKO Output Enable 10 10 read-write 0 PCKO output is disabled (fixed to the high level) #0 1 PCKO output is enabled. #1 HERIE Horizontal Byte Number Setting Error Interrupt Enable 9 9 read-write 0 Generation of horizontal byte number setting error interrupt requests is disabled. #0 1 Generation of horizontal byte number setting error interrupt requests is enabled. #1 VERIE Vertical Line Number Setting Error Interrupt Enable 8 8 read-write 0 Generation of vertical line number setting error interrupt requests is disabled. #0 1 Generation of vertical line number setting error interrupt requests is enabled. #1 UDRIE Underrun Interrupt Enable 7 7 read-write 0 Generation of underrun interrupt requests is disabled. #0 1 Generation of underrun interrupt requests is enabled. #1 OVIE Overrun Interrupt Enable 6 6 read-write 0 Generation of overrun interrupt requests is disabled. #0 1 Generation of overrun interrupt requests is enabled. #1 FEIE Frame End Interrupt Enable 5 5 read-write 0 Generation of frame end interrupt requests is disabled. #0 1 Generation of frame end interrupt requests is enabled. #1 DFIE Receive Data Ready Interrupt Enable 4 4 read-write 0 Generation of receive data ready interrupt requests is disabled. #0 1 Generation of receive data ready interrupt requests is enabled. #1 PRST PDC Reset 3 3 write-only 0 PDC reset is not applied. #0 1 PDC is reset. #1 HPS HSYNC Signal Polarity Select 2 2 read-write 0 HSYNC signal is active high. #0 1 HSYNC signal is active low. #1 VPS VSYNC Signal Polarity Select 1 1 read-write 0 VSYNC signal is active high. #0 1 VSYNC signal is active low. #1 PCKE Channel 0 GTCNT Count Clear 0 0 read-write 0 Operations for reception are stopped. #0 1 Operations for reception are ongoing. #1 PCCR1 PDC Control Register 1 0x004 32 read-write 0x00000000 0xFFFFFFFF PCE PDC Operation Enable 0 0 read-write 0 Operations for reception are disabled. #0 1 Operations for reception are enabled. #1 PCSR PDC Status Register 0x008 32 read-write 0x00000002 0xFFFFFFFF HERF Horizontal Byte Number Setting Error Flag 6 6 read-write zeroToClear modify 0 Horizontal byte number setting error has not been generated. #0 1 Horizontal byte number setting error has been generated. #1 VERF Vertical Line Number Setting Error Flag 5 5 read-write zeroToClear modify 0 Vertical line number setting error has not been generated. #0 1 Vertical line number setting error has been generated. #1 UDRF Underrun Flag 4 4 read-write zeroToClear modify 0 Underrun has not been generated. #0 1 Underrun has been generated. #1 OVRF Overrun Flag 3 3 read-write zeroToClear modify 0 FIFO overrun has not been generated. #0 1 FIFO overrun has been generated. #1 FEF Frame End Flag 2 2 read-write zeroToClear modify 0 Frame end has not been generated. #0 1 Frame end has been generated. #1 FEMPF FIFO Empty Flag 1 1 read-only 0 FIFO is not empty. #0 1 FIFO is empty. #1 FBSY Frame Busy Flag 0 0 read-only 0 Operations for reception are stopped. #0 1 Operations for reception are ongoing. #1 PCMONR PDC Pin Monitor Register 0x00C 32 read-only 0x00000000 0xFFFFFFFF HSYNC HSYNC Signal Status Flag 1 1 read-only 0 HSYNC signal is at the low level. #0 1 HSYNC signal is at the high level. #1 VSYNC VSYNC Signal Status Flag 0 0 read-only 0 VSYNC signal is at the low level. #0 1 VSYNC signal is at the high level. #1 PCDR PDC Receive Data Register 0x010 32 read-only 0x00000000 0xFFFFFFFF PCDR The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time. 0 31 read-only VCR Vertical Capture Register 0x014 32 read-write 0x00000000 0xFFFFFFFF VSZ Vertical Capture Size Number of lines to be captured. 16 27 read-write VST Vertical Capture Start Line PositionNumber of the line where capture is to start. 0 11 read-write HCR Horizontal Capture Register 0x018 32 read-write 0x00000000 0xFFFFFFFF HSZ Horizontal Capture Size Number of bytes to capture horizontally. 16 27 read-write HST Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start. 0 11 read-write QSPI Quad-SPI 0x64000000 0x00 28 registers 0x20 12 registers 0x30 8 registers 0x4C 4 registers 0x800 12 registers SFMSMD Transfer Mode Control Register 0x000 32 read-write 0x00000000 0xFFFFFFFF SFMCCE Read instruction code selection. 15 15 read-write 0 Default instruction code set for each instruction #0 1 Instruction code written in the SFMSIC register #1 SFMOSW Setup time adjustment for serial transmission 11 11 read-write 0 Does not extend the low-level width of SCK at transmission time #0 1 Extends the low-level width of SCK by 1*PCLKA at transmission time #1 SFMOHW Hold time adjustment for serial transmission 10 10 read-write 0 Does not extend the high-level width of SCK at transmission time #0 1 Extends the high-level width of SCK by 1*PCLKA at transmission time #1 SFMOEX Extension of the I/O buffer output enable signal for the serial interface 9 9 read-write 0 Does not extend the output enable signal #0 1 Extends the output enable signal by 1*QSPCLK #1 SFMMD3 SPI mode selection. An initial value is determined by input to CFGMD3. 8 8 read-write 0 SPI mode 0 #0 1 SPI mode 3 #1 SFMPAE Selection of the function for stopping prefetch at locations other than on byte boundaries 7 7 read-write 0 Disables prefetch stopping at locations other than on byte boundaries #0 1 Enables prefetch stopping at locations other than on byte boundaries #1 SFMPFE Selection of the prefetch function 6 6 read-write 0 Disables prefetch #0 1 Enables prefetch #1 SFMSE Selection of the prefetch function 4 5 read-write 00 Does not extend QSSL #00 01 Extends QSSL by 33*QSPCLK #01 10 Extends QSSL by 129*QSPCLK #10 11 Extends QSSL infinitely #11 SFMRM Serial interface read mode selection 0 2 read-write 000 Standard Read #000 001 Fast Read #001 010 Fast Read Dual Output #010 011 Fast Read Dual I/O #011 100 Fast Read Quad Output #100 101 Fast Read Quad I/O #101 110 Setting prohibited #110 111 Setting prohibited #111 SFMSSC Chip Selection Control Register 0x004 32 read-write 0x00000037 0xFFFFFFFF SFMSLD QSSL signal output timing selection 5 5 read-write 0 Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK #0 1 Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK #1 SFMSHD QSSL signal release timing selection 4 4 read-write 0 Releases QSSL 0.5*SCK after the last rising edge of QSPCLK #0 1 Releases QSSL 1.5*SCK after the last rising edge of QSPCLK #1 SFMSW Selection of a minimum high-level width of the QSSL signal 0 3 read-write 0000 1 x QSPCLK #0000 0001 2 x QSPCLK #0001 0010 3 x QSPCLK #0010 0011 4 x QSPCLK #0011 0100 5 x QSPCLK #0100 0101 6 x QSPCLK #0101 0110 7 x QSPCLK #0110 0111 8 x QSPCLK #0111 1000 9 x QSPCLK #1000 1001 10 x QSPCLK #1001 1010 11 x QSPCLK #1010 1011 12 x QSPCLK #1011 1100 13 x QSPCLK #1100 1101 14 x QSPCLK #1101 1110 15 x QSPCLK #1110 1111 16 x QSPCLK #1111 SFMSKC Clock Control Register 0x008 32 read-write 0x00000008 0xFFFFFFFF SFMDTY Selection of a duty ratio correction function for the SCK signal 5 5 read-write 0 Serial interface reference cycle selection (* Pay attention to the irregularity.) #0 1 Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number) #1 SFMDV Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. 0 4 read-write 10000 18 x PCLKA #10000 10001 20 x PCLKA #10001 10010 22 x PCLKA #10010 10011 24 x PCLKA #10011 10100 26 x PCLKA #10100 10101 28 x PCLKA #10101 10110 30 x PCLKA #10110 10111 32 x PCLKA #10111 11000 34 x PCLKA #11000 11001 36 x PCLKA #11001 11010 38 x PCLKA #11010 11011 40 x PCLKA #11011 11100 42 x PCLKA #11100 11101 44 x PCLKA #11101 11110 46 x PCLKA #11110 11111 48 x PCLKA #11111 others ( SFMDV + 2 ) x PCLKA true SFMSST Status Register 0x00C 32 read-only 0x00000080 0xFFFFFFFF PFOFF Prefetch function operation state 7 7 read-only 0 The prefetch function is operating. #0 1 The prefetch function is not enabled or is not operating. #1 PFFUL Prefetch buffer state 6 6 read-only 0 The prefetch buffer has a free space. #0 1 The prefetch buffer is full. #1 PFCNT Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.) 0 4 read-only 00000 Nodata has been prefetched. #00000 others Data of (PFCNT) bytes hs been prefetched. true SFMCOM Communication Port Register 0x010 32 read-write 0x00000000 0xFFFFFF00 SFMD Port for direct communication with the SPI bus.Input/output to and from this port is converted to an SPI bus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode. 0 7 read-write SFMCMD Communication Mode Control Register 0x014 32 read-write 0x00000000 0xFFFFFFFF DCOM Selection of a mode of communication with the SPI bus 0 0 read-write 0 ROM access mode #0 1 Direct communication mode #1 SFMCST Communication Status Register 0x018 32 read-write 0x00000000 0xFFFFFFFF EROMR Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored. 7 7 read-only 0 ROM access is not detected in direct communication mode #0 1 ROM access is detected in direct communication mode #1 COMBSY SPI bus cycle completion state in direct communication 0 0 read-only 0 There is no serial transfer being processed. #0 1 There is a serial transfer being processed. #1 SFMSIC Instruction Code Register 0x020 32 read-write 0x00000000 0xFFFFFFFF SFMCIC Serial ROM instruction code to substitute 0 7 read-write SFMSAC Address Mode Control Register 0x024 32 read-write 0x00000002 0xFFFFFFFF SFM4BC Selection of a default instruction code, when Serial Interface address width is selected 4 bytes. 4 4 read-write 0 Does not use 4 Byte address read Instruction code #0 1 Use 4 Byte address read Instruction code #1 SFMAS Selection the number of address bits of the serial interface 0 1 read-write 00 1byte #00 01 2bytes #01 10 3bytes #10 11 4 bytes #11 SFMSDC Dummy Cycle Control Register 0x028 32 read-write 0x0000FF00 0xFFFFFFFF SFMXD Mode data for serial ROM. (Control XIP mode) 8 15 read-write 0 XIP mode is prohibited #0 1 XIP mode is permitted #1 SFMXEN XIP mode permission 7 7 read-write 0 XIP mode is prohibited #0 1 XIP mode is permitted #1 SFMXST XIP mode status 6 6 read-only 0 Normal (non-XIP) mode is operating #0 1 XIP mode is operating #1 SFMDN Selection of the number of dummy cycles of Fast Read instructions 0 3 read-write 0000 Default dummy cycles of each instruction. #0000 others ( SFMDN + 2 ) x SCK true SFMSPC SPI Protocol Control Register 0x030 32 read-write 0x00000010 0xFFFFFFFF SFMSDE Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected. 4 4 read-write 0 Does not allocate minimum switch time #0 1 Allocate the minimum switch time equivalent to 1*QSPXLK #1 SFMSPI Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately. 0 1 read-write 00 Extended SPI protocol #00 01 Dual SPI protocol #01 10 Quad SPI protocol #10 11 Setting prohibited. #11 SFMPMD Port Control Register 0x034 32 read-write 0x00000000 0xFFFFFFFF SFMWPL Specify level of WP pin 2 2 read-write 0 Low level #0 1 High level #1 SFMCNT1 External QSPI Address Register 1 0x804 32 read-write 0x00000000 0xFFFFFFFF QSPI_EXT BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. 26 31 read-write MMF Memory Mirror Function 0x40001000 0x00 8 registers MMSFR MemMirror Special Function Register 0x00 32 read-write 0x00000000 0xFFFFFFFF KEY MMSFR Key Code 24 31 write-only 0xDB Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB. 0xDB others Writing to the MEMMIRADDR bits are invalid. true MEMMIRADDR Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0. 7 22 read-write MMEN MemMirror Enable Register 0x04 32 read-write 0x00000000 0xFFFFFFFF KEY MMEN Key Code 24 31 write-only 0xDB Writing to the EN bit is valid, when the KEY bits are written 0xDB. 0xDB others Writing to the EN bit is invalid. true EN Memory Mirror Function Enable 0 0 read-write 1 Memory Mirror Function is enabled. #1 0 Memory Mirror Function is disabled. #0 DMAC0 Direct memory access controller 0 0x40005000 0x00 14 registers 0x10 2 registers 0x13 3 registers 0x18 7 registers DMSAR DMA Source Address Register 0x00 32 read-write 0x00000000 0xFFFFFFFF DMSAR Specifies the transfer source start address. 0 31 read-write DMDAR DMA Destination Address Register 0x04 32 read-write 0x00000000 0xFFFFFFFF DMDAR Specifies the transfer destination start address. 0 31 read-write DMCRA DMA Transfer Count Register 0x08 32 read-write 0x00000000 0xFFFFFFFF DMCRAH Upper bits of transfer count 16 25 read-write DMCRAL Lower bits of transfer count 0 15 read-write DMCRB DMA Block Transfer Count Register 0x0C 16 read-write 0x0000 0xFFFF DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write 0000 65,536 blocks #0000 others DMCRB blocks true DMTMD DMA Transfer Mode Register 0x10 16 read-write 0x0000 0xFFFF MD Transfer Mode Select 14 15 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 DTS Repeat Area Select 12 13 read-write 00 Specify destination as the repeat area or block area #00 01 Specify source as the repeat area or block area #01 10 Do not specify repeat area or block area #10 11 Setting prohibited #11 SZ Transfer Data Size Select 8 9 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts from peripheral modules or external interrupt input pins #01 others Setting prohibited true DMINT DMA Interrupt Setting Register 0x13 8 read-write 0x00 0xFF DTIE Transfer End Interrupt Enable 4 4 read-write 0 Disable #0 1 Enable. #1 ESIE Transfer Escape End Interrupt Enable 3 3 read-write 0 Disable #0 1 Enable. #1 RPTIE Repeat Size End Interrupt Enable 2 2 read-write 0 Disable #0 1 Enable. #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 Disable #0 1 Enable. #1 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 Disable #0 1 Enable. #1 DMAMD DMA Address Mode Register 0x14 16 read-write 0x0000 0xFFFF SM Source Address Update Mode 14 15 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 12 read-write DM Destination Address Update Mode 6 7 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DMOFR DMA Offset Register 0x18 32 read-write 0x00000000 0xFFFFFFFF DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMCNT DMA Transfer Enable Register 0x1C 8 read-write 0x00 0xFF DTE DMA Transfer Enable 0 0 read-write modify 0 Disable #0 1 Enable #1 DMREQ DMA Software Start Register 0x1D 8 read-write 0x00 0xFF CLRS DMA Software Start Bit Auto Clear Select 4 4 read-write 0 Clear SWREQ bit after DMA transfer is started by software #0 1 Do not clear SWREQ bit after DMA transfer is started by software #1 SWREQ DMA Software Start 0 0 read-write modify 0 Do not request DMA transfer #0 1 Request DMA transfer. #1 DMSTS DMAC Module Activation Register 0x1E 8 read-write 0x00 0xFF ACT DMA Active Flag 7 7 read-only 0 DMAC operation is suspended. #0 1 DMAC is operating. #1 DTIF Transfer End Interrupt Flag 4 4 read-write zeroToClear modify 0 No interrupt occurred #0 1 Interrupt occurred. #1 ESIF Transfer Escape End Interrupt Flag 0 0 read-write zeroToClear modify 0 A transfer escape end interrupt has not been generated. #0 1 A transfer escape end interrupt has been generated. #1 DMAC1 Direct memory access controller 1 0x40005040 DMAC2 Direct memory access controller 2 0x40005080 DMAC3 Direct memory access controller 3 0x400050C0 DMAC4 Direct memory access controller 4 0x40005100 DMAC5 Direct memory access controller 5 0x40005140 DMAC6 Direct memory access controller 6 0x40005180 DMAC7 Direct memory access controller 7 0x400051C0 DMA DMAC Module Activation 0x40005200 0x00 1 registers DMAST DMA Module Activation Register 0x00 8 read-write 0x00 0xFF DMST DMAC Operation Enable 0 0 read-write 0 DMAC activation is disabled. #0 1 DMAC activation is enabled. #1 DTC Data Transfer Controller 0x40005400 0x00 1 registers 0x04 4 registers 0x0C 1 registers 0x0E 2 registers DTCCR DTC Control Register 0x00 8 read-write 0x08 0xFF RRS DTC Transfer Information Read Skip Enable. 4 4 read-write 0 Do not skip transfer information read #0 1 Skip transfer information read when vector numbers match #1 DTCVBR DTC Vector Base Register 0x04 32 read-write 0x00000000 0xFFFFFFFF DTCVBR DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. 0 31 read-write DTCST DTC Module Start Register 0x0C 8 read-write 0x00 0xFF DTCST DTC Module Start 0 0 read-write 0 DTC module stop #0 1 DTC module start #1 DTCSTS DTC Status Register 0x0E 16 read-only 0x0000 0xFFFF ACT DTC Active Flag 15 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 VECN DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) 0 7 read-only DBG Debug Function 0x4001B000 0x00 4 registers 0x10 4 registers 0x20 4 registers DBGSTR Debug Status Register 0x000 32 read-only 0x00000000 0xFFFFFFFF CDBGPWRUPACK Debug power-up acknowledge 29 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 CDBGPWRUPREQ Debug power-up request 28 28 read-only 0 OCD is not requesting debug power-up #0 1 OCD is requesting debug power-up #1 DBGSTOPCR Debug Stop Control Register 0x010 32 read-write 0x00000003 0xFFFFFFFF DBGSTOP_RECCR Mask bit for RAM ECC error reset/interrupt 25 25 read-write 0 Enable RAM ECC error reset/interrupt #0 1 Mask RAM ECC error reset/interrupt #1 DBGSTOP_RPER Mask bit for RAM parity error reset/interrupt 24 24 read-write 0 Enable RAM parity error reset/interrupt #0 1 Mask RAM parity error reset/interrupt #1 DBGSTOP_LVD b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask) 16 18 read-write DBGSTOP_WDT Mask bit for WDT reset/interrupt 1 1 read-write 0 Mask WDT reset/interrupt #0 1 Enable WDT reset #1 DBGSTOP_IWDT Mask bit for IWDT reset/interrupt 0 0 read-write 0 Mask IWDT reset/interrupt #0 1 Enable IWDT reset #1 TRACECTR Trace Control Register 0x020 32 read-write 0x00000000 0xFFFFFFFF ENETBFULL Enable bit for halt request by ETB full 31 31 read-write 0 ETB full does not cause CPU halt #0 1 ETB full cause CPU halt #1 TSN Temperature Sensor 0x4005D000 0x00 1 registers TSCR Temperature Sensor Control Register 0x00 8 read-write 0x00 0xFF TSEN Temperature Sensor Output Enable 7 7 read-write 0 Stops the temperature sensor. #0 1 Starts the temperature sensor. #1 TSOE Temperature Sensor Enable 4 4 read-write 0 Disables output from the temperature sensor to the 12-bit A/D converter. #0 1 Enables output from the temperature sensor to the 12-bit A/D converter. #1 ACMPHS0 High-Speed Analog Comparator 0 0x40085000 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0x10 1 registers CMPCTL Comparator Control Register 0x000 8 read-write 0x00 0xFF HCMPON Comparator operation control 7 7 read-write 0 Operation stopped (the comparator outputs a low-level signal) #0 1 Operation enabled (input to the comparator pins is enabled #1 CDFS Noise filter selection 5 6 read-write 00 Noise filter not used. #00 01 Noise filter sampling frequency is 2^3/PCLKB. #01 10 Noise filter sampling frequency is 2^4/PCLKB. #10 11 Noise filter sampling frequency is 2^5/PCLKB. #11 CEG Selection of valid edge (Edge selector) 3 4 read-write 00 No edge selection. #00 01 Rising edge selection. #01 10 Falling edge selection #10 11 Both-edge selection #11 CSTEN Interrupt Select 2 2 read-write 0 Output via the Edge selector #0 1 Direct output #1 COE Comparator output enable 1 1 read-write 0 Comparator output disabled (the output signal is low level). #0 1 Comparator output enabled #1 CINV Comparator output polarity selection 0 0 read-write 0 Comparator output not inverted #0 1 Comparator output inverted #1 CMPSEL0 Comparator Input Select Register 0x004 8 read-write 0x00 0xFF CMPSEL Comparator input selection 0 3 read-write 0000 No input #0000 0001 IVCMP0 selected #0001 0010 IVCMP1 selected #0010 0100 IVCMP2 selected #0100 1000 IVCMP3 selected #1000 others Setting prohibited true CMPSEL1 Comparator Reference Voltage Select Register 0x008 8 read-write 0x00 0xFF CRVS Reference voltage selection 0 3 read-write 0000 No reference voltage #0000 0001 IVREF0 selected #0001 0010 IVREF1 selected #0010 0100 IVREF2 selected #0100 1000 IVREF3 selected #1000 others Setting prohibited true CMPMON Comparator Output Monitor Register 0x00C 8 read-only 0x00 0xFF CMPMON Comparator output monitor 0 0 read-only 0 Comparator output Low #0 1 Comparator output High #1 CPIOC Comparator Output Control Register 0x010 8 read-write 0x00 0xFF VREFEN Internal Vref enable 7 7 read-write 0 Internal Vref disable #0 1 Internal Vref enable #1 CPOE Comparator output selection 0 0 read-write 0 VCOUT pin output of the comparator is disabled (the output signal is low level). #0 1 VCOUT pin output of the comparator is enabled #1 ACMPHS1 High-Speed Analog Comparator 1 0x40085100 0x00 1 registers 0x04 1 registers 0x08 1 registers 0x0C 1 registers 0x10 1 registers CMPCTL Comparator Control Register 0x000 8 read-write 0x00 0xFF HCMPON Comparator operation control 7 7 read-write 0 Operation stopped (the comparator outputs a low-level signal) #0 1 Operation enabled (input to the comparator pins is enabled #1 CDFS Noise filter selection 5 6 read-write 00 Noise filter not used. #00 01 Noise filter sampling frequency is 2^3/PCLKB. #01 10 Noise filter sampling frequency is 2^4/PCLKB. #10 11 Noise filter sampling frequency is 2^5/PCLKB. #11 CEG Selection of valid edge (Edge selector) 3 4 read-write 00 No edge selection. #00 01 Rising edge selection. #01 10 Falling edge selection #10 11 Both-edge selection #11 CSTEN Interrupt Select 2 2 read-write 0 Output via the Edge selector #0 1 Direct output #1 COE Comparator output enable 1 1 read-write 0 Comparator output disabled (the output signal is low level). #0 1 Comparator output enabled #1 CINV Comparator output polarity selection 0 0 read-write 0 Comparator output not inverted #0 1 Comparator output inverted #1 CMPSEL0 Comparator Input Select Register 0x004 8 read-write 0x00 0xFF CMPSEL Comparator input selection 0 3 read-write 0000 No input #0000 0001 IVCMP0 selected #0001 0010 IVCMP1 selected #0010 0100 IVCMP2 selected #0100 1000 IVCMP3 selected #1000 others Setting prohibited true CMPSEL1 Comparator Reference Voltage Select Register 0x008 8 read-write 0x00 0xFF CRVS Reference voltage selection 0 3 read-write 0000 No reference voltage #0000 0001 IVREF0 selected #0001 0010 IVREF1 selected #0010 0100 IVREF2 selected #0100 1000 IVREF3 selected #1000 others Setting prohibited true CMPMON Comparator Output Monitor Register 0x00C 8 read-only 0x00 0xFF CMPMON Comparator output monitor 0 0 read-only 0 Comparator output Low #0 1 Comparator output High #1 CPIOC Comparator Output Control Register 0x010 8 read-write 0x00 0xFF VREFEN Internal Vref enable 7 7 read-write 0 Internal Vref disable #0 1 Internal Vref enable #1 CPOE Comparator output selection 0 0 read-write 0 VCOUT pin output of the comparator is disabled (the output signal is low level). #0 1 VCOUT pin output of the comparator is enabled #1 ACMPHS2 High-Speed Analog Comparator 2 0x40085200 ACMPHS3 High-Speed Analog Comparator 3 0x40085300 ACMPHS4 High-Speed Analog Comparator 4 0x40085400 ACMPHS5 High-Speed Analog Comparator 5 0x40085500 ELC Event Link Controller 0x40041000 0x00 1 registers 0x02 4 registers 0x10 76 registers ELCR Event Link Controller Register 0x00 8 read-write 0x00 0xFF ELCON All Event Link Enable 7 7 read-write 0 Disable ELC function #0 1 Enable ELC function. #1 2 0x2 0,1 ELSEGR%s Event Link Software Event Generation Register %s 0x02 8 read-write 0x80 0xFF WI ELSEGR Register Write Disable 7 7 write-only 0 Enable writes to ELSEGR register #0 1 Disable writes to ELSEGR register. #1 WE SEG Bit Write Enable 6 6 read-write 0 Disable writes to SEG bit #0 1 Enable writes to SEG bit #1 SEG Software Event Generation 0 0 write-only 0 Normal operation #0 1 Generate a software event #1 19 0x4 0-18 ELSR%s Event Link Setting Register %s 0x10 16 read-write 0x0000 0xFFFF ELS Event Link Select 0 8 read-write 0x000 Event output to the corresponding peripheral module is disabled. 0x000 others Set the number for the event signal to be linked. true WDT Watchdog Timer 0x40044200 0x00 1 registers 0x02 5 registers 0x08 1 registers WDTRR WDT Refresh Register 0x00 8 read-write 0xFF 0xFF WDTRR WDTRR is an 8-bit register that refreshes the down-counter of the WDT. 0 7 read-write WDTCR WDT Control Register 0x02 16 read-write 0x33F3 0xFFFF RPSS Window Start Position Selection 12 13 read-write 00 25 percent #00 01 50 percent #01 10 75 percent #10 11 100 percent (window start position is not specified) #11 RPES Window End Position Selection 8 9 read-write 00 75 percent #00 01 50 percent #01 10 25 percent #10 11 0 percent (window end position is not specified) #11 CKS Clock Division Ratio Selection 4 7 read-write 0001 PCLK/4 #0001 0100 PCLK/64 #0100 1111 PCLK/128 #1111 0110 PCLK/512 #0110 0111 PCLK/2048 #0111 1000 PCLK/8192 #1000 others setting prohibited true TOPS Timeout Period Selection 0 1 read-write 00 1,024 cycles (03FFh) #00 01 4,096 cycles (0FFFh) #01 10 8,192 cycles (1FFFh) #10 11 16,384 cycles (3FFFh) #11 WDTSR WDT Status Register 0x04 16 read-write 0x0000 0xFFFF REFEF Refresh Error Flag 15 15 read-write zeroToClear modify 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 14 read-write zeroToClear modify 0 No underflow occurred #0 1 Underflow occurred #1 CNTVAL Down-Counter ValueValue counted by the down-counter 0 13 read-only WDTRCR WDT Reset Control Register 0x06 8 read-write 0x80 0xFF RSTIRQS Reset Interrupt Request Selection 7 7 read-write 0 Non-maskable interrupt request or interrupt request output is enabled #0 1 Reset output is enabled. #1 WDTCSTPR WDT Count Stop Control Register 0x08 8 read-write 0x80 0xFF SLCSTP Sleep-Mode Count Stop Control 7 7 read-write 0 Count stop is disabled. #0 1 Count is stopped at a transition to sleep mode. #1 IWDT Independent Watchdog Timer 0x40044400 0x00 1 registers 0x04 2 registers IWDTRR IWDT Refresh Register 0x00 8 read-write 0xFF 0xFF IWDTRR The counter is refreshed by writing 0x00 and then writing 0xFF to this register. 0 7 read-write IWDTSR IWDT Status Register 0x04 16 read-write 0x0000 0xFFFF REFEF Refresh Error Flag 15 15 read-write zeroToClear modify 0 Refresh error not occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 14 read-write zeroToClear modify 0 Underflow not occurred #0 1 Underflow occurred #1 CNTVAL Counter ValueValue counted by the counter 0 13 read-only KINT Key Interrupt Function 0x40080000 0x00 1 registers 0x04 1 registers 0x08 1 registers KRCTL KEY Return Control Register 0x00 8 read-write 0x00 0xFF KRMD Usage of Key Interrupt Flags(KR0 to KR7) 7 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags. #1 KREG Detection Edge Selection (KRF0 to KRF7) 0 0 read-write 0 Falling edge #0 1 Rising edge #1 KRF KEY Return Flag Register 0x04 8 read-write 0x00 0xFF zeroToClear modify KRF7 Key interrupt flag 7 7 7 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF6 Key interrupt flag 6 6 6 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF5 Key interrupt flag 5 5 5 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF4 Key interrupt flag 4 4 4 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF3 Key interrupt flag 3 3 3 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF2 Key interrupt flag 2 2 2 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF1 Key interrupt flag 1 1 1 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF0 Key interrupt flag 0 0 0 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRM KEY Return Mode Register 0x08 8 read-write 0x00 0xFF KRM7 Key interrupt mode control 7 7 7 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM6 Key interrupt mode control 6 6 6 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM5 Key interrupt mode control 5 5 5 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM4 Key interrupt mode control 4 4 4 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM3 Key interrupt mode control 3 3 3 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM2 Key interrupt mode control 2 2 2 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM1 Key interrupt mode control 1 1 1 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM0 Key interrupt mode control 0 0 0 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 DOC Data Operation Circuit 0x40054100 0x00 1 registers 0x02 4 registers DOCR DOC Control Register 0x00 8 read-write 0x00 0xFF DOPCFCL DOPCF Clear 6 6 read-write 0 Maintains the DOPCF flag state. #0 1 Clears the DOPCF flag. #1 DOPCF Data Operation Circuit FlagIndicates the result of an operation. 5 5 read-only DCSEL Detection Condition Select 2 2 read-write 0 DOPCF is set when data mismatch is detected. #0 1 DOPCF is set when data match is detected. #1 OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 DODIR DOC Data Input Register 0x02 16 read-write 0x0000 0xFFFF DODIR 16-bit read-write register in which 16-bit data for use in the operations are stored. 0 15 read-write DODSR DOC Data Setting Register 0x04 16 read-write 0x0000 0xFFFF DODSR This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. 0 15 read-write CAC Clock Frequency Accuracy Measurement Circuit 0x40044600 0x00 5 registers 0x06 6 registers CACR0 CAC Control Register 0 0x00 8 read-write 0x00 0xFF CFME Clock Frequency Measurement Enable. 0 0 read-write 0 Disable #0 1 Enable #1 CACR1 CAC Control Register 1 0x01 8 read-write 0x00 0xFF EDGES Valid Edge Select 6 7 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 TCSS Measurement Target Clock Frequency Division Ratio Select 4 5 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 FMCS Measurement Target Clock Select 1 3 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 CACREFE CACREF Pin Input Enable 0 0 read-write 0 Disable #0 1 Enable #1 CACR2 CAC Control Register 2 0x02 8 read-write 0x00 0xFF DFS Digital Filter Selection 6 7 read-write 00 Digital filtering is disabled. #00 01 The sampling clock for the digital filter is the frequency measuring clock. #01 10 The sampling clock for the digital filter is the frequency measuring clock divided by 4. #10 11 The sampling clock for the digital filter is the frequency measuring clock divided by 16. #11 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 5 read-write 00 1/32 clock #00 01 1/128 clock #01 10 1/1024 clock #10 11 1/8192 clock #11 RSCS Measurement Reference Clock Select 1 3 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 RPS Reference Signal Select 0 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 CAICR CAC Interrupt Control Register 0x03 8 read-write 0x00 0xFF OVFFCL OVFF Clear 6 6 write-only 0 No effect on operations #0 1 Clears the OVFF flag #1 MENDFCL MENDF Clear 5 5 write-only 0 No effect on operations #0 1 Clears the MENDF flag #1 FERRFCL FERRF Clear 4 4 write-only 0 No effect on operations #0 1 Clears the FERRF flag #1 OVFIE Overflow Interrupt Request Enable 2 2 read-write 0 Disable #0 1 Enable #1 MENDIE Measurement End Interrupt Request Enable 1 1 read-write 0 Disable #0 1 Enable #1 FERRIE Frequency Error Interrupt Request Enable 0 0 read-write 0 Disable #0 1 Enable #1 CASTR CAC Status Register 0x04 8 read-only 0x00 0xFF OVFF Counter Overflow Flag 2 2 read-only 0 The counter has not overflowed. #0 1 The counter has overflowed. #1 MENDF Measurement End Flag 1 1 read-only 0 Measurement is in progress. #0 1 Measurement has ended. #1 FERRF Frequency Error Flag 0 0 read-only 0 The clock frequency is within the range corresponding to the settings. #0 1 The clock frequency has deviated beyond the range corresponding to the settings (frequency error). #1 CAULVR CAC Upper-Limit Value Setting Register 0x06 16 read-write 0x0000 0xFFFF CAULVR CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. 0 15 read-write CALLVR CAC Lower-Limit Value Setting Register 0x08 16 read-write 0x0000 0xFFFF CALLVR CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. 0 15 read-write CACNTBR CAC Counter Buffer Register 0x0A 16 read-only 0x0000 0xFFFF CACNTBR CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input 0 15 read-only