7382 lines
269 KiB
XML
7382 lines
269 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
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<vendorID>ESPRESSIF</vendorID>
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<name>ESP32-C6-LP</name>
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<series>ESP32 Series</series>
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<version>1</version>
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<description>32-bit RISC-V MCU</description>
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<licenseText>
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Copyright 2023 Espressif Systems (Shanghai) PTE LTD
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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</licenseText>
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<cpu>
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<name>RV32IMAC</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>32</addressUnitBits>
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<width>32</width>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>LP_I2C</name>
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<description>Low-power I2C (Inter-Integrated Circuit) Controller</description>
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<groupName>I2C</groupName>
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<baseAddress>0x600B1800</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x88</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>LP_I2C</name>
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<value>17</value>
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</interrupt>
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<registers>
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<register>
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<name>SCL_LOW_PERIOD</name>
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<description>Configures the low level width of the SCL
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Clock</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<fields>
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<field>
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<name>SCL_LOW_PERIOD</name>
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<description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>9</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CTR</name>
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<description>Transmission setting</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<resetValue>0x00000208</resetValue>
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<fields>
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<field>
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<name>SDA_FORCE_OUT</name>
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<description>1: direct output, 0: open drain output.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>SCL_FORCE_OUT</name>
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<description>1: direct output, 0: open drain output.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>SAMPLE_SCL_LEVEL</name>
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<description>This register is used to select the sample mode.
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1: sample SDA data on the SCL low level.
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0: sample SDA data on the SCL high level.</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RX_FULL_ACK_LEVEL</name>
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<description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TRANS_START</name>
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<description>Set this bit to start sending the data in txfifo.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>TX_LSB_FIRST</name>
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<description>This bit is used to control the sending mode for data needing to be sent.
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1: send data from the least significant bit,
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0: send data from the most significant bit.</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RX_LSB_FIRST</name>
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<description>This bit is used to control the storage mode for received data.
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1: receive data from the least significant bit,
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0: receive data from the most significant bit.</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>CLK_EN</name>
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<description>Reserved</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>ARBITRATION_EN</name>
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<description>This is the enable bit for arbitration_lost.</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>FSM_RST</name>
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<description>This register is used to reset the scl FMS.</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>CONF_UPGATE</name>
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<description>synchronization bit</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>SR</name>
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<description>Describe I2C work status.</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<fields>
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<field>
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<name>RESP_REC</name>
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<description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>ARB_LOST</name>
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<description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>BUS_BUSY</name>
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<description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>RXFIFO_CNT</name>
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<description>This field represents the amount of data needed to be sent.</description>
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<bitOffset>8</bitOffset>
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<bitWidth>5</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TXFIFO_CNT</name>
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<description>This field stores the amount of received data in RAM.</description>
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<bitOffset>18</bitOffset>
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<bitWidth>5</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>SCL_MAIN_STATE_LAST</name>
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<description>This field indicates the states of the I2C module state machine.
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0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
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<bitOffset>24</bitOffset>
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<bitWidth>3</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>SCL_STATE_LAST</name>
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<description>This field indicates the states of the state machine used to produce SCL.
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0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
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<bitOffset>28</bitOffset>
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<bitWidth>3</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>TO</name>
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<description>Setting time out control for receiving data.</description>
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<addressOffset>0xC</addressOffset>
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<size>0x20</size>
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<resetValue>0x00000010</resetValue>
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<fields>
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<field>
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<name>TIME_OUT_VALUE</name>
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<description>This register is used to configure the timeout for receiving a data bit in APB
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clock cycles.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>5</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TIME_OUT_EN</name>
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<description>This is the enable bit for time out control.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FIFO_ST</name>
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<description>FIFO status register.</description>
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<addressOffset>0x14</addressOffset>
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<size>0x20</size>
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<fields>
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<field>
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<name>RXFIFO_RADDR</name>
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<description>This is the offset address of the APB reading from rxfifo</description>
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<bitOffset>0</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>RXFIFO_WADDR</name>
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<description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TXFIFO_RADDR</name>
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<description>This is the offset address of i2c module reading from txfifo.</description>
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<bitOffset>10</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TXFIFO_WADDR</name>
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<description>This is the offset address of APB bus writing to txfifo.</description>
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<bitOffset>15</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FIFO_CONF</name>
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<description>FIFO configuration register.</description>
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<addressOffset>0x18</addressOffset>
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<size>0x20</size>
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<resetValue>0x00004046</resetValue>
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<fields>
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<field>
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<name>RXFIFO_WM_THRHD</name>
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<description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TXFIFO_WM_THRHD</name>
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<description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>NONFIFO_EN</name>
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<description>Set this bit to enable APB nonfifo access.</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RX_FIFO_RST</name>
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<description>Set this bit to reset rx-fifo.</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TX_FIFO_RST</name>
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<description>Set this bit to reset tx-fifo.</description>
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<bitOffset>13</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>FIFO_PRT_EN</name>
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<description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>DATA</name>
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<description>Rx FIFO read data.</description>
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<addressOffset>0x1C</addressOffset>
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<size>0x20</size>
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<fields>
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<field>
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<name>FIFO_RDATA</name>
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<description>The value of rx FIFO read data.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>INT_RAW</name>
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<description>Raw interrupt status</description>
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<addressOffset>0x20</addressOffset>
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<size>0x20</size>
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<resetValue>0x00000002</resetValue>
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<fields>
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<field>
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<name>RXFIFO_WM_INT_RAW</name>
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<description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TXFIFO_WM_INT_RAW</name>
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<description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>RXFIFO_OVF_INT_RAW</name>
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<description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>END_DETECT_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>BYTE_TRANS_DONE_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>ARBITRATION_LOST_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>MST_TXFIFO_UDF_INT_RAW</name>
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<description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TRANS_COMPLETE_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TIME_OUT_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>TRANS_START_INT_RAW</name>
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<description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
|
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</field>
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<field>
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<name>NACK_INT_RAW</name>
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<description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
|
|
<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_OVF_INT_RAW</name>
|
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<description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
|
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</field>
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<field>
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<name>RXFIFO_UDF_INT_RAW</name>
|
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<description>The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt.</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
|
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<access>read-only</access>
|
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</field>
|
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<field>
|
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<name>SCL_ST_TO_INT_RAW</name>
|
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<description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
|
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<bitOffset>13</bitOffset>
|
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<bitWidth>1</bitWidth>
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<access>read-only</access>
|
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</field>
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<field>
|
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<name>SCL_MAIN_ST_TO_INT_RAW</name>
|
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<description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
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|
<access>read-only</access>
|
|
</field>
|
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<field>
|
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<name>DET_START_INT_RAW</name>
|
|
<description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>Interrupt clear bits</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_WM_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_WM_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>END_DETECT_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BYTE_TRANS_DONE_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBITRATION_LOST_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MST_TXFIFO_UDF_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_COMPLETE_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIME_OUT_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_START_INT_CLR</name>
|
|
<description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_OVF_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_UDF_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_RXFIFO_UDF_INT interrupt.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_ST_TO_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_MAIN_ST_TO_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DET_START_INT_CLR</name>
|
|
<description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ENA</name>
|
|
<description>Interrupt enable bits</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_WM_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_WM_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>END_DETECT_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYTE_TRANS_DONE_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBITRATION_LOST_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MST_TXFIFO_UDF_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_COMPLETE_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIME_OUT_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_START_INT_ENA</name>
|
|
<description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_OVF_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_UDF_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_ST_TO_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_MAIN_ST_TO_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DET_START_INT_ENA</name>
|
|
<description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_STATUS</name>
|
|
<description>Status of captured I2C communication events</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_WM_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_WM_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>END_DETECT_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BYTE_TRANS_DONE_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBITRATION_LOST_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MST_TXFIFO_UDF_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_COMPLETE_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIME_OUT_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS_START_INT_ST</name>
|
|
<description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_OVF_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_UDF_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_ST_TO_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_MAIN_ST_TO_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DET_START_INT_ST</name>
|
|
<description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDA_HOLD</name>
|
|
<description>Configures the hold time after a negative SCL edge.</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure the time to hold the data after the negative
|
|
edge of SCL, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDA_SAMPLE</name>
|
|
<description>Configures the sample time after a positive SCL edge.</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_HIGH_PERIOD</name>
|
|
<description>Configures the high level width of SCL</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_HIGH_PERIOD</name>
|
|
<description>This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_WAIT_HIGH_PERIOD</name>
|
|
<description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_START_HOLD</name>
|
|
<description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure the time between the negative edge
|
|
of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_RSTART_SETUP</name>
|
|
<description>Configures the delay between the positive
|
|
edge of SCL and the negative edge of SDA</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure the time between the positive
|
|
edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_STOP_HOLD</name>
|
|
<description>Configures the delay after the SCL clock
|
|
edge for a stop condition</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure the delay after the STOP condition,
|
|
in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_STOP_SETUP</name>
|
|
<description>Configures the delay between the SDA and
|
|
SCL positive edge for a stop condition</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>This register is used to configure the time between the positive edge
|
|
of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER_CFG</name>
|
|
<description>SCL and SDA filter configuration register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000300</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_FILTER_THRES</name>
|
|
<description>When a pulse on the SCL input has smaller width than this register value
|
|
in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SDA_FILTER_THRES</name>
|
|
<description>When a pulse on the SDA input has smaller width than this register value
|
|
in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_FILTER_EN</name>
|
|
<description>This is the filter enable bit for SCL.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SDA_FILTER_EN</name>
|
|
<description>This is the filter enable bit for SDA.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_CONF</name>
|
|
<description>I2C CLK configuration register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00200000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCLK_DIV_NUM</name>
|
|
<description>the integral part of the fractional divisor for i2c module</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_DIV_A</name>
|
|
<description>the numerator of the fractional part of the fractional divisor for i2c module</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_DIV_B</name>
|
|
<description>the denominator of the fractional part of the fractional divisor for i2c module</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_SEL</name>
|
|
<description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_ACTIVE</name>
|
|
<description>The clock switch for i2c module</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD0</name>
|
|
<description>I2C command register 0</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND0</name>
|
|
<description>This is the content of command 0. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND0_DONE</name>
|
|
<description>When command 0 is done in I2C Master mode, this bit changes to high
|
|
level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD1</name>
|
|
<description>I2C command register 1</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND1</name>
|
|
<description>This is the content of command 1. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND1_DONE</name>
|
|
<description>When command 1 is done in I2C Master mode, this bit changes to high
|
|
level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD2</name>
|
|
<description>I2C command register 2</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND2</name>
|
|
<description>This is the content of command 2. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND2_DONE</name>
|
|
<description>When command 2 is done in I2C Master mode, this bit changes to high
|
|
Level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD3</name>
|
|
<description>I2C command register 3</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND3</name>
|
|
<description>This is the content of command 3. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND3_DONE</name>
|
|
<description>When command 3 is done in I2C Master mode, this bit changes to high
|
|
level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD4</name>
|
|
<description>I2C command register 4</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND4</name>
|
|
<description>This is the content of command 4. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND4_DONE</name>
|
|
<description>When command 4 is done in I2C Master mode, this bit changes to high
|
|
level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD5</name>
|
|
<description>I2C command register 5</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND5</name>
|
|
<description>This is the content of command 5. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND5_DONE</name>
|
|
<description>When command 5 is done in I2C Master mode, this bit changes to high level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD6</name>
|
|
<description>I2C command register 6</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND6</name>
|
|
<description>This is the content of command 6. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND6_DONE</name>
|
|
<description>When command 6 is done in I2C Master mode, this bit changes to high level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMD7</name>
|
|
<description>I2C command register 7</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>COMMAND7</name>
|
|
<description>This is the content of command 7. It consists of three parts:
|
|
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
|
|
Byte_num represents the number of bytes that need to be sent or received.
|
|
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
|
|
Information.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMMAND7_DONE</name>
|
|
<description>When command 7 is done in I2C Master mode, this bit changes to high level.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_ST_TIME_OUT</name>
|
|
<description>SCL status time out register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_ST_TO_I2C</name>
|
|
<description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_MAIN_ST_TIME_OUT</name>
|
|
<description>SCL main status time out register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_MAIN_ST_TO_I2C</name>
|
|
<description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCL_SP_CONF</name>
|
|
<description>Power configuration register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_RST_SLV_EN</name>
|
|
<description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_RST_SLV_NUM</name>
|
|
<description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCL_PD_EN</name>
|
|
<description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SDA_PD_EN</name>
|
|
<description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>Version register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02201143</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>This is the the version register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFO_START_ADDR</name>
|
|
<description>I2C TXFIFO base address register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO_START_ADDR</name>
|
|
<description>This is the I2C txfifo first address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFO_START_ADDR</name>
|
|
<description>I2C RXFIFO base address register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_START_ADDR</name>
|
|
<description>This is the I2C rxfifo first address.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_PERI</name>
|
|
<description>LP_PERI Peripheral</description>
|
|
<groupName>LPPERI</groupName>
|
|
<baseAddress>0x600B2800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LP_PERI_TIMEOUT</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x7F800000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_TOUCH_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RNG_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTP_DBG_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_UART_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_IO_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_EXT_I2C_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_ANA_I2C_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EFUSE_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_CPU_CK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BUS_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_TOUCH_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTP_DBG_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_UART_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_IO_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_EXT_I2C_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_ANA_I2C_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EFUSE_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_CPU_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNG_DATA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RND_DATA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPCORE_DBGM_UNAVALIABLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUS_TIMEOUT</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xBFFFC000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_PERI_TIMEOUT_THRES</name>
|
|
<description>need_des</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_PERI_TIMEOUT_INT_CLEAR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_PERI_TIMEOUT_PROTECT_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUS_TIMEOUT_ADDR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_PERI_TIMEOUT_ADDR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUS_TIMEOUT_UID</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_PERI_TIMEOUT_UID</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEM_CTRL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UART_WAKEUP_FLAG_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_WAKEUP_FLAG</name>
|
|
<description>need_des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_WAKEUP_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_MEM_FORCE_PD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_MEM_FORCE_PU</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTERRUPT_SOURCE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_INTERRUPT_SOURCE</name>
|
|
<description>BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02206130</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPPERI_DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_ANA_PERI</name>
|
|
<description>LP_ANA_PERI Peripheral</description>
|
|
<groupName>LP_ANA</groupName>
|
|
<baseAddress>0x600B2C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>BOD_MODE0_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0FFC0100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_CLOSE_FLASH_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_PD_RF_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_INTR_WAIT</name>
|
|
<description>need_des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_RESET_WAIT</name>
|
|
<description>need_des</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_CNT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_INTR_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_RESET_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOD_MODE0_RESET_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOD_MODE1_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE1_RESET_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CK_GLITCH_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>CK_GLITCH_RESET_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIB_ENABLE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ANA_FIB_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_RAW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ST</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ENA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_LP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_LP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_LP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_MODE0_LP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02202260</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_ANA_DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_AON</name>
|
|
<description>LP_AON Peripheral</description>
|
|
<groupName>LP_AON</groupName>
|
|
<baseAddress>0x600B1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x5C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>STORE0</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE1</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE2</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE2</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE3</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE3</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE4</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE4</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE5</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE5</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE6</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE6</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE7</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE7</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE8</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE8</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STORE9</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_STORE9</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_MUX</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_HOLD0</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_HOLD0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_HOLD1</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_HOLD1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_CFG</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>FORCE_DOWNLOAD_BOOT</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPSYS_SW_RESET</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUCORE0_CFG</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x40000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPU_CORE0_SW_STALL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_CORE0_SW_RESET</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_CORE0_OCD_HALT_ON_RESET</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_CORE0_STAT_VECTOR_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_CORE0_DRESET_MASK</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IO_MUX</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RESET_DISABLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXT_WAKEUP_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>EXT_WAKEUP_STATUS</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT_WAKEUP_STATUS_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT_WAKEUP_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT_WAKEUP_LV</name>
|
|
<description>need_des</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT_WAKEUP_FILTER</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RESET_DISABLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPBUS</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xB0200000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FAST_MEM_WPULSE</name>
|
|
<description>This field controls fast memory WPULSE parameter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_WA</name>
|
|
<description>This field controls fast memory WA parameter.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_RA</name>
|
|
<description>This field controls fast memory RA parameter.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_MUX_FSM_IDLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_MUX_SEL_STATUS</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_MUX_SEL_UPDATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_MEM_MUX_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDIO_ACTIVE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02800000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDIO_ACT_DNUM</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPCORE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>ETM_WAKEUP_FLAG_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETM_WAKEUP_FLAG</name>
|
|
<description>need_des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAR_CCT</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SAR2_PWDET_CCT</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02205280</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_APM</name>
|
|
<description>Low-power Access Permission Management Controller</description>
|
|
<groupName>LP_APM</groupName>
|
|
<baseAddress>0x600B3800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x64</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LP_APM_M0</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LP_APM_M1</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>REGION_FILTER_EN</name>
|
|
<description>Region filter enable register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION_FILTER_EN</name>
|
|
<description>Region filter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION0_ADDR_START</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION0_ADDR_START</name>
|
|
<description>Start address of region0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION0_ADDR_END</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION0_ADDR_END</name>
|
|
<description>End address of region0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION0_PMS_ATTR</name>
|
|
<description>Region access authority attribute register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION0_R0_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R0_PMS_W</name>
|
|
<description>Region write authority in REE_MODE0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R0_PMS_R</name>
|
|
<description>Region read authority in REE_MODE0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R1_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R1_PMS_W</name>
|
|
<description>Region write authority in REE_MODE1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R1_PMS_R</name>
|
|
<description>Region read authority in REE_MODE1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R2_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R2_PMS_W</name>
|
|
<description>Region write authority in REE_MODE2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION0_R2_PMS_R</name>
|
|
<description>Region read authority in REE_MODE2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION1_ADDR_START</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION1_ADDR_START</name>
|
|
<description>Start address of region1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION1_ADDR_END</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION1_ADDR_END</name>
|
|
<description>End address of region1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION1_PMS_ATTR</name>
|
|
<description>Region access authority attribute register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION1_R0_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R0_PMS_W</name>
|
|
<description>Region write authority in REE_MODE0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R0_PMS_R</name>
|
|
<description>Region read authority in REE_MODE0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R1_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R1_PMS_W</name>
|
|
<description>Region write authority in REE_MODE1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R1_PMS_R</name>
|
|
<description>Region read authority in REE_MODE1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R2_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R2_PMS_W</name>
|
|
<description>Region write authority in REE_MODE2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION1_R2_PMS_R</name>
|
|
<description>Region read authority in REE_MODE2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION2_ADDR_START</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION2_ADDR_START</name>
|
|
<description>Start address of region2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION2_ADDR_END</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION2_ADDR_END</name>
|
|
<description>End address of region2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION2_PMS_ATTR</name>
|
|
<description>Region access authority attribute register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION2_R0_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R0_PMS_W</name>
|
|
<description>Region write authority in REE_MODE0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R0_PMS_R</name>
|
|
<description>Region read authority in REE_MODE0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R1_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R1_PMS_W</name>
|
|
<description>Region write authority in REE_MODE1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R1_PMS_R</name>
|
|
<description>Region read authority in REE_MODE1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R2_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R2_PMS_W</name>
|
|
<description>Region write authority in REE_MODE2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION2_R2_PMS_R</name>
|
|
<description>Region read authority in REE_MODE2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION3_ADDR_START</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION3_ADDR_START</name>
|
|
<description>Start address of region3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION3_ADDR_END</name>
|
|
<description>Region address register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION3_ADDR_END</name>
|
|
<description>End address of region3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGION3_PMS_ATTR</name>
|
|
<description>Region access authority attribute register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REGION3_R0_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R0_PMS_W</name>
|
|
<description>Region write authority in REE_MODE0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R0_PMS_R</name>
|
|
<description>Region read authority in REE_MODE0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R1_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R1_PMS_W</name>
|
|
<description>Region write authority in REE_MODE1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R1_PMS_R</name>
|
|
<description>Region read authority in REE_MODE1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R2_PMS_X</name>
|
|
<description>Region execute authority in REE_MODE2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R2_PMS_W</name>
|
|
<description>Region write authority in REE_MODE2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REGION3_R2_PMS_R</name>
|
|
<description>Region read authority in REE_MODE2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FUNC_CTRL</name>
|
|
<description>PMS function control register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0_PMS_FUNC_EN</name>
|
|
<description>PMS M0 function enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1_PMS_FUNC_EN</name>
|
|
<description>PMS M1 function enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0_STATUS</name>
|
|
<description>M0 status register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M0_EXCEPTION_STATUS</name>
|
|
<description>Exception status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0_STATUS_CLR</name>
|
|
<description>M0 status clear register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M0_REGION_STATUS_CLR</name>
|
|
<description>Clear exception status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0_EXCEPTION_INFO0</name>
|
|
<description>M0 exception_info0 register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M0_EXCEPTION_REGION</name>
|
|
<description>Exception region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>M0_EXCEPTION_MODE</name>
|
|
<description>Exception mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>M0_EXCEPTION_ID</name>
|
|
<description>Exception id information</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0_EXCEPTION_INFO1</name>
|
|
<description>M0 exception_info1 register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M0_EXCEPTION_ADDR</name>
|
|
<description>Exception addr</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M1_STATUS</name>
|
|
<description>M1 status register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M1_EXCEPTION_STATUS</name>
|
|
<description>Exception status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M1_STATUS_CLR</name>
|
|
<description>M1 status clear register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M1_REGION_STATUS_CLR</name>
|
|
<description>Clear exception status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M1_EXCEPTION_INFO0</name>
|
|
<description>M1 exception_info0 register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M1_EXCEPTION_REGION</name>
|
|
<description>Exception region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>M1_EXCEPTION_MODE</name>
|
|
<description>Exception mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>M1_EXCEPTION_ID</name>
|
|
<description>Exception id information</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M1_EXCEPTION_INFO1</name>
|
|
<description>M1 exception_info1 register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M1_EXCEPTION_ADDR</name>
|
|
<description>Exception addr</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_EN</name>
|
|
<description>APM interrupt enable register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>M0_APM_INT_EN</name>
|
|
<description>APM M0 interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M1_APM_INT_EN</name>
|
|
<description>APM M1 interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK_GATE</name>
|
|
<description>clock gating register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>reg_clk_en</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>Version register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02205240</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>reg_date</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_CLKRST</name>
|
|
<description>LP_CLKRST Peripheral</description>
|
|
<groupName>LP_CLKRST</groupName>
|
|
<baseAddress>0x600B0400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>LP_CLK_CONF</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000004</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLOW_CLK_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_CLK_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_PERI_DIV_NUM</name>
|
|
<description>need_des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_CLK_PO_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x000007FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AON_SLOW_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AON_FAST_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOSC_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FOSC_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC32K_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTAL32K_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CORE_EFUSE_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLOW_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FAST_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RNG_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPBUS_OEN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_CLK_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>FAST_ORI_GATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_RST_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>AON_EFUSE_CORE_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_TIMER_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ANA_PERI_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_CAUSE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000020</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESET_CAUSE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CORE0_RESET_FLAG</name>
|
|
<description>need_des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CORE0_RESET_CAUSE_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CORE0_RESET_FLAG_SET</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CORE0_RESET_FLAG_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU_RESET</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x04400000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_WDT_CPU_RESET_LENGTH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTC_WDT_CPU_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_STALL_WAIT</name>
|
|
<description>need_des</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_STALL_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOSC_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x2B000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FOSC_DFREQ</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RC32K_CNTL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x2B000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RC32K_DFREQ</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_TO_HP</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xF0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ICG_HP_XTAL32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICG_HP_SOSC</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICG_HP_OSC32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICG_HP_FOSC</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMEM_FORCE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LPMEM_CLK_FORCE_ON</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPPERI</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_CLK_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_UART_CLK_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XTAL32K</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x66C00000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DRES_XTAL32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DGM_XTAL32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBUF_XTAL32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC_XTAL32K</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02206090</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKRST_DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_I2C_ANA_MST</name>
|
|
<description>LP_I2C_ANA_MST Peripheral</description>
|
|
<groupName>LP_I2C_ANA_MST</groupName>
|
|
<baseAddress>0x600B2400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>I2C0_CTRL</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_CTRL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_BUSY</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C0_CONF</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x07000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_CONF</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_STATUS</name>
|
|
<description>reserved</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2C0_DATA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000900</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_RDATA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C0_CLK_SEL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C_MST_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ANA_CONF1</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_ANA_CONF1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NOUSE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C_MST_NOUSE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICE_EN</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C_DEVICE_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02007301</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C_MAT_DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_ANA_MAST_I2C_MAT_CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_IO_MUX</name>
|
|
<description>Low-power Input/Output Multiplexer</description>
|
|
<groupName>LP_IO</groupName>
|
|
<baseAddress>0x600B2000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x7C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>OUT_DATA</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_OUT_DATA</name>
|
|
<description>set lp gpio output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_DATA_W1TS</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_OUT_DATA_W1TS</name>
|
|
<description>set one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_DATA_W1TC</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_OUT_DATA_W1TC</name>
|
|
<description>clear one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_ENABLE</name>
|
|
<description>need des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_ENABLE</name>
|
|
<description>set lp gpio output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_ENABLE_W1TS</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_ENABLE_W1TS</name>
|
|
<description>set one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_ENABLE_W1TC</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_ENABLE_W1TC</name>
|
|
<description>clear one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_STATUS_INTERRUPT</name>
|
|
<description>set lp gpio output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_W1TS</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_STATUS_W1TS</name>
|
|
<description>set one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_W1TC</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_STATUS_W1TC</name>
|
|
<description>clear one time output data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_IN_DATA_NEXT</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN0</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO0_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN1</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO1_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN2</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO2_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN3</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO3_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN4</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO4_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN5</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO5_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN6</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO6_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN7</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO7_SYNC_BYPASS</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_PAD_DRIVER</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_EDGE_WAKEUP_CLR</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_INT_TYPE</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_WAKEUP_ENABLE</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_FILTER_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO0</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO0_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO1</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO1_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO2</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO2_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO3</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO3_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO4</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO4_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO5</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO5_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO6</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO6_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO7</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_OE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_SLP_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_FUN_WPD</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_FUN_WPU</name>
|
|
<description>need des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_FUN_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_FUN_DRV</name>
|
|
<description>need des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_GPIO7_MCU_SEL</name>
|
|
<description>need des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_INTERRUPT</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_GPIO_STATUS_INTERRUPT_NEXT</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_SEL0</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_DEBUG_SEL0</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_DEBUG_SEL1</name>
|
|
<description>need des</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_DEBUG_SEL2</name>
|
|
<description>need des</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_DEBUG_SEL3</name>
|
|
<description>need des</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_SEL1</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_DEBUG_SEL4</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_I2C_SDA_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_I2C_SCL_IE</name>
|
|
<description>need des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02202100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_IO_DATE</name>
|
|
<description>need des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_TEE</name>
|
|
<description>Low-power Trusted Execution Environment</description>
|
|
<groupName>LP_TEE</groupName>
|
|
<baseAddress>0x600B3400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>M0_MODE_CTRL</name>
|
|
<description>Tee mode control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0_MODE</name>
|
|
<description>M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLOCK_GATE</name>
|
|
<description>Clock gating register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>reg_clk_en</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FORCE_ACC_HP</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>LP_AON_FORCE_ACC_HPMEM_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>Version register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02205270</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>reg_tee_date</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_TIMER</name>
|
|
<description>Low-power Timer</description>
|
|
<groupName>LP_TIMER</groupName>
|
|
<baseAddress>0x600B0C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LP_TIMER</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TAR0_LOW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_LOW0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR0_HIGH</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_HIGH0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_EN0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR1_LOW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_LOW1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR1_HIGH</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_HIGH1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_TAR_EN1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UPDATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_UPDATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_XTAL_OFF</name>
|
|
<description>need_des</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_SYS_STALL</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_SYS_RST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAIN_BUF0_LOW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_BUF0_LOW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAIN_BUF0_HIGH</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_BUF0_HIGH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAIN_BUF1_LOW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_BUF1_LOW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAIN_BUF1_HIGH</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_BUF1_HIGH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAIN_OVERFLOW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_ALARM_LOAD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_RAW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>OVERFLOW_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOC_WAKEUP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ST</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>OVERFLOW_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOC_WAKEUP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ENA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>OVERFLOW_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOC_WAKEUP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>OVERFLOW_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOC_WAKEUP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_OVERFLOW_LP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_LP_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_OVERFLOW_LP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_LP_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_OVERFLOW_LP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_LP_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MAIN_TIMER_OVERFLOW_LP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAIN_TIMER_LP_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02111150</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_UART</name>
|
|
<description>Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
|
|
<groupName>LP_UART</groupName>
|
|
<baseAddress>0x600B1400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x84</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LP_UART</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>FIFO data register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_RD_BYTE</name>
|
|
<description>UART 0 accesses FIFO via this register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_RAW</name>
|
|
<description>Raw interrupt status</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_FULL_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_EMPTY_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_ERR_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_ERR_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR_CHG_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS_CHG_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRK_DET_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_TOUT_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XON_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XOFF_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GLITCH_DET_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_DONE_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_IDLE_DONE_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_DONE_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AT_CMD_CHAR_DET_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_INT_RAW</name>
|
|
<description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ST</name>
|
|
<description>Masked interrupt status</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_FULL_INT_ST</name>
|
|
<description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_EMPTY_INT_ST</name>
|
|
<description>This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_ERR_INT_ST</name>
|
|
<description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_ERR_INT_ST</name>
|
|
<description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_ST</name>
|
|
<description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR_CHG_INT_ST</name>
|
|
<description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS_CHG_INT_ST</name>
|
|
<description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BRK_DET_INT_ST</name>
|
|
<description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_TOUT_INT_ST</name>
|
|
<description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XON_INT_ST</name>
|
|
<description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XOFF_INT_ST</name>
|
|
<description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GLITCH_DET_INT_ST</name>
|
|
<description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_DONE_INT_ST</name>
|
|
<description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_IDLE_DONE_INT_ST</name>
|
|
<description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_DONE_INT_ST</name>
|
|
<description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AT_CMD_CHAR_DET_INT_ST</name>
|
|
<description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_INT_ST</name>
|
|
<description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ENA</name>
|
|
<description>Interrupt enable bits</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_FULL_INT_ENA</name>
|
|
<description>This is the enable bit for rxfifo_full_int_st register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_EMPTY_INT_ENA</name>
|
|
<description>This is the enable bit for txfifo_empty_int_st register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_ERR_INT_ENA</name>
|
|
<description>This is the enable bit for parity_err_int_st register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_ERR_INT_ENA</name>
|
|
<description>This is the enable bit for frm_err_int_st register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_ENA</name>
|
|
<description>This is the enable bit for rxfifo_ovf_int_st register.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR_CHG_INT_ENA</name>
|
|
<description>This is the enable bit for dsr_chg_int_st register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS_CHG_INT_ENA</name>
|
|
<description>This is the enable bit for cts_chg_int_st register.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRK_DET_INT_ENA</name>
|
|
<description>This is the enable bit for brk_det_int_st register.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_TOUT_INT_ENA</name>
|
|
<description>This is the enable bit for rxfifo_tout_int_st register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XON_INT_ENA</name>
|
|
<description>This is the enable bit for sw_xon_int_st register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XOFF_INT_ENA</name>
|
|
<description>This is the enable bit for sw_xoff_int_st register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GLITCH_DET_INT_ENA</name>
|
|
<description>This is the enable bit for glitch_det_int_st register.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_DONE_INT_ENA</name>
|
|
<description>This is the enable bit for tx_brk_done_int_st register.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_IDLE_DONE_INT_ENA</name>
|
|
<description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_DONE_INT_ENA</name>
|
|
<description>This is the enable bit for tx_done_int_st register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AT_CMD_CHAR_DET_INT_ENA</name>
|
|
<description>This is the enable bit for at_cmd_char_det_int_st register.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_INT_ENA</name>
|
|
<description>This is the enable bit for uart_wakeup_int_st register.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>Interrupt clear bits</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_FULL_INT_CLR</name>
|
|
<description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_EMPTY_INT_CLR</name>
|
|
<description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_ERR_INT_CLR</name>
|
|
<description>Set this bit to clear parity_err_int_raw interrupt.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRM_ERR_INT_CLR</name>
|
|
<description>Set this bit to clear frm_err_int_raw interrupt.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_OVF_INT_CLR</name>
|
|
<description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR_CHG_INT_CLR</name>
|
|
<description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS_CHG_INT_CLR</name>
|
|
<description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BRK_DET_INT_CLR</name>
|
|
<description>Set this bit to clear the brk_det_int_raw interrupt.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_TOUT_INT_CLR</name>
|
|
<description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XON_INT_CLR</name>
|
|
<description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_XOFF_INT_CLR</name>
|
|
<description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GLITCH_DET_INT_CLR</name>
|
|
<description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_DONE_INT_CLR</name>
|
|
<description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_BRK_IDLE_DONE_INT_CLR</name>
|
|
<description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_DONE_INT_CLR</name>
|
|
<description>Set this bit to clear the tx_done_int_raw interrupt.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AT_CMD_CHAR_DET_INT_CLR</name>
|
|
<description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_INT_CLR</name>
|
|
<description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV_SYNC</name>
|
|
<description>Clock divider configuration</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x000002B6</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>The integral part of the frequency divider factor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV_FRAG</name>
|
|
<description>The decimal part of the frequency divider factor.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_FILT</name>
|
|
<description>Rx Filter configuration</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GLITCH_FILT</name>
|
|
<description>when input pulse width is lower than this value the pulse is ignored.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GLITCH_FILT_EN</name>
|
|
<description>Set this bit to enable Rx signal filter.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>UART status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xE000C000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_CNT</name>
|
|
<description>Stores the byte number of valid data in Rx-FIFO.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRN</name>
|
|
<description>The register represent the level value of the internal uart dsr signal.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSN</name>
|
|
<description>This register represent the level value of the internal uart cts signal.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>This register represent the level value of the internal uart rxd signal.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_CNT</name>
|
|
<description>Stores the byte number of data in Tx-FIFO.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTRN</name>
|
|
<description>This bit represents the level of the internal uart dtr signal.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSN</name>
|
|
<description>This bit represents the level of the internal uart rts signal.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>This bit represents the level of the internal uart txd signal.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF0_SYNC</name>
|
|
<description>Configuration register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0010001C</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>This register is used to configure the parity check mode.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_EN</name>
|
|
<description>Set this bit to enable uart parity check.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT_NUM</name>
|
|
<description>This register is used to set the length of data.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_BIT_NUM</name>
|
|
<description>This register is used to set the length of stop bit.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD_BRK</name>
|
|
<description>Set this bit to enbale transmitter to send NULL when the process of sending data is done.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBACK</name>
|
|
<description>Set this bit to enable uart loopback test mode.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_FLOW_EN</name>
|
|
<description>Set this bit to enable flow control function for transmitter.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD_INV</name>
|
|
<description>Set this bit to inverse the level value of uart rxd signal.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD_INV</name>
|
|
<description>Set this bit to inverse the level value of uart txd signal.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS_RX_DAT_OVF</name>
|
|
<description>Disable UART Rx data overflow detect.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR_WR_MASK</name>
|
|
<description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM_CLK_EN</name>
|
|
<description>UART memory clock gate enable signal.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_RTS</name>
|
|
<description>This register is used to configure the software rts signal which is used in software flow control.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO_RST</name>
|
|
<description>Set this bit to reset the uart receive-FIFO.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_RST</name>
|
|
<description>Set this bit to reset the uart transmit-FIFO.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF1</name>
|
|
<description>Configuration register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00006060</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO_FULL_THRHD</name>
|
|
<description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFO_EMPTY_THRHD</name>
|
|
<description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS_INV</name>
|
|
<description>Set this bit to inverse the level value of uart cts signal.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR_INV</name>
|
|
<description>Set this bit to inverse the level value of uart dsr signal.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTS_INV</name>
|
|
<description>Set this bit to inverse the level value of uart rts signal.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTR_INV</name>
|
|
<description>Set this bit to inverse the level value of uart dtr signal.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_DTR</name>
|
|
<description>This register is used to configure the software dtr signal which is used in software flow control.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWFC_CONF_SYNC</name>
|
|
<description>Hardware flow-control configuration</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RX_FLOW_THRHD</name>
|
|
<description>This register is used to configure the maximum amount of data that can be received when hardware flow control works.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_FLOW_EN</name>
|
|
<description>This is the flow enable bit for UART receiver.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLEEP_CONF0</name>
|
|
<description>UART sleep configure register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>WK_CHAR1</name>
|
|
<description>This register restores the specified wake up char1 to wake up</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_CHAR2</name>
|
|
<description>This register restores the specified wake up char2 to wake up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_CHAR3</name>
|
|
<description>This register restores the specified wake up char3 to wake up</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_CHAR4</name>
|
|
<description>This register restores the specified wake up char4 to wake up</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLEEP_CONF1</name>
|
|
<description>UART sleep configure register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>WK_CHAR0</name>
|
|
<description>This register restores the specified char0 to wake up</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLEEP_CONF2</name>
|
|
<description>UART sleep configure register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x001420F0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE_THRESHOLD</name>
|
|
<description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_WAKE_UP_THRHD</name>
|
|
<description>In wake up mode 1 this field is used to set the received data number threshold to wake up chip.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_CHAR_NUM</name>
|
|
<description>This register is used to select number of wake up char.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_CHAR_MASK</name>
|
|
<description>This register is used to mask wake up char.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WK_MODE_SEL</name>
|
|
<description>This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWFC_CONF0_SYNC</name>
|
|
<description>Software flow-control character configuration</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00001311</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XON_CHAR</name>
|
|
<description>This register stores the Xon flow control char.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XOFF_CHAR</name>
|
|
<description>This register stores the Xoff flow control char.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XON_XOFF_STILL_SEND</name>
|
|
<description>In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_FLOW_CON_EN</name>
|
|
<description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XONOFF_DEL</name>
|
|
<description>Set this bit to remove flow control char from the received data.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_XON</name>
|
|
<description>Set this bit to enable the transmitter to go on sending data.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_XOFF</name>
|
|
<description>Set this bit to stop the transmitter from sending data.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEND_XON</name>
|
|
<description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEND_XOFF</name>
|
|
<description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWFC_CONF1</name>
|
|
<description>Software flow-control character configuration</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00006000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XON_THRESHOLD</name>
|
|
<description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XOFF_THRESHOLD</name>
|
|
<description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBRK_CONF_SYNC</name>
|
|
<description>Tx Break character configuration</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000000A</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TX_BRK_NUM</name>
|
|
<description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDLE_CONF_SYNC</name>
|
|
<description>Frame-end idle configuration</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00040100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RX_IDLE_THRHD</name>
|
|
<description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_IDLE_NUM</name>
|
|
<description>This register is used to configure the duration time between transfers.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485_CONF_SYNC</name>
|
|
<description>RS485 mode configuration</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>DL0_EN</name>
|
|
<description>Set this bit to delay the stop bit by 1 bit.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DL1_EN</name>
|
|
<description>Set this bit to delay the stop bit by 1 bit.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AT_CMD_PRECNT_SYNC</name>
|
|
<description>Pre-sequence timing configuration</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000901</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRE_IDLE_NUM</name>
|
|
<description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AT_CMD_POSTCNT_SYNC</name>
|
|
<description>Post-sequence timing configuration</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000901</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>POST_IDLE_NUM</name>
|
|
<description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AT_CMD_GAPTOUT_SYNC</name>
|
|
<description>Timeout configuration</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000000B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RX_GAP_TOUT</name>
|
|
<description>This register is used to configure the duration time between the at_cmd chars.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AT_CMD_CHAR_SYNC</name>
|
|
<description>AT escape sequence detection configuration</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000032B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AT_CMD_CHAR</name>
|
|
<description>This register is used to configure the content of at_cmd char.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAR_NUM</name>
|
|
<description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEM_CONF</name>
|
|
<description>UART memory power configuration</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>MEM_FORCE_PD</name>
|
|
<description>Set this bit to force power down UART memory.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM_FORCE_PU</name>
|
|
<description>Set this bit to force power up UART memory.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOUT_CONF_SYNC</name>
|
|
<description>UART threshold and allocation configuration</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000028</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RX_TOUT_EN</name>
|
|
<description>This is the enble bit for uart receiver's timeout function.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_TOUT_FLOW_DIS</name>
|
|
<description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_TOUT_THRHD</name>
|
|
<description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEM_TX_STATUS</name>
|
|
<description>Tx-SRAM write and read offset address.</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>TX_SRAM_WADDR</name>
|
|
<description>This register stores the offset write address in Tx-SRAM.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_SRAM_RADDR</name>
|
|
<description>This register stores the offset read address in Tx-SRAM.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEM_RX_STATUS</name>
|
|
<description>Rx-SRAM write and read offset address.</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00010080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RX_SRAM_RADDR</name>
|
|
<description>This register stores the offset read address in RX-SRAM.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_SRAM_WADDR</name>
|
|
<description>This register stores the offset write address in Rx-SRAM.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSM_STATUS</name>
|
|
<description>UART transmit and receive status.</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>ST_URX_OUT</name>
|
|
<description>This is the status register of receiver.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ST_UTX_OUT</name>
|
|
<description>This is the status register of transmitter.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_CONF</name>
|
|
<description>UART core clock configuration</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x03701000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCLK_DIV_B</name>
|
|
<description>The denominator of the frequency divider factor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_DIV_A</name>
|
|
<description>The numerator of the frequency divider factor.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_DIV_NUM</name>
|
|
<description>The integral part of the frequency divider factor.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_SEL</name>
|
|
<description>UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLK_EN</name>
|
|
<description>Set this bit to enable UART Tx/Rx clock.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RST_CORE</name>
|
|
<description>Write 1 then write 0 to this bit to reset UART Tx/Rx.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_SCLK_EN</name>
|
|
<description>Set this bit to enable UART Tx clock.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_SCLK_EN</name>
|
|
<description>Set this bit to enable UART Rx clock.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_RST_CORE</name>
|
|
<description>Write 1 then write 0 to this bit to reset UART Tx.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_RST_CORE</name>
|
|
<description>Write 1 then write 0 to this bit to reset UART Rx.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>UART Version register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02201260</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATE</name>
|
|
<description>This is the version register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFIFO_STATUS</name>
|
|
<description>UART AFIFO Status</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000000A</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TX_AFIFO_FULL</name>
|
|
<description>Full signal of APB TX AFIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_AFIFO_EMPTY</name>
|
|
<description>Empty signal of APB TX AFIFO.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_AFIFO_FULL</name>
|
|
<description>Full signal of APB RX AFIFO.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_AFIFO_EMPTY</name>
|
|
<description>Empty signal of APB RX AFIFO.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_UPDATE</name>
|
|
<description>UART Registers Configuration Update register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>REG_UPDATE</name>
|
|
<description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID</name>
|
|
<description>UART ID register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000500</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>This register is used to configure the uart_id.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LP_WDT</name>
|
|
<description>Low-power Watchdog Timer</description>
|
|
<groupName>LP_WDT</groupName>
|
|
<baseAddress>0x600B1C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LP_WDT</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONFIG0</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00013214</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_CHIP_RESET_WIDTH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CHIP_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_PAUSE_IN_SLP</name>
|
|
<description>need_des</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_APPCPU_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_PROCPU_RESET_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_FLASHBOOT_MOD_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_SYS_RESET_LENGTH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CPU_RESET_LENGTH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_STG3</name>
|
|
<description>need_des</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_STG2</name>
|
|
<description>need_des</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_STG1</name>
|
|
<description>need_des</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_STG0</name>
|
|
<description>need_des</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDT_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG1</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00030D40</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_STG0_HOLD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG2</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00013880</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_STG1_HOLD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG3</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_STG2_HOLD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG4</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_STG3_HOLD</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEED</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_WDT_FEED</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPROTECT</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_WKEY</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWD_CONFIG</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x12C00000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWD_RESET_FLAG</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWD_AUTO_FEED_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWD_RST_FLAG_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWD_SIGNAL_WIDTH</name>
|
|
<description>need_des</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWD_DISABLE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWD_FEED</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWD_WPROTECT</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SWD_WKEY</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_RAW</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SUPER_WDT_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_WDT_INT_RAW</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ST</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SUPER_WDT_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_WDT_INT_ST</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_ENA</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SUPER_WDT_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_WDT_INT_ENA</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<fields>
|
|
<field>
|
|
<name>SUPER_WDT_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_WDT_INT_CLR</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<description>need_des</description>
|
|
<addressOffset>0x3FC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x02112080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LP_WDT_DATE</name>
|
|
<description>need_des</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>need_des</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> |