ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C6-LP ESP32 Series 1 32-bit RISC-V MCU Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. RV32IMAC r0p0 little false false 4 false 32 32 0x00000000 0xFFFFFFFF LP_I2C Low-power I2C (Inter-Integrated Circuit) Controller I2C 0x600B1800 0x0 0x88 registers LP_I2C 17 SCL_LOW_PERIOD Configures the low level width of the SCL Clock 0x0 0x20 SCL_LOW_PERIOD This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. 0 9 read-write CTR Transmission setting 0x4 0x20 0x00000208 SDA_FORCE_OUT 1: direct output, 0: open drain output. 0 1 read-write SCL_FORCE_OUT 1: direct output, 0: open drain output. 1 1 read-write SAMPLE_SCL_LEVEL This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level. 2 1 read-write RX_FULL_ACK_LEVEL This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. 3 1 read-write TRANS_START Set this bit to start sending the data in txfifo. 5 1 write-only TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit. 6 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit. 7 1 read-write CLK_EN Reserved 8 1 read-write ARBITRATION_EN This is the enable bit for arbitration_lost. 9 1 read-write FSM_RST This register is used to reset the scl FMS. 10 1 write-only CONF_UPGATE synchronization bit 11 1 write-only SR Describe I2C work status. 0x8 0x20 RESP_REC The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 0 1 read-only ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. 3 1 read-only BUS_BUSY 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. 4 1 read-only RXFIFO_CNT This field represents the amount of data needed to be sent. 8 5 read-only TXFIFO_CNT This field stores the amount of received data in RAM. 18 5 read-only SCL_MAIN_STATE_LAST This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK 24 3 read-only SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop 28 3 read-only TO Setting time out control for receiving data. 0xC 0x20 0x00000010 TIME_OUT_VALUE This register is used to configure the timeout for receiving a data bit in APB clock cycles. 0 5 read-write TIME_OUT_EN This is the enable bit for time out control. 5 1 read-write FIFO_ST FIFO status register. 0x14 0x20 RXFIFO_RADDR This is the offset address of the APB reading from rxfifo 0 4 read-only RXFIFO_WADDR This is the offset address of i2c module receiving data and writing to rxfifo. 5 4 read-only TXFIFO_RADDR This is the offset address of i2c module reading from txfifo. 10 4 read-only TXFIFO_WADDR This is the offset address of APB bus writing to txfifo. 15 4 read-only FIFO_CONF FIFO configuration register. 0x18 0x20 0x00004046 RXFIFO_WM_THRHD The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. 0 4 read-write TXFIFO_WM_THRHD The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. 5 4 read-write NONFIFO_EN Set this bit to enable APB nonfifo access. 10 1 read-write RX_FIFO_RST Set this bit to reset rx-fifo. 12 1 read-write TX_FIFO_RST Set this bit to reset tx-fifo. 13 1 read-write FIFO_PRT_EN The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 14 1 read-write DATA Rx FIFO read data. 0x1C 0x20 FIFO_RDATA The value of rx FIFO read data. 0 8 read-only INT_RAW Raw interrupt status 0x20 0x20 0x00000002 RXFIFO_WM_INT_RAW The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_RAW The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_RAW The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_RAW The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_RAW The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_RAW The raw interrupt bit for I2C_DET_START_INT interrupt. 15 1 read-only INT_CLR Interrupt clear bits 0x24 0x20 RXFIFO_WM_INT_CLR Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 0 1 write-only TXFIFO_WM_INT_CLR Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 1 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 2 1 write-only END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 3 1 write-only BYTE_TRANS_DONE_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 4 1 write-only ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 5 1 write-only MST_TXFIFO_UDF_INT_CLR Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 6 1 write-only TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 7 1 write-only TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. 8 1 write-only TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. 9 1 write-only NACK_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 10 1 write-only TXFIFO_OVF_INT_CLR Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 11 1 write-only RXFIFO_UDF_INT_CLR Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 12 1 write-only SCL_ST_TO_INT_CLR Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 13 1 write-only SCL_MAIN_ST_TO_INT_CLR Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 write-only DET_START_INT_CLR Set this bit to clear I2C_DET_START_INT interrupt. 15 1 write-only INT_ENA Interrupt enable bits 0x28 0x20 RXFIFO_WM_INT_ENA The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-write TXFIFO_WM_INT_ENA The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-write RXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-write END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 3 1 read-write BYTE_TRANS_DONE_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 4 1 read-write ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-write MST_TXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-write TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-write TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-write TRANS_START_INT_ENA The interrupt enable bit for the I2C_TRANS_START_INT interrupt. 9 1 read-write NACK_INT_ENA The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-write TXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-write RXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-write SCL_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-write SCL_MAIN_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-write DET_START_INT_ENA The interrupt enable bit for I2C_DET_START_INT interrupt. 15 1 read-write INT_STATUS Status of captured I2C communication events 0x2C 0x20 RXFIFO_WM_INT_ST The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_ST The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_ST The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_ST The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_ST The masked interrupt status bit for I2C_DET_START_INT interrupt. 15 1 read-only SDA_HOLD Configures the hold time after a negative SCL edge. 0x30 0x20 TIME This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles. 0 9 read-write SDA_SAMPLE Configures the sample time after a positive SCL edge. 0x34 0x20 TIME This register is used to configure for how long SDA is sampled, in I2C module clock cycles. 0 9 read-write SCL_HIGH_PERIOD Configures the high level width of SCL 0x38 0x20 SCL_HIGH_PERIOD This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. 0 9 read-write SCL_WAIT_HIGH_PERIOD This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. 9 7 read-write SCL_START_HOLD Configures the delay between the SDA and SCL negative edge for a start condition 0x40 0x20 0x00000008 TIME This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. 0 9 read-write SCL_RSTART_SETUP Configures the delay between the positive edge of SCL and the negative edge of SDA 0x44 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_HOLD Configures the delay after the SCL clock edge for a stop condition 0x48 0x20 0x00000008 TIME This register is used to configure the delay after the STOP condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_SETUP Configures the delay between the SDA and SCL positive edge for a stop condition 0x4C 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles. 0 9 read-write FILTER_CFG SCL and SDA filter configuration register 0x50 0x20 0x00000300 SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 0 4 read-write SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 4 4 read-write SCL_FILTER_EN This is the filter enable bit for SCL. 8 1 read-write SDA_FILTER_EN This is the filter enable bit for SDA. 9 1 read-write CLK_CONF I2C CLK configuration register 0x54 0x20 0x00200000 SCLK_DIV_NUM the integral part of the fractional divisor for i2c module 0 8 read-write SCLK_DIV_A the numerator of the fractional part of the fractional divisor for i2c module 8 6 read-write SCLK_DIV_B the denominator of the fractional part of the fractional divisor for i2c module 14 6 read-write SCLK_SEL The clock selection for i2c module:0-XTAL,1-CLK_8MHz. 20 1 read-write SCLK_ACTIVE The clock switch for i2c module 21 1 read-write COMD0 I2C command register 0 0x58 0x20 COMMAND0 This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND0_DONE When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD1 I2C command register 1 0x5C 0x20 COMMAND1 This is the content of command 1. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND1_DONE When command 1 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD2 I2C command register 2 0x60 0x20 COMMAND2 This is the content of command 2. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND2_DONE When command 2 is done in I2C Master mode, this bit changes to high Level. 31 1 read-write COMD3 I2C command register 3 0x64 0x20 COMMAND3 This is the content of command 3. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND3_DONE When command 3 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD4 I2C command register 4 0x68 0x20 COMMAND4 This is the content of command 4. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND4_DONE When command 4 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD5 I2C command register 5 0x6C 0x20 COMMAND5 This is the content of command 5. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND5_DONE When command 5 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD6 I2C command register 6 0x70 0x20 COMMAND6 This is the content of command 6. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND6_DONE When command 6 is done in I2C Master mode, this bit changes to high level. 31 1 read-write COMD7 I2C command register 7 0x74 0x20 COMMAND7 This is the content of command 7. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND7_DONE When command 7 is done in I2C Master mode, this bit changes to high level. 31 1 read-write SCL_ST_TIME_OUT SCL status time out register 0x78 0x20 0x00000010 SCL_ST_TO_I2C The threshold value of SCL_FSM state unchanged period. It should be o more than 23 0 5 read-write SCL_MAIN_ST_TIME_OUT SCL main status time out register 0x7C 0x20 0x00000010 SCL_MAIN_ST_TO_I2C The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 0 5 read-write SCL_SP_CONF Power configuration register 0x80 0x20 SCL_RST_SLV_EN When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. 0 1 read-write SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. 1 5 read-write SCL_PD_EN The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 6 1 read-write SDA_PD_EN The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 7 1 read-write DATE Version register 0xF8 0x20 0x02201143 DATE This is the the version register. 0 32 read-write TXFIFO_START_ADDR I2C TXFIFO base address register 0x100 0x20 TXFIFO_START_ADDR This is the I2C txfifo first address. 0 32 read-only RXFIFO_START_ADDR I2C RXFIFO base address register 0x180 0x20 RXFIFO_START_ADDR This is the I2C rxfifo first address. 0 32 read-only LP_PERI LP_PERI Peripheral LPPERI 0x600B2800 0x0 0x28 registers LP_PERI_TIMEOUT 19 CLK_EN need_des 0x0 0x20 0x7F800000 LP_TOUCH_CK_EN need_des 23 1 read-write RNG_CK_EN need_des 24 1 read-write OTP_DBG_CK_EN need_des 25 1 read-write LP_UART_CK_EN need_des 26 1 read-write LP_IO_CK_EN need_des 27 1 read-write LP_EXT_I2C_CK_EN need_des 28 1 read-write LP_ANA_I2C_CK_EN need_des 29 1 read-write EFUSE_CK_EN need_des 30 1 read-write LP_CPU_CK_EN need_des 31 1 read-write RESET_EN need_des 0x4 0x20 BUS_RESET_EN need_des 23 1 write-only LP_TOUCH_RESET_EN need_des 24 1 read-write OTP_DBG_RESET_EN need_des 25 1 read-write LP_UART_RESET_EN need_des 26 1 read-write LP_IO_RESET_EN need_des 27 1 read-write LP_EXT_I2C_RESET_EN need_des 28 1 read-write LP_ANA_I2C_RESET_EN need_des 29 1 read-write EFUSE_RESET_EN need_des 30 1 read-write LP_CPU_RESET_EN need_des 31 1 write-only RNG_DATA need_des 0x8 0x20 RND_DATA need_des 0 32 read-only CPU need_des 0xC 0x20 0x80000000 LPCORE_DBGM_UNAVALIABLE need_des 31 1 read-write BUS_TIMEOUT need_des 0x10 0x20 0xBFFFC000 LP_PERI_TIMEOUT_THRES need_des 14 16 read-write LP_PERI_TIMEOUT_INT_CLEAR need_des 30 1 write-only LP_PERI_TIMEOUT_PROTECT_EN need_des 31 1 read-write BUS_TIMEOUT_ADDR need_des 0x14 0x20 LP_PERI_TIMEOUT_ADDR need_des 0 32 read-only BUS_TIMEOUT_UID need_des 0x18 0x20 LP_PERI_TIMEOUT_UID need_des 0 7 read-only MEM_CTRL need_des 0x1C 0x20 0x80000000 UART_WAKEUP_FLAG_CLR need_des 0 1 write-only UART_WAKEUP_FLAG need_des 1 1 read-write UART_WAKEUP_EN need_des 29 1 read-write UART_MEM_FORCE_PD need_des 30 1 read-write UART_MEM_FORCE_PU need_des 31 1 read-write INTERRUPT_SOURCE need_des 0x20 0x20 LP_INTERRUPT_SOURCE BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int 0 6 read-only DATE need_des 0x3FC 0x20 0x02206130 LPPERI_DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write LP_ANA_PERI LP_ANA_PERI Peripheral LP_ANA 0x600B2C00 0x0 0x34 registers BOD_MODE0_CNTL need_des 0x0 0x20 0x0FFC0100 BOD_MODE0_CLOSE_FLASH_ENA need_des 6 1 read-write BOD_MODE0_PD_RF_ENA need_des 7 1 read-write BOD_MODE0_INTR_WAIT need_des 8 10 read-write BOD_MODE0_RESET_WAIT need_des 18 10 read-write BOD_MODE0_CNT_CLR need_des 28 1 read-write BOD_MODE0_INTR_ENA need_des 29 1 read-write BOD_MODE0_RESET_SEL need_des 30 1 read-write BOD_MODE0_RESET_ENA need_des 31 1 read-write BOD_MODE1_CNTL need_des 0x4 0x20 BOD_MODE1_RESET_ENA need_des 31 1 read-write CK_GLITCH_CNTL need_des 0x8 0x20 CK_GLITCH_RESET_ENA need_des 31 1 read-write FIB_ENABLE need_des 0xC 0x20 0xFFFFFFFF ANA_FIB_ENA need_des 0 32 read-write INT_RAW need_des 0x10 0x20 BOD_MODE0_INT_RAW need_des 31 1 read-write INT_ST need_des 0x14 0x20 BOD_MODE0_INT_ST need_des 31 1 read-only INT_ENA need_des 0x18 0x20 BOD_MODE0_INT_ENA need_des 31 1 read-write INT_CLR need_des 0x1C 0x20 BOD_MODE0_INT_CLR need_des 31 1 write-only LP_INT_RAW need_des 0x20 0x20 BOD_MODE0_LP_INT_RAW need_des 31 1 read-write LP_INT_ST need_des 0x24 0x20 BOD_MODE0_LP_INT_ST need_des 31 1 read-only LP_INT_ENA need_des 0x28 0x20 BOD_MODE0_LP_INT_ENA need_des 31 1 read-write LP_INT_CLR need_des 0x2C 0x20 BOD_MODE0_LP_INT_CLR need_des 31 1 write-only DATE need_des 0x3FC 0x20 0x02202260 LP_ANA_DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write LP_AON LP_AON Peripheral LP_AON 0x600B1000 0x0 0x5C registers STORE0 need_des 0x0 0x20 LP_AON_STORE0 need_des 0 32 read-write STORE1 need_des 0x4 0x20 LP_AON_STORE1 need_des 0 32 read-write STORE2 need_des 0x8 0x20 LP_AON_STORE2 need_des 0 32 read-write STORE3 need_des 0xC 0x20 LP_AON_STORE3 need_des 0 32 read-write STORE4 need_des 0x10 0x20 LP_AON_STORE4 need_des 0 32 read-write STORE5 need_des 0x14 0x20 LP_AON_STORE5 need_des 0 32 read-write STORE6 need_des 0x18 0x20 LP_AON_STORE6 need_des 0 32 read-write STORE7 need_des 0x1C 0x20 LP_AON_STORE7 need_des 0 32 read-write STORE8 need_des 0x20 0x20 LP_AON_STORE8 need_des 0 32 read-write STORE9 need_des 0x24 0x20 LP_AON_STORE9 need_des 0 32 read-write GPIO_MUX need_des 0x28 0x20 SEL need_des 0 8 read-write GPIO_HOLD0 need_des 0x2C 0x20 GPIO_HOLD0 need_des 0 32 read-write GPIO_HOLD1 need_des 0x30 0x20 GPIO_HOLD1 need_des 0 32 read-write SYS_CFG need_des 0x34 0x20 FORCE_DOWNLOAD_BOOT need_des 30 1 read-write HPSYS_SW_RESET need_des 31 1 write-only CPUCORE0_CFG need_des 0x38 0x20 0x40000000 CPU_CORE0_SW_STALL need_des 0 8 read-write CPU_CORE0_SW_RESET need_des 28 1 write-only CPU_CORE0_OCD_HALT_ON_RESET need_des 29 1 read-write CPU_CORE0_STAT_VECTOR_SEL need_des 30 1 read-write CPU_CORE0_DRESET_MASK need_des 31 1 read-write IO_MUX need_des 0x3C 0x20 RESET_DISABLE need_des 31 1 read-write EXT_WAKEUP_CNTL need_des 0x40 0x20 EXT_WAKEUP_STATUS need_des 0 8 read-only EXT_WAKEUP_STATUS_CLR need_des 14 1 write-only EXT_WAKEUP_SEL need_des 15 8 read-write EXT_WAKEUP_LV need_des 23 8 read-write EXT_WAKEUP_FILTER need_des 31 1 read-write USB need_des 0x44 0x20 RESET_DISABLE need_des 31 1 read-write LPBUS need_des 0x48 0x20 0xB0200000 FAST_MEM_WPULSE This field controls fast memory WPULSE parameter. 16 3 read-write FAST_MEM_WA This field controls fast memory WA parameter. 19 3 read-write FAST_MEM_RA This field controls fast memory RA parameter. 22 2 read-write FAST_MEM_MUX_FSM_IDLE need_des 28 1 read-only FAST_MEM_MUX_SEL_STATUS need_des 29 1 read-only FAST_MEM_MUX_SEL_UPDATE need_des 30 1 write-only FAST_MEM_MUX_SEL need_des 31 1 read-write SDIO_ACTIVE need_des 0x4C 0x20 0x02800000 SDIO_ACT_DNUM need_des 22 10 read-write LPCORE need_des 0x50 0x20 ETM_WAKEUP_FLAG_CLR need_des 0 1 write-only ETM_WAKEUP_FLAG need_des 1 1 read-write DISABLE need_des 31 1 read-write SAR_CCT need_des 0x54 0x20 SAR2_PWDET_CCT need_des 29 3 read-write DATE need_des 0x3FC 0x20 0x02205280 DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write LP_APM Low-power Access Permission Management Controller LP_APM 0x600B3800 0x0 0x64 registers LP_APM_M0 20 LP_APM_M1 21 REGION_FILTER_EN Region filter enable register 0x0 0x20 0x00000001 REGION_FILTER_EN Region filter enable 0 4 read-write REGION0_ADDR_START Region address register 0x4 0x20 REGION0_ADDR_START Start address of region0 0 32 read-write REGION0_ADDR_END Region address register 0x8 0x20 0xFFFFFFFF REGION0_ADDR_END End address of region0 0 32 read-write REGION0_PMS_ATTR Region access authority attribute register 0xC 0x20 REGION0_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write REGION0_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write REGION0_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write REGION0_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write REGION0_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write REGION0_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write REGION0_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write REGION0_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write REGION0_R2_PMS_R Region read authority in REE_MODE2 10 1 read-write REGION1_ADDR_START Region address register 0x10 0x20 REGION1_ADDR_START Start address of region1 0 32 read-write REGION1_ADDR_END Region address register 0x14 0x20 0xFFFFFFFF REGION1_ADDR_END End address of region1 0 32 read-write REGION1_PMS_ATTR Region access authority attribute register 0x18 0x20 REGION1_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write REGION1_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write REGION1_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write REGION1_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write REGION1_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write REGION1_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write REGION1_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write REGION1_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write REGION1_R2_PMS_R Region read authority in REE_MODE2 10 1 read-write REGION2_ADDR_START Region address register 0x1C 0x20 REGION2_ADDR_START Start address of region2 0 32 read-write REGION2_ADDR_END Region address register 0x20 0x20 0xFFFFFFFF REGION2_ADDR_END End address of region2 0 32 read-write REGION2_PMS_ATTR Region access authority attribute register 0x24 0x20 REGION2_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write REGION2_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write REGION2_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write REGION2_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write REGION2_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write REGION2_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write REGION2_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write REGION2_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write REGION2_R2_PMS_R Region read authority in REE_MODE2 10 1 read-write REGION3_ADDR_START Region address register 0x28 0x20 REGION3_ADDR_START Start address of region3 0 32 read-write REGION3_ADDR_END Region address register 0x2C 0x20 0xFFFFFFFF REGION3_ADDR_END End address of region3 0 32 read-write REGION3_PMS_ATTR Region access authority attribute register 0x30 0x20 REGION3_R0_PMS_X Region execute authority in REE_MODE0 0 1 read-write REGION3_R0_PMS_W Region write authority in REE_MODE0 1 1 read-write REGION3_R0_PMS_R Region read authority in REE_MODE0 2 1 read-write REGION3_R1_PMS_X Region execute authority in REE_MODE1 4 1 read-write REGION3_R1_PMS_W Region write authority in REE_MODE1 5 1 read-write REGION3_R1_PMS_R Region read authority in REE_MODE1 6 1 read-write REGION3_R2_PMS_X Region execute authority in REE_MODE2 8 1 read-write REGION3_R2_PMS_W Region write authority in REE_MODE2 9 1 read-write REGION3_R2_PMS_R Region read authority in REE_MODE2 10 1 read-write FUNC_CTRL PMS function control register 0xC4 0x20 0x00000003 M0_PMS_FUNC_EN PMS M0 function enable 0 1 read-write M1_PMS_FUNC_EN PMS M1 function enable 1 1 read-write M0_STATUS M0 status register 0xC8 0x20 M0_EXCEPTION_STATUS Exception status 0 2 read-only M0_STATUS_CLR M0 status clear register 0xCC 0x20 M0_REGION_STATUS_CLR Clear exception status 0 1 write-only M0_EXCEPTION_INFO0 M0 exception_info0 register 0xD0 0x20 M0_EXCEPTION_REGION Exception region 0 4 read-only M0_EXCEPTION_MODE Exception mode 16 2 read-only M0_EXCEPTION_ID Exception id information 18 5 read-only M0_EXCEPTION_INFO1 M0 exception_info1 register 0xD4 0x20 M0_EXCEPTION_ADDR Exception addr 0 32 read-only M1_STATUS M1 status register 0xD8 0x20 M1_EXCEPTION_STATUS Exception status 0 2 read-only M1_STATUS_CLR M1 status clear register 0xDC 0x20 M1_REGION_STATUS_CLR Clear exception status 0 1 write-only M1_EXCEPTION_INFO0 M1 exception_info0 register 0xE0 0x20 M1_EXCEPTION_REGION Exception region 0 4 read-only M1_EXCEPTION_MODE Exception mode 16 2 read-only M1_EXCEPTION_ID Exception id information 18 5 read-only M1_EXCEPTION_INFO1 M1 exception_info1 register 0xE4 0x20 M1_EXCEPTION_ADDR Exception addr 0 32 read-only INT_EN APM interrupt enable register 0xE8 0x20 M0_APM_INT_EN APM M0 interrupt enable 0 1 read-write M1_APM_INT_EN APM M1 interrupt enable 1 1 read-write CLOCK_GATE clock gating register 0xEC 0x20 0x00000001 CLK_EN reg_clk_en 0 1 read-write DATE Version register 0xFC 0x20 0x02205240 DATE reg_date 0 28 read-write LP_CLKRST LP_CLKRST Peripheral LP_CLKRST 0x600B0400 0x0 0x34 registers LP_CLK_CONF need_des 0x0 0x20 0x00000004 SLOW_CLK_SEL need_des 0 2 read-write FAST_CLK_SEL need_des 2 1 read-write LP_PERI_DIV_NUM need_des 3 8 read-write LP_CLK_PO_EN need_des 0x4 0x20 0x000007FF AON_SLOW_OEN need_des 0 1 read-write AON_FAST_OEN need_des 1 1 read-write SOSC_OEN need_des 2 1 read-write FOSC_OEN need_des 3 1 read-write OSC32K_OEN need_des 4 1 read-write XTAL32K_OEN need_des 5 1 read-write CORE_EFUSE_OEN need_des 6 1 read-write SLOW_OEN need_des 7 1 read-write FAST_OEN need_des 8 1 read-write RNG_OEN need_des 9 1 read-write LPBUS_OEN need_des 10 1 read-write LP_CLK_EN need_des 0x8 0x20 FAST_ORI_GATE need_des 31 1 read-write LP_RST_EN need_des 0xC 0x20 AON_EFUSE_CORE_RESET_EN need_des 28 1 read-write LP_TIMER_RESET_EN need_des 29 1 read-write WDT_RESET_EN need_des 30 1 read-write ANA_PERI_RESET_EN need_des 31 1 read-write RESET_CAUSE need_des 0x10 0x20 0x00000020 RESET_CAUSE need_des 0 5 read-only CORE0_RESET_FLAG need_des 5 1 read-only CORE0_RESET_CAUSE_CLR need_des 29 1 write-only CORE0_RESET_FLAG_SET need_des 30 1 write-only CORE0_RESET_FLAG_CLR need_des 31 1 write-only CPU_RESET need_des 0x14 0x20 0x04400000 RTC_WDT_CPU_RESET_LENGTH need_des 22 3 read-write RTC_WDT_CPU_RESET_EN need_des 25 1 read-write CPU_STALL_WAIT need_des 26 5 read-write CPU_STALL_EN need_des 31 1 read-write FOSC_CNTL need_des 0x18 0x20 0x2B000000 FOSC_DFREQ need_des 22 10 read-write RC32K_CNTL need_des 0x1C 0x20 0x2B000000 RC32K_DFREQ need_des 22 10 read-write CLK_TO_HP need_des 0x20 0x20 0xF0000000 ICG_HP_XTAL32K need_des 28 1 read-write ICG_HP_SOSC need_des 29 1 read-write ICG_HP_OSC32K need_des 30 1 read-write ICG_HP_FOSC need_des 31 1 read-write LPMEM_FORCE need_des 0x24 0x20 LPMEM_CLK_FORCE_ON need_des 31 1 read-write LPPERI need_des 0x28 0x20 LP_I2C_CLK_SEL need_des 30 1 read-write LP_UART_CLK_SEL need_des 31 1 read-write XTAL32K need_des 0x2C 0x20 0x66C00000 DRES_XTAL32K need_des 22 3 read-write DGM_XTAL32K need_des 25 3 read-write DBUF_XTAL32K need_des 28 1 read-write DAC_XTAL32K need_des 29 3 read-write DATE need_des 0x3FC 0x20 0x02206090 CLKRST_DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write LP_I2C_ANA_MST LP_I2C_ANA_MST Peripheral LP_I2C_ANA_MST 0x600B2400 0x0 0x1C registers I2C0_CTRL need_des 0x0 0x20 LP_I2C_ANA_MAST_I2C0_CTRL need_des 0 25 read-write LP_I2C_ANA_MAST_I2C0_BUSY need_des 25 1 read-only I2C0_CONF need_des 0x4 0x20 0x07000000 LP_I2C_ANA_MAST_I2C0_CONF need_des 0 24 read-write LP_I2C_ANA_MAST_I2C0_STATUS reserved 24 8 read-only I2C0_DATA need_des 0x8 0x20 0x00000900 LP_I2C_ANA_MAST_I2C0_RDATA need_des 0 8 read-only LP_I2C_ANA_MAST_I2C0_CLK_SEL need_des 8 3 read-write LP_I2C_ANA_MAST_I2C_MST_SEL need des 11 1 read-write ANA_CONF1 need_des 0xC 0x20 LP_I2C_ANA_MAST_ANA_CONF1 need_des 0 24 read-write NOUSE need_des 0x10 0x20 LP_I2C_ANA_MAST_I2C_MST_NOUSE need_des 0 32 read-write DEVICE_EN need_des 0x14 0x20 LP_I2C_ANA_MAST_I2C_DEVICE_EN need_des 0 12 read-write DATE need_des 0x3FC 0x20 0x02007301 LP_I2C_ANA_MAST_I2C_MAT_DATE need_des 0 28 read-write LP_I2C_ANA_MAST_I2C_MAT_CLK_EN need_des 28 1 read-write LP_IO_MUX Low-power Input/Output Multiplexer LP_IO 0x600B2000 0x0 0x7C registers OUT_DATA need des 0x0 0x20 LP_GPIO_OUT_DATA set lp gpio output data 0 8 read-write OUT_DATA_W1TS need des 0x4 0x20 LP_GPIO_OUT_DATA_W1TS set one time output data 0 8 write-only OUT_DATA_W1TC need des 0x8 0x20 LP_GPIO_OUT_DATA_W1TC clear one time output data 0 8 write-only OUT_ENABLE need des 0xC 0x20 LP_GPIO_ENABLE set lp gpio output data 0 8 read-write OUT_ENABLE_W1TS need des 0x10 0x20 LP_GPIO_ENABLE_W1TS set one time output data 0 8 write-only OUT_ENABLE_W1TC need des 0x14 0x20 LP_GPIO_ENABLE_W1TC clear one time output data 0 8 write-only STATUS need des 0x18 0x20 LP_GPIO_STATUS_INTERRUPT set lp gpio output data 0 8 read-write STATUS_W1TS need des 0x1C 0x20 LP_GPIO_STATUS_W1TS set one time output data 0 8 write-only STATUS_W1TC need des 0x20 0x20 LP_GPIO_STATUS_W1TC clear one time output data 0 8 write-only IN need des 0x24 0x20 LP_GPIO_IN_DATA_NEXT need des 0 8 read-only PIN0 need des 0x28 0x20 LP_GPIO0_SYNC_BYPASS need des 0 2 read-write LP_GPIO0_PAD_DRIVER need des 2 1 read-write LP_GPIO0_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO0_INT_TYPE need des 7 3 read-write LP_GPIO0_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO0_FILTER_EN need des 11 1 read-write PIN1 need des 0x2C 0x20 LP_GPIO1_SYNC_BYPASS need des 0 2 read-write LP_GPIO1_PAD_DRIVER need des 2 1 read-write LP_GPIO1_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO1_INT_TYPE need des 7 3 read-write LP_GPIO1_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO1_FILTER_EN need des 11 1 read-write PIN2 need des 0x30 0x20 LP_GPIO2_SYNC_BYPASS need des 0 2 read-write LP_GPIO2_PAD_DRIVER need des 2 1 read-write LP_GPIO2_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO2_INT_TYPE need des 7 3 read-write LP_GPIO2_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO2_FILTER_EN need des 11 1 read-write PIN3 need des 0x34 0x20 LP_GPIO3_SYNC_BYPASS need des 0 2 read-write LP_GPIO3_PAD_DRIVER need des 2 1 read-write LP_GPIO3_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO3_INT_TYPE need des 7 3 read-write LP_GPIO3_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO3_FILTER_EN need des 11 1 read-write PIN4 need des 0x38 0x20 LP_GPIO4_SYNC_BYPASS need des 0 2 read-write LP_GPIO4_PAD_DRIVER need des 2 1 read-write LP_GPIO4_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO4_INT_TYPE need des 7 3 read-write LP_GPIO4_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO4_FILTER_EN need des 11 1 read-write PIN5 need des 0x3C 0x20 LP_GPIO5_SYNC_BYPASS need des 0 2 read-write LP_GPIO5_PAD_DRIVER need des 2 1 read-write LP_GPIO5_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO5_INT_TYPE need des 7 3 read-write LP_GPIO5_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO5_FILTER_EN need des 11 1 read-write PIN6 need des 0x40 0x20 LP_GPIO6_SYNC_BYPASS need des 0 2 read-write LP_GPIO6_PAD_DRIVER need des 2 1 read-write LP_GPIO6_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO6_INT_TYPE need des 7 3 read-write LP_GPIO6_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO6_FILTER_EN need des 11 1 read-write PIN7 need des 0x44 0x20 LP_GPIO7_SYNC_BYPASS need des 0 2 read-write LP_GPIO7_PAD_DRIVER need des 2 1 read-write LP_GPIO7_EDGE_WAKEUP_CLR need des 3 1 write-only LP_GPIO7_INT_TYPE need des 7 3 read-write LP_GPIO7_WAKEUP_ENABLE need des 10 1 read-write LP_GPIO7_FILTER_EN need des 11 1 read-write GPIO0 need des 0x48 0x20 LP_GPIO0_MCU_OE need des 0 1 read-write LP_GPIO0_SLP_SEL need des 1 1 read-write LP_GPIO0_MCU_WPD need des 2 1 read-write LP_GPIO0_MCU_WPU need des 3 1 read-write LP_GPIO0_MCU_IE need des 4 1 read-write LP_GPIO0_MCU_DRV need des 5 2 read-write LP_GPIO0_FUN_WPD need des 7 1 read-write LP_GPIO0_FUN_WPU need des 8 1 read-write LP_GPIO0_FUN_IE need des 9 1 read-write LP_GPIO0_FUN_DRV need des 10 2 read-write LP_GPIO0_MCU_SEL need des 12 3 read-write GPIO1 need des 0x4C 0x20 LP_GPIO1_MCU_OE need des 0 1 read-write LP_GPIO1_SLP_SEL need des 1 1 read-write LP_GPIO1_MCU_WPD need des 2 1 read-write LP_GPIO1_MCU_WPU need des 3 1 read-write LP_GPIO1_MCU_IE need des 4 1 read-write LP_GPIO1_MCU_DRV need des 5 2 read-write LP_GPIO1_FUN_WPD need des 7 1 read-write LP_GPIO1_FUN_WPU need des 8 1 read-write LP_GPIO1_FUN_IE need des 9 1 read-write LP_GPIO1_FUN_DRV need des 10 2 read-write LP_GPIO1_MCU_SEL need des 12 3 read-write GPIO2 need des 0x50 0x20 LP_GPIO2_MCU_OE need des 0 1 read-write LP_GPIO2_SLP_SEL need des 1 1 read-write LP_GPIO2_MCU_WPD need des 2 1 read-write LP_GPIO2_MCU_WPU need des 3 1 read-write LP_GPIO2_MCU_IE need des 4 1 read-write LP_GPIO2_MCU_DRV need des 5 2 read-write LP_GPIO2_FUN_WPD need des 7 1 read-write LP_GPIO2_FUN_WPU need des 8 1 read-write LP_GPIO2_FUN_IE need des 9 1 read-write LP_GPIO2_FUN_DRV need des 10 2 read-write LP_GPIO2_MCU_SEL need des 12 3 read-write GPIO3 need des 0x54 0x20 LP_GPIO3_MCU_OE need des 0 1 read-write LP_GPIO3_SLP_SEL need des 1 1 read-write LP_GPIO3_MCU_WPD need des 2 1 read-write LP_GPIO3_MCU_WPU need des 3 1 read-write LP_GPIO3_MCU_IE need des 4 1 read-write LP_GPIO3_MCU_DRV need des 5 2 read-write LP_GPIO3_FUN_WPD need des 7 1 read-write LP_GPIO3_FUN_WPU need des 8 1 read-write LP_GPIO3_FUN_IE need des 9 1 read-write LP_GPIO3_FUN_DRV need des 10 2 read-write LP_GPIO3_MCU_SEL need des 12 3 read-write GPIO4 need des 0x58 0x20 LP_GPIO4_MCU_OE need des 0 1 read-write LP_GPIO4_SLP_SEL need des 1 1 read-write LP_GPIO4_MCU_WPD need des 2 1 read-write LP_GPIO4_MCU_WPU need des 3 1 read-write LP_GPIO4_MCU_IE need des 4 1 read-write LP_GPIO4_MCU_DRV need des 5 2 read-write LP_GPIO4_FUN_WPD need des 7 1 read-write LP_GPIO4_FUN_WPU need des 8 1 read-write LP_GPIO4_FUN_IE need des 9 1 read-write LP_GPIO4_FUN_DRV need des 10 2 read-write LP_GPIO4_MCU_SEL need des 12 3 read-write GPIO5 need des 0x5C 0x20 LP_GPIO5_MCU_OE need des 0 1 read-write LP_GPIO5_SLP_SEL need des 1 1 read-write LP_GPIO5_MCU_WPD need des 2 1 read-write LP_GPIO5_MCU_WPU need des 3 1 read-write LP_GPIO5_MCU_IE need des 4 1 read-write LP_GPIO5_MCU_DRV need des 5 2 read-write LP_GPIO5_FUN_WPD need des 7 1 read-write LP_GPIO5_FUN_WPU need des 8 1 read-write LP_GPIO5_FUN_IE need des 9 1 read-write LP_GPIO5_FUN_DRV need des 10 2 read-write LP_GPIO5_MCU_SEL need des 12 3 read-write GPIO6 need des 0x60 0x20 LP_GPIO6_MCU_OE need des 0 1 read-write LP_GPIO6_SLP_SEL need des 1 1 read-write LP_GPIO6_MCU_WPD need des 2 1 read-write LP_GPIO6_MCU_WPU need des 3 1 read-write LP_GPIO6_MCU_IE need des 4 1 read-write LP_GPIO6_MCU_DRV need des 5 2 read-write LP_GPIO6_FUN_WPD need des 7 1 read-write LP_GPIO6_FUN_WPU need des 8 1 read-write LP_GPIO6_FUN_IE need des 9 1 read-write LP_GPIO6_FUN_DRV need des 10 2 read-write LP_GPIO6_MCU_SEL need des 12 3 read-write GPIO7 need des 0x64 0x20 LP_GPIO7_MCU_OE need des 0 1 read-write LP_GPIO7_SLP_SEL need des 1 1 read-write LP_GPIO7_MCU_WPD need des 2 1 read-write LP_GPIO7_MCU_WPU need des 3 1 read-write LP_GPIO7_MCU_IE need des 4 1 read-write LP_GPIO7_MCU_DRV need des 5 2 read-write LP_GPIO7_FUN_WPD need des 7 1 read-write LP_GPIO7_FUN_WPU need des 8 1 read-write LP_GPIO7_FUN_IE need des 9 1 read-write LP_GPIO7_FUN_DRV need des 10 2 read-write LP_GPIO7_MCU_SEL need des 12 3 read-write STATUS_INTERRUPT need des 0x68 0x20 LP_GPIO_STATUS_INTERRUPT_NEXT need des 0 8 read-only DEBUG_SEL0 need des 0x6C 0x20 LP_DEBUG_SEL0 need des 0 7 read-write LP_DEBUG_SEL1 need des 7 7 read-write LP_DEBUG_SEL2 need des 14 7 read-write LP_DEBUG_SEL3 need des 21 7 read-write DEBUG_SEL1 need des 0x70 0x20 LP_DEBUG_SEL4 need des 0 7 read-write LPI2C need des 0x74 0x20 0xC0000000 LP_I2C_SDA_IE need des 30 1 read-write LP_I2C_SCL_IE need des 31 1 read-write DATE need des 0x3FC 0x20 0x02202100 LP_IO_DATE need des 0 31 read-write CLK_EN need des 31 1 read-write LP_TEE Low-power Trusted Execution Environment LP_TEE 0x600B3400 0x0 0x10 registers M0_MODE_CTRL Tee mode control register 0x0 0x20 0x00000003 M0_MODE M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write CLOCK_GATE Clock gating register 0x4 0x20 0x00000001 CLK_EN reg_clk_en 0 1 read-write FORCE_ACC_HP need_des 0x90 0x20 LP_AON_FORCE_ACC_HPMEM_EN need_des 0 1 read-write DATE Version register 0xFC 0x20 0x02205270 DATE reg_tee_date 0 28 read-write LP_TIMER Low-power Timer LP_TIMER 0x600B0C00 0x0 0x4C registers LP_TIMER 7 TAR0_LOW need_des 0x0 0x20 MAIN_TIMER_TAR_LOW0 need_des 0 32 read-write TAR0_HIGH need_des 0x4 0x20 MAIN_TIMER_TAR_HIGH0 need_des 0 16 read-write MAIN_TIMER_TAR_EN0 need_des 31 1 write-only TAR1_LOW need_des 0x8 0x20 MAIN_TIMER_TAR_LOW1 need_des 0 32 read-write TAR1_HIGH need_des 0xC 0x20 MAIN_TIMER_TAR_HIGH1 need_des 0 16 read-write MAIN_TIMER_TAR_EN1 need_des 31 1 write-only UPDATE need_des 0x10 0x20 MAIN_TIMER_UPDATE need_des 28 1 write-only MAIN_TIMER_XTAL_OFF need_des 29 1 read-write MAIN_TIMER_SYS_STALL need_des 30 1 read-write MAIN_TIMER_SYS_RST need_des 31 1 read-write MAIN_BUF0_LOW need_des 0x14 0x20 MAIN_TIMER_BUF0_LOW need_des 0 32 read-only MAIN_BUF0_HIGH need_des 0x18 0x20 MAIN_TIMER_BUF0_HIGH need_des 0 16 read-only MAIN_BUF1_LOW need_des 0x1C 0x20 MAIN_TIMER_BUF1_LOW need_des 0 32 read-only MAIN_BUF1_HIGH need_des 0x20 0x20 MAIN_TIMER_BUF1_HIGH need_des 0 16 read-only MAIN_OVERFLOW need_des 0x24 0x20 MAIN_TIMER_ALARM_LOAD need_des 31 1 write-only INT_RAW need_des 0x28 0x20 OVERFLOW_RAW need_des 30 1 read-write SOC_WAKEUP_INT_RAW need_des 31 1 read-write INT_ST need_des 0x2C 0x20 OVERFLOW_ST need_des 30 1 read-only SOC_WAKEUP_INT_ST need_des 31 1 read-only INT_ENA need_des 0x30 0x20 OVERFLOW_ENA need_des 30 1 read-write SOC_WAKEUP_INT_ENA need_des 31 1 read-write INT_CLR need_des 0x34 0x20 OVERFLOW_CLR need_des 30 1 write-only SOC_WAKEUP_INT_CLR need_des 31 1 write-only LP_INT_RAW need_des 0x38 0x20 MAIN_TIMER_OVERFLOW_LP_INT_RAW need_des 30 1 read-write MAIN_TIMER_LP_INT_RAW need_des 31 1 read-write LP_INT_ST need_des 0x3C 0x20 MAIN_TIMER_OVERFLOW_LP_INT_ST need_des 30 1 read-only MAIN_TIMER_LP_INT_ST need_des 31 1 read-only LP_INT_ENA need_des 0x40 0x20 MAIN_TIMER_OVERFLOW_LP_INT_ENA need_des 30 1 read-write MAIN_TIMER_LP_INT_ENA need_des 31 1 read-write LP_INT_CLR need_des 0x44 0x20 MAIN_TIMER_OVERFLOW_LP_INT_CLR need_des 30 1 write-only MAIN_TIMER_LP_INT_CLR need_des 31 1 write-only DATE need_des 0x3FC 0x20 0x02111150 DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write LP_UART Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller LP_UART 0x600B1400 0x0 0x84 registers LP_UART 16 FIFO FIFO data register 0x0 0x20 RXFIFO_RD_BYTE UART 0 accesses FIFO via this register. 0 8 read-only INT_RAW Raw interrupt status 0x4 0x20 0x00000002 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 read-write TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 read-write PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 read-write FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 read-write RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 read-write DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 read-write CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 read-write BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 read-write RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 read-write SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 read-write SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 read-write GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 read-write TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. 12 1 read-write TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 read-write TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 read-write AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 read-write WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 read-write INT_ST Masked interrupt status 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 14 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. 18 1 read-only WAKEUP_INT_ST This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for rxfifo_full_int_st register. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for txfifo_empty_int_st register. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for parity_err_int_st register. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for frm_err_int_st register. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for dsr_chg_int_st register. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for cts_chg_int_st register. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for brk_det_int_st register. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write SW_XON_INT_ENA This is the enable bit for sw_xon_int_st register. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for sw_xoff_int_st register. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for glitch_det_int_st register. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for tx_brk_done_int_st register. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for tx_brk_idle_done_int_st register. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for tx_done_int_st register. 14 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for at_cmd_char_det_int_st register. 18 1 read-write WAKEUP_INT_ENA This is the enable bit for uart_wakeup_int_st register. 19 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear parity_err_int_raw interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear frm_err_int_raw interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear rxfifo_ovf_int_raw interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear the dsr_chg_int_raw interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear the cts_chg_int_raw interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear the brk_det_int_raw interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear the rxfifo_tout_int_raw interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear the sw_xoff_int_raw interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear the glitch_det_int_raw interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear the tx_done_int_raw interrupt. 14 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the at_cmd_char_det_int_raw interrupt. 18 1 write-only WAKEUP_INT_CLR Set this bit to clear the uart_wakeup_int_raw interrupt. 19 1 write-only CLKDIV_SYNC Clock divider configuration 0x14 0x20 0x000002B6 CLKDIV The integral part of the frequency divider factor. 0 12 read-write CLKDIV_FRAG The decimal part of the frequency divider factor. 20 4 read-write RX_FILT Rx Filter configuration 0x18 0x20 0x00000008 GLITCH_FILT when input pulse width is lower than this value the pulse is ignored. 0 8 read-write GLITCH_FILT_EN Set this bit to enable Rx signal filter. 8 1 read-write STATUS UART status register 0x1C 0x20 0xE000C000 RXFIFO_CNT Stores the byte number of valid data in Rx-FIFO. 3 5 read-only DSRN The register represent the level value of the internal uart dsr signal. 13 1 read-only CTSN This register represent the level value of the internal uart cts signal. 14 1 read-only RXD This register represent the level value of the internal uart rxd signal. 15 1 read-only TXFIFO_CNT Stores the byte number of data in Tx-FIFO. 19 5 read-only DTRN This bit represents the level of the internal uart dtr signal. 29 1 read-only RTSN This bit represents the level of the internal uart rts signal. 30 1 read-only TXD This bit represents the level of the internal uart txd signal. 31 1 read-only CONF0_SYNC Configuration register 0 0x20 0x20 0x0010001C PARITY This register is used to configure the parity check mode. 0 1 read-write PARITY_EN Set this bit to enable uart parity check. 1 1 read-write BIT_NUM This register is used to set the length of data. 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 4 2 read-write TXD_BRK Set this bit to enbale transmitter to send NULL when the process of sending data is done. 6 1 read-write LOOPBACK Set this bit to enable uart loopback test mode. 12 1 read-write TX_FLOW_EN Set this bit to enable flow control function for transmitter. 13 1 read-write RXD_INV Set this bit to inverse the level value of uart rxd signal. 15 1 read-write TXD_INV Set this bit to inverse the level value of uart txd signal. 16 1 read-write DIS_RX_DAT_OVF Disable UART Rx data overflow detect. 17 1 read-write ERR_WR_MASK 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. 18 1 read-write MEM_CLK_EN UART memory clock gate enable signal. 20 1 read-write SW_RTS This register is used to configure the software rts signal which is used in software flow control. 21 1 read-write RXFIFO_RST Set this bit to reset the uart receive-FIFO. 22 1 read-write TXFIFO_RST Set this bit to reset the uart transmit-FIFO. 23 1 read-write CONF1 Configuration register 1 0x24 0x20 0x00006060 RXFIFO_FULL_THRHD It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. 3 5 read-write TXFIFO_EMPTY_THRHD It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. 11 5 read-write CTS_INV Set this bit to inverse the level value of uart cts signal. 16 1 read-write DSR_INV Set this bit to inverse the level value of uart dsr signal. 17 1 read-write RTS_INV Set this bit to inverse the level value of uart rts signal. 18 1 read-write DTR_INV Set this bit to inverse the level value of uart dtr signal. 19 1 read-write SW_DTR This register is used to configure the software dtr signal which is used in software flow control. 20 1 read-write CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 21 1 read-write HWFC_CONF_SYNC Hardware flow-control configuration 0x2C 0x20 RX_FLOW_THRHD This register is used to configure the maximum amount of data that can be received when hardware flow control works. 3 5 read-write RX_FLOW_EN This is the flow enable bit for UART receiver. 8 1 read-write SLEEP_CONF0 UART sleep configure register 0 0x30 0x20 WK_CHAR1 This register restores the specified wake up char1 to wake up 0 8 read-write WK_CHAR2 This register restores the specified wake up char2 to wake up 8 8 read-write WK_CHAR3 This register restores the specified wake up char3 to wake up 16 8 read-write WK_CHAR4 This register restores the specified wake up char4 to wake up 24 8 read-write SLEEP_CONF1 UART sleep configure register 1 0x34 0x20 WK_CHAR0 This register restores the specified char0 to wake up 0 8 read-write SLEEP_CONF2 UART sleep configure register 2 0x38 0x20 0x001420F0 ACTIVE_THRESHOLD The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. 0 10 read-write RX_WAKE_UP_THRHD In wake up mode 1 this field is used to set the received data number threshold to wake up chip. 13 5 read-write WK_CHAR_NUM This register is used to select number of wake up char. 18 3 read-write WK_CHAR_MASK This register is used to mask wake up char. 21 5 read-write WK_MODE_SEL This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than 26 2 read-write SWFC_CONF0_SYNC Software flow-control character configuration 0x3C 0x20 0x00001311 XON_CHAR This register stores the Xon flow control char. 0 8 read-write XOFF_CHAR This register stores the Xoff flow control char. 8 8 read-write XON_XOFF_STILL_SEND In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. 16 1 read-write SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. 17 1 read-write XONOFF_DEL Set this bit to remove flow control char from the received data. 18 1 read-write FORCE_XON Set this bit to enable the transmitter to go on sending data. 19 1 read-write FORCE_XOFF Set this bit to stop the transmitter from sending data. 20 1 read-write SEND_XON Set this bit to send Xon char. It is cleared by hardware automatically. 21 1 read-write SEND_XOFF Set this bit to send Xoff char. It is cleared by hardware automatically. 22 1 read-write SWFC_CONF1 Software flow-control character configuration 0x40 0x20 0x00006000 XON_THRESHOLD When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. 3 5 read-write XOFF_THRESHOLD When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. 11 5 read-write TXBRK_CONF_SYNC Tx Break character configuration 0x44 0x20 0x0000000A TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. 0 8 read-write IDLE_CONF_SYNC Frame-end idle configuration 0x48 0x20 0x00040100 RX_IDLE_THRHD It will produce frame end signal when receiver takes more time to receive one byte data than this register value. 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers. 10 10 read-write RS485_CONF_SYNC RS485 mode configuration 0x4C 0x20 DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write AT_CMD_PRECNT_SYNC Pre-sequence timing configuration 0x50 0x20 0x00000901 PRE_IDLE_NUM This register is used to configure the idle duration time before the first at_cmd is received by receiver. 0 16 read-write AT_CMD_POSTCNT_SYNC Post-sequence timing configuration 0x54 0x20 0x00000901 POST_IDLE_NUM This register is used to configure the duration time between the last at_cmd and the next data. 0 16 read-write AT_CMD_GAPTOUT_SYNC Timeout configuration 0x58 0x20 0x0000000B RX_GAP_TOUT This register is used to configure the duration time between the at_cmd chars. 0 16 read-write AT_CMD_CHAR_SYNC AT escape sequence detection configuration 0x5C 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of at_cmd char. 0 8 read-write CHAR_NUM This register is used to configure the num of continuous at_cmd chars received by receiver. 8 8 read-write MEM_CONF UART memory power configuration 0x60 0x20 MEM_FORCE_PD Set this bit to force power down UART memory. 25 1 read-write MEM_FORCE_PU Set this bit to force power up UART memory. 26 1 read-write TOUT_CONF_SYNC UART threshold and allocation configuration 0x64 0x20 0x00000028 RX_TOUT_EN This is the enble bit for uart receiver's timeout function. 0 1 read-write RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control works. 1 1 read-write RX_TOUT_THRHD This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. 2 10 read-write MEM_TX_STATUS Tx-SRAM write and read offset address. 0x68 0x20 TX_SRAM_WADDR This register stores the offset write address in Tx-SRAM. 3 5 read-only TX_SRAM_RADDR This register stores the offset read address in Tx-SRAM. 12 5 read-only MEM_RX_STATUS Rx-SRAM write and read offset address. 0x6C 0x20 0x00010080 RX_SRAM_RADDR This register stores the offset read address in RX-SRAM. 3 5 read-only RX_SRAM_WADDR This register stores the offset write address in Rx-SRAM. 12 5 read-only FSM_STATUS UART transmit and receive status. 0x70 0x20 ST_URX_OUT This is the status register of receiver. 0 4 read-only ST_UTX_OUT This is the status register of transmitter. 4 4 read-only CLK_CONF UART core clock configuration 0x88 0x20 0x03701000 SCLK_DIV_B The denominator of the frequency divider factor. 0 6 read-write SCLK_DIV_A The numerator of the frequency divider factor. 6 6 read-write SCLK_DIV_NUM The integral part of the frequency divider factor. 12 8 read-write SCLK_SEL UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. 20 2 read-write SCLK_EN Set this bit to enable UART Tx/Rx clock. 22 1 read-write RST_CORE Write 1 then write 0 to this bit to reset UART Tx/Rx. 23 1 read-write TX_SCLK_EN Set this bit to enable UART Tx clock. 24 1 read-write RX_SCLK_EN Set this bit to enable UART Rx clock. 25 1 read-write TX_RST_CORE Write 1 then write 0 to this bit to reset UART Tx. 26 1 read-write RX_RST_CORE Write 1 then write 0 to this bit to reset UART Rx. 27 1 read-write DATE UART Version register 0x8C 0x20 0x02201260 DATE This is the version register. 0 32 read-write AFIFO_STATUS UART AFIFO Status 0x90 0x20 0x0000000A TX_AFIFO_FULL Full signal of APB TX AFIFO. 0 1 read-only TX_AFIFO_EMPTY Empty signal of APB TX AFIFO. 1 1 read-only RX_AFIFO_FULL Full signal of APB RX AFIFO. 2 1 read-only RX_AFIFO_EMPTY Empty signal of APB RX AFIFO. 3 1 read-only REG_UPDATE UART Registers Configuration Update register 0x98 0x20 REG_UPDATE Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. 0 1 read-write ID UART ID register 0x9C 0x20 0x00000500 ID This register is used to configure the uart_id. 0 32 read-write LP_WDT Low-power Watchdog Timer LP_WDT 0x600B1C00 0x0 0x38 registers LP_WDT 18 CONFIG0 need_des 0x0 0x20 0x00013214 WDT_CHIP_RESET_WIDTH need_des 0 8 read-write WDT_CHIP_RESET_EN need_des 8 1 read-write WDT_PAUSE_IN_SLP need_des 9 1 read-write WDT_APPCPU_RESET_EN need_des 10 1 read-write WDT_PROCPU_RESET_EN need_des 11 1 read-write WDT_FLASHBOOT_MOD_EN need_des 12 1 read-write WDT_SYS_RESET_LENGTH need_des 13 3 read-write WDT_CPU_RESET_LENGTH need_des 16 3 read-write WDT_STG3 need_des 19 3 read-write WDT_STG2 need_des 22 3 read-write WDT_STG1 need_des 25 3 read-write WDT_STG0 need_des 28 3 read-write WDT_EN need_des 31 1 read-write CONFIG1 need_des 0x4 0x20 0x00030D40 WDT_STG0_HOLD need_des 0 32 read-write CONFIG2 need_des 0x8 0x20 0x00013880 WDT_STG1_HOLD need_des 0 32 read-write CONFIG3 need_des 0xC 0x20 0x00000FFF WDT_STG2_HOLD need_des 0 32 read-write CONFIG4 need_des 0x10 0x20 0x00000FFF WDT_STG3_HOLD need_des 0 32 read-write FEED need_des 0x14 0x20 RTC_WDT_FEED need_des 31 1 write-only WPROTECT need_des 0x18 0x20 WDT_WKEY need_des 0 32 read-write SWD_CONFIG need_des 0x1C 0x20 0x12C00000 SWD_RESET_FLAG need_des 0 1 read-only SWD_AUTO_FEED_EN need_des 18 1 read-write SWD_RST_FLAG_CLR need_des 19 1 write-only SWD_SIGNAL_WIDTH need_des 20 10 read-write SWD_DISABLE need_des 30 1 read-write SWD_FEED need_des 31 1 write-only SWD_WPROTECT need_des 0x20 0x20 SWD_WKEY need_des 0 32 read-write INT_RAW need_des 0x24 0x20 SUPER_WDT_INT_RAW need_des 30 1 read-write LP_WDT_INT_RAW need_des 31 1 read-write INT_ST need_des 0x28 0x20 SUPER_WDT_INT_ST need_des 30 1 read-only LP_WDT_INT_ST need_des 31 1 read-only INT_ENA need_des 0x2C 0x20 SUPER_WDT_INT_ENA need_des 30 1 read-write LP_WDT_INT_ENA need_des 31 1 read-write INT_CLR need_des 0x30 0x20 SUPER_WDT_INT_CLR need_des 30 1 write-only LP_WDT_INT_CLR need_des 31 1 write-only DATE need_des 0x3FC 0x20 0x02112080 LP_WDT_DATE need_des 0 31 read-write CLK_EN need_des 31 1 read-write