402 lines
17 KiB
C
402 lines
17 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_ll_utils.h
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* @author MCD Application Team
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* @brief Header file of UTILS LL module.
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******************************************************************************
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* @attention
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL UTILS driver contains a set of generic APIs that can be
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used by user:
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(+) Device electronic signature
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(+) Timing functions
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(+) PLL configuration functions
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@endverbatim
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_LL_UTILS_H
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#define STM32H7xx_LL_UTILS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx.h"
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#include "stm32h7xx_ll_system.h"
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#include "stm32h7xx_ll_bus.h"
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/** @addtogroup STM32H7xx_LL_Driver
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* @{
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*/
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/** @defgroup UTILS_LL UTILS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
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* @{
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*/
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/* Max delay can be used in LL_mDelay */
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#define LL_MAX_DELAY 0xFFFFFFFFU
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/**
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* @brief Unique device ID register base address
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*/
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#define UID_BASE_ADDRESS UID_BASE
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/**
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* @brief Flash size data register base address
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*/
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#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
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/**
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* @brief Package data register base address
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*/
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#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
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* @{
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*/
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/**
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* @brief UTILS PLL structure definition
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*/
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typedef struct
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{
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uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
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This parameter must be a number between Min_Data = 0 and Max_Data = 63
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetM(). */
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uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
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This parameter must be a number between Min_Data = 4 and Max_Data = 512
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetN(). */
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uint32_t PLLP; /*!< Division for the main system clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 128
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odd division factors are not allowed
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetP(). */
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uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
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This parameter can be a value between 0 and 8191
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetFRACN(). */
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uint32_t VCO_Input; /*!< PLL clock Input range.
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This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetVCOInputRange(). */
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uint32_t VCO_Output; /*!< PLL clock Output range.
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This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetVCOOutputRange(). */
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} LL_UTILS_PLLInitTypeDef;
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/**
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* @brief UTILS System, AHB and APB buses clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
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This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetSysPrescaler(). */
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAHBPrescaler(). */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB1Prescaler(). */
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uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB2Prescaler(). */
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uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB3Prescaler(). */
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uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB4Prescaler(). */
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} LL_UTILS_ClkInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
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* @{
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*/
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/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
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* @{
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*/
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#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
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#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
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/**
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* @}
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*/
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/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
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* @{
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*/
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#if (STM32H7_DEV_ID == 0x450UL)
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#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */
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#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */
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#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
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#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
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#elif (STM32H7_DEV_ID == 0x480UL)
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#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */
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#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */
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#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */
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#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */
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#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */
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#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */
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#elif (STM32H7_DEV_ID == 0x483UL)
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#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */
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#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */
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#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */
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#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */
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#endif /* STM32H7_DEV_ID == 0x450UL */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
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* @{
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*/
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/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
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* @{
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*/
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/**
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* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
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* @retval UID[31:0]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
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}
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/**
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* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
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* @retval UID[63:32]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
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}
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/**
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* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
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* @retval UID[95:64]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
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}
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/**
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* @brief Get Flash memory size
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* @note This bitfield indicates the size of the device Flash memory expressed in
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* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
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* @retval FLASH_SIZE[15:0]: Flash memory size
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*/
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__STATIC_INLINE uint32_t LL_GetFlashSize(void)
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{
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return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
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}
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/**
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* @brief Get Package type
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
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* @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
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* @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*)
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* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*)
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*
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* (*) Packages available on some STM32H7 lines only.
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* @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
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the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
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*/
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__STATIC_INLINE uint32_t LL_GetPackageType(void)
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{
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#if defined(SYSCFG_PKGR_PKG)
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return LL_SYSCFG_GetPackage();
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#else
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return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
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#endif /* SYSCFG_PKGR_PKG */
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}
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/**
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* @}
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*/
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/** @defgroup UTILS_LL_EF_DELAY DELAY
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* @{
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*/
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/**
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* @brief This function configures the Cortex-M SysTick source of the time base.
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* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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* @note When a RTOS is used, it is recommended to avoid changing the SysTick
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* configuration by calling this function, for a delay use rather osDelay RTOS service.
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* @param Ticks Frequency of Ticks (Hz)
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* @retval None
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*/
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__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
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{
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/* Configure the SysTick to have interrupt in 1ms time base */
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SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
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}
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void LL_Init1msTick(uint32_t CPU_Frequency);
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void LL_mDelay(uint32_t Delay);
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/**
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* @}
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*/
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/** @defgroup UTILS_EF_SYSTEM SYSTEM
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* @{
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*/
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void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
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ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
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LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
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uint32_t HSEBypass,
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LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
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LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32H7xx_LL_UTILS_H */
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