903 lines
34 KiB
C
903 lines
34 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_ll_hsem.h
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* @author MCD Application Team
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* @brief Header file of HSEM LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_LL_HSEM_H
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#define STM32H7xx_LL_HSEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx.h"
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/** @addtogroup STM32H7xx_LL_Driver
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* @{
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*/
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#if defined(HSEM)
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/** @defgroup HSEM_LL HSEM
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
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* @{
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*/
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/** @defgroup HSEM_LL_EC_COREID COREID Defines
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* @{
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*/
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#define LL_HSEM_COREID_NONE 0U
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#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
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#if defined(DUAL_CORE)
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#define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
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#endif /* DUAL_CORE */
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#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT
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/**
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* @}
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*/
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/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_HSEM_ReadReg function
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* @{
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*/
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#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
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#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
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#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
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#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
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#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
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#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
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#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
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#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
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#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
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#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
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#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
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#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
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#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
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#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
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#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
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#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
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#if (HSEM_SEMID_MAX == 15)
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#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU
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#else /* HSEM_SEMID_MAX == 31 */
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#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
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#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
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#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
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#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
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#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
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#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
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#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
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#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
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#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
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#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
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#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
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#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
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#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
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#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
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#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
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#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
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#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
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#endif /* HSEM_SEMID_MAX == 15 */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
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* @{
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*/
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/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in HSEM register
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* @param __INSTANCE__ HSEM Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in HSEM register
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* @param __INSTANCE__ HSEM Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
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* @{
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*/
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/** @defgroup HSEM_LL_EF_Data_Management Data_Management
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* @{
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*/
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/**
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* @brief Return 1 if the semaphore is locked, else return 0.
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* @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
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{
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return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
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}
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/**
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* @brief Get core id.
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* @rmtoll R COREID LL_HSEM_GetCoreId
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_HSEM_COREID_NONE
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* @arg @ref LL_HSEM_COREID_CPU1
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* @arg @ref LL_HSEM_COREID_CPU2
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*/
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__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
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{
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return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
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}
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/**
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* @brief Get process id.
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* @rmtoll R PROCID LL_HSEM_GetProcessId
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @retval Process number. Value between Min_Data=0 and Max_Data=255
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*/
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__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
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{
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return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
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}
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/**
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* @brief Get the lock by writing in R register.
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* @note The R register has to be read to determined if the lock is taken.
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* @rmtoll R LOCK LL_HSEM_SetLock
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* @rmtoll R COREID LL_HSEM_SetLock
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* @rmtoll R PROCID LL_HSEM_SetLock
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @param process Process id. Value between Min_Data=0 and Max_Data=255
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
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{
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WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
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}
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/**
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* @brief Get the lock with 2-step lock.
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* @rmtoll R LOCK LL_HSEM_2StepLock
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* @rmtoll R COREID LL_HSEM_2StepLock
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* @rmtoll R PROCID LL_HSEM_2StepLock
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @param process Process id. Value between Min_Data=0 and Max_Data=255
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* @retval 1 lock fail, 0 lock successful or already locked by same process and core
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*/
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__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
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{
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WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
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return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
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}
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/**
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* @brief Get the lock with 1-step lock.
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* @rmtoll RLR LOCK LL_HSEM_1StepLock
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* @rmtoll RLR COREID LL_HSEM_1StepLock
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* @rmtoll RLR PROCID LL_HSEM_1StepLock
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @retval 1 lock fail, 0 lock successful or already locked by same core
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*/
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__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
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{
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return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
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}
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/**
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* @brief Release the lock of the semaphore.
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* @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
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* @rmtoll R LOCK LL_HSEM_ReleaseLock
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @param process Process number. Value between Min_Data=0 and Max_Data=255
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
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{
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WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
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}
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/**
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* @brief Get the lock status of the semaphore.
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* @rmtoll R LOCK LL_HSEM_GetStatus
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* @param HSEMx HSEM Instance.
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* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
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* @retval 0 semaphore is free, 1 semaphore is locked */
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__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
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{
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return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
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}
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/**
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* @brief Set the key.
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* @rmtoll KEYR KEY LL_HSEM_SetKey
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* @param HSEMx HSEM Instance.
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* @param key Key value.
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
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{
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WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
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}
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/**
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* @brief Get the key.
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* @rmtoll KEYR KEY LL_HSEM_GetKey
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* @param HSEMx HSEM Instance.
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* @retval key to unlock all semaphore from the same core
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*/
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__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx)
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{
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return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
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}
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/**
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* @brief Release all semaphore with the same core id.
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* @rmtoll CR KEY LL_HSEM_ResetAllLock
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* @rmtoll CR SEC LL_HSEM_ResetAllLock
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* @rmtoll CR PRIV LL_HSEM_ResetAllLock
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* @param HSEMx HSEM Instance.
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* @param key Key value.
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* @param core This parameter can be one of the following values:
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* @arg @ref LL_HSEM_COREID_CPU1
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* @arg @ref LL_HSEM_COREID_CPU2
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
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{
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WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
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}
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/**
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* @}
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*/
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/** @defgroup HSEM_LL_EF_IT_Management IT_Management
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* @{
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*/
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/**
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* @brief Enable interrupt.
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* @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER
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* @param HSEMx HSEM Instance.
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* @param SemaphoreMask This parameter can be a combination of the following values:
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* @arg @ref LL_HSEM_SEMAPHORE_0
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* @arg @ref LL_HSEM_SEMAPHORE_1
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* @arg @ref LL_HSEM_SEMAPHORE_2
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* @arg @ref LL_HSEM_SEMAPHORE_3
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* @arg @ref LL_HSEM_SEMAPHORE_4
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* @arg @ref LL_HSEM_SEMAPHORE_5
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* @arg @ref LL_HSEM_SEMAPHORE_6
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* @arg @ref LL_HSEM_SEMAPHORE_7
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* @arg @ref LL_HSEM_SEMAPHORE_8
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* @arg @ref LL_HSEM_SEMAPHORE_9
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* @arg @ref LL_HSEM_SEMAPHORE_10
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* @arg @ref LL_HSEM_SEMAPHORE_11
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* @arg @ref LL_HSEM_SEMAPHORE_12
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* @arg @ref LL_HSEM_SEMAPHORE_13
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* @arg @ref LL_HSEM_SEMAPHORE_14
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* @arg @ref LL_HSEM_SEMAPHORE_15
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* @arg @ref LL_HSEM_SEMAPHORE_16
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* @arg @ref LL_HSEM_SEMAPHORE_17
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* @arg @ref LL_HSEM_SEMAPHORE_18
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* @arg @ref LL_HSEM_SEMAPHORE_19
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* @arg @ref LL_HSEM_SEMAPHORE_20
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* @arg @ref LL_HSEM_SEMAPHORE_21
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* @arg @ref LL_HSEM_SEMAPHORE_22
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* @arg @ref LL_HSEM_SEMAPHORE_23
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* @arg @ref LL_HSEM_SEMAPHORE_24
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* @arg @ref LL_HSEM_SEMAPHORE_25
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* @arg @ref LL_HSEM_SEMAPHORE_26
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* @arg @ref LL_HSEM_SEMAPHORE_27
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* @arg @ref LL_HSEM_SEMAPHORE_28
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* @arg @ref LL_HSEM_SEMAPHORE_29
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* @arg @ref LL_HSEM_SEMAPHORE_30
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* @arg @ref LL_HSEM_SEMAPHORE_31
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* @arg @ref LL_HSEM_SEMAPHORE_ALL
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* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
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* depends on devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
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{
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SET_BIT(HSEMx->C1IER, SemaphoreMask);
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}
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/**
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* @brief Disable interrupt.
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* @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER
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* @param HSEMx HSEM Instance.
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* @param SemaphoreMask This parameter can be a combination of the following values:
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* @arg @ref LL_HSEM_SEMAPHORE_0
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* @arg @ref LL_HSEM_SEMAPHORE_1
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* @arg @ref LL_HSEM_SEMAPHORE_2
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* @arg @ref LL_HSEM_SEMAPHORE_3
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* @arg @ref LL_HSEM_SEMAPHORE_4
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* @arg @ref LL_HSEM_SEMAPHORE_5
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* @arg @ref LL_HSEM_SEMAPHORE_6
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* @arg @ref LL_HSEM_SEMAPHORE_7
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* @arg @ref LL_HSEM_SEMAPHORE_8
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* @arg @ref LL_HSEM_SEMAPHORE_9
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* @arg @ref LL_HSEM_SEMAPHORE_10
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* @arg @ref LL_HSEM_SEMAPHORE_11
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* @arg @ref LL_HSEM_SEMAPHORE_12
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* @arg @ref LL_HSEM_SEMAPHORE_13
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* @arg @ref LL_HSEM_SEMAPHORE_14
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* @arg @ref LL_HSEM_SEMAPHORE_15
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* @arg @ref LL_HSEM_SEMAPHORE_16
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* @arg @ref LL_HSEM_SEMAPHORE_17
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* @arg @ref LL_HSEM_SEMAPHORE_18
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* @arg @ref LL_HSEM_SEMAPHORE_19
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* @arg @ref LL_HSEM_SEMAPHORE_20
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* @arg @ref LL_HSEM_SEMAPHORE_21
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* @arg @ref LL_HSEM_SEMAPHORE_22
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* @arg @ref LL_HSEM_SEMAPHORE_23
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* @arg @ref LL_HSEM_SEMAPHORE_24
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* @arg @ref LL_HSEM_SEMAPHORE_25
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* @arg @ref LL_HSEM_SEMAPHORE_26
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* @arg @ref LL_HSEM_SEMAPHORE_27
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* @arg @ref LL_HSEM_SEMAPHORE_28
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* @arg @ref LL_HSEM_SEMAPHORE_29
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* @arg @ref LL_HSEM_SEMAPHORE_30
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* @arg @ref LL_HSEM_SEMAPHORE_31
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* @arg @ref LL_HSEM_SEMAPHORE_ALL
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* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
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* depends on devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
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{
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CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
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}
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/**
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* @brief Check if interrupt is enabled.
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* @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
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* @param HSEMx HSEM Instance.
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* @param SemaphoreMask This parameter can be a combination of the following values:
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* @arg @ref LL_HSEM_SEMAPHORE_0
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* @arg @ref LL_HSEM_SEMAPHORE_1
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* @arg @ref LL_HSEM_SEMAPHORE_2
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* @arg @ref LL_HSEM_SEMAPHORE_3
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* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
|
|
* depends on devices.
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(DUAL_CORE)
|
|
/**
|
|
* @brief Enable interrupt.
|
|
* @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
SET_BIT(HSEMx->C2IER, SemaphoreMask);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable interrupt.
|
|
* @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if interrupt is enabled.
|
|
* @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* DUAL_CORE */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Clear interrupt status.
|
|
* @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
|
|
* depends on devices.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status from ISR register.
|
|
* @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
|
|
* depends on devices.
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status from MISR register.
|
|
* @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
|
|
* depends on devices.
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(DUAL_CORE)
|
|
/**
|
|
* @brief Clear interrupt status.
|
|
* @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
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|
* @retval None
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*/
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__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
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|
{
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|
WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
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}
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|
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|
/**
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|
* @brief Get interrupt status from ISR register.
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|
* @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR
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|
* @param HSEMx HSEM Instance.
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|
* @param SemaphoreMask This parameter can be a combination of the following values:
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|
* @arg @ref LL_HSEM_SEMAPHORE_0
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|
* @arg @ref LL_HSEM_SEMAPHORE_1
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|
* @arg @ref LL_HSEM_SEMAPHORE_2
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|
* @arg @ref LL_HSEM_SEMAPHORE_3
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|
* @arg @ref LL_HSEM_SEMAPHORE_4
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|
* @arg @ref LL_HSEM_SEMAPHORE_5
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|
* @arg @ref LL_HSEM_SEMAPHORE_6
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|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
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|
* @arg @ref LL_HSEM_SEMAPHORE_13
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|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get interrupt status from MISR register.
|
|
* @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR
|
|
* @param HSEMx HSEM Instance.
|
|
* @param SemaphoreMask This parameter can be a combination of the following values:
|
|
* @arg @ref LL_HSEM_SEMAPHORE_0
|
|
* @arg @ref LL_HSEM_SEMAPHORE_1
|
|
* @arg @ref LL_HSEM_SEMAPHORE_2
|
|
* @arg @ref LL_HSEM_SEMAPHORE_3
|
|
* @arg @ref LL_HSEM_SEMAPHORE_4
|
|
* @arg @ref LL_HSEM_SEMAPHORE_5
|
|
* @arg @ref LL_HSEM_SEMAPHORE_6
|
|
* @arg @ref LL_HSEM_SEMAPHORE_7
|
|
* @arg @ref LL_HSEM_SEMAPHORE_8
|
|
* @arg @ref LL_HSEM_SEMAPHORE_9
|
|
* @arg @ref LL_HSEM_SEMAPHORE_10
|
|
* @arg @ref LL_HSEM_SEMAPHORE_11
|
|
* @arg @ref LL_HSEM_SEMAPHORE_12
|
|
* @arg @ref LL_HSEM_SEMAPHORE_13
|
|
* @arg @ref LL_HSEM_SEMAPHORE_14
|
|
* @arg @ref LL_HSEM_SEMAPHORE_15
|
|
* @arg @ref LL_HSEM_SEMAPHORE_16
|
|
* @arg @ref LL_HSEM_SEMAPHORE_17
|
|
* @arg @ref LL_HSEM_SEMAPHORE_18
|
|
* @arg @ref LL_HSEM_SEMAPHORE_19
|
|
* @arg @ref LL_HSEM_SEMAPHORE_20
|
|
* @arg @ref LL_HSEM_SEMAPHORE_21
|
|
* @arg @ref LL_HSEM_SEMAPHORE_22
|
|
* @arg @ref LL_HSEM_SEMAPHORE_23
|
|
* @arg @ref LL_HSEM_SEMAPHORE_24
|
|
* @arg @ref LL_HSEM_SEMAPHORE_25
|
|
* @arg @ref LL_HSEM_SEMAPHORE_26
|
|
* @arg @ref LL_HSEM_SEMAPHORE_27
|
|
* @arg @ref LL_HSEM_SEMAPHORE_28
|
|
* @arg @ref LL_HSEM_SEMAPHORE_29
|
|
* @arg @ref LL_HSEM_SEMAPHORE_30
|
|
* @arg @ref LL_HSEM_SEMAPHORE_31
|
|
* @arg @ref LL_HSEM_SEMAPHORE_ALL
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
|
|
{
|
|
return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* DUAL_CORE */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined(HSEM) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32H7xx_LL_HSEM_H */
|