790 lines
37 KiB
C
790 lines
37 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_smbus.h
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* @author MCD Application Team
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* @brief Header file of SMBUS HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_HAL_SMBUS_H
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#define STM32H7xx_HAL_SMBUS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal_def.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup SMBUS
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
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* @{
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*/
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/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
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* @brief SMBUS Configuration Structure definition
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* @{
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*/
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typedef struct
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{
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uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
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This parameter calculated by referring to SMBUS initialization section
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in Reference manual */
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uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
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This parameter can be a value of @ref SMBUS_Analog_Filter */
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uint32_t OwnAddress1; /*!< Specifies the first device own address.
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This parameter can be a 7-bit or 10-bit address. */
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uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
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This parameter can be a value of @ref SMBUS_addressing_mode */
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uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
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This parameter can be a value of @ref SMBUS_dual_addressing_mode */
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uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
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This parameter can be a 7-bit address. */
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uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
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if dual addressing mode is selected
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This parameter can be a value of @ref SMBUS_own_address2_masks. */
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uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
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This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
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uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
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This parameter can be a value of @ref SMBUS_nostretch_mode */
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uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
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This parameter can be a value of @ref SMBUS_packet_error_check_mode */
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uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
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This parameter can be a value of @ref SMBUS_peripheral_mode */
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uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
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(Enable bits and different timeout values)
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This parameter calculated by referring to SMBUS initialization section
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in Reference manual */
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} SMBUS_InitTypeDef;
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/**
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* @}
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*/
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/** @defgroup HAL_state_definition HAL state definition
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* @brief HAL State definition
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* @{
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*/
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#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
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#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
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#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
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#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
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#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
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#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
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#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
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#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
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/**
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* @}
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*/
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/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
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* @brief SMBUS Error Code definition
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* @{
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*/
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#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
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#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
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#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
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#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
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#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
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#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
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#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
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#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
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#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
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#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
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#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
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#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
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#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
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/**
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* @}
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*/
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/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
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* @brief SMBUS handle Structure definition
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* @{
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*/
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#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
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typedef struct __SMBUS_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
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{
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I2C_TypeDef *Instance; /*!< SMBUS registers base address */
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SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
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uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
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uint16_t XferSize; /*!< SMBUS transfer size */
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__IO uint16_t XferCount; /*!< SMBUS transfer counter */
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__IO uint32_t XferOptions; /*!< SMBUS transfer options */
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__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
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HAL_LockTypeDef Lock; /*!< SMBUS locking object */
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__IO uint32_t State; /*!< SMBUS communication state */
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__IO uint32_t ErrorCode; /*!< SMBUS Error code */
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#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
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void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Master Tx Transfer completed callback */
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void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Master Rx Transfer completed callback */
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void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Slave Tx Transfer completed callback */
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void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Slave Rx Transfer completed callback */
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void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Listen Complete callback */
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void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Error callback */
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void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
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/*!< SMBUS Slave Address Match callback */
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void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Msp Init callback */
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void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
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/*!< SMBUS Msp DeInit callback */
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#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
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} SMBUS_HandleTypeDef;
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#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL SMBUS Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
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HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
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HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
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HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
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HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
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HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
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HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
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HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
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} HAL_SMBUS_CallbackIDTypeDef;
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/**
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* @brief HAL SMBUS Callback pointer definition
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*/
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typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
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/*!< pointer to an SMBUS callback function */
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typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
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uint16_t AddrMatchCode);
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/*!< pointer to an SMBUS Address Match callback function */
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#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
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* @{
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*/
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/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
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* @{
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*/
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#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
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#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
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/**
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* @}
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*/
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/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
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* @{
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*/
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#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
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#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
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/**
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* @}
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*/
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/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
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* @{
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*/
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#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
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#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
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/**
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* @}
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*/
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/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
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* @{
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*/
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#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
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#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
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#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
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#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
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#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
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#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
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#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
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#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
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/**
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* @}
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*/
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/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
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* @{
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*/
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#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
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#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
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/**
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* @}
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*/
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/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
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* @{
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*/
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#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
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#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
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/**
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* @}
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*/
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/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
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* @{
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*/
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#define SMBUS_PEC_DISABLE (0x00000000U)
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#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
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/**
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* @}
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*/
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/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
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* @{
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*/
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#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
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#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
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#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
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/**
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* @}
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*/
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/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
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* @{
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*/
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#define SMBUS_SOFTEND_MODE (0x00000000U)
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#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
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#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
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#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
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/**
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* @}
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*/
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/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
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* @{
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*/
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#define SMBUS_NO_STARTSTOP (0x00000000U)
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#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
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#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
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#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
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/**
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* @}
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*/
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/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
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* @{
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*/
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/* List of XferOptions in usage of :
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* 1- Restart condition when direction change
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* 2- No Restart condition in other use cases
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*/
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#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
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#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
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#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
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#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
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#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
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#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
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#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
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/* List of XferOptions in usage of :
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* 1- Restart condition in all use cases (direction change or not)
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*/
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#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
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#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
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#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
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#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
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/**
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* @}
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*/
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/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
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* @brief SMBUS Interrupt definition
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* Elements values convention: 0xXXXXXXXX
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* - XXXXXXXX : Interrupt control mask
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* @{
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*/
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#define SMBUS_IT_ERRI I2C_CR1_ERRIE
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#define SMBUS_IT_TCI I2C_CR1_TCIE
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#define SMBUS_IT_STOPI I2C_CR1_STOPIE
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#define SMBUS_IT_NACKI I2C_CR1_NACKIE
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#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
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#define SMBUS_IT_RXI I2C_CR1_RXIE
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#define SMBUS_IT_TXI I2C_CR1_TXIE
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#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
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SMBUS_IT_NACKI | SMBUS_IT_TXI)
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#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
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SMBUS_IT_RXI)
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#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
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#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
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/**
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* @}
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*/
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/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
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* @brief Flag definition
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* Elements values convention: 0xXXXXYYYY
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* - XXXXXXXX : Flag mask
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* @{
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*/
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#define SMBUS_FLAG_TXE I2C_ISR_TXE
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#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
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#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
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#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
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#define SMBUS_FLAG_AF I2C_ISR_NACKF
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#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
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#define SMBUS_FLAG_TC I2C_ISR_TC
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#define SMBUS_FLAG_TCR I2C_ISR_TCR
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#define SMBUS_FLAG_BERR I2C_ISR_BERR
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#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
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#define SMBUS_FLAG_OVR I2C_ISR_OVR
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#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
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#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
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#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
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#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
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#define SMBUS_FLAG_DIR I2C_ISR_DIR
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros ------------------------------------------------------------*/
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/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
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* @{
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*/
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/** @brief Reset SMBUS handle state.
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* @param __HANDLE__ specifies the SMBUS Handle.
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* @retval None
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*/
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#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
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#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
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(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
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(__HANDLE__)->MspInitCallback = NULL; \
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(__HANDLE__)->MspDeInitCallback = NULL; \
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} while(0)
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#else
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#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
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#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
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/** @brief Enable the specified SMBUS interrupts.
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* @param __HANDLE__ specifies the SMBUS Handle.
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* @param __INTERRUPT__ specifies the interrupt source to enable.
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* This parameter can be one of the following values:
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* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
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* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
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* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
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* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
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* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
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* @arg @ref SMBUS_IT_RXI RX interrupt enable
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* @arg @ref SMBUS_IT_TXI TX interrupt enable
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*
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* @retval None
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*/
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#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
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/** @brief Disable the specified SMBUS interrupts.
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* @param __HANDLE__ specifies the SMBUS Handle.
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* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
|
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
|
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
|
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
|
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
|
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
|
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
|
*
|
|
* @retval None
|
|
*/
|
|
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
|
|
|
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
|
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
|
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
|
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
|
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
|
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
|
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
|
*
|
|
* @retval The new state of __IT__ (SET or RESET).
|
|
*/
|
|
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
|
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
|
|
/** @brief Check whether the specified SMBUS flag is set or not.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @param __FLAG__ specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
|
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
|
|
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
|
|
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
|
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
|
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
|
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
|
|
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
|
|
* @arg @ref SMBUS_FLAG_BERR Bus error
|
|
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
|
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
|
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
|
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
|
* @arg @ref SMBUS_FLAG_BUSY Bus busy
|
|
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
|
|
*
|
|
* @retval The new state of __FLAG__ (SET or RESET).
|
|
*/
|
|
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
|
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
|
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
|
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
|
|
|
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @param __FLAG__ specifies the flag to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
|
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
|
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
|
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
|
* @arg @ref SMBUS_FLAG_BERR Bus error
|
|
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
|
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
|
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
|
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
|
*
|
|
* @retval None
|
|
*/
|
|
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
|
|
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
|
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
|
|
|
/** @brief Enable the specified SMBUS peripheral.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
|
|
/** @brief Disable the specified SMBUS peripheral.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
|
|
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
|
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Private constants ---------------------------------------------------------*/
|
|
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
|
|
* @{
|
|
*/
|
|
|
|
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
|
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
|
|
|
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
|
|
|
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
|
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
|
|
|
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
|
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
|
|
|
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
|
((MASK) == SMBUS_OA2_MASK01) || \
|
|
((MASK) == SMBUS_OA2_MASK02) || \
|
|
((MASK) == SMBUS_OA2_MASK03) || \
|
|
((MASK) == SMBUS_OA2_MASK04) || \
|
|
((MASK) == SMBUS_OA2_MASK05) || \
|
|
((MASK) == SMBUS_OA2_MASK06) || \
|
|
((MASK) == SMBUS_OA2_MASK07))
|
|
|
|
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
|
|
((CALL) == SMBUS_GENERALCALL_ENABLE))
|
|
|
|
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
|
|
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
|
|
|
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
|
((PEC) == SMBUS_PEC_ENABLE))
|
|
|
|
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
|
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
|
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
|
|
|
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
|
((MODE) == SMBUS_AUTOEND_MODE) || \
|
|
((MODE) == SMBUS_SOFTEND_MODE) || \
|
|
((MODE) == SMBUS_SENDPEC_MODE) || \
|
|
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
|
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
|
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
|
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
|
|
SMBUS_RELOAD_MODE )))
|
|
|
|
|
|
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
|
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
|
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
|
((REQUEST) == SMBUS_NO_STARTSTOP))
|
|
|
|
|
|
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
|
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
|
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
|
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
|
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
|
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
|
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
|
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
|
|
|
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
|
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
|
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
|
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
|
|
|
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
|
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
|
|
I2C_CR1_PECEN)))
|
|
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
|
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
|
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
|
I2C_CR2_RD_WRN)))
|
|
|
|
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
|
|
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
|
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
|
(~I2C_CR2_RD_WRN)) : \
|
|
(uint32_t)((((uint32_t)(__ADDRESS__) & \
|
|
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
|
|
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
|
|
|
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
|
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
|
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
|
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
|
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
|
|
|
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
|
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
|
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
|
|
|
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
|
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Include SMBUS HAL Extended module */
|
|
#include "stm32h7xx_hal_smbus_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
|
|
/* Initialization and de-initialization functions ****************************/
|
|
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
|
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
|
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
|
|
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
|
|
|
|
/* Callbacks Register/UnRegister functions ***********************************/
|
|
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
|
pSMBUS_CallbackTypeDef pCallback);
|
|
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
|
|
|
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
pSMBUS_AddrCallbackTypeDef pCallback);
|
|
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
|
* @{
|
|
*/
|
|
|
|
/* IO operation functions *****************************************************/
|
|
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
|
* @{
|
|
*/
|
|
/******* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
|
uint32_t Timeout);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
|
* @{
|
|
*/
|
|
/******* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
|
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
|
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
|
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
|
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
|
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
|
uint32_t XferOptions);
|
|
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
|
uint32_t XferOptions);
|
|
|
|
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|
* @{
|
|
*/
|
|
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
|
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
|
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
|
* @{
|
|
*/
|
|
|
|
/* Peripheral State and Errors functions **************************************************/
|
|
uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
|
|
uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private Functions ---------------------------------------------------------*/
|
|
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
|
* @{
|
|
*/
|
|
/* Private functions are defined in stm32h7xx_hal_smbus.c file */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif /* STM32H7xx_HAL_SMBUS_H */
|