1125 lines
42 KiB
C
1125 lines
42 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_rcc.c
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* @author MCD Application Team
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* @brief RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Reset and Clock Control (RCC) peripheral:
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* + Initialization and de-initialization functions
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* + Peripheral Control functions
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*
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@verbatim
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==============================================================================
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##### RCC specific features #####
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==============================================================================
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[..]
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After reset the device is running from Internal High Speed oscillator
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(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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and I-Cache are disabled, and all peripherals are off except internal
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SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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all peripherals mapped on these busses are running at HSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in input floating state, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..]
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Once the device started from reset, the user application has to:
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(+) Configure the clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB busses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals which clocks are not
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derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
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after the clock enable bit is set on the hardware register
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(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
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after the clock enable bit is set on the hardware register
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[..]
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Implemented Workaround:
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(+) For AHB & APB peripherals, a dummy read to the peripheral register has been
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inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCC RCC
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* @brief RCC HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup RCC_Private_Constants
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* @{
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*/
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/* Private macro -------------------------------------------------------------*/
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#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define MCO1_GPIO_PORT GPIOA
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#define MCO1_PIN GPIO_PIN_8
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#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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#define MCO2_GPIO_PORT GPIOC
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#define MCO2_PIN GPIO_PIN_9
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/** @defgroup RCC_Private_Variables RCC Private Variables
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* @{
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*/
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCC_Exported_Functions RCC Exported Functions
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* @{
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*/
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to configure the internal/external oscillators
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(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
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and APB2).
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[..] Internal/external clock and PLL configuration
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(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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the PLL as System clock source.
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(#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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clock source.
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(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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through the PLL as System clock source. Can be used also as RTC clock source.
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(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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(++) The first output is used to generate the high speed system clock (up to 168 MHz)
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(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
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(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
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and if a HSE clock failure occurs(HSE used directly or through PLL as System
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clock source), the System clocks automatically switched to HSI and an interrupt
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is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
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(Non-Maskable Interrupt) exception vector.
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(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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clock (through a configurable prescaler) on PA8 pin.
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(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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clock (through a configurable prescaler) on PC9 pin.
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[..] System, AHB and APB busses clocks configuration
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(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
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HSE and PLL.
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The AHB clock (HCLK) is derived from System clock through configurable
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prescaler and used to clock the CPU, memory and peripherals mapped
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on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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from AHB clock through configurable prescalers and used to clock
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the peripherals mapped on these busses. You can use
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"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
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frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
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Depending on the device voltage range, the maximum frequency should
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be adapted accordingly (refer to the product datasheets for more details).
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(#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
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the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
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Depending on the device voltage range, the maximum frequency should
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be adapted accordingly (refer to the product datasheets for more details).
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(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
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PCLK2 84 MHz and PCLK1 42 MHz.
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Depending on the device voltage range, the maximum frequency should
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be adapted accordingly (refer to the product datasheets for more details).
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(#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
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PCLK2 100 MHz and PCLK1 50 MHz.
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Depending on the device voltage range, the maximum frequency should
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be adapted accordingly (refer to the product datasheets for more details).
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@endverbatim
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* @{
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*/
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/**
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* @brief Resets the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE and PLL OFF
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* - AHB, APB1 and APB2 prescaler set to 1.
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* - CSS, MCO1 and MCO2 OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval HAL status
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*/
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__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
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{
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return HAL_OK;
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}
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/**
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* @brief Initializes the RCC Oscillators according to the specified parameters in the
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* RCC_OscInitTypeDef.
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* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
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* contains the configuration information for the RCC Oscillators.
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* @note The PLL is not disabled when used as system clock.
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* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
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* supported by this API. User should request a transition to LSE Off
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* first and then LSE On or LSE Bypass.
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* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
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* supported by this API. User should request a transition to HSE Off
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* first and then HSE On or HSE Bypass.
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* @retval HAL status
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*/
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__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
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{
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uint32_t tickstart;
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uint32_t pll_config;
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/* Check Null pointer */
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if (RCC_OscInitStruct == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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/*------------------------------- HSE Configuration ------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
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if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
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((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
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{
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if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
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{
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return HAL_ERROR;
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}
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}
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else
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{
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/* Set the new HSE configuration ---------------------------------------*/
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__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
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/* Check the HSE State */
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if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSE is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
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{
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if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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else
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSE is bypassed or disabled */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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{
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if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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}
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/*----------------------------- HSI Configuration --------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
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assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
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/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
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((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
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{
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/* When HSI is used as system clock it will not disabled */
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if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
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{
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return HAL_ERROR;
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}
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/* Otherwise, just the calibration is allowed */
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else
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{
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/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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}
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}
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else
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{
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/* Check the HSI State */
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if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
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{
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/* Enable the Internal High Speed oscillator (HSI). */
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__HAL_RCC_HSI_ENABLE();
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till HSI is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
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{
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if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
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__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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}
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else
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{
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/* Disable the Internal High Speed oscillator (HSI). */
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__HAL_RCC_HSI_DISABLE();
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till HSI is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
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{
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if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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}
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/*------------------------------ LSI Configuration -------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
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/* Check the LSI State */
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if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
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{
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/* Enable the Internal Low Speed oscillator (LSI). */
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__HAL_RCC_LSI_ENABLE();
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till LSI is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
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{
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if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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else
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{
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/* Disable the Internal Low Speed oscillator (LSI). */
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__HAL_RCC_LSI_DISABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSI is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
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{
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if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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/*------------------------------ LSE Configuration -------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
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{
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FlagStatus pwrclkchanged = RESET;
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/* Check the parameters */
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assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
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/* Update LSE configuration in Backup Domain control register */
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/* Requires to enable write access to Backup Domain of necessary */
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if (__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR, PWR_CR_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Set the new LSE configuration -----------------------------------------*/
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__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
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/* Check the LSE State */
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if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
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{
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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else
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
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{
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if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Restore clock configuration if changed */
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if (pwrclkchanged == SET)
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{
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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}
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/*-------------------------------- PLL Configuration -----------------------*/
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/* Check the parameters */
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assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
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if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
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{
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/* Check if the PLL is used as system clock or not */
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if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
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{
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if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
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{
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/* Check the parameters */
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assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
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assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
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assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
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assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
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assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
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/* Disable the main PLL. */
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__HAL_RCC_PLL_DISABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till PLL is disabled */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
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{
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if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
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{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
RCC_OscInitStruct->PLL.PLLM | \
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
#else
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
|
|
* parameters in the RCC_ClkInitStruct.
|
|
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* contains the configuration information for the RCC peripheral.
|
|
* @param FLatency FLASH Latency, this parameter depend on device selected
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated by HAL_RCC_GetHCLKFreq() function called within this function
|
|
*
|
|
* @note The HSI is used (enabled by hardware) as system clock source after
|
|
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
|
|
* of failure of the HSE used directly or indirectly as system clock
|
|
* (if the Clock Security System CSS is enabled).
|
|
*
|
|
* @note A switch from one clock source to another occurs only if the target
|
|
* clock source is ready (clock stable after startup delay or PLL locked).
|
|
* If a clock source which is not yet ready is selected, the switch will
|
|
* occur when the clock source will be ready.
|
|
*
|
|
* @note Depending on the device voltage range, the software has to set correctly
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
|
|
assert_param(IS_FLASH_LATENCY(FLatency));
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
|
* @brief RCC clocks control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral Control functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the RCC Clocks
|
|
frequencies.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
|
|
* @note PA8/PC9 should be configured in alternate function mode.
|
|
* @param RCC_MCOx specifies the output direction for the clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
|
|
* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
|
|
* @param RCC_MCOSource specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
|
|
* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
|
|
* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
|
|
* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
|
|
* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
|
|
* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
|
|
* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
|
|
* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
|
|
* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
|
|
* @param RCC_MCODiv specifies the MCOx prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg RCC_MCODIV_1: no division applied to MCOx clock
|
|
* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
|
|
* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
|
|
* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
|
|
* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
|
|
* @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
|
|
* at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
|
{
|
|
GPIO_InitTypeDef GPIO_InitStruct;
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO(RCC_MCOx));
|
|
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
|
/* RCC_MCO1 */
|
|
if (RCC_MCOx == RCC_MCO1)
|
|
{
|
|
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
|
|
|
/* MCO1 Clock Enable */
|
|
__MCO1_CLK_ENABLE();
|
|
|
|
/* Configure the MCO1 pin in alternate function mode */
|
|
GPIO_InitStruct.Pin = MCO1_PIN;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
|
HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
|
|
|
|
/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
|
|
|
|
/* This RCC MCO1 enable feature is available only on STM32F410xx devices */
|
|
#if defined(RCC_CFGR_MCO1EN)
|
|
__HAL_RCC_MCO1_ENABLE();
|
|
#endif /* RCC_CFGR_MCO1EN */
|
|
}
|
|
#if defined(RCC_CFGR_MCO2)
|
|
else
|
|
{
|
|
assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
|
|
|
|
/* MCO2 Clock Enable */
|
|
__MCO2_CLK_ENABLE();
|
|
|
|
/* Configure the MCO2 pin in alternate function mode */
|
|
GPIO_InitStruct.Pin = MCO2_PIN;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
|
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
|
|
|
|
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
|
|
|
|
/* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
|
|
#if defined(RCC_CFGR_MCO2EN)
|
|
__HAL_RCC_MCO2_ENABLE();
|
|
#endif /* RCC_CFGR_MCO2EN */
|
|
}
|
|
#endif /* RCC_CFGR_MCO2 */
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the Clock Security System.
|
|
* @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
* is automatically disabled and an interrupt is generated to inform the
|
|
* software about the failure (Clock Security System Interrupt, CSSI),
|
|
* allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_EnableCSS(void)
|
|
{
|
|
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables the Clock Security System.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_DisableCSS(void)
|
|
{
|
|
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the SYSCLK frequency
|
|
*
|
|
* @note The system frequency computed by this function is not the real
|
|
* frequency in the chip. It is calculated based on the predefined
|
|
* constant and the selected clock source:
|
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
|
* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
|
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
|
* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
|
* 16 MHz) but the real value may vary depending on the variations
|
|
* in voltage and temperature.
|
|
* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
|
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
* frequency of the crystal used. Otherwise, this function may
|
|
* have wrong result.
|
|
*
|
|
* @note The result of this function could be not correct when using fractional
|
|
* value for HSE crystal.
|
|
*
|
|
* @note This function can be used by the user application to compute the
|
|
* baudrate for the communication peripherals or configure other parameters.
|
|
*
|
|
* @note Each time SYSCLK changes, this function must be called to update the
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
uint32_t pllm = 0U;
|
|
uint32_t pllvco = 0U;
|
|
uint32_t pllp = 0U;
|
|
uint32_t sysclockfreq = 0U;
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
break;
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
break;
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
break;
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
break;
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the HCLK frequency
|
|
* @note Each time HCLK changes, this function must be called to update the
|
|
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
return SystemCoreClock;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the PCLK1 frequency
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the PCLK2 frequency
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the RCC_OscInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* will be configured.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
/* Set all possible values for the Oscillator type parameter ---------------*/
|
|
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
|
|
|
/* Get the HSE configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
|
}
|
|
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
|
}
|
|
|
|
/* Get the HSI configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
|
}
|
|
|
|
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
|
|
|
|
/* Get the LSE configuration -----------------------------------------------*/
|
|
if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
|
}
|
|
else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
|
}
|
|
|
|
/* Get the LSI configuration -----------------------------------------------*/
|
|
if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
|
}
|
|
|
|
/* Get the PLL configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
|
}
|
|
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
|
|
RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
|
|
RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the RCC_ClkInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles the RCC CSS interrupt request.
|
|
* @note This API should be called under the NMI_Handler().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_NMI_IRQHandler(void)
|
|
{
|
|
/* Check RCC CSSF flag */
|
|
if (__HAL_RCC_GET_IT(RCC_IT_CSS))
|
|
{
|
|
/* RCC Clock Security System interrupt user callback */
|
|
HAL_RCC_CSSCallback();
|
|
|
|
/* Clear RCC CSS pending bit */
|
|
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief RCC Clock Security System interrupt callback
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_RCC_CSSCallback(void)
|
|
{
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_RCC_CSSCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|