16305 lines
560 KiB
XML
16305 lines
560 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<!-- ************************************************************************ -->
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<!-- Licence Terms -->
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<!-- ************************************************************************ -->
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<!-- -->
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<!-- FUJITSU SEMICONDUCTOR LIMITED (gLICENSORh) hereby grants and -->
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<!-- you (gLICENSEEh) hereby accept a non transferable, non-exclusive -->
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<!-- licence to use and copy the deliverables (gDeliverablesh) solely for -->
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<!-- the purpose of; (i) developing LICENSEEfs development tools and -->
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<!-- distributing such development tools to third parties; (ii) generating -->
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<!-- derivative representations of the Deliverables to develop and debug -->
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<!-- software for LICENSORfs targeted devices or device series identified -->
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<!-- within the Deliverables, (together the gPurposeh) under the following -->
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<!-- terms and conditions: -->
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<!-- -->
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<!-- 1. Ownership. -->
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<!-- The Deliverables are the property of LICENSOR. LICENSEE acquires no -->
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<!-- right, title or interest in the Deliverables other than the licence -->
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<!-- rights granted herein. -->
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<!-- -->
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<!-- 2. Use. -->
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<!-- LICENSEE shall only be permitted to use the Deliverables for the -->
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<!-- Purpose. LICENSEE shall not reverse engineer, decompile or -->
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<!-- disassemble the Deliverables, in whole or in part. -->
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<!-- -->
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<!-- 3. Copies. -->
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<!-- All copies of the Deliverables must bear the same notice(s) contained -->
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<!-- on the original copies of the Deliverables. -->
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<!-- -->
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<!-- 4. No Warranty. -->
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<!-- THE DELIVERABLES ARE PROVIDED gAS ISh AND ANY EXPRESS, IMPLIED OR -->
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<!-- STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -->
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<!-- WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR -->
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<!-- A PARTICULAR PURPOSE ARE DISCLAIMED. -->
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<!-- IN NO EVENT SHALL LICENSOR BE LIABLE FOR ANY DIRECT, INDIRECT, -->
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<!-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES HOWEVER CAUSED -->
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<!-- AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -->
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<!-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -->
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<!-- THE USE OF THE DELIVERABLES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -->
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<!-- DAMAGE. -->
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<!-- LICENSEE EXPRESSLY ASSUMES ALL LIABILITIES AND RISKS, FOR USE OR -->
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<!-- OPERATION OF THE DELIVERABLES. -->
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<!-- -->
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<!-- 5.In the event that LICENSEE receives early access to the Deliverables, -->
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<!-- LICENSEE acknowledges and agrees that; -->
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<!-- (a) notwithstanding the licence grants above, LICENSEE shall only be -->
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<!-- permitted to use the Deliverables solely internally for evaluation and -->
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<!-- providing feedback to LICENSOR; -->
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<!-- (b) except with respect to the limited licence grants in 5(a), LICENSEE -->
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<!-- shall be subject to all of the terms and conditions set out above; and -->
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<!-- (c) the Deliverables are confidential information and LICENSEE shall -->
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<!-- maintain in confidence the Deliverables and apply security measures no -->
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<!-- less stringent than the measures that LICENSEE applies to its own like -->
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<!-- information, but not less than a reasonable degree of care, to prevent -->
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<!-- unauthorised disclosure and use of the Deliverables. -->
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<!-- -->
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<!-- ************************************************************************ -->
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<!-- 2012.10.1 generated by svdgen_v03b -->
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<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
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<name>MB9AF31xK</name>
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<version>1.7</version>
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<description>MB9AF31xK</description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000000</resetMask>
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<peripherals>
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<!-- ************************************************************************************** -->
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<!-- peripheral:WorkFlashMemory -->
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<!-- ************************************************************************************** -->
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<!-- PERIPHERAL "WORKFLASH_IF" -->
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<peripheral>
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<name>WORKFLASH_IF</name>
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<description>WorkFlash Memory</description>
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<groupName>WORKFLASH_IF</groupName>
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<baseAddress>0x200E0000</baseAddress>
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<!-- ADDRESS BLOCK -->
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|
<addressBlock>
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|
<offset>0x0</offset>
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|
<size>0xC</size>
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|
<usage>registers</usage>
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</addressBlock>
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<!-- REGISTERS -->
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<registers>
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|
<!-- REGISTER "WFASZR" -->
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<register>
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|
<name>WFASZR</name>
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<description>WorkFlash Access Size Register</description>
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<addressOffset>0x0</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x1</resetValue>
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<resetMask>0x1</resetMask>
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<!-- FIELDS -->
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<fields>
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|
<!-- FIELD "ASZ" -->
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<field>
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<name>ASZ</name>
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<description>WorkFlash Access Size</description>
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<lsb>0</lsb>
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<msb>0</msb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<!-- REGISTER "WFRWTR" -->
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<register>
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<name>WFRWTR</name>
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<description>WorkFlash Read Wait Register</description>
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<addressOffset>0x4</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x2</resetValue>
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<resetMask>0x7</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "RWT" -->
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|
<field>
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<name>RWT</name>
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<description>Read Wait Cycle</description>
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<lsb>0</lsb>
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<msb>2</msb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<!-- REGISTER "WFSTR" -->
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<register>
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<name>WFSTR</name>
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<description>WorkFlash Status Register</description>
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<addressOffset>0x8</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x0</resetValue>
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<resetMask>0x3</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "HNG" -->
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<field>
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<name>HNG</name>
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<description>WorkFlash Hang</description>
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<lsb>1</lsb>
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<msb>1</msb>
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<access>read-only</access>
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</field>
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<!-- FIELD "RDY" -->
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<field>
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<name>RDY</name>
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<description>WorkFlash Rdy</description>
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<lsb>0</lsb>
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<msb>0</msb>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<!-- PERIPHERAL "FLASH_IF" -->
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<peripheral>
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<name>FLASH_IF</name>
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<description>Flash Memory</description>
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<groupName>FLASH_IF</groupName>
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<baseAddress>0x40000000</baseAddress>
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<!-- ADDRESS BLOCK -->
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<addressBlock>
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<offset>0x0</offset>
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<size>0xC</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x10</offset>
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<size>0x4</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x100</offset>
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<size>0x4</size>
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<usage>registers</usage>
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</addressBlock>
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<!-- REGISTERS -->
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<registers>
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<!-- REGISTER "FASZR" -->
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<register>
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<name>FASZR</name>
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<description>Flash Access Size Register</description>
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<addressOffset>0x00</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000002</resetValue>
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<resetMask>0x00000003</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "ASZ" -->
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<field>
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<name>ASZ</name>
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<description>Flash Access Size </description>
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<lsb>0</lsb>
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<msb>1</msb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<!-- REGISTER "FRWTR" -->
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<register>
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<name>FRWTR</name>
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<description>Flash Read Wait Register</description>
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<addressOffset>0x04</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000003</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "RWT" -->
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<field>
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<name>RWT</name>
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<description>Read Wait Cycle</description>
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<lsb>0</lsb>
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<msb>1</msb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<!-- REGISTER "FSTR" -->
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<register>
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<name>FSTR</name>
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<description>Flash Status Register</description>
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<addressOffset>0x08</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000007</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "ERR" -->
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<field>
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<name>ERR</name>
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<description>Flash ECC Error </description>
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<lsb>2</lsb>
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<msb>2</msb>
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<access>read-write</access>
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</field>
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<!-- FIELD "HNG" -->
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<field>
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<name>HNG</name>
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<description>Flash Hang flag</description>
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<lsb>1</lsb>
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<msb>1</msb>
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<access>read-only</access>
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</field>
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<!-- FIELD "RDY" -->
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<field>
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<name>RDY</name>
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<description>Flash Rdy</description>
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<lsb>0</lsb>
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<msb>0</msb>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<!-- REGISTER "FSYNDN" -->
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<register>
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<name>FSYNDN</name>
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<description>Flash Sync Down Register</description>
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<addressOffset>0x10</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000007</resetMask>
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<!-- FIELDS -->
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<fields>
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<!-- FIELD "SD" -->
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|
<field>
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|
<name>SD</name>
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|
<description>Flash Sync</description>
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<lsb>0</lsb>
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<msb>2</msb>
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<access>read-write</access>
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</field>
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|
</fields>
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|
</register>
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|
<!-- REGISTER "CRTRMM" -->
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|
<register>
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|
<name>CRTRMM</name>
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|
<description>CR Trimming Data Mirror Register</description>
|
|
<addressOffset>0x100</addressOffset>
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|
<size>32</size>
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|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
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|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TRMM" -->
|
|
<field>
|
|
<name>TRMM</name>
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|
<description>CR Trimming Data Mirror</description>
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|
<lsb>0</lsb>
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|
<msb>9</msb>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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|
</registers>
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</peripheral>
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<!-- PERIPHERAL "CRG" -->
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<peripheral>
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|
<name>CRG</name>
|
|
<description>Clock Unit Registers</description>
|
|
<groupName>CRG</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x44</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x48</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x50</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x60</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x64</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x68</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "CSV" -->
|
|
<interrupt>
|
|
<name>CSV</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "OSC_PLL_WC_RTC" -->
|
|
<interrupt>
|
|
<name>OSC_PLL_WC_RTC</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "SCM_CTL" -->
|
|
<register>
|
|
<name>SCM_CTL</name>
|
|
<description>System Clock Mode Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFA</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RCS" -->
|
|
<field>
|
|
<name>RCS</name>
|
|
<description>Master clock switch control bits </description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PLLE" -->
|
|
<field>
|
|
<name>PLLE</name>
|
|
<description>PLL oscillation enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOSCE" -->
|
|
<field>
|
|
<name>SOSCE</name>
|
|
<description>Sub clock oscillation enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOSCE" -->
|
|
<field>
|
|
<name>MOSCE</name>
|
|
<description>Main clock oscillation enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
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|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCM_STR" -->
|
|
<register>
|
|
<name>SCM_STR</name>
|
|
<description>System Clock Mode Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFA</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RCM" -->
|
|
<field>
|
|
<name>RCM</name>
|
|
<description>Master clock selection bits </description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PLRDY" -->
|
|
<field>
|
|
<name>PLRDY</name>
|
|
<description>PLL oscillation stable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SORDY" -->
|
|
<field>
|
|
<name>SORDY</name>
|
|
<description>Sub clock oscillation stable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MORDY" -->
|
|
<field>
|
|
<name>MORDY</name>
|
|
<description>Main clock oscillation stable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "BSC_PSR" -->
|
|
<register>
|
|
<name>BSC_PSR</name>
|
|
<description>Base Clock Prescaler Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x07</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BSR" -->
|
|
<field>
|
|
<name>BSR</name>
|
|
<description>Base clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "APBC0_PSR" -->
|
|
<register>
|
|
<name>APBC0_PSR</name>
|
|
<description>APB0 Prescaler Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "APBC0" -->
|
|
<field>
|
|
<name>APBC0</name>
|
|
<description>APB0 bus clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "APBC1_PSR" -->
|
|
<register>
|
|
<name>APBC1_PSR</name>
|
|
<description>APB1 Prescaler Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0x93</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "APBC1EN" -->
|
|
<field>
|
|
<name>APBC1EN</name>
|
|
<description>APB1 clock enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "APBC1RST" -->
|
|
<field>
|
|
<name>APBC1RST</name>
|
|
<description>APB1 bus reset control bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "APBC1" -->
|
|
<field>
|
|
<name>APBC1</name>
|
|
<description>APB1 bus clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "APBC2_PSR" -->
|
|
<register>
|
|
<name>APBC2_PSR</name>
|
|
<description>APB2 Prescaler Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0x93</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "APBC2EN" -->
|
|
<field>
|
|
<name>APBC2EN</name>
|
|
<description>APB2 clock enable bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "APBC2RST" -->
|
|
<field>
|
|
<name>APBC2RST</name>
|
|
<description>APB2 bus reset control bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "APBC2" -->
|
|
<field>
|
|
<name>APBC2</name>
|
|
<description>APB2 bus clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SWC_PSR" -->
|
|
<register>
|
|
<name>SWC_PSR</name>
|
|
<description>Software Watchdog Clock Prescaler Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TESTB" -->
|
|
<field>
|
|
<name>TESTB</name>
|
|
<description>TEST bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SWDS" -->
|
|
<field>
|
|
<name>SWDS</name>
|
|
<description>Software watchdog clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "TTC_PSR" -->
|
|
<register>
|
|
<name>TTC_PSR</name>
|
|
<description>Trace Clock Prescaler Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TTC" -->
|
|
<field>
|
|
<name>TTC</name>
|
|
<description>Trace clock frequency division ratio setting bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSW_TMR" -->
|
|
<register>
|
|
<name>CSW_TMR</name>
|
|
<description>Clock Stabilization Wait Time Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SOWT" -->
|
|
<field>
|
|
<name>SOWT</name>
|
|
<description>Sub clock stabilization wait time setup bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOWT" -->
|
|
<field>
|
|
<name>MOWT</name>
|
|
<description>Main clock stabilization wait time setup bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PSW_TMR" -->
|
|
<register>
|
|
<name>PSW_TMR</name>
|
|
<description>PLL Clock Stabilization Wait Time Setup Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x17</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PINC" -->
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PLL input clock select bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "POWT" -->
|
|
<field>
|
|
<name>POWT</name>
|
|
<description>PLL clock stabilization wait time setup bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PLL_CTL1" -->
|
|
<register>
|
|
<name>PLL_CTL1</name>
|
|
<description>PLL Control Register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PLLK" -->
|
|
<field>
|
|
<name>PLLK</name>
|
|
<description>PLL input clock frequency division ratio setting bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PLLM" -->
|
|
<field>
|
|
<name>PLLM</name>
|
|
<description>PLL VCO clock frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PLL_CTL2" -->
|
|
<register>
|
|
<name>PLL_CTL2</name>
|
|
<description>PLL Control Register 2</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PLLN" -->
|
|
<field>
|
|
<name>PLLN</name>
|
|
<description>PLL feedback frequency division ratio setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DBWDT_CTL" -->
|
|
<register>
|
|
<name>DBWDT_CTL</name>
|
|
<description>Debug Break Watchdog Timer Control Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xA0</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DPHWBE" -->
|
|
<field>
|
|
<name>DPHWBE</name>
|
|
<description>HW-WDG debug mode break bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DPSWBE" -->
|
|
<field>
|
|
<name>DPSWBE</name>
|
|
<description>SW-WDG debug mode break bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "INT_ENR" -->
|
|
<register>
|
|
<name>INT_ENR</name>
|
|
<description> Interrupt Enable Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x27</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FCSE" -->
|
|
<field>
|
|
<name>FCSE</name>
|
|
<description>Anomalous frequency detection interrupt enable bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCSE" -->
|
|
<field>
|
|
<name>PCSE</name>
|
|
<description>PLL oscillation stabilization completion interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCSE" -->
|
|
<field>
|
|
<name>SCSE</name>
|
|
<description>Sub oscillation stabilization completion interrupt enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MCSE" -->
|
|
<field>
|
|
<name>MCSE</name>
|
|
<description>Main oscillation stabilization completion interrupt enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "INT_STR" -->
|
|
<register>
|
|
<name>INT_STR</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x27</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FCSI" -->
|
|
<field>
|
|
<name>FCSI</name>
|
|
<description>Anomalous frequency detection interrupt status bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PCSI" -->
|
|
<field>
|
|
<name>PCSI</name>
|
|
<description>PLL oscillation stabilization completion interrupt status bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SCSI" -->
|
|
<field>
|
|
<name>SCSI</name>
|
|
<description>Sub oscillation stabilization completion interrupt status bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MCSI" -->
|
|
<field>
|
|
<name>MCSI</name>
|
|
<description>Main oscillation stabilization completion interrupt status bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "INT_CLR" -->
|
|
<register>
|
|
<name>INT_CLR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x27</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FCSC" -->
|
|
<field>
|
|
<name>FCSC</name>
|
|
<description>Anomalous frequency detection interrupt cause clear bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "PCSC" -->
|
|
<field>
|
|
<name>PCSC</name>
|
|
<description>PLL oscillation stabilization completion interrupt cause clear bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SCSC" -->
|
|
<field>
|
|
<name>SCSC</name>
|
|
<description>Sub oscillation stabilization completion interrupt cause clear bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "MCSC" -->
|
|
<field>
|
|
<name>MCSC</name>
|
|
<description>Main oscillation stabilization completion interrupt cause clear bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RST_STR" -->
|
|
<register>
|
|
<name>RST_STR</name>
|
|
<description>Reset Cause Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0x01F3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SRST" -->
|
|
<field>
|
|
<name>SRST</name>
|
|
<description>Software reset flag</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FCSR" -->
|
|
<field>
|
|
<name>FCSR</name>
|
|
<description>Flag for anomalous frequency detection reset</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CSVR" -->
|
|
<field>
|
|
<name>CSVR</name>
|
|
<description>Clock failure detection reset flag </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "HWDG" -->
|
|
<field>
|
|
<name>HWDG</name>
|
|
<description>Hardware watchdog reset flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SWDG" -->
|
|
<field>
|
|
<name>SWDG</name>
|
|
<description>Software watchdog reset flag </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "INITX" -->
|
|
<field>
|
|
<name>INITX</name>
|
|
<description>INITX pin input reset flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PONR" -->
|
|
<field>
|
|
<name>PONR</name>
|
|
<description>Power-on reset/low-voltage detection reset flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "STB_CTL" -->
|
|
<register>
|
|
<name>STB_CTL</name>
|
|
<description>Standby Mode Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFF0017</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "KEY" -->
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Standby mode control write control bit </description>
|
|
<lsb>16</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPL" -->
|
|
<field>
|
|
<name>SPL</name>
|
|
<description>Standby pin level setting bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DSTM" -->
|
|
<field>
|
|
<name>DSTM</name>
|
|
<description>Deep standby mode select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STM" -->
|
|
<field>
|
|
<name>STM</name>
|
|
<description>Standby mode selection bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSV_CTL" -->
|
|
<register>
|
|
<name>CSV_CTL</name>
|
|
<description>CSV control register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7003</resetValue>
|
|
<resetMask>0x7303</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FCD" -->
|
|
<field>
|
|
<name>FCD</name>
|
|
<description>FCS count cycle setting bits</description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCSRE" -->
|
|
<field>
|
|
<name>FCSRE</name>
|
|
<description>FCS reset output enable bit </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCSDE" -->
|
|
<field>
|
|
<name>FCSDE</name>
|
|
<description>FCS function enable bit </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCSVE" -->
|
|
<field>
|
|
<name>SCSVE</name>
|
|
<description>Sub CSV function enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MCSVE" -->
|
|
<field>
|
|
<name>MCSVE</name>
|
|
<description>Main CSV function enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSV_STR" -->
|
|
<register>
|
|
<name>CSV_STR</name>
|
|
<description>CSV status register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SCMF" -->
|
|
<field>
|
|
<name>SCMF</name>
|
|
<description>Sub clock failure detection flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MCMF" -->
|
|
<field>
|
|
<name>MCMF</name>
|
|
<description>Main clock failure detection flag </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "FCSWH_CTL" -->
|
|
<register>
|
|
<name>FCSWH_CTL</name>
|
|
<description>Frequency detection window setting register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "FCSWL_CTL" -->
|
|
<register>
|
|
<name>FCSWL_CTL</name>
|
|
<description>Frequency detection window setting register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "FCSWD_CTL" -->
|
|
<register>
|
|
<name>FCSWD_CTL</name>
|
|
<description>Frequency detection counter register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "CRTRIM" -->
|
|
<peripheral>
|
|
<name>CRTRIM</name>
|
|
<description>CR Trimming Registers</description>
|
|
<groupName>CRTRIM</groupName>
|
|
<baseAddress>0x4002E000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "MCR_PSR" -->
|
|
<register>
|
|
<name>MCR_PSR</name>
|
|
<description>High-speed CR oscillation Frequency Division Setup Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CSR" -->
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>High-speed CR oscillation frequency division ratio setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "MCR_FTRM" -->
|
|
<register>
|
|
<name>MCR_FTRM</name>
|
|
<description>High-speed CR oscillation Frequency Trimming Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x007F</resetValue>
|
|
<resetMask>0x00FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TRD" -->
|
|
<field>
|
|
<name>TRD</name>
|
|
<description>Frequency trimming setup bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "MCR_RLR" -->
|
|
<register>
|
|
<name>MCR_RLR</name>
|
|
<description>High-Speed CR Oscillation Register Write-Protect Register </description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TRMLCK" -->
|
|
<field>
|
|
<name>TRMLCK</name>
|
|
<description>Register write-protect bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "SWWDT" -->
|
|
<peripheral>
|
|
<name>SWWDT</name>
|
|
<description>Software Watchdog Timer</description>
|
|
<groupName>SWWDT</groupName>
|
|
<baseAddress>0x40012000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC00</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "SWDT" -->
|
|
<interrupt>
|
|
<name>SWDT</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "WDOGLOAD" -->
|
|
<register>
|
|
<name>WDOGLOAD</name>
|
|
<description>Software Watchdog Timer Load Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDOGVALUE" -->
|
|
<register>
|
|
<name>WDOGVALUE</name>
|
|
<description>Software Watchdog Timer Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDOGCONTROL" -->
|
|
<register>
|
|
<name>WDOGCONTROL</name>
|
|
<description>Software Watchdog Timer Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RESEN" -->
|
|
<field>
|
|
<name>RESEN</name>
|
|
<description>Reset enable bit of the software watchdog</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTEN" -->
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt and counter enable bit of the software watchdog </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WDOGINTCLR" -->
|
|
<register>
|
|
<name>WDOGINTCLR</name>
|
|
<description>Software Watchdog Timer Clear Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDOGRIS" -->
|
|
<register>
|
|
<name>WDOGRIS</name>
|
|
<description>Software Watchdog Timer Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RIS" -->
|
|
<field>
|
|
<name>RIS</name>
|
|
<description>Software watchdog interrupt status bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WDOGLOCK" -->
|
|
<register>
|
|
<name>WDOGLOCK</name>
|
|
<description>Software Watchdog Timer Lock Register</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "HWWDT" -->
|
|
<peripheral>
|
|
<name>HWWDT</name>
|
|
<description>Hardware Watchdog Timer</description>
|
|
<groupName>HWWDT</groupName>
|
|
<baseAddress>0x40011000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC00</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "WDG_LDR" -->
|
|
<register>
|
|
<name>WDG_LDR</name>
|
|
<description>Hardware Watchdog Timer Load Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDG_VLR" -->
|
|
<register>
|
|
<name>WDG_VLR</name>
|
|
<description>Hardware Watchdog Timer Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDG_CTL" -->
|
|
<register>
|
|
<name>WDG_CTL</name>
|
|
<description>Hardware Watchdog Timer Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RESEN" -->
|
|
<field>
|
|
<name>RESEN</name>
|
|
<description>Hardware watchdog reset enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTEN" -->
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Hardware watchdog interrupt and counter enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WDG_ICL" -->
|
|
<register>
|
|
<name>WDG_ICL</name>
|
|
<description>Hardware Watchdog Timer Clear Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WDG_RIS" -->
|
|
<register>
|
|
<name>WDG_RIS</name>
|
|
<description>Hardware Watchdog Timer Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>1</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RIS" -->
|
|
<field>
|
|
<name>RIS</name>
|
|
<description>Hardware watchdog interrupt status bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WDG_LCK" -->
|
|
<register>
|
|
<name>WDG_LCK</name>
|
|
<description>Hardware Watchdog Timer Lock Register</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "DTIM" -->
|
|
<peripheral>
|
|
<name>DTIM</name>
|
|
<description>Dual Timer</description>
|
|
<groupName>DTIM</groupName>
|
|
<baseAddress>0x40015000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "DTIM_QDU" -->
|
|
<interrupt>
|
|
<name>DTIM_QDU</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "TIMER1LOAD" -->
|
|
<register>
|
|
<name>TIMER1LOAD</name>
|
|
<description>Load Register</description>
|
|
<alternateGroup>DualTimer1</alternateGroup>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "TIMER1VALUE" -->
|
|
<register>
|
|
<name>TIMER1VALUE</name>
|
|
<description>Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "TIMER1CONTROL" -->
|
|
<register>
|
|
<name>TIMER1CONTROL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0x000000EF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TimerEn" -->
|
|
<field>
|
|
<name>TimerEn</name>
|
|
<description>Enable bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TimerMode" -->
|
|
<field>
|
|
<name>TimerMode</name>
|
|
<description>Mode bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IntEnable" -->
|
|
<field>
|
|
<name>IntEnable</name>
|
|
<description>Interrupt enable bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TimerPre" -->
|
|
<field>
|
|
<name>TimerPre</name>
|
|
<description>Prescale bits</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TimerSize" -->
|
|
<field>
|
|
<name>TimerSize</name>
|
|
<description>Counter size bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OneShot" -->
|
|
<field>
|
|
<name>OneShot</name>
|
|
<description>One-shot mode bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "TIMER1INTCLR" -->
|
|
<register>
|
|
<name>TIMER1INTCLR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "TIMER1RIS" -->
|
|
<register>
|
|
<name>TIMER1RIS</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TIMER1RIS" -->
|
|
<field>
|
|
<name>TIMER1RIS</name>
|
|
<description>Interrupt Status Register bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "TIMER1MIS" -->
|
|
<register>
|
|
<name>TIMER1MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TIMER1MIS" -->
|
|
<field>
|
|
<name>TIMER1MIS</name>
|
|
<description>Masked Interrupt Status bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "TIMER1BGLOAD" -->
|
|
<register>
|
|
<name>TIMER1BGLOAD</name>
|
|
<description>Background Load Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "TIMER2LOAD" -->
|
|
<register derivedFrom="TIMER1LOAD">
|
|
<name>TIMER2LOAD</name>
|
|
<description>Load Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2VALUE" -->
|
|
<register derivedFrom="TIMER1VALUE">
|
|
<name>TIMER2VALUE</name>
|
|
<description>Value Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2CONTROL" -->
|
|
<register derivedFrom="TIMER1CONTROL">
|
|
<name>TIMER2CONTROL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2INTCLR" -->
|
|
<register derivedFrom="TIMER1INTCLR">
|
|
<name>TIMER2INTCLR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2RIS" -->
|
|
<register derivedFrom="TIMER1RIS">
|
|
<name>TIMER2RIS</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2MIS" -->
|
|
<register derivedFrom="TIMER1MIS">
|
|
<name>TIMER2MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TIMER2BGLOAD" -->
|
|
<register derivedFrom="TIMER1BGLOAD">
|
|
<name>TIMER2BGLOAD</name>
|
|
<description>Background Load Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFT0" -->
|
|
<peripheral>
|
|
<name>MFT0</name>
|
|
<description>Multifunction Timer 0</description>
|
|
<groupName>MFT0</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x44</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x48</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x50</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x58</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x5C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x60</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x68</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x6C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x70</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x74</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x78</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x7C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x80</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x84</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x88</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x90</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x94</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x98</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x9C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xA8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xAC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB8</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xBC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "WFG" -->
|
|
<interrupt>
|
|
<name>WFG</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "FRTIM" -->
|
|
<interrupt>
|
|
<name>FRTIM</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "INCAP" -->
|
|
<interrupt>
|
|
<name>INCAP</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "OUTCOMP" -->
|
|
<interrupt>
|
|
<name>OUTCOMP</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "FRT_TCSA0" -->
|
|
<register>
|
|
<name>FRT_TCSA0</name>
|
|
<description>FRT-ch.0 Control Register A</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0xE3FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CLK" -->
|
|
<field>
|
|
<name>CLK</name>
|
|
<description>FRT clock cycle</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCLR" -->
|
|
<field>
|
|
<name>SCLR</name>
|
|
<description>FRT operation state initialization request</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "MODE" -->
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>FRT's count mode</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STOP" -->
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Puts FRT in stopping state</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BFE" -->
|
|
<field>
|
|
<name>BFE</name>
|
|
<description>Enables TCCP's buffer function</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICRE" -->
|
|
<field>
|
|
<name>ICRE</name>
|
|
<description>"Generates interrupt when ""1"" is set to TCSA.ICLR"</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICLR" -->
|
|
<field>
|
|
<name>ICLR</name>
|
|
<description>interrupt flag</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQZE" -->
|
|
<field>
|
|
<name>IRQZE</name>
|
|
<description>"Generates interrupt, when ""1"" is set to TCSA.IRQZF"</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQZF" -->
|
|
<field>
|
|
<name>IRQZF</name>
|
|
<description>zero interrupt flag</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECKE" -->
|
|
<field>
|
|
<name>ECKE</name>
|
|
<description>Uses an external input clock (FRCK) as FRT's count clock</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCSA1" -->
|
|
<register derivedFrom="FRT_TCSA0">
|
|
<name>FRT_TCSA1</name>
|
|
<description>FRT-ch.1 Control Register A</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCSA2" -->
|
|
<register derivedFrom="FRT_TCSA0">
|
|
<name>FRT_TCSA2</name>
|
|
<description>FRT-ch.2 Control Register A</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCSB0" -->
|
|
<register>
|
|
<name>FRT_TCSB0</name>
|
|
<description>FRT-ch.0 Control Register B</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0007</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AD2E" -->
|
|
<field>
|
|
<name>AD2E</name>
|
|
<description>Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD1E" -->
|
|
<field>
|
|
<name>AD1E</name>
|
|
<description>Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD0E" -->
|
|
<field>
|
|
<name>AD0E</name>
|
|
<description>Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCSB1" -->
|
|
<register derivedFrom="FRT_TCSB0">
|
|
<name>FRT_TCSB1</name>
|
|
<description>FRT-ch.1 Control Register B</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCSB2" -->
|
|
<register derivedFrom="FRT_TCSB0">
|
|
<name>FRT_TCSB2</name>
|
|
<description>FRT-ch.2 Control Register B</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCCP0" -->
|
|
<register>
|
|
<name>FRT_TCCP0</name>
|
|
<description>FRT-ch.0 Cycle Setting Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCCP1" -->
|
|
<register derivedFrom="FRT_TCCP0">
|
|
<name>FRT_TCCP1</name>
|
|
<description>FRT-ch.1 Cycle Setting Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCCP2" -->
|
|
<register derivedFrom="FRT_TCCP0">
|
|
<name>FRT_TCCP2</name>
|
|
<description>FRT-ch.2 Cycle Setting Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCDT0" -->
|
|
<register>
|
|
<name>FRT_TCDT0</name>
|
|
<description>FRT-ch.0 Count Value Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCDT1" -->
|
|
<register derivedFrom="FRT_TCDT0">
|
|
<name>FRT_TCDT1</name>
|
|
<description>FRT-ch.1 Count Value Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "FRT_TCDT2" -->
|
|
<register derivedFrom="FRT_TCDT0">
|
|
<name>FRT_TCDT2</name>
|
|
<description>FRT-ch.2 Count Value Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCFS10" -->
|
|
<register>
|
|
<name>OCU_OCFS10</name>
|
|
<description>"OCU ch.1,0 Connecting FRT Select Register"</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FSO0" -->
|
|
<field>
|
|
<name>FSO0</name>
|
|
<description>Connects FRT ch.x to OCU ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSO1" -->
|
|
<field>
|
|
<name>FSO1</name>
|
|
<description>Connects FRT ch.x to OCU ch.1</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCFS32" -->
|
|
<register derivedFrom="OCU_OCFS10">
|
|
<name>OCU_OCFS32</name>
|
|
<description>"OCU ch.3,2 Connecting FRT Select Register"</description>
|
|
<addressOffset>0x59</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCFS54" -->
|
|
<register derivedFrom="OCU_OCFS10">
|
|
<name>OCU_OCFS54</name>
|
|
<description>"OCU ch.5,4 Connecting FRT Select Register"</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSA10" -->
|
|
<register>
|
|
<name>OCU_OCSA10</name>
|
|
<description>"OCU ch.1,0 Control Register A"</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CST0" -->
|
|
<field>
|
|
<name>CST0</name>
|
|
<description>Enables the operation of OCU ch.(0)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CST1" -->
|
|
<field>
|
|
<name>CST1</name>
|
|
<description>Enables the operation of OCU ch.(1)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDIS0" -->
|
|
<field>
|
|
<name>BDIS0</name>
|
|
<description>Disables the buffer function of the OCCP(0) register</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDIS1" -->
|
|
<field>
|
|
<name>BDIS1</name>
|
|
<description>Disables the buffer function of the OCCP(1) register</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IOE0" -->
|
|
<field>
|
|
<name>IOE0</name>
|
|
<description>"Generates interrupt, when ""1"" is set to OCSA.IOP0"</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IOE1" -->
|
|
<field>
|
|
<name>IOE1</name>
|
|
<description>"Generates interrupt, when ""1"" is set to OCSA.IOP1"</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IOP0" -->
|
|
<field>
|
|
<name>IOP0</name>
|
|
<description>Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IOP1" -->
|
|
<field>
|
|
<name>IOP1</name>
|
|
<description>Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1).</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSA32" -->
|
|
<register derivedFrom="OCU_OCSA10">
|
|
<name>OCU_OCSA32</name>
|
|
<description>"OCU ch.3,2 Control Register A"</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSA54" -->
|
|
<register derivedFrom="OCU_OCSA10">
|
|
<name>OCU_OCSA54</name>
|
|
<description>"OCU ch.5,4 Control Register A"</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSB10" -->
|
|
<register>
|
|
<name>OCU_OCSB10</name>
|
|
<description>"OCU ch.1,0 Control Register B"</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0x73</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "OTD0" -->
|
|
<field>
|
|
<name>OTD0</name>
|
|
<description>Indicates that the RT(0) output pin is in the High-level output state. </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OTD1" -->
|
|
<field>
|
|
<name>OTD1</name>
|
|
<description>Indicates that the RT(1) output pin is in the High-level output state.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMOD" -->
|
|
<field>
|
|
<name>CMOD</name>
|
|
<description>selects OCU's operation mode in combination with OCSC.MOD0 to MOD5</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BTS0" -->
|
|
<field>
|
|
<name>BTS0</name>
|
|
<description>Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BTS1" -->
|
|
<field>
|
|
<name>BTS1</name>
|
|
<description>Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSB32" -->
|
|
<register derivedFrom="OCU_OCSB10">
|
|
<name>OCU_OCSB32</name>
|
|
<description>"OCU ch.3,2 Control Register B"</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSB54" -->
|
|
<register derivedFrom="OCU_OCSB10">
|
|
<name>OCU_OCSB54</name>
|
|
<description>"OCU ch.5,4 Control Register B"</description>
|
|
<addressOffset>0x21</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCSC" -->
|
|
<register>
|
|
<name>OCU_OCSC</name>
|
|
<description>OCU Control Register C</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x3F00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MOD0" -->
|
|
<field>
|
|
<name>MOD0</name>
|
|
<description>OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOD1" -->
|
|
<field>
|
|
<name>MOD1</name>
|
|
<description>OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOD2" -->
|
|
<field>
|
|
<name>MOD2</name>
|
|
<description>OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOD3" -->
|
|
<field>
|
|
<name>MOD3</name>
|
|
<description>OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOD4" -->
|
|
<field>
|
|
<name>MOD4</name>
|
|
<description>OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOD5" -->
|
|
<field>
|
|
<name>MOD5</name>
|
|
<description>OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP0" -->
|
|
<register>
|
|
<name>OCU_OCCP0</name>
|
|
<description>OCU ch.0 Compare Value Store Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP1" -->
|
|
<register derivedFrom="OCU_OCCP0">
|
|
<name>OCU_OCCP1</name>
|
|
<description>OCU ch.1 Compare Value Store Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP2" -->
|
|
<register derivedFrom="OCU_OCCP0">
|
|
<name>OCU_OCCP2</name>
|
|
<description>OCU ch.2 Compare Value Store Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP3" -->
|
|
<register derivedFrom="OCU_OCCP0">
|
|
<name>OCU_OCCP3</name>
|
|
<description>OCU ch.3 Compare Value Store Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP4" -->
|
|
<register derivedFrom="OCU_OCCP0">
|
|
<name>OCU_OCCP4</name>
|
|
<description>OCU ch.4 Compare Value Store Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "OCU_OCCP5" -->
|
|
<register derivedFrom="OCU_OCCP0">
|
|
<name>OCU_OCCP5</name>
|
|
<description>OCU ch.5 Compare Value Store Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFSA10" -->
|
|
<register>
|
|
<name>WFG_WFSA10</name>
|
|
<description>WFG ch.10 Control Register A</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x1FFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DCK" -->
|
|
<field>
|
|
<name>DCK</name>
|
|
<description>clock cycle of the WFG timer</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMD" -->
|
|
<field>
|
|
<name>TMD</name>
|
|
<description>WFG's operation mode</description>
|
|
<lsb>3</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "GTEN" -->
|
|
<field>
|
|
<name>GTEN</name>
|
|
<description>the CH_GATE signal for each channel of WFG</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PSEL" -->
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>the PPG timer unit to be used at each channel of WFG</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PGEN" -->
|
|
<field>
|
|
<name>PGEN</name>
|
|
<description>specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DMOD" -->
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>specifies which polarity will be used to output the non-overlap signal</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFSA32" -->
|
|
<register derivedFrom="WFG_WFSA10">
|
|
<name>WFG_WFSA32</name>
|
|
<description>WFG ch.32 Control Register A</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFSA54" -->
|
|
<register derivedFrom="WFG_WFSA10">
|
|
<name>WFG_WFSA54</name>
|
|
<description>WFG ch.54 Control Register A</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFTM10" -->
|
|
<register>
|
|
<name>WFG_WFTM10</name>
|
|
<description>WFG ch.10 Timer Value Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFTM32" -->
|
|
<register derivedFrom="WFG_WFTM10">
|
|
<name>WFG_WFTM32</name>
|
|
<description>WFG ch.32 Timer Value Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFTM54" -->
|
|
<register derivedFrom="WFG_WFTM10">
|
|
<name>WFG_WFTM54</name>
|
|
<description>WFG ch.54 Timer Value Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "WFG_NZCL" -->
|
|
<register>
|
|
<name>WFG_NZCL</name>
|
|
<description>NZCL Control Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x001F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DTIE" -->
|
|
<field>
|
|
<name>DTIE</name>
|
|
<description>DTIF interrupt enable</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "NWS" -->
|
|
<field>
|
|
<name>NWS</name>
|
|
<description>noise-canceling width of the noise-canceller for the DTTIX pin</description>
|
|
<lsb>1</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SDTI" -->
|
|
<field>
|
|
<name>SDTI</name>
|
|
<description>Forcibly generates DTIF interrupt</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WFG_WFIR" -->
|
|
<register>
|
|
<name>WFG_WFIR</name>
|
|
<description>WFG Interrupt Control Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFF3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DTIF" -->
|
|
<field>
|
|
<name>DTIF</name>
|
|
<description>Indicates that DTIF interrupt has been generated.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "DTIC" -->
|
|
<field>
|
|
<name>DTIC</name>
|
|
<description>Clears WFIR.DTIF and deasserts the DTIF interrupt signal.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIF10" -->
|
|
<field>
|
|
<name>TMIF10</name>
|
|
<description>Indicates that WFG10 timer interrupt has been generated.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIC10" -->
|
|
<field>
|
|
<name>TMIC10</name>
|
|
<description>Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIE10" -->
|
|
<field>
|
|
<name>TMIE10</name>
|
|
<description>Starts the WFG10 timer</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMIS10" -->
|
|
<field>
|
|
<name>TMIS10</name>
|
|
<description>Stops the WFG10 timer</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIF32" -->
|
|
<field>
|
|
<name>TMIF32</name>
|
|
<description>Indicates that WFG32 timer interrupt has been generated.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIC32" -->
|
|
<field>
|
|
<name>TMIC32</name>
|
|
<description>Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIE32" -->
|
|
<field>
|
|
<name>TMIE32</name>
|
|
<description>Starts the WFG32 timer</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMIS32" -->
|
|
<field>
|
|
<name>TMIS32</name>
|
|
<description>Stops the WFG32 timer</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIF54" -->
|
|
<field>
|
|
<name>TMIF54</name>
|
|
<description>Indicates that WFG54 timer interrupt has been generated.</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIC54" -->
|
|
<field>
|
|
<name>TMIC54</name>
|
|
<description>Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal.</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "TMIE54" -->
|
|
<field>
|
|
<name>TMIE54</name>
|
|
<description>Starts the WFG54 timer</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMIS54" -->
|
|
<field>
|
|
<name>TMIS54</name>
|
|
<description>Stops the WFG54 timer</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICFS10" -->
|
|
<register>
|
|
<name>ICU_ICFS10</name>
|
|
<description>"ICU ch.1,0 Connecting FRT Select Register"</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FSI0" -->
|
|
<field>
|
|
<name>FSI0</name>
|
|
<description>Connects FRT ch.x to ICU ch.(0)</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSI1" -->
|
|
<field>
|
|
<name>FSI1</name>
|
|
<description>Connects FRT ch.x to ICU ch.(1)</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICFS32" -->
|
|
<register derivedFrom="ICU_ICFS10">
|
|
<name>ICU_ICFS32</name>
|
|
<description>"ICU ch.3,2 Connecting FRT Select Register"</description>
|
|
<addressOffset>0x61</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICSA10" -->
|
|
<register>
|
|
<name>ICU_ICSA10</name>
|
|
<description>"ICU ch.1,0 Control Register A"</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EG0" -->
|
|
<field>
|
|
<name>EG0</name>
|
|
<description>enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EG1" -->
|
|
<field>
|
|
<name>EG1</name>
|
|
<description>enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICE0" -->
|
|
<field>
|
|
<name>ICE0</name>
|
|
<description>"Generates interrupt, when ""1"" is set to ICSA.ICP0."</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICE1" -->
|
|
<field>
|
|
<name>ICE1</name>
|
|
<description>"Generates interrupt, when ""1"" is set to ICSA.ICP1."</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICP0" -->
|
|
<field>
|
|
<name>ICP0</name>
|
|
<description>Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ICP1" -->
|
|
<field>
|
|
<name>ICP1</name>
|
|
<description>Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICSA32" -->
|
|
<register derivedFrom="ICU_ICSA10">
|
|
<name>ICU_ICSA32</name>
|
|
<description>"ICU ch.3,2 Control Register A"</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICSB10" -->
|
|
<register>
|
|
<name>ICU_ICSB10</name>
|
|
<description>"ICU ch.1,0 Control Register B"</description>
|
|
<addressOffset>0x79</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "IEI0" -->
|
|
<field>
|
|
<name>IEI0</name>
|
|
<description>indicates the latest valid edge of ICU-ch.(0)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "IEI1" -->
|
|
<field>
|
|
<name>IEI1</name>
|
|
<description>indicates the latest valid edge of ICU-ch.(1)</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICSB32" -->
|
|
<register derivedFrom="ICU_ICSB10">
|
|
<name>ICU_ICSB32</name>
|
|
<description>"ICU ch.3,2 Control Register B"</description>
|
|
<addressOffset>0x7D</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICCP0" -->
|
|
<register>
|
|
<name>ICU_ICCP0</name>
|
|
<description>ICU ch.0 Capture value store register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICCP1" -->
|
|
<register derivedFrom="ICU_ICCP0">
|
|
<name>ICU_ICCP1</name>
|
|
<description>ICU ch.1 Capture value store register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICCP2" -->
|
|
<register derivedFrom="ICU_ICCP0">
|
|
<name>ICU_ICCP2</name>
|
|
<description>ICU ch.2 Capture value store register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ICU_ICCP3" -->
|
|
<register derivedFrom="ICU_ICCP0">
|
|
<name>ICU_ICCP3</name>
|
|
<description>ICU ch.3 Capture value store register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACSA" -->
|
|
<register>
|
|
<name>ADCMP_ACSA</name>
|
|
<description>ADCMP Control Register A</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x3F3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CE0" -->
|
|
<field>
|
|
<name>CE0</name>
|
|
<description>enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CE1" -->
|
|
<field>
|
|
<name>CE1</name>
|
|
<description>enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CE2" -->
|
|
<field>
|
|
<name>CE2</name>
|
|
<description>enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL0" -->
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL1" -->
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL2" -->
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACSB" -->
|
|
<register>
|
|
<name>ADCMP_ACSB</name>
|
|
<description>ADCMP Control Register B</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x07</resetValue>
|
|
<resetMask>0x77</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BDIS0" -->
|
|
<field>
|
|
<name>BDIS0</name>
|
|
<description>Disables the buffer function of the ACCP0 and ACCPDN0 registers</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDIS1" -->
|
|
<field>
|
|
<name>BDIS1</name>
|
|
<description>Disables the buffer function of the ACCP1 and ACCPDN1 registers</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDIS2" -->
|
|
<field>
|
|
<name>BDIS2</name>
|
|
<description>Disables the buffer function of the ACCP2 and ACCPDN2 registers</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BTS0" -->
|
|
<field>
|
|
<name>BTS0</name>
|
|
<description>Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BTS1" -->
|
|
<field>
|
|
<name>BTS1</name>
|
|
<description>Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BTS2" -->
|
|
<field>
|
|
<name>BTS2</name>
|
|
<description>Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCP0" -->
|
|
<register>
|
|
<name>ADCMP_ACCP0</name>
|
|
<description>ADCMP ch.0 Compare Value Store Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCP1" -->
|
|
<register derivedFrom="ADCMP_ACCP0">
|
|
<name>ADCMP_ACCP1</name>
|
|
<description>ADCMP ch.1 Compare Value Store Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCP2" -->
|
|
<register derivedFrom="ADCMP_ACCP0">
|
|
<name>ADCMP_ACCP2</name>
|
|
<description>ADCMP ch.2 Compare Value Store Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCPDN0" -->
|
|
<register>
|
|
<name>ADCMP_ACCPDN0</name>
|
|
<description>ADCMP ch.0 Compare Value Store Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCPDN1" -->
|
|
<register derivedFrom="ADCMP_ACCPDN0">
|
|
<name>ADCMP_ACCPDN1</name>
|
|
<description>ADCMP ch.1 Compare Value Store Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ACCPDN2" -->
|
|
<register derivedFrom="ADCMP_ACCPDN0">
|
|
<name>ADCMP_ACCPDN2</name>
|
|
<description>ADCMP ch.2 Compare Value Store Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADCMP_ATSA" -->
|
|
<register>
|
|
<name>ADCMP_ATSA</name>
|
|
<description>ADC Start Trigger Select Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x3F3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AD0S" -->
|
|
<field>
|
|
<name>AD0S</name>
|
|
<description>selects the start signal to be used to start the scan conversion of ADC unit0</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD1S" -->
|
|
<field>
|
|
<name>AD1S</name>
|
|
<description>selects the start signal to be used to start the scan conversion of ADC unit1</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD2S" -->
|
|
<field>
|
|
<name>AD2S</name>
|
|
<description>selects the start signal to be used to start the scan conversion of ADC unit2</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD0P" -->
|
|
<field>
|
|
<name>AD0P</name>
|
|
<description>selects the start signal to be used to start priority conversion of ADC unit0</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD1P" -->
|
|
<field>
|
|
<name>AD1P</name>
|
|
<description>selects the start signal to be used to start priority conversion of ADC unit1</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD2P" -->
|
|
<field>
|
|
<name>AD2P</name>
|
|
<description>selects the start signal to be used to start priority conversion of ADC unit2</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BTIOSEL03" -->
|
|
<peripheral>
|
|
<name>BTIOSEL03</name>
|
|
<description> Base Timer I/O Select</description>
|
|
<groupName>BTIOSEL03</groupName>
|
|
<baseAddress>0x40025100</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "BTSEL0123" -->
|
|
<register>
|
|
<name>BTSEL0123</name>
|
|
<description>I/O Select Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SEL23_" -->
|
|
<field>
|
|
<name>SEL23_</name>
|
|
<description>I/O select bits for Ch.2/Ch.3 </description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL01_" -->
|
|
<field>
|
|
<name>SEL01_</name>
|
|
<description>I/O select bits for Ch.0/Ch.1 </description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BTIOSEL47" -->
|
|
<peripheral>
|
|
<name>BTIOSEL47</name>
|
|
<description> Base Timer I/O Select</description>
|
|
<groupName>BTIOSEL47</groupName>
|
|
<baseAddress>0x40025300</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "BTSEL4567" -->
|
|
<register>
|
|
<name>BTSEL4567</name>
|
|
<description>I/O Select Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SEL67_" -->
|
|
<field>
|
|
<name>SEL67_</name>
|
|
<description>I/O select bits for Ch.6/Ch.7 </description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL45_" -->
|
|
<field>
|
|
<name>SEL45_</name>
|
|
<description>I/O select bits for Ch.4/Ch.5</description>
|
|
<lsb>8</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "SBSSR" -->
|
|
<peripheral>
|
|
<name>SBSSR</name>
|
|
<description>Software-based Simultaneous Startup Register</description>
|
|
<groupName>SBSSR</groupName>
|
|
<baseAddress>0x40025F00</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0FC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "BTSSSR" -->
|
|
<register>
|
|
<name>BTSSSR</name>
|
|
<description>Software-based Simultaneous Startup Register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SSSR15" -->
|
|
<field>
|
|
<name>SSSR15</name>
|
|
<description>Bit15 of BTSSSR</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR14" -->
|
|
<field>
|
|
<name>SSSR14</name>
|
|
<description>Bit14 of BTSSSR</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR13" -->
|
|
<field>
|
|
<name>SSSR13</name>
|
|
<description>Bit13 of BTSSSR</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR12" -->
|
|
<field>
|
|
<name>SSSR12</name>
|
|
<description>Bit12 of BTSSSR</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR11" -->
|
|
<field>
|
|
<name>SSSR11</name>
|
|
<description>Bit11 of BTSSSR</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR10" -->
|
|
<field>
|
|
<name>SSSR10</name>
|
|
<description>Bit10 of BTSSSR</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR9" -->
|
|
<field>
|
|
<name>SSSR9</name>
|
|
<description>Bit9 of BTSSSR</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR8" -->
|
|
<field>
|
|
<name>SSSR8</name>
|
|
<description>Bit8 of BTSSSR</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR7" -->
|
|
<field>
|
|
<name>SSSR7</name>
|
|
<description>Bit7 of BTSSSR</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR6" -->
|
|
<field>
|
|
<name>SSSR6</name>
|
|
<description>Bit6 of BTSSSR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR5" -->
|
|
<field>
|
|
<name>SSSR5</name>
|
|
<description>Bit5 of BTSSSR</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR4" -->
|
|
<field>
|
|
<name>SSSR4</name>
|
|
<description>Bit4 of BTSSSR</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR3" -->
|
|
<field>
|
|
<name>SSSR3</name>
|
|
<description>Bit3 of BTSSSR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR2" -->
|
|
<field>
|
|
<name>SSSR2</name>
|
|
<description>Bit2 of BTSSSR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR1" -->
|
|
<field>
|
|
<name>SSSR1</name>
|
|
<description>Bit1 of BTSSSR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<!-- FIELD "SSSR0" -->
|
|
<field>
|
|
<name>SSSR0</name>
|
|
<description>Bit0 of BTSSSR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT0" -->
|
|
<peripheral>
|
|
<name>BT0</name>
|
|
<description>Base Timer 0</description>
|
|
<groupName>BT0</groupName>
|
|
<baseAddress>0x40025000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "BTIM0_7" -->
|
|
<interrupt>
|
|
<name>BTIM0_7</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "PWM_TMCR" -->
|
|
<register>
|
|
<name>PWM_TMCR</name>
|
|
<description>Timer Control Register</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7F7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS2_0" -->
|
|
<field>
|
|
<name>CKS2_0</name>
|
|
<description>Count clock selection bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTGEN" -->
|
|
<field>
|
|
<name>RTGEN</name>
|
|
<description>Restart enable bit </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PMSK" -->
|
|
<field>
|
|
<name>PMSK</name>
|
|
<description>Pulse output mask bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EGS" -->
|
|
<field>
|
|
<name>EGS</name>
|
|
<description>Trigger input edge selection bits </description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FMD" -->
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Timer function selection bits </description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OSEL" -->
|
|
<field>
|
|
<name>OSEL</name>
|
|
<description>Output polarity specification bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MDSE" -->
|
|
<field>
|
|
<name>MDSE</name>
|
|
<description>Mode selection bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CTEN" -->
|
|
<field>
|
|
<name>CTEN</name>
|
|
<description>Count operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STRG" -->
|
|
<field>
|
|
<name>STRG</name>
|
|
<description>Software trigger bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWM_TMCR2" -->
|
|
<register>
|
|
<name>PWM_TMCR2</name>
|
|
<description>Timer Control Register 2</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS3" -->
|
|
<field>
|
|
<name>CKS3</name>
|
|
<description>Count clock selection bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWM_STC" -->
|
|
<register>
|
|
<name>PWM_STC</name>
|
|
<description> Status Control Register</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x77</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TGIE" -->
|
|
<field>
|
|
<name>TGIE</name>
|
|
<description>Trigger interrupt request enable bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DTIE" -->
|
|
<field>
|
|
<name>DTIE</name>
|
|
<description>Duty match interrupt request enable bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIE" -->
|
|
<field>
|
|
<name>UDIE</name>
|
|
<description>Underflow interrupt request enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TGIR" -->
|
|
<field>
|
|
<name>TGIR</name>
|
|
<description>Trigger interrupt request bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DTIR" -->
|
|
<field>
|
|
<name>DTIR</name>
|
|
<description>Duty match interrupt request bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIR" -->
|
|
<field>
|
|
<name>UDIR</name>
|
|
<description>Underflow interrupt request bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWM_PCSR" -->
|
|
<register>
|
|
<name>PWM_PCSR</name>
|
|
<description>PWM Cycle Set Register</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PWM_PDUT" -->
|
|
<register>
|
|
<name>PWM_PDUT</name>
|
|
<description>PWM Duty Set Register</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PWM_TMR" -->
|
|
<register>
|
|
<name>PWM_TMR</name>
|
|
<description>Timer Register</description>
|
|
<alternateGroup>PWM</alternateGroup>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PPG_TMCR" -->
|
|
<register>
|
|
<name>PPG_TMCR</name>
|
|
<description>Timer Control Register</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7F7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS2_0" -->
|
|
<field>
|
|
<name>CKS2_0</name>
|
|
<description>Count clock selection bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTGEN" -->
|
|
<field>
|
|
<name>RTGEN</name>
|
|
<description>Restart enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PMSK" -->
|
|
<field>
|
|
<name>PMSK</name>
|
|
<description> Pulse output mask bit </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EGS" -->
|
|
<field>
|
|
<name>EGS</name>
|
|
<description>Trigger input edge selection bits</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FMD" -->
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Timer function selection bits</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OSEL" -->
|
|
<field>
|
|
<name>OSEL</name>
|
|
<description>Output polarity specification bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MDSE" -->
|
|
<field>
|
|
<name>MDSE</name>
|
|
<description>Mode selection bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CTEN" -->
|
|
<field>
|
|
<name>CTEN</name>
|
|
<description>Count operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STRG" -->
|
|
<field>
|
|
<name>STRG</name>
|
|
<description>Software trigger bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PPG_TMCR2" -->
|
|
<register>
|
|
<name>PPG_TMCR2</name>
|
|
<description>Timer Control Register 2</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS3" -->
|
|
<field>
|
|
<name>CKS3</name>
|
|
<description>Count clock selection bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PPG_STC" -->
|
|
<register>
|
|
<name>PPG_STC</name>
|
|
<description>Status Control Register</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x55</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TGIE" -->
|
|
<field>
|
|
<name>TGIE</name>
|
|
<description>Trigger interrupt request enable bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIE" -->
|
|
<field>
|
|
<name>UDIE</name>
|
|
<description>Underflow interrupt request enable bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TGIR" -->
|
|
<field>
|
|
<name>TGIR</name>
|
|
<description>Trigger interrupt request bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIR" -->
|
|
<field>
|
|
<name>UDIR</name>
|
|
<description>Underflow interrupt request bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PPG_PRLL" -->
|
|
<register>
|
|
<name>PPG_PRLL</name>
|
|
<description>LOW Width Reload Register</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PPG_PRLH" -->
|
|
<register>
|
|
<name>PPG_PRLH</name>
|
|
<description>HIGH Width Reload Register</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PPG_TMR" -->
|
|
<register>
|
|
<name>PPG_TMR</name>
|
|
<description>Timer Register</description>
|
|
<alternateGroup>PPG</alternateGroup>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "RT_TMCR" -->
|
|
<register>
|
|
<name>RT_TMCR</name>
|
|
<description>Timer Control Register</description>
|
|
<alternateGroup>RT</alternateGroup>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x73FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS2_0" -->
|
|
<field>
|
|
<name>CKS2_0</name>
|
|
<description>Count clock selection bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EGS" -->
|
|
<field>
|
|
<name>EGS</name>
|
|
<description>Trigger input edge selection bits</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "T32" -->
|
|
<field>
|
|
<name>T32</name>
|
|
<description>32-bit timer selection bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FMD" -->
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Timer function selection bits </description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OSEL" -->
|
|
<field>
|
|
<name>OSEL</name>
|
|
<description>Output polarity specification bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MDSE" -->
|
|
<field>
|
|
<name>MDSE</name>
|
|
<description>Mode selection bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CTEN" -->
|
|
<field>
|
|
<name>CTEN</name>
|
|
<description>Timer enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STRG" -->
|
|
<field>
|
|
<name>STRG</name>
|
|
<description>Software trigger bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RT_TMCR2" -->
|
|
<register>
|
|
<name>RT_TMCR2</name>
|
|
<description>Timer Control Register 2</description>
|
|
<alternateGroup>RT</alternateGroup>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS3" -->
|
|
<field>
|
|
<name>CKS3</name>
|
|
<description>Count clock selection bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RT_STC" -->
|
|
<register>
|
|
<name>RT_STC</name>
|
|
<description>Status Control Register</description>
|
|
<alternateGroup>RT</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x55</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TGIE" -->
|
|
<field>
|
|
<name>TGIE</name>
|
|
<description>Trigger interrupt request enable bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIE" -->
|
|
<field>
|
|
<name>UDIE</name>
|
|
<description>Underflow interrupt request enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TGIR" -->
|
|
<field>
|
|
<name>TGIR</name>
|
|
<description>Trigger interrupt request bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UDIR" -->
|
|
<field>
|
|
<name>UDIR</name>
|
|
<description>Underflow interrupt request bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RT_PCSR" -->
|
|
<register>
|
|
<name>RT_PCSR</name>
|
|
<description>PWM Cycle Set Register</description>
|
|
<alternateGroup>RT</alternateGroup>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "RT_TMR" -->
|
|
<register>
|
|
<name>RT_TMR</name>
|
|
<description>Timer Register</description>
|
|
<alternateGroup>RT</alternateGroup>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
</register>
|
|
<!-- REGISTER "PWC_TMCR" -->
|
|
<register>
|
|
<name>PWC_TMCR</name>
|
|
<description>Timer Control Register</description>
|
|
<alternateGroup>PWC</alternateGroup>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x77F6</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS2_0" -->
|
|
<field>
|
|
<name>CKS2_0</name>
|
|
<description>Count clock selection bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EGS" -->
|
|
<field>
|
|
<name>EGS</name>
|
|
<description>Measurement edge selection bits </description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "T32" -->
|
|
<field>
|
|
<name>T32</name>
|
|
<description>32-bit timer selection bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FMD" -->
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Timer function selection bits </description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MDSE" -->
|
|
<field>
|
|
<name>MDSE</name>
|
|
<description>Mode selection bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CTEN" -->
|
|
<field>
|
|
<name>CTEN</name>
|
|
<description>Timer enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWC_TMCR2" -->
|
|
<register>
|
|
<name>PWC_TMCR2</name>
|
|
<description>Timer Control Register 2</description>
|
|
<alternateGroup>PWC</alternateGroup>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CKS3" -->
|
|
<field>
|
|
<name>CKS3</name>
|
|
<description>Count clock selection bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWC_STC" -->
|
|
<register>
|
|
<name>PWC_STC</name>
|
|
<description>Status Control Register</description>
|
|
<alternateGroup>PWC</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xD5</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ERR" -->
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Error flag bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "EDIE" -->
|
|
<field>
|
|
<name>EDIE</name>
|
|
<description>Measurement completion interrupt request enable bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OVIE" -->
|
|
<field>
|
|
<name>OVIE</name>
|
|
<description>Overflow interrupt request enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EDIR" -->
|
|
<field>
|
|
<name>EDIR</name>
|
|
<description>Measurement completion interrupt request bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OVIR" -->
|
|
<field>
|
|
<name>OVIR</name>
|
|
<description>Overflow interrupt request bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PWC_DTBF" -->
|
|
<register>
|
|
<name>PWC_DTBF</name>
|
|
<description>Data Buffer Register</description>
|
|
<alternateGroup>PWC</alternateGroup>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT1" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT1</name>
|
|
<baseAddress>0x40025040</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT2" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT2</name>
|
|
<baseAddress>0x40025080</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT3" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT3</name>
|
|
<baseAddress>0x400250C0</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT4" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT4</name>
|
|
<baseAddress>0x40025200</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT5" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT5</name>
|
|
<baseAddress>0x40025240</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT6" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT6</name>
|
|
<baseAddress>0x40025280</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "BT7" -->
|
|
<peripheral derivedFrom="BT0">
|
|
<name>BT7</name>
|
|
<baseAddress>0x400252C0</baseAddress>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "QPRC0" -->
|
|
<peripheral>
|
|
<name>QPRC0</name>
|
|
<description>Quadrature Position/Revolution Counter 0</description>
|
|
<groupName>QPRC0</groupName>
|
|
<baseAddress>0x40026000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3E</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "QPCR" -->
|
|
<register>
|
|
<name>QPCR</name>
|
|
<description>QPRC Position Count Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QRCR" -->
|
|
<register>
|
|
<name>QRCR</name>
|
|
<description>QPRC Revolution Count Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QPCCR" -->
|
|
<register>
|
|
<name>QPCCR</name>
|
|
<description>QPRC Position Counter Compare Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QPRCR" -->
|
|
<register>
|
|
<name>QPRCR</name>
|
|
<description>QPRC Position and Revolution Counter Compare Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QCR" -->
|
|
<register>
|
|
<name>QCR</name>
|
|
<description>QPRC Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CGE" -->
|
|
<field>
|
|
<name>CGE</name>
|
|
<description>Detection edge selection bits</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BES" -->
|
|
<field>
|
|
<name>BES</name>
|
|
<description>BIN detection edge selection bits</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AES" -->
|
|
<field>
|
|
<name>AES</name>
|
|
<description>AIN detection edge selection bits</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCRM" -->
|
|
<field>
|
|
<name>PCRM</name>
|
|
<description>Position counter reset mask bits</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SWAP" -->
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RSEL" -->
|
|
<field>
|
|
<name>RSEL</name>
|
|
<description>Register function selection bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CGSC" -->
|
|
<field>
|
|
<name>CGSC</name>
|
|
<description>Count clear or gate selection bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PSTP" -->
|
|
<field>
|
|
<name>PSTP</name>
|
|
<description>Position counter stop bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RCM" -->
|
|
<field>
|
|
<name>RCM</name>
|
|
<description>Revolution counter mode bits</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCM" -->
|
|
<field>
|
|
<name>PCM</name>
|
|
<description>Position counter mode bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "QECR" -->
|
|
<register>
|
|
<name>QECR</name>
|
|
<description>QPRC Extension Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0007</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ORNGIE" -->
|
|
<field>
|
|
<name>ORNGIE</name>
|
|
<description>Outrange interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ORNGF" -->
|
|
<field>
|
|
<name>ORNGF</name>
|
|
<description>Outrange interrupt request flag bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ORNGMD" -->
|
|
<field>
|
|
<name>ORNGMD</name>
|
|
<description>Outrange mode selection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "QICRL" -->
|
|
<register>
|
|
<name>QICRL</name>
|
|
<description>Low-Order Bytes of QPRC Interrupt Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ZIIF" -->
|
|
<field>
|
|
<name>ZIIF</name>
|
|
<description>Zero index interrupt request flag bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OFDF" -->
|
|
<field>
|
|
<name>OFDF</name>
|
|
<description>Overflow interrupt request flag bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UFDF" -->
|
|
<field>
|
|
<name>UFDF</name>
|
|
<description>Underflow interrupt request flag bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OUZIE" -->
|
|
<field>
|
|
<name>OUZIE</name>
|
|
<description>"Overflow, underflow, or zero index interrupt enable bit"</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QPRCMF" -->
|
|
<field>
|
|
<name>QPRCMF</name>
|
|
<description>PC and RC match interrupt request flag bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QPRCMIE" -->
|
|
<field>
|
|
<name>QPRCMIE</name>
|
|
<description>PC and RC match interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QPCMF" -->
|
|
<field>
|
|
<name>QPCMF</name>
|
|
<description>PC match interrupt request flag bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QPCMIE" -->
|
|
<field>
|
|
<name>QPCMIE</name>
|
|
<description>PC match interrupt enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "QICRH" -->
|
|
<register>
|
|
<name>QICRH</name>
|
|
<description>High-Order Bytes of QPRC Interrupt Control Register</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "QPCNRCMF" -->
|
|
<field>
|
|
<name>QPCNRCMF</name>
|
|
<description>PC match and RC match interrupt request flag bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QPCNRCMIE" -->
|
|
<field>
|
|
<name>QPCNRCMIE</name>
|
|
<description>PC match and RC match interrupt enable bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DIROU" -->
|
|
<field>
|
|
<name>DIROU</name>
|
|
<description>Last position counter flow direction bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "DIRPC" -->
|
|
<field>
|
|
<name>DIRPC</name>
|
|
<description>Last position counter direction bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CDCF" -->
|
|
<field>
|
|
<name>CDCF</name>
|
|
<description>Count inversion interrupt request flag bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CDCIE" -->
|
|
<field>
|
|
<name>CDCIE</name>
|
|
<description>Count inversion interrupt enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "QMPR" -->
|
|
<register>
|
|
<name>QMPR</name>
|
|
<description>QPRC Maximum Position Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QRCRR" -->
|
|
<register>
|
|
<name>QRCRR</name>
|
|
<description>Quad counter rotation count Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "QPCRR" -->
|
|
<register>
|
|
<name>QPCRR</name>
|
|
<description>Quad counter position count Register</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "WC" -->
|
|
<peripheral>
|
|
<name>WC</name>
|
|
<description>Watch Counter</description>
|
|
<groupName>WC</groupName>
|
|
<baseAddress>0x4003A000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "WCRD" -->
|
|
<register>
|
|
<name>WCRD</name>
|
|
<description>Watch Counter Read Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CTR" -->
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>counter value</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WCRL" -->
|
|
<register>
|
|
<name>WCRL</name>
|
|
<description>Watch Counter Reload Register</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RLC" -->
|
|
<field>
|
|
<name>RLC</name>
|
|
<description>reload value</description>
|
|
<lsb>0</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WCCR" -->
|
|
<register>
|
|
<name>WCCR</name>
|
|
<description>Watch Counter Control Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xCF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WCEN" -->
|
|
<field>
|
|
<name>WCEN</name>
|
|
<description>Watch counter operation enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WCOP" -->
|
|
<field>
|
|
<name>WCOP</name>
|
|
<description>Watch counter operating state flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CS" -->
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Count clock select bits</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WCIE" -->
|
|
<field>
|
|
<name>WCIE</name>
|
|
<description>Interrupt request enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WCIF" -->
|
|
<field>
|
|
<name>WCIF</name>
|
|
<description>Interrupt request flag bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CLK_SEL" -->
|
|
<register>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock Selection Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0101</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SEL_OUT" -->
|
|
<field>
|
|
<name>SEL_OUT</name>
|
|
<description>Output clock selection bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SEL_IN" -->
|
|
<field>
|
|
<name>SEL_IN</name>
|
|
<description>Input clock selection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CLK_EN" -->
|
|
<register>
|
|
<name>CLK_EN</name>
|
|
<description>Division Clock Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CLK_EN_R" -->
|
|
<field>
|
|
<name>CLK_EN_R</name>
|
|
<description>Division clock enable read bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CLK_EN" -->
|
|
<field>
|
|
<name>CLK_EN</name>
|
|
<description>Division clock enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFT_PPG" -->
|
|
<peripheral>
|
|
<name>MFT_PPG</name>
|
|
<description>PPG Configuration</description>
|
|
<groupName>MFT_PPG</groupName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x104</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x200</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x204</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x208</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x210</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x214</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x218</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x240</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x244</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x248</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x250</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x254</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x258</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "PPG" -->
|
|
<interrupt>
|
|
<name>PPG</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "TTCR0" -->
|
|
<register>
|
|
<name>TTCR0</name>
|
|
<description>PPG Start Trigger Control Register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TRG6O" -->
|
|
<field>
|
|
<name>TRG6O</name>
|
|
<description>PPG6 trigger stop bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TRG4O" -->
|
|
<field>
|
|
<name>TRG4O</name>
|
|
<description>PPG4 trigger stop bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TRG2O" -->
|
|
<field>
|
|
<name>TRG2O</name>
|
|
<description>PPG2 trigger stop bit</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TRG0O" -->
|
|
<field>
|
|
<name>TRG0O</name>
|
|
<description>PPG0 trigger stop bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CS0" -->
|
|
<field>
|
|
<name>CS0</name>
|
|
<description>8-bit UP counter clock select bits for comparison</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MONI0" -->
|
|
<field>
|
|
<name>MONI0</name>
|
|
<description>8-bit UP counter operation state monitor bit for comparison</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "STR0" -->
|
|
<field>
|
|
<name>STR0</name>
|
|
<description>8-bit UP counter operation enable bit for comparison</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "COMP0" -->
|
|
<register>
|
|
<name>COMP0</name>
|
|
<description>PPG Compare Register 0</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFF00</resetMask>
|
|
</register>
|
|
<!-- REGISTER "COMP2" -->
|
|
<register>
|
|
<name>COMP2</name>
|
|
<description>PPG Compare Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "COMP4" -->
|
|
<register derivedFrom="COMP0">
|
|
<name>COMP4</name>
|
|
<description>PPG Compare Register 4</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "COMP6" -->
|
|
<register derivedFrom="COMP2">
|
|
<name>COMP6</name>
|
|
<description>PPG Compare Register 6</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TRG" -->
|
|
<register>
|
|
<name>TRG</name>
|
|
<description>PPG Start Register 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PEN07" -->
|
|
<field>
|
|
<name>PEN07</name>
|
|
<description>PPG7 Start Trigger bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN06" -->
|
|
<field>
|
|
<name>PEN06</name>
|
|
<description>PPG6 Start Trigger bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN05" -->
|
|
<field>
|
|
<name>PEN05</name>
|
|
<description>PPG5 Start Trigger bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN04" -->
|
|
<field>
|
|
<name>PEN04</name>
|
|
<description>PPG4 Start Trigger bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN03" -->
|
|
<field>
|
|
<name>PEN03</name>
|
|
<description>PPG3 Start Trigger bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN02" -->
|
|
<field>
|
|
<name>PEN02</name>
|
|
<description>PPG2 Start Trigger bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN01" -->
|
|
<field>
|
|
<name>PEN01</name>
|
|
<description>PPG1 Start Trigger bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN00" -->
|
|
<field>
|
|
<name>PEN00</name>
|
|
<description>PPG0 Start Trigger bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "REVC" -->
|
|
<register>
|
|
<name>REVC</name>
|
|
<description>Output Reverse Register 0</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "REV07" -->
|
|
<field>
|
|
<name>REV07</name>
|
|
<description>PPG7 Output Reverse Enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV06" -->
|
|
<field>
|
|
<name>REV06</name>
|
|
<description>PPG6 Output Reverse Enable bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV05" -->
|
|
<field>
|
|
<name>REV05</name>
|
|
<description>PPG5 Output Reverse Enable bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV04" -->
|
|
<field>
|
|
<name>REV04</name>
|
|
<description>PPG4 Output Reverse Enable bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV03" -->
|
|
<field>
|
|
<name>REV03</name>
|
|
<description>PPG3 Output Reverse Enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV02" -->
|
|
<field>
|
|
<name>REV02</name>
|
|
<description>PPG2 Output Reverse Enable bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV01" -->
|
|
<field>
|
|
<name>REV01</name>
|
|
<description>PPG1 Output Reverse Enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "REV00" -->
|
|
<field>
|
|
<name>REV00</name>
|
|
<description>PPG0 Output Reverse Enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PPGC0" -->
|
|
<register>
|
|
<name>PPGC0</name>
|
|
<description>PPG Operation Mode Control Register 0</description>
|
|
<addressOffset>0x201</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PIE" -->
|
|
<field>
|
|
<name>PIE</name>
|
|
<description>PPG Interrupt Enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PUF" -->
|
|
<field>
|
|
<name>PUF</name>
|
|
<description>PPG Counter Underflow bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTM" -->
|
|
<field>
|
|
<name>INTM</name>
|
|
<description>Interrupt Mode Select bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCS" -->
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>PPG DOWN Counter Operation Clock Select bits</description>
|
|
<lsb>3</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MD" -->
|
|
<field>
|
|
<name>MD</name>
|
|
<description>PPG Operation Mode Set bits</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TTRG" -->
|
|
<field>
|
|
<name>TTRG</name>
|
|
<description>PPG start trigger select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PPGC1" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC1</name>
|
|
<description>PPG Operation Mode Control Register 1</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC2" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC2</name>
|
|
<description>PPG Operation Mode Control Register 2</description>
|
|
<addressOffset>0x205</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC3" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC3</name>
|
|
<description>PPG Operation Mode Control Register 3</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC4" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC4</name>
|
|
<description>PPG Operation Mode Control Register 4</description>
|
|
<addressOffset>0x241</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC5" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC5</name>
|
|
<description>PPG Operation Mode Control Register 5</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC6" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC6</name>
|
|
<description>PPG Operation Mode Control Register 6</description>
|
|
<addressOffset>0x245</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PPGC7" -->
|
|
<register derivedFrom="PPGC0">
|
|
<name>PPGC7</name>
|
|
<description>PPG Operation Mode Control Register 7</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH0" -->
|
|
<register>
|
|
<name>PRLH0</name>
|
|
<description>PPG0 Reload Registers High</description>
|
|
<addressOffset>0x209</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PRLH" -->
|
|
<field>
|
|
<name>PRLH</name>
|
|
<description>Reload Registers High</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PRLL0" -->
|
|
<register>
|
|
<name>PRLL0</name>
|
|
<description>PPG0 Reload Registers Low</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PRLL" -->
|
|
<field>
|
|
<name>PRLL</name>
|
|
<description>Reload Registers Low</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PRLH1" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH1</name>
|
|
<description>PPG1 Reload Registers High</description>
|
|
<addressOffset>0x20D</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL1" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL1</name>
|
|
<description>PPG1 Reload Registers Low</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH2" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH2</name>
|
|
<description>PPG2 Reload Registers High</description>
|
|
<addressOffset>0x211</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL2" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL2</name>
|
|
<description>PPG2 Reload Registers Low</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH3" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH3</name>
|
|
<description>PPG3 Reload Registers High</description>
|
|
<addressOffset>0x215</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL3" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL3</name>
|
|
<description>PPG3 Reload Registers Low</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH4" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH4</name>
|
|
<description>PPG4 Reload Registers High</description>
|
|
<addressOffset>0x249</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL4" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL4</name>
|
|
<description>PPG4 Reload Registers Low</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH5" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH5</name>
|
|
<description>PPG5 Reload Registers High</description>
|
|
<addressOffset>0x24D</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL5" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL5</name>
|
|
<description>PPG5 Reload Registers Low</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH6" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH6</name>
|
|
<description>PPG6 Reload Registers High</description>
|
|
<addressOffset>0x251</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL6" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL6</name>
|
|
<description>PPG6 Reload Registers Low</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLH7" -->
|
|
<register derivedFrom="PRLH0">
|
|
<name>PRLH7</name>
|
|
<description>PPG7 Reload Registers High</description>
|
|
<addressOffset>0x255</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PRLL7" -->
|
|
<register derivedFrom="PRLL0">
|
|
<name>PRLL7</name>
|
|
<description>PPG7 Reload Registers Low</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "GATEC0" -->
|
|
<register>
|
|
<name>GATEC0</name>
|
|
<description>PPG Gate Function Control Registers 0</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x33</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "STRG2" -->
|
|
<field>
|
|
<name>STRG2</name>
|
|
<description>Select a trigger for PPG2</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EDGE2" -->
|
|
<field>
|
|
<name>EDGE2</name>
|
|
<description>Select Start Effective Level for PPG2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STRG0" -->
|
|
<field>
|
|
<name>STRG0</name>
|
|
<description>Select a trigger for PPG0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EDGE0" -->
|
|
<field>
|
|
<name>EDGE0</name>
|
|
<description>Select Start Effective Level for PPG0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "GATEC4" -->
|
|
<register>
|
|
<name>GATEC4</name>
|
|
<description>PPG Gate Function Control Registers 4</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x33</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "STRG6" -->
|
|
<field>
|
|
<name>STRG6</name>
|
|
<description>Select a trigger for PPG6</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EDGE6" -->
|
|
<field>
|
|
<name>EDGE6</name>
|
|
<description>Select Start Effective Level for PPG6</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STRG4" -->
|
|
<field>
|
|
<name>STRG4</name>
|
|
<description>Select a trigger for PPG4</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EDGE4" -->
|
|
<field>
|
|
<name>EDGE4</name>
|
|
<description>Select Start Effective Level for PPG4</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "ADC0" -->
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>ADC0 Registers</description>
|
|
<groupName>ADC0</groupName>
|
|
<baseAddress>0x40027000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x26</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "ADC0" -->
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "ADCR" -->
|
|
<register>
|
|
<name>ADCR</name>
|
|
<description>A/D Control Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xEF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SCIF" -->
|
|
<field>
|
|
<name>SCIF</name>
|
|
<description>Scan conversion interrupt request bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCIF" -->
|
|
<field>
|
|
<name>PCIF</name>
|
|
<description>Priority conversion interrupt request bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMPIF" -->
|
|
<field>
|
|
<name>CMPIF</name>
|
|
<description>Conversion result comparison interrupt request bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCIE" -->
|
|
<field>
|
|
<name>SCIE</name>
|
|
<description>Scan conversion interrupt enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCIE" -->
|
|
<field>
|
|
<name>PCIE</name>
|
|
<description>Priority conversion interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMPIE" -->
|
|
<field>
|
|
<name>CMPIE</name>
|
|
<description>Conversion result comparison interrupt enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "OVRIE" -->
|
|
<field>
|
|
<name>OVRIE</name>
|
|
<description>FIFO overrun interrupt enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADSR" -->
|
|
<register>
|
|
<name>ADSR</name>
|
|
<description>A/D Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xC7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ADSTP" -->
|
|
<field>
|
|
<name>ADSTP</name>
|
|
<description>A/D conversion forced stop bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FDAS" -->
|
|
<field>
|
|
<name>FDAS</name>
|
|
<description>FIFO data placement selection bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCNS" -->
|
|
<field>
|
|
<name>PCNS</name>
|
|
<description>Priority conversion pending flag </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PCS" -->
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Priority conversion status flag </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCS" -->
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>Scan conversion status flag </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCCR" -->
|
|
<register>
|
|
<name>SCCR</name>
|
|
<description>Scan Conversion Control Register</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xF7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SEMP" -->
|
|
<field>
|
|
<name>SEMP</name>
|
|
<description>Scan conversion FIFO empty bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SFUL" -->
|
|
<field>
|
|
<name>SFUL</name>
|
|
<description>Scan conversion FIFO full bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SOVR" -->
|
|
<field>
|
|
<name>SOVR</name>
|
|
<description>Scan conversion overrun flag </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SFCLR" -->
|
|
<field>
|
|
<name>SFCLR</name>
|
|
<description>Scan conversion FIFO clear bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RPT" -->
|
|
<field>
|
|
<name>RPT</name>
|
|
<description>Scan conversion repeat bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SHEN" -->
|
|
<field>
|
|
<name>SHEN</name>
|
|
<description>Scan conversion timer start enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SSTR" -->
|
|
<field>
|
|
<name>SSTR</name>
|
|
<description>Scan conversion start bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SFNS" -->
|
|
<register>
|
|
<name>SFNS</name>
|
|
<description>Scan Conversion FIFO Stage Count Setup Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SFS" -->
|
|
<field>
|
|
<name>SFS</name>
|
|
<description>Scan conversion FIFO stage count setting bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCFD" -->
|
|
<register>
|
|
<name>SCFD</name>
|
|
<description>Scan Conversion FIFO Data Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFF0131F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SD" -->
|
|
<field>
|
|
<name>SD</name>
|
|
<description>Scan conversion result </description>
|
|
<lsb>20</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "INVL" -->
|
|
<field>
|
|
<name>INVL</name>
|
|
<description>A/D conversion result disable bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RS" -->
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Scan conversion start factor</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CS" -->
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Conversion input channel bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCIS3" -->
|
|
<register>
|
|
<name>SCIS3</name>
|
|
<description>Scan Conversion Input Selection Register 3</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AN31" -->
|
|
<field>
|
|
<name>AN31</name>
|
|
<description>Bit7 of SCIS3</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN30" -->
|
|
<field>
|
|
<name>AN30</name>
|
|
<description>Bit6 of SCIS3</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN29" -->
|
|
<field>
|
|
<name>AN29</name>
|
|
<description>Bit5 of SCIS3</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN28" -->
|
|
<field>
|
|
<name>AN28</name>
|
|
<description>Bit4 of SCIS3</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN27" -->
|
|
<field>
|
|
<name>AN27</name>
|
|
<description>Bit3 of SCIS3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN26" -->
|
|
<field>
|
|
<name>AN26</name>
|
|
<description>Bit2 of SCIS3</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN25" -->
|
|
<field>
|
|
<name>AN25</name>
|
|
<description>Bit1 of SCIS3</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN24" -->
|
|
<field>
|
|
<name>AN24</name>
|
|
<description>Bit0 of SCIS3</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCIS2" -->
|
|
<register>
|
|
<name>SCIS2</name>
|
|
<description>Scan Conversion Input Selection Register 2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AN23" -->
|
|
<field>
|
|
<name>AN23</name>
|
|
<description>Bit7 of SCIS2</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN22" -->
|
|
<field>
|
|
<name>AN22</name>
|
|
<description>Bit6 of SCIS2</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN21" -->
|
|
<field>
|
|
<name>AN21</name>
|
|
<description>Bit5 of SCIS2</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN20" -->
|
|
<field>
|
|
<name>AN20</name>
|
|
<description>Bit4 of SCIS2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN19" -->
|
|
<field>
|
|
<name>AN19</name>
|
|
<description>Bit3 of SCIS2</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN18" -->
|
|
<field>
|
|
<name>AN18</name>
|
|
<description>Bit2 of SCIS2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN17" -->
|
|
<field>
|
|
<name>AN17</name>
|
|
<description>Bit1 of SCIS2</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN16" -->
|
|
<field>
|
|
<name>AN16</name>
|
|
<description>Bit0 of SCIS2</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCIS1" -->
|
|
<register>
|
|
<name>SCIS1</name>
|
|
<description>Scan Conversion Input Selection Register 1</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AN15" -->
|
|
<field>
|
|
<name>AN15</name>
|
|
<description>Bit7 of SCIS1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN14" -->
|
|
<field>
|
|
<name>AN14</name>
|
|
<description>Bit6 of SCIS1</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN13" -->
|
|
<field>
|
|
<name>AN13</name>
|
|
<description>Bit5 of SCIS1</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN12" -->
|
|
<field>
|
|
<name>AN12</name>
|
|
<description>Bit4 of SCIS1</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN11" -->
|
|
<field>
|
|
<name>AN11</name>
|
|
<description>Bit3 of SCIS1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN10" -->
|
|
<field>
|
|
<name>AN10</name>
|
|
<description>Bit2 of SCIS1</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN9" -->
|
|
<field>
|
|
<name>AN9</name>
|
|
<description>Bit1 of SCIS1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN8" -->
|
|
<field>
|
|
<name>AN8</name>
|
|
<description>Bit0 of SCIS1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCIS0" -->
|
|
<register>
|
|
<name>SCIS0</name>
|
|
<description>Scan Conversion Input Selection Register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AN7" -->
|
|
<field>
|
|
<name>AN7</name>
|
|
<description>Bit7 of SCIS0</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN6" -->
|
|
<field>
|
|
<name>AN6</name>
|
|
<description>Bit6 of SCIS0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN5" -->
|
|
<field>
|
|
<name>AN5</name>
|
|
<description>Bit5 of SCIS0</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN4" -->
|
|
<field>
|
|
<name>AN4</name>
|
|
<description>Bit4 of SCIS0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN3" -->
|
|
<field>
|
|
<name>AN3</name>
|
|
<description>Bit3 of SCIS0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN2" -->
|
|
<field>
|
|
<name>AN2</name>
|
|
<description>Bit2 of SCIS0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN1" -->
|
|
<field>
|
|
<name>AN1</name>
|
|
<description>Bit1 of SCIS0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN0" -->
|
|
<field>
|
|
<name>AN0</name>
|
|
<description>Bit0 of SCIS0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFNS" -->
|
|
<register>
|
|
<name>PFNS</name>
|
|
<description>Priority Conversion FIFO Stage Count Setup Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x33</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TEST" -->
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test bits</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PFS" -->
|
|
<field>
|
|
<name>PFS</name>
|
|
<description>Priority conversion FIFO stage count setting bits </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PCCR" -->
|
|
<register>
|
|
<name>PCCR</name>
|
|
<description>Priority Conversion Control Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PEMP" -->
|
|
<field>
|
|
<name>PEMP</name>
|
|
<description>Priority conversion FIFO empty bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PFUL" -->
|
|
<field>
|
|
<name>PFUL</name>
|
|
<description>Priority conversion FIFO full bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "POVR" -->
|
|
<field>
|
|
<name>POVR</name>
|
|
<description>Priority conversion overrun flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PFCLR" -->
|
|
<field>
|
|
<name>PFCLR</name>
|
|
<description>Priority conversion FIFO clear bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ESCE" -->
|
|
<field>
|
|
<name>ESCE</name>
|
|
<description>External trigger analog input selection bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEEN" -->
|
|
<field>
|
|
<name>PEEN</name>
|
|
<description>Priority conversion external start enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PHEN" -->
|
|
<field>
|
|
<name>PHEN</name>
|
|
<description>Priority conversion timer start enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PSTR" -->
|
|
<field>
|
|
<name>PSTR</name>
|
|
<description>Priority conversion start bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PCFD" -->
|
|
<register>
|
|
<name>PCFD</name>
|
|
<description>Priority Conversion FIFO Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFF0131F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PD" -->
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Priority conversion result </description>
|
|
<lsb>20</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "INVL" -->
|
|
<field>
|
|
<name>INVL</name>
|
|
<description>A/D conversion result disable bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RS" -->
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Scan conversion start factor</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PC" -->
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Conversion input channel bits </description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PCIS" -->
|
|
<register>
|
|
<name>PCIS</name>
|
|
<description>Priority Conversion Input Selection Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P2A" -->
|
|
<field>
|
|
<name>P2A</name>
|
|
<description>Priority level 2 analog input selection </description>
|
|
<lsb>3</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1A" -->
|
|
<field>
|
|
<name>P1A</name>
|
|
<description>Priority level 1 analog input selection </description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CMPCR" -->
|
|
<register>
|
|
<name>CMPCR</name>
|
|
<description>A/D Comparison Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CMPEN" -->
|
|
<field>
|
|
<name>CMPEN</name>
|
|
<description>Conversion result comparison function operation enable bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMD" -->
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Comparison mode 1</description>
|
|
<lsb>5</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CCH" -->
|
|
<field>
|
|
<name>CCH</name>
|
|
<description>Comparison mode 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CMPD" -->
|
|
<register>
|
|
<name>CMPD</name>
|
|
<description>A/D Comparison Value Setup Register</description>
|
|
<addressOffset>0x26</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFC0</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CMAD" -->
|
|
<field>
|
|
<name>CMAD</name>
|
|
<description>A/D conversion result value setting bits </description>
|
|
<lsb>6</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADSS3" -->
|
|
<register>
|
|
<name>ADSS3</name>
|
|
<description>Sampling Time Selection Register 3</description>
|
|
<addressOffset>0x29</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TS31" -->
|
|
<field>
|
|
<name>TS31</name>
|
|
<description>Bit7 of ADSS3</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS30" -->
|
|
<field>
|
|
<name>TS30</name>
|
|
<description>Bit6 of ADSS3</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS29" -->
|
|
<field>
|
|
<name>TS29</name>
|
|
<description>Bit5 of ADSS3</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS28" -->
|
|
<field>
|
|
<name>TS28</name>
|
|
<description>Bit4 of ADSS3</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS27" -->
|
|
<field>
|
|
<name>TS27</name>
|
|
<description>Bit3 of ADSS3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS26" -->
|
|
<field>
|
|
<name>TS26</name>
|
|
<description>Bit2 of ADSS3</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS25" -->
|
|
<field>
|
|
<name>TS25</name>
|
|
<description>Bit1 of ADSS3</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS24" -->
|
|
<field>
|
|
<name>TS24</name>
|
|
<description>Bit0 of ADSS3</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADSS2" -->
|
|
<register>
|
|
<name>ADSS2</name>
|
|
<description>Sampling Time Selection Register 2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TS23" -->
|
|
<field>
|
|
<name>TS23</name>
|
|
<description>Bit7 of ADSS2</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS22" -->
|
|
<field>
|
|
<name>TS22</name>
|
|
<description>Bit6 of ADSS2</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS21" -->
|
|
<field>
|
|
<name>TS21</name>
|
|
<description>Bit5 of ADSS2</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS20" -->
|
|
<field>
|
|
<name>TS20</name>
|
|
<description>Bit4 of ADSS2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS19" -->
|
|
<field>
|
|
<name>TS19</name>
|
|
<description>Bit3 of ADSS2</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS18" -->
|
|
<field>
|
|
<name>TS18</name>
|
|
<description>Bit2 of ADSS2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS17" -->
|
|
<field>
|
|
<name>TS17</name>
|
|
<description>Bit1 of ADSS2</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS16" -->
|
|
<field>
|
|
<name>TS16</name>
|
|
<description>Bit0 of ADSS2</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADSS1" -->
|
|
<register>
|
|
<name>ADSS1</name>
|
|
<description>Sampling Time Selection Register 1</description>
|
|
<addressOffset>0x2D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TS15" -->
|
|
<field>
|
|
<name>TS15</name>
|
|
<description>Bit7 of ADSS1</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS14" -->
|
|
<field>
|
|
<name>TS14</name>
|
|
<description>Bit6 of ADSS1</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS13" -->
|
|
<field>
|
|
<name>TS13</name>
|
|
<description>Bit5 of ADSS1</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS12" -->
|
|
<field>
|
|
<name>TS12</name>
|
|
<description>Bit4 of ADSS1</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS11" -->
|
|
<field>
|
|
<name>TS11</name>
|
|
<description>Bit3 of ADSS1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS10" -->
|
|
<field>
|
|
<name>TS10</name>
|
|
<description>Bit2 of ADSS1</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS9" -->
|
|
<field>
|
|
<name>TS9</name>
|
|
<description>Bit1 of ADSS1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS8" -->
|
|
<field>
|
|
<name>TS8</name>
|
|
<description>Bit0 of ADSS1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADSS0" -->
|
|
<register>
|
|
<name>ADSS0</name>
|
|
<description>Sampling Time Selection Register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TS7" -->
|
|
<field>
|
|
<name>TS7</name>
|
|
<description>Bit7 of ADSS0</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS6" -->
|
|
<field>
|
|
<name>TS6</name>
|
|
<description>Bit6 of ADSS0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS5" -->
|
|
<field>
|
|
<name>TS5</name>
|
|
<description>Bit5 of ADSS0</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS4" -->
|
|
<field>
|
|
<name>TS4</name>
|
|
<description>Bit4 of ADSS0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS3" -->
|
|
<field>
|
|
<name>TS3</name>
|
|
<description>Bit3 of ADSS0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS2" -->
|
|
<field>
|
|
<name>TS2</name>
|
|
<description>Bit2 of ADSS0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS1" -->
|
|
<field>
|
|
<name>TS1</name>
|
|
<description>Bit1 of ADSS0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TS0" -->
|
|
<field>
|
|
<name>TS0</name>
|
|
<description>Bit0 of ADSS0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADST1" -->
|
|
<register>
|
|
<name>ADST1</name>
|
|
<description>Sampling Time Setup Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "STX1" -->
|
|
<field>
|
|
<name>STX1</name>
|
|
<description>Sampling time N times setting bits</description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ST" -->
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Sampling time setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADST0" -->
|
|
<register>
|
|
<name>ADST0</name>
|
|
<description>Sampling Time Setup Register 0</description>
|
|
<addressOffset>0x31</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "STX0" -->
|
|
<field>
|
|
<name>STX0</name>
|
|
<description>Sampling time N times setting bits </description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ST" -->
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Sampling time setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADCT" -->
|
|
<register>
|
|
<name>ADCT</name>
|
|
<description>Comparison Time Setup Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x07</resetValue>
|
|
<resetMask>0x07</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CT" -->
|
|
<field>
|
|
<name>CT</name>
|
|
<description>Compare clock frequency division ratio setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PRTSL" -->
|
|
<register>
|
|
<name>PRTSL</name>
|
|
<description>Priority Conversion Timer Trigger Selection Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PRTSL" -->
|
|
<field>
|
|
<name>PRTSL</name>
|
|
<description>Priority conversion timer trigger selection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SCTSL" -->
|
|
<register>
|
|
<name>SCTSL</name>
|
|
<description>Scan Conversion Timer Trigger Selection Register</description>
|
|
<addressOffset>0x39</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SCTSL" -->
|
|
<field>
|
|
<name>SCTSL</name>
|
|
<description>Scan conversion timer trigger selection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ADCEN" -->
|
|
<register>
|
|
<name>ADCEN</name>
|
|
<description>A/D Operation Enable Setup Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x33</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "CYCLSL" -->
|
|
<field>
|
|
<name>CYCLSL</name>
|
|
<description>Basic cycle selection bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "READY" -->
|
|
<field>
|
|
<name>READY</name>
|
|
<description>A/D operation enable state bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ENBL" -->
|
|
<field>
|
|
<name>ENBL</name>
|
|
<description>A/D operation enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "ADC1" -->
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<baseAddress>0x40027100</baseAddress>
|
|
<!-- INTERRUPT "ADC1" -->
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "EXTI" -->
|
|
<peripheral>
|
|
<name>EXTI</name>
|
|
<description>External Interrupt and NMI Control</description>
|
|
<groupName>EXTI</groupName>
|
|
<baseAddress>0x40030000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "EXTINT0_7" -->
|
|
<interrupt>
|
|
<name>EXTINT0_7</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "EXTINT8_15" -->
|
|
<interrupt>
|
|
<name>EXTINT8_15</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "ENIR" -->
|
|
<register>
|
|
<name>ENIR</name>
|
|
<description>Enable Interrupt Request Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x804F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EN15" -->
|
|
<field>
|
|
<name>EN15</name>
|
|
<description>Bit15 of ENIR</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EN6" -->
|
|
<field>
|
|
<name>EN6</name>
|
|
<description>Bit6 of ENIR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EN3" -->
|
|
<field>
|
|
<name>EN3</name>
|
|
<description>Bit3 of ENIR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EN2" -->
|
|
<field>
|
|
<name>EN2</name>
|
|
<description>Bit2 of ENIR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EN1" -->
|
|
<field>
|
|
<name>EN1</name>
|
|
<description>Bit1 of ENIR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EN0" -->
|
|
<field>
|
|
<name>EN0</name>
|
|
<description>Bit0 of ENIR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EIRR" -->
|
|
<register>
|
|
<name>EIRR</name>
|
|
<description>External Interrupt Request Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ER15" -->
|
|
<field>
|
|
<name>ER15</name>
|
|
<description>Bit15 of EIRR</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ER6" -->
|
|
<field>
|
|
<name>ER6</name>
|
|
<description>Bit6 of EIRR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ER3" -->
|
|
<field>
|
|
<name>ER3</name>
|
|
<description>Bit3 of EIRR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ER2" -->
|
|
<field>
|
|
<name>ER2</name>
|
|
<description>Bit2 of EIRR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ER1" -->
|
|
<field>
|
|
<name>ER1</name>
|
|
<description>Bit1 of EIRR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ER0" -->
|
|
<field>
|
|
<name>ER0</name>
|
|
<description>Bit0 of EIRR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EICL" -->
|
|
<register>
|
|
<name>EICL</name>
|
|
<description>External Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0x804F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ECL15" -->
|
|
<field>
|
|
<name>ECL15</name>
|
|
<description>Bit15 of EICL</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECL6" -->
|
|
<field>
|
|
<name>ECL6</name>
|
|
<description>Bit6 of EICL</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECL3" -->
|
|
<field>
|
|
<name>ECL3</name>
|
|
<description>Bit3 of EICL</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECL2" -->
|
|
<field>
|
|
<name>ECL2</name>
|
|
<description>Bit2 of EICL</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECL1" -->
|
|
<field>
|
|
<name>ECL1</name>
|
|
<description>Bit1 of EICL</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ECL0" -->
|
|
<field>
|
|
<name>ECL0</name>
|
|
<description>Bit0 of EICL</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ELVR" -->
|
|
<register>
|
|
<name>ELVR</name>
|
|
<description>External Interrupt Level Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC00030FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LB15" -->
|
|
<field>
|
|
<name>LB15</name>
|
|
<description>Bit31 of ELVR</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA15" -->
|
|
<field>
|
|
<name>LA15</name>
|
|
<description>Bit30 of ELVR</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LB6" -->
|
|
<field>
|
|
<name>LB6</name>
|
|
<description>Bit13 of ELVR</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA6" -->
|
|
<field>
|
|
<name>LA6</name>
|
|
<description>Bit12 of ELVR</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LB3" -->
|
|
<field>
|
|
<name>LB3</name>
|
|
<description>Bit7 of ELVR</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA3" -->
|
|
<field>
|
|
<name>LA3</name>
|
|
<description>Bit6 of ELVR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LB2" -->
|
|
<field>
|
|
<name>LB2</name>
|
|
<description>Bit5 of ELVR</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA2" -->
|
|
<field>
|
|
<name>LA2</name>
|
|
<description>Bit4 of ELVR</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LB1" -->
|
|
<field>
|
|
<name>LB1</name>
|
|
<description>Bit3 of ELVR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA1" -->
|
|
<field>
|
|
<name>LA1</name>
|
|
<description>Bit2 of ELVR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LB0" -->
|
|
<field>
|
|
<name>LB0</name>
|
|
<description>Bit1 of ELVR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LA0" -->
|
|
<field>
|
|
<name>LA0</name>
|
|
<description>Bit0 of ELVR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "NMIRR" -->
|
|
<register>
|
|
<name>NMIRR</name>
|
|
<description>Non Maskable Interrupt Request Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "NR" -->
|
|
<field>
|
|
<name>NR</name>
|
|
<description>NMI interrupt request detection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "NMICL" -->
|
|
<register>
|
|
<name>NMICL</name>
|
|
<description>Non Maskable Interrupt Clear Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "NCL" -->
|
|
<field>
|
|
<name>NCL</name>
|
|
<description>NMI interrupt cause clear bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "INTREQ" -->
|
|
<peripheral>
|
|
<name>INTREQ</name>
|
|
<description>Interrupts</description>
|
|
<groupName>INTREQ</groupName>
|
|
<baseAddress>0x40031000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xB</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0xC4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x210</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "DRQSEL" -->
|
|
<register>
|
|
<name>DRQSEL</name>
|
|
<description>DMA Request Selection Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EXINT3" -->
|
|
<field>
|
|
<name>EXINT3</name>
|
|
<description>The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EXINT2" -->
|
|
<field>
|
|
<name>EXINT2</name>
|
|
<description>The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EXINT1" -->
|
|
<field>
|
|
<name>EXINT1</name>
|
|
<description>The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EXINT0" -->
|
|
<field>
|
|
<name>EXINT0</name>
|
|
<description>The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS7TX" -->
|
|
<field>
|
|
<name>MFS7TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS7RX" -->
|
|
<field>
|
|
<name>MFS7RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS6TX" -->
|
|
<field>
|
|
<name>MFS6TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS6RX" -->
|
|
<field>
|
|
<name>MFS6RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS5TX" -->
|
|
<field>
|
|
<name>MFS5TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS5RX" -->
|
|
<field>
|
|
<name>MFS5RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS4TX" -->
|
|
<field>
|
|
<name>MFS4TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS4RX" -->
|
|
<field>
|
|
<name>MFS4RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS3TX" -->
|
|
<field>
|
|
<name>MFS3TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS3RX" -->
|
|
<field>
|
|
<name>MFS3RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS2TX" -->
|
|
<field>
|
|
<name>MFS2TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS2RX" -->
|
|
<field>
|
|
<name>MFS2RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS1TX" -->
|
|
<field>
|
|
<name>MFS1TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS1RX" -->
|
|
<field>
|
|
<name>MFS1RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS0TX" -->
|
|
<field>
|
|
<name>MFS0TX</name>
|
|
<description>The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MFS0RX" -->
|
|
<field>
|
|
<name>MFS0RX</name>
|
|
<description>The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQ0BT6" -->
|
|
<field>
|
|
<name>IRQ0BT6</name>
|
|
<description>The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC.</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQ0BT4" -->
|
|
<field>
|
|
<name>IRQ0BT4</name>
|
|
<description>The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC.</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQ0BT3" -->
|
|
<field>
|
|
<name>IRQ0BT3</name>
|
|
<description>The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC.</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IRQ0BT0" -->
|
|
<field>
|
|
<name>IRQ0BT0</name>
|
|
<description>The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ADCSCAN2" -->
|
|
<field>
|
|
<name>ADCSCAN2</name>
|
|
<description>The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC.</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ADCSCAN1" -->
|
|
<field>
|
|
<name>ADCSCAN1</name>
|
|
<description>The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC.</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ADCSCAN0" -->
|
|
<field>
|
|
<name>ADCSCAN0</name>
|
|
<description>The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBEP5" -->
|
|
<field>
|
|
<name>USBEP5</name>
|
|
<description>The EP5 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBEP4" -->
|
|
<field>
|
|
<name>USBEP4</name>
|
|
<description>The EP4 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBEP3" -->
|
|
<field>
|
|
<name>USBEP3</name>
|
|
<description>The EP3 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBEP2" -->
|
|
<field>
|
|
<name>USBEP2</name>
|
|
<description>The EP2 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBEP1" -->
|
|
<field>
|
|
<name>USBEP1</name>
|
|
<description>The EP1 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ODDPKS" -->
|
|
<register>
|
|
<name>ODDPKS</name>
|
|
<description>USB ch.0 Odd Packet Size DMA Enable Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ODDPKS4" -->
|
|
<field>
|
|
<name>ODDPKS4</name>
|
|
<description>"When the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte."</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ODDPKS3" -->
|
|
<field>
|
|
<name>ODDPKS3</name>
|
|
<description>"When the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte."</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ODDPKS2" -->
|
|
<field>
|
|
<name>ODDPKS2</name>
|
|
<description>"When the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte."</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ODDPKS1" -->
|
|
<field>
|
|
<name>ODDPKS1</name>
|
|
<description>"When the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte."</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ODDPKS0" -->
|
|
<field>
|
|
<name>ODDPKS0</name>
|
|
<description>"When the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte."</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQCMODE" -->
|
|
<register>
|
|
<name>IRQCMODE</name>
|
|
<description>Interrupt Factor Vector Relocate Setting Register </description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "IRQCMODE" -->
|
|
<field>
|
|
<name>IRQCMODE</name>
|
|
<description>Interrupt Factor Vector Relocate Setting</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EXC02MON" -->
|
|
<register>
|
|
<name>EXC02MON</name>
|
|
<description>EXC02 batch read register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "HWINT" -->
|
|
<field>
|
|
<name>HWINT</name>
|
|
<description>Hardware watchdog timer interrupt request</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "NMI" -->
|
|
<field>
|
|
<name>NMI</name>
|
|
<description>External NMIX pin interrupt request </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ00MON" -->
|
|
<register>
|
|
<name>IRQ00MON</name>
|
|
<description>IRQ00 Batch Read Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FCSINT" -->
|
|
<field>
|
|
<name>FCSINT</name>
|
|
<description>Anomalous frequency detection by CSV interrupt request </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ01MON" -->
|
|
<register>
|
|
<name>IRQ01MON</name>
|
|
<description>IRQ01 Batch Read Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SWWDTINT" -->
|
|
<field>
|
|
<name>SWWDTINT</name>
|
|
<description>Software watchdog timer interrupt request </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ02MON" -->
|
|
<register>
|
|
<name>IRQ02MON</name>
|
|
<description>IRQ02 Batch Read Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDINT" -->
|
|
<field>
|
|
<name>LVDINT</name>
|
|
<description>Low voltage detection (LVD) interrupt request </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ03MON" -->
|
|
<register>
|
|
<name>IRQ03MON</name>
|
|
<description>IRQ03 Batch Read Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WAVE0INT3" -->
|
|
<field>
|
|
<name>WAVE0INT3</name>
|
|
<description>WFG timer 54 interrupt request in MFT unit 0 </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WAVE0INT2" -->
|
|
<field>
|
|
<name>WAVE0INT2</name>
|
|
<description>WFG timer 32 interrupt request in MFT unit 0 </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WAVE0INT1" -->
|
|
<field>
|
|
<name>WAVE0INT1</name>
|
|
<description>WFG timer 10 interrupt request in MFT unit 0 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WAVE0INT0" -->
|
|
<field>
|
|
<name>WAVE0INT0</name>
|
|
<description>DTIF (motor emergency stop) interrupt request in MFT unit 0 </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ04MON" -->
|
|
<register>
|
|
<name>IRQ04MON</name>
|
|
<description>IRQ04 Batch Read Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x4F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EXTINT6" -->
|
|
<field>
|
|
<name>EXTINT6</name>
|
|
<description>Interrupt request on external interrupt ch.6</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "EXTINT3" -->
|
|
<field>
|
|
<name>EXTINT3</name>
|
|
<description>Interrupt request on external interrupt ch.3</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "EXTINT2" -->
|
|
<field>
|
|
<name>EXTINT2</name>
|
|
<description>Interrupt request on external interrupt ch.2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "EXTINT1" -->
|
|
<field>
|
|
<name>EXTINT1</name>
|
|
<description>Interrupt request on external interrupt ch.1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "EXTINT0" -->
|
|
<field>
|
|
<name>EXTINT0</name>
|
|
<description>Interrupt request on external interrupt ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ05MON" -->
|
|
<register>
|
|
<name>IRQ05MON</name>
|
|
<description>IRQ05 Batch Read Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EXTINT7" -->
|
|
<field>
|
|
<name>EXTINT7</name>
|
|
<description>Interrupt request on external interrupt ch.15</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ06MON" -->
|
|
<register>
|
|
<name>IRQ06MON</name>
|
|
<description>IRQ06 Batch Read Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "QUD0INT5" -->
|
|
<field>
|
|
<name>QUD0INT5</name>
|
|
<description>PC match and RC match interrupt request on QPRC ch.0</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "QUD0INT4" -->
|
|
<field>
|
|
<name>QUD0INT4</name>
|
|
<description>Interrupt request detected RC out of range on QPRC ch.0</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "QUD0INT3" -->
|
|
<field>
|
|
<name>QUD0INT3</name>
|
|
<description>PC count invert interrupt request on QPRC ch.0</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "QUD0INT2" -->
|
|
<field>
|
|
<name>QUD0INT2</name>
|
|
<description>Overflow/underflow/zero index interrupt request on QPRC ch.0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "QUD0INT1" -->
|
|
<field>
|
|
<name>QUD0INT1</name>
|
|
<description>PC and RC match interrupt request on QPRC ch.0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "QUD0INT0" -->
|
|
<field>
|
|
<name>QUD0INT0</name>
|
|
<description>PC match interrupt request on QPRC ch.0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TIMINT2" -->
|
|
<field>
|
|
<name>TIMINT2</name>
|
|
<description>Dual timer 2 interrupt request </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TIMINT1" -->
|
|
<field>
|
|
<name>TIMINT1</name>
|
|
<description>Dual timer 1 interrupt request </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ07MON" -->
|
|
<register>
|
|
<name>IRQ07MON</name>
|
|
<description>IRQ07 Batch Read Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT" -->
|
|
<field>
|
|
<name>MFSINT</name>
|
|
<description>Reception interrupt request on MFS ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ08MON" -->
|
|
<register>
|
|
<name>IRQ08MON</name>
|
|
<description>IRQ08 Batch Read Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT1" -->
|
|
<field>
|
|
<name>MFSINT1</name>
|
|
<description>Status interrupt request on MFS ch.0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MFSINT0" -->
|
|
<field>
|
|
<name>MFSINT0</name>
|
|
<description>Transmission interrupt request on MFS ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ09MON" -->
|
|
<register>
|
|
<name>IRQ09MON</name>
|
|
<description>IRQ09 Batch Read Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT" -->
|
|
<field>
|
|
<name>MFSINT</name>
|
|
<description>Reception interrupt request on MFS ch.1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ10MON" -->
|
|
<register>
|
|
<name>IRQ10MON</name>
|
|
<description>IRQ10 Batch Read Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT1" -->
|
|
<field>
|
|
<name>MFSINT1</name>
|
|
<description>Status interrupt request on MFS ch.1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MFSINT0" -->
|
|
<field>
|
|
<name>MFSINT0</name>
|
|
<description>Transmission interrupt request on MFS ch.1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ13MON" -->
|
|
<register>
|
|
<name>IRQ13MON</name>
|
|
<description>IRQ13 Batch Read Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT" -->
|
|
<field>
|
|
<name>MFSINT</name>
|
|
<description>Reception interrupt request on MFS ch.3</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ14MON" -->
|
|
<register>
|
|
<name>IRQ14MON</name>
|
|
<description>IRQ14 Batch Read Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT1" -->
|
|
<field>
|
|
<name>MFSINT1</name>
|
|
<description>Status interrupt request on MFS ch.3</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MFSINT0" -->
|
|
<field>
|
|
<name>MFSINT0</name>
|
|
<description>Transmission interrupt request on MFS ch.3</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ17MON" -->
|
|
<register>
|
|
<name>IRQ17MON</name>
|
|
<description>IRQ17 Batch Read Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT" -->
|
|
<field>
|
|
<name>MFSINT</name>
|
|
<description>Reception interrupt request on MFS ch.5</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ18MON" -->
|
|
<register>
|
|
<name>IRQ18MON</name>
|
|
<description>IRQ18 Batch Read Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MFSINT1" -->
|
|
<field>
|
|
<name>MFSINT1</name>
|
|
<description>Status interrupt request on MFS ch.5</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MFSINT0" -->
|
|
<field>
|
|
<name>MFSINT0</name>
|
|
<description>Transmission interrupt request on MFS ch.5</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ23MON" -->
|
|
<register>
|
|
<name>IRQ23MON</name>
|
|
<description>IRQ23 Batch Read Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PPGINT2" -->
|
|
<field>
|
|
<name>PPGINT2</name>
|
|
<description>Interrupt request on PPG ch.4 </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PPGINT1" -->
|
|
<field>
|
|
<name>PPGINT1</name>
|
|
<description>Interrupt request on PPG ch.2 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "PPGINT0" -->
|
|
<field>
|
|
<name>PPGINT0</name>
|
|
<description>Interrupt request on PPG ch.0 </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ24MON" -->
|
|
<register>
|
|
<name>IRQ24MON</name>
|
|
<description>IRQ24 Batch Read Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RTCINT" -->
|
|
<field>
|
|
<name>RTCINT</name>
|
|
<description>RTC interrupt request </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WCINT" -->
|
|
<field>
|
|
<name>WCINT</name>
|
|
<description>Watch counter interrupt request</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "UPLLINT" -->
|
|
<field>
|
|
<name>UPLLINT</name>
|
|
<description>Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation.</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MPLLINT" -->
|
|
<field>
|
|
<name>MPLLINT</name>
|
|
<description>Stabilization wait completion interrupt request for main PLL oscillation </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SOSCINT" -->
|
|
<field>
|
|
<name>SOSCINT</name>
|
|
<description>Stabilization wait completion interrupt request for sub-clock oscillation</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "MOSCINT" -->
|
|
<field>
|
|
<name>MOSCINT</name>
|
|
<description>Stabilization wait completion interrupt request for main clock oscillation </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ25MON" -->
|
|
<register>
|
|
<name>IRQ25MON</name>
|
|
<description>IRQ25 Batch Read Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ADCINT3" -->
|
|
<field>
|
|
<name>ADCINT3</name>
|
|
<description>Conversion result comparison interrupt request in the corresponding A/D unit 0. </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT2" -->
|
|
<field>
|
|
<name>ADCINT2</name>
|
|
<description>FIFO overrun interrupt request in the corresponding A/D unit 0. </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT1" -->
|
|
<field>
|
|
<name>ADCINT1</name>
|
|
<description>Scan conversion interrupt request in the corresponding A/D unit 0. </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT0" -->
|
|
<field>
|
|
<name>ADCINT0</name>
|
|
<description>Priority conversion interrupt request in the corresponding A/D unit 0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ26MON" -->
|
|
<register>
|
|
<name>IRQ26MON</name>
|
|
<description>IRQ26 Batch Read Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ADCINT3" -->
|
|
<field>
|
|
<name>ADCINT3</name>
|
|
<description>Conversion result comparison interrupt request in the corresponding A/D unit 1 </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT2" -->
|
|
<field>
|
|
<name>ADCINT2</name>
|
|
<description>FIFO overrun interrupt request in the corresponding A/D unit 1 </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT1" -->
|
|
<field>
|
|
<name>ADCINT1</name>
|
|
<description>Scan conversion interrupt request in the corresponding A/D unit 1 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ADCINT0" -->
|
|
<field>
|
|
<name>ADCINT0</name>
|
|
<description>Priority conversion interrupt request in the corresponding A/D unit 1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ28MON" -->
|
|
<register>
|
|
<name>IRQ28MON</name>
|
|
<description>IRQ28 Batch Read Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FRT0INT5" -->
|
|
<field>
|
|
<name>FRT0INT5</name>
|
|
<description>Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRT0INT4" -->
|
|
<field>
|
|
<name>FRT0INT4</name>
|
|
<description>Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRT0INT3" -->
|
|
<field>
|
|
<name>FRT0INT3</name>
|
|
<description>Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRT0INT2" -->
|
|
<field>
|
|
<name>FRT0INT2</name>
|
|
<description>Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRT0INT1" -->
|
|
<field>
|
|
<name>FRT0INT1</name>
|
|
<description>Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRT0INT0" -->
|
|
<field>
|
|
<name>FRT0INT0</name>
|
|
<description>Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ29MON" -->
|
|
<register>
|
|
<name>IRQ29MON</name>
|
|
<description>IRQ29 Batch Read Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ICU0INT3" -->
|
|
<field>
|
|
<name>ICU0INT3</name>
|
|
<description>Interrupt request on the input capture ch.3 in the MFT unit 0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ICU0INT2" -->
|
|
<field>
|
|
<name>ICU0INT2</name>
|
|
<description>Interrupt request on the input capture ch.2 in the MFT unit 0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ICU0INT1" -->
|
|
<field>
|
|
<name>ICU0INT1</name>
|
|
<description>Interrupt request on the input capture ch.1 in the MFT unit 0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ICU0INT0" -->
|
|
<field>
|
|
<name>ICU0INT0</name>
|
|
<description>Interrupt request on the input capture ch.0 in the MFT unit 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ30MON" -->
|
|
<register>
|
|
<name>IRQ30MON</name>
|
|
<description>IRQ30 Batch Read Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "OCU0INT5" -->
|
|
<field>
|
|
<name>OCU0INT5</name>
|
|
<description>Interrupt request on the output compare ch.5 in the MFT unit 0 </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OCU0INT4" -->
|
|
<field>
|
|
<name>OCU0INT4</name>
|
|
<description>Interrupt request on the output compare ch.4 in the MFT unit 0 </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OCU0INT3" -->
|
|
<field>
|
|
<name>OCU0INT3</name>
|
|
<description>Interrupt request on the output compare ch.3 in the MFT unit 0 </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OCU0INT2" -->
|
|
<field>
|
|
<name>OCU0INT2</name>
|
|
<description>Interrupt request on the output compare ch.2 in the MFT unit 0 </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OCU0INT1" -->
|
|
<field>
|
|
<name>OCU0INT1</name>
|
|
<description>Interrupt request on the output compare ch.1 in the MFT unit 0 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "OCU0INT0" -->
|
|
<field>
|
|
<name>OCU0INT0</name>
|
|
<description>Interrupt request on the output compare ch.0 in the MFT unit 0 </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ31MON" -->
|
|
<register>
|
|
<name>IRQ31MON</name>
|
|
<description>IRQ31 Batch Read Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BTINT15" -->
|
|
<field>
|
|
<name>BTINT15</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.7</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT14" -->
|
|
<field>
|
|
<name>BTINT14</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.7</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT13" -->
|
|
<field>
|
|
<name>BTINT13</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.6</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT12" -->
|
|
<field>
|
|
<name>BTINT12</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.6</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT11" -->
|
|
<field>
|
|
<name>BTINT11</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.5</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT10" -->
|
|
<field>
|
|
<name>BTINT10</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.5</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT9" -->
|
|
<field>
|
|
<name>BTINT9</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.4</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT8" -->
|
|
<field>
|
|
<name>BTINT8</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.4</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT7" -->
|
|
<field>
|
|
<name>BTINT7</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.3</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT6" -->
|
|
<field>
|
|
<name>BTINT6</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.3</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT5" -->
|
|
<field>
|
|
<name>BTINT5</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.2</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT4" -->
|
|
<field>
|
|
<name>BTINT4</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT3" -->
|
|
<field>
|
|
<name>BTINT3</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT2" -->
|
|
<field>
|
|
<name>BTINT2</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.1</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT1" -->
|
|
<field>
|
|
<name>BTINT1</name>
|
|
<description>IRQ1 interrupt request on the base timer ch.0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "BTINT0" -->
|
|
<field>
|
|
<name>BTINT0</name>
|
|
<description>IRQ0 interrupt request on the base timer ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ34MON" -->
|
|
<register>
|
|
<name>IRQ34MON</name>
|
|
<description>IRQ34 Batch Read Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "USB0INT4" -->
|
|
<field>
|
|
<name>USB0INT4</name>
|
|
<description>Endpoint 5 DRQ interrupt request on the USB ch.0 </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT3" -->
|
|
<field>
|
|
<name>USB0INT3</name>
|
|
<description>Endpoint 4 DRQ interrupt request on the USB ch.0 </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT2" -->
|
|
<field>
|
|
<name>USB0INT2</name>
|
|
<description>Endpoint 3 DRQ interrupt request on the USB ch.0 </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT1" -->
|
|
<field>
|
|
<name>USB0INT1</name>
|
|
<description>Endpoint 2 DRQ interrupt request on the USB ch.0 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT0" -->
|
|
<field>
|
|
<name>USB0INT0</name>
|
|
<description>Endpoint 1 DRQ interrupt request on the USB ch.0 </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ35MON" -->
|
|
<register>
|
|
<name>IRQ35MON</name>
|
|
<description>IRQ35 Batch Read Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "USB0INT5" -->
|
|
<field>
|
|
<name>USB0INT5</name>
|
|
<description>"Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.0 "</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT4" -->
|
|
<field>
|
|
<name>USB0INT4</name>
|
|
<description>"Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.0 "</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT3" -->
|
|
<field>
|
|
<name>USB0INT3</name>
|
|
<description>Status (SPK) interrupt request on the USB ch.0 </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT2" -->
|
|
<field>
|
|
<name>USB0INT2</name>
|
|
<description>"Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.0 "</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT1" -->
|
|
<field>
|
|
<name>USB0INT1</name>
|
|
<description>Endpoint 0 DRQO interrupt request on the USB ch.0 </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USB0INT0" -->
|
|
<field>
|
|
<name>USB0INT0</name>
|
|
<description>Endpoint 0 DRQI interrupt request on the USB ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ38MON" -->
|
|
<register>
|
|
<name>IRQ38MON</name>
|
|
<description>IRQ38 Batch Read Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DMAINT" -->
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>Interrupt request on DMA ch.0.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ39MON" -->
|
|
<register>
|
|
<name>IRQ39MON</name>
|
|
<description>IRQ39 Batch Read Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DMAINT" -->
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>Interrupt request on DMA ch.1.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ40MON" -->
|
|
<register>
|
|
<name>IRQ40MON</name>
|
|
<description>IRQ40 Batch Read Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DMAINT" -->
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>Interrupt request on DMA ch.2.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "IRQ41MON" -->
|
|
<register>
|
|
<name>IRQ41MON</name>
|
|
<description>IRQ41 Batch Read Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DMAINT" -->
|
|
<field>
|
|
<name>DMAINT</name>
|
|
<description>Interrupt request on DMA ch.3.</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RCINTSEL0" -->
|
|
<register>
|
|
<name>RCINTSEL0</name>
|
|
<description>Interrupt Factor Selection Register 0</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "INTSEL3" -->
|
|
<field>
|
|
<name>INTSEL3</name>
|
|
<description>select the interrupt factor of the interrupt vector No.22.</description>
|
|
<lsb>24</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL2" -->
|
|
<field>
|
|
<name>INTSEL2</name>
|
|
<description>select the interrupt factor of the interrupt vector No.21.</description>
|
|
<lsb>16</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL1" -->
|
|
<field>
|
|
<name>INTSEL1</name>
|
|
<description>select the interrupt factor of the interrupt vector No.20.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL0" -->
|
|
<field>
|
|
<name>INTSEL0</name>
|
|
<description>select the interrupt factor of the interrupt vector No.19.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "RCINTSEL1" -->
|
|
<register>
|
|
<name>RCINTSEL1</name>
|
|
<description>Interrupt Factor Selection Register 1</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "INTSEL7" -->
|
|
<field>
|
|
<name>INTSEL7</name>
|
|
<description>select the interrupt factor of the interrupt vector No.26.</description>
|
|
<lsb>24</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL6" -->
|
|
<field>
|
|
<name>INTSEL6</name>
|
|
<description>select the interrupt factor of the interrupt vector No.25.</description>
|
|
<lsb>16</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL5" -->
|
|
<field>
|
|
<name>INTSEL5</name>
|
|
<description>select the interrupt factor of the interrupt vector No.24.</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSEL4" -->
|
|
<field>
|
|
<name>INTSEL4</name>
|
|
<description>select the interrupt factor of the interrupt vector No.23.</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "GPIO" -->
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<description>General-purpose I/O ports</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x40033000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x740</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "PFR0" -->
|
|
<register>
|
|
<name>PFR0</name>
|
|
<description>Port function setting register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001F</resetValue>
|
|
<resetMask>0x0000801F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PF" -->
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Bit15 of PFR0</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P4" -->
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Bit4 of PFR0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P3" -->
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Bit3 of PFR0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit2 of PFR0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFR0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR1" -->
|
|
<register>
|
|
<name>PFR1</name>
|
|
<description>Port function setting register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P5" -->
|
|
<field>
|
|
<name>P5</name>
|
|
<description>Bit5 of PFR1</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P4" -->
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Bit4 of PFR1</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P3" -->
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Bit3 of PFR1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit2 of PFR1</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR1</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFR1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR2" -->
|
|
<register>
|
|
<name>PFR2</name>
|
|
<description>Port function setting register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0000000E</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P3" -->
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Bit3 of PFR2</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit2 of PFR2</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR2</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR3" -->
|
|
<register>
|
|
<name>PFR3</name>
|
|
<description>Port function setting register 3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0000FE00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PF" -->
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Bit15 of PFR3</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PE" -->
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Bit14 of PFR3</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PD" -->
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Bit13 of PFR3</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PC" -->
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Bit12 of PFR3</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PB" -->
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Bit11 of PFR3</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PA" -->
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Bit10 of PFR3</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P9" -->
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Bit9 of PFR3</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR4" -->
|
|
<register>
|
|
<name>PFR4</name>
|
|
<description>Port function setting register 4</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x000006C0</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PA" -->
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Bit10 of PFR4</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P9" -->
|
|
<field>
|
|
<name>P9</name>
|
|
<description>Bit9 of PFR4</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P7" -->
|
|
<field>
|
|
<name>P7</name>
|
|
<description>Bit7 of PFR4</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P6" -->
|
|
<field>
|
|
<name>P6</name>
|
|
<description>Bit6 of PFR4</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR5" -->
|
|
<register>
|
|
<name>PFR5</name>
|
|
<description>Port function setting register 5</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit2 of PFR5</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR5</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFR5</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR6" -->
|
|
<register>
|
|
<name>PFR6</name>
|
|
<description>Port function setting register 6</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR6</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFR6</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFR8" -->
|
|
<register>
|
|
<name>PFR8</name>
|
|
<description>Port function setting register 8</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of PFR8</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFR8</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PFRE" -->
|
|
<register>
|
|
<name>PFRE</name>
|
|
<description>Port function setting register E</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xB</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "P3" -->
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Bit2 of PFRE</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit1 of PFRE</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of PFRE</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PCR0" -->
|
|
<register derivedFrom="PFR0">
|
|
<name>PCR0</name>
|
|
<description>Pull-up Setting Register 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR1" -->
|
|
<register derivedFrom="PFR1">
|
|
<name>PCR1</name>
|
|
<description>Pull-up Setting Register 1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR2" -->
|
|
<register derivedFrom="PFR2">
|
|
<name>PCR2</name>
|
|
<description>Pull-up Setting Register 2</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR3" -->
|
|
<register derivedFrom="PFR3">
|
|
<name>PCR3</name>
|
|
<description>Pull-up Setting Register 3</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR4" -->
|
|
<register derivedFrom="PFR4">
|
|
<name>PCR4</name>
|
|
<description>Pull-up Setting Register 4</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR5" -->
|
|
<register derivedFrom="PFR5">
|
|
<name>PCR5</name>
|
|
<description>Pull-up Setting Register 5</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCR6" -->
|
|
<register derivedFrom="PFR6">
|
|
<name>PCR6</name>
|
|
<description>Pull-up Setting Register 6</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PCRE" -->
|
|
<register derivedFrom="PFRE">
|
|
<name>PCRE</name>
|
|
<description>Pull-up Setting Register E</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR0" -->
|
|
<register>
|
|
<name>DDR0</name>
|
|
<description>Port input/output direction setting register 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0000801F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "PF" -->
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Bit15 of DDR0</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P4" -->
|
|
<field>
|
|
<name>P4</name>
|
|
<description>Bit4 of DDR0</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P3" -->
|
|
<field>
|
|
<name>P3</name>
|
|
<description>Bit3 of DDR0</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P2" -->
|
|
<field>
|
|
<name>P2</name>
|
|
<description>Bit2 of DDR0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P1" -->
|
|
<field>
|
|
<name>P1</name>
|
|
<description>Bit1 of DDR0</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P0" -->
|
|
<field>
|
|
<name>P0</name>
|
|
<description>Bit0 of DDR0</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DDR1" -->
|
|
<register derivedFrom="PFR1">
|
|
<name>DDR1</name>
|
|
<description>Port input/output direction setting register 1</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR2" -->
|
|
<register derivedFrom="PFR2">
|
|
<name>DDR2</name>
|
|
<description>Port input/output direction setting register 2</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR3" -->
|
|
<register derivedFrom="PFR3">
|
|
<name>DDR3</name>
|
|
<description>Port input/output direction setting register 3</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR4" -->
|
|
<register derivedFrom="PFR4">
|
|
<name>DDR4</name>
|
|
<description>Port input/output direction setting register 4</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR5" -->
|
|
<register derivedFrom="PFR5">
|
|
<name>DDR5</name>
|
|
<description>Port input/output direction setting register 5</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR6" -->
|
|
<register derivedFrom="PFR6">
|
|
<name>DDR6</name>
|
|
<description>Port input/output direction setting register 6</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDR8" -->
|
|
<register derivedFrom="PFR8">
|
|
<name>DDR8</name>
|
|
<description>Port input/output direction setting register 8</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DDRE" -->
|
|
<register derivedFrom="PFRE">
|
|
<name>DDRE</name>
|
|
<description>Port input/output direction setting register E</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR0" -->
|
|
<register derivedFrom="DDR0">
|
|
<name>PDIR0</name>
|
|
<description>Port input data register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR1" -->
|
|
<register derivedFrom="DDR1">
|
|
<name>PDIR1</name>
|
|
<description>Port input data register 1</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR2" -->
|
|
<register derivedFrom="DDR2">
|
|
<name>PDIR2</name>
|
|
<description>Port input data register 2</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR3" -->
|
|
<register derivedFrom="DDR3">
|
|
<name>PDIR3</name>
|
|
<description>Port input data register 3</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR4" -->
|
|
<register derivedFrom="DDR4">
|
|
<name>PDIR4</name>
|
|
<description>Port input data register 4</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR5" -->
|
|
<register derivedFrom="DDR5">
|
|
<name>PDIR5</name>
|
|
<description>Port input data register 5</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR6" -->
|
|
<register derivedFrom="DDR6">
|
|
<name>PDIR6</name>
|
|
<description>Port input data register 6</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIR8" -->
|
|
<register derivedFrom="DDR8">
|
|
<name>PDIR8</name>
|
|
<description>Port input data register 8</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDIRE" -->
|
|
<register derivedFrom="DDRE">
|
|
<name>PDIRE</name>
|
|
<description>Port input data register E</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR0" -->
|
|
<register derivedFrom="DDR0">
|
|
<name>PDOR0</name>
|
|
<description>Port output data register 0</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR1" -->
|
|
<register derivedFrom="DDR1">
|
|
<name>PDOR1</name>
|
|
<description>Port output data register 1</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR2" -->
|
|
<register derivedFrom="DDR2">
|
|
<name>PDOR2</name>
|
|
<description>Port output data register 2</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR3" -->
|
|
<register derivedFrom="DDR3">
|
|
<name>PDOR3</name>
|
|
<description>Port output data register 3</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR4" -->
|
|
<register derivedFrom="DDR4">
|
|
<name>PDOR4</name>
|
|
<description>Port output data register 4</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR5" -->
|
|
<register derivedFrom="DDR5">
|
|
<name>PDOR5</name>
|
|
<description>Port output data register 5</description>
|
|
<addressOffset>0x414</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR6" -->
|
|
<register derivedFrom="DDR6">
|
|
<name>PDOR6</name>
|
|
<description>Port output data register 6</description>
|
|
<addressOffset>0x418</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDOR8" -->
|
|
<register derivedFrom="DDR8">
|
|
<name>PDOR8</name>
|
|
<description>Port output data register 8</description>
|
|
<addressOffset>0x420</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PDORE" -->
|
|
<register derivedFrom="DDRE">
|
|
<name>PDORE</name>
|
|
<description>Port output data register E</description>
|
|
<addressOffset>0x438</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "ADE" -->
|
|
<register>
|
|
<name>ADE</name>
|
|
<description>Analog input setting register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "AN7" -->
|
|
<field>
|
|
<name>AN7</name>
|
|
<description>Bit7 of ADE</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN6" -->
|
|
<field>
|
|
<name>AN6</name>
|
|
<description>Bit6 of ADE</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN5" -->
|
|
<field>
|
|
<name>AN5</name>
|
|
<description>Bit5 of ADE</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN4" -->
|
|
<field>
|
|
<name>AN4</name>
|
|
<description>Bit4 of ADE</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN3" -->
|
|
<field>
|
|
<name>AN3</name>
|
|
<description>Bit3 of ADE</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN2" -->
|
|
<field>
|
|
<name>AN2</name>
|
|
<description>Bit2 of ADE</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN1" -->
|
|
<field>
|
|
<name>AN1</name>
|
|
<description>Bit1 of ADE</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AN0" -->
|
|
<field>
|
|
<name>AN0</name>
|
|
<description>Bit0 of ADE</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "SPSR" -->
|
|
<register>
|
|
<name>SPSR</name>
|
|
<description>Special port setting register</description>
|
|
<addressOffset>0x580</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0x15</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "USB0C" -->
|
|
<field>
|
|
<name>USB0C</name>
|
|
<description>USBch0 pin setting bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MAINXC" -->
|
|
<field>
|
|
<name>MAINXC</name>
|
|
<description>Main clock(oscillation) pin setting bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SUBXC" -->
|
|
<field>
|
|
<name>SUBXC</name>
|
|
<description>Sub clock(oscillation) pin setting bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR00" -->
|
|
<register>
|
|
<name>EPFR00</name>
|
|
<description>Extended pin function setting register 00</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30000</resetValue>
|
|
<resetMask>0x302F7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "JTAGEN1S" -->
|
|
<field>
|
|
<name>JTAGEN1S</name>
|
|
<description>JTAG function select bit1</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "JTAGEN0B" -->
|
|
<field>
|
|
<name>JTAGEN0B</name>
|
|
<description>JTAG function select bit0</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USBP0E" -->
|
|
<field>
|
|
<name>USBP0E</name>
|
|
<description>USBch0 function select bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SUBOUTE" -->
|
|
<field>
|
|
<name>SUBOUTE</name>
|
|
<description>Sub clock divide output function select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTCCOE" -->
|
|
<field>
|
|
<name>RTCCOE</name>
|
|
<description>RTC clock output select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CROUTE" -->
|
|
<field>
|
|
<name>CROUTE</name>
|
|
<description>Internal high-speed CR oscillation output function select bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "NMIS" -->
|
|
<field>
|
|
<name>NMIS</name>
|
|
<description>NMIX function select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR01" -->
|
|
<register>
|
|
<name>EPFR01</name>
|
|
<description>Extended pin function setting register 01</description>
|
|
<addressOffset>0x604</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF1FFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "IC03S" -->
|
|
<field>
|
|
<name>IC03S</name>
|
|
<description>IC03 input select bit</description>
|
|
<lsb>29</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IC02S" -->
|
|
<field>
|
|
<name>IC02S</name>
|
|
<description>IC02 input select bit</description>
|
|
<lsb>26</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IC01S" -->
|
|
<field>
|
|
<name>IC01S</name>
|
|
<description>IC01 input select bit</description>
|
|
<lsb>23</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IC00S" -->
|
|
<field>
|
|
<name>IC00S</name>
|
|
<description>IC00 input select bit</description>
|
|
<lsb>20</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRCK0S" -->
|
|
<field>
|
|
<name>FRCK0S</name>
|
|
<description>FRCK0 input select bit</description>
|
|
<lsb>18</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DTTI0S" -->
|
|
<field>
|
|
<name>DTTI0S</name>
|
|
<description>DTTIX0 input select bit</description>
|
|
<lsb>16</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DTTI0C" -->
|
|
<field>
|
|
<name>DTTI0C</name>
|
|
<description>DTTIX0 function select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO05E" -->
|
|
<field>
|
|
<name>RTO05E</name>
|
|
<description>RTO05E output select bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO04E" -->
|
|
<field>
|
|
<name>RTO04E</name>
|
|
<description>RTO04E output select bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO03E" -->
|
|
<field>
|
|
<name>RTO03E</name>
|
|
<description>RTO03E output select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO02E" -->
|
|
<field>
|
|
<name>RTO02E</name>
|
|
<description>RTO02E output select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO01E" -->
|
|
<field>
|
|
<name>RTO01E</name>
|
|
<description>RTO01E output select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTO00E" -->
|
|
<field>
|
|
<name>RTO00E</name>
|
|
<description>RTO00E output select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR04" -->
|
|
<register>
|
|
<name>EPFR04</name>
|
|
<description>Extended pin function setting register 04</description>
|
|
<addressOffset>0x610</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0F3C3F7C</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TIOA3E" -->
|
|
<field>
|
|
<name>TIOA3E</name>
|
|
<description>TIOA3E output select bit</description>
|
|
<lsb>26</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA3S" -->
|
|
<field>
|
|
<name>TIOA3S</name>
|
|
<description>TIOA3 input select bit</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOB2S" -->
|
|
<field>
|
|
<name>TIOB2S</name>
|
|
<description>TIOB2 input select bit</description>
|
|
<lsb>20</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA2E" -->
|
|
<field>
|
|
<name>TIOA2E</name>
|
|
<description>TIOA2 output select bit</description>
|
|
<lsb>18</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOB1S" -->
|
|
<field>
|
|
<name>TIOB1S</name>
|
|
<description>TIOB1 input select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA1E" -->
|
|
<field>
|
|
<name>TIOA1E</name>
|
|
<description>TIOA1E output select bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA1S" -->
|
|
<field>
|
|
<name>TIOA1S</name>
|
|
<description>TIOA1 input select bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOB0S" -->
|
|
<field>
|
|
<name>TIOB0S</name>
|
|
<description>TIOB0 input select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA0E" -->
|
|
<field>
|
|
<name>TIOA0E</name>
|
|
<description>TIOA0 output select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR05" -->
|
|
<register>
|
|
<name>EPFR05</name>
|
|
<description>Extended pin function setting register 05</description>
|
|
<addressOffset>0x614</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3F000F0C</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TIOB7S" -->
|
|
<field>
|
|
<name>TIOB7S</name>
|
|
<description>TIOB7 input select Bit</description>
|
|
<lsb>28</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA7E" -->
|
|
<field>
|
|
<name>TIOA7E</name>
|
|
<description>TIOA7E output select bit</description>
|
|
<lsb>26</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA7S" -->
|
|
<field>
|
|
<name>TIOA7S</name>
|
|
<description>TIOA7 input select bit</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA5E" -->
|
|
<field>
|
|
<name>TIOA5E</name>
|
|
<description>TIOA5E output select bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA5S" -->
|
|
<field>
|
|
<name>TIOA5S</name>
|
|
<description>TIOA5 input select bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIOA4E" -->
|
|
<field>
|
|
<name>TIOA4E</name>
|
|
<description>TIOA4 output select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR06" -->
|
|
<register>
|
|
<name>EPFR06</name>
|
|
<description>Extended pin function setting register 06</description>
|
|
<addressOffset>0x618</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xC00030FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EINT15S" -->
|
|
<field>
|
|
<name>EINT15S</name>
|
|
<description>External interrupt 15 input select bit</description>
|
|
<lsb>30</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EINT06S" -->
|
|
<field>
|
|
<name>EINT06S</name>
|
|
<description>External interrupt 6 input select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EINT03S" -->
|
|
<field>
|
|
<name>EINT03S</name>
|
|
<description>External interrupt 3 input select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EINT02S" -->
|
|
<field>
|
|
<name>EINT02S</name>
|
|
<description>External interrupt 2 input select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EINT01S" -->
|
|
<field>
|
|
<name>EINT01S</name>
|
|
<description>External interrupt 1 input select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EINT00S" -->
|
|
<field>
|
|
<name>EINT00S</name>
|
|
<description>External interrupt 0 input select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR07" -->
|
|
<register>
|
|
<name>EPFR07</name>
|
|
<description>Extended pin function setting register 07</description>
|
|
<addressOffset>0x61C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0FC0FFF0</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SCK3B" -->
|
|
<field>
|
|
<name>SCK3B</name>
|
|
<description>SCK3 input/output select bit</description>
|
|
<lsb>26</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOT3B" -->
|
|
<field>
|
|
<name>SOT3B</name>
|
|
<description>SOT3B input/output select bit</description>
|
|
<lsb>24</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIN3S" -->
|
|
<field>
|
|
<name>SIN3S</name>
|
|
<description>SIN3S input select bit</description>
|
|
<lsb>22</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCK1B" -->
|
|
<field>
|
|
<name>SCK1B</name>
|
|
<description>SCK1 input/output select bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOT1B" -->
|
|
<field>
|
|
<name>SOT1B</name>
|
|
<description>SCK1B input/output select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIN1S" -->
|
|
<field>
|
|
<name>SIN1S</name>
|
|
<description>SIN1S input select bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCK0B" -->
|
|
<field>
|
|
<name>SCK0B</name>
|
|
<description>SCK0 input/output select bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOT0B" -->
|
|
<field>
|
|
<name>SOT0B</name>
|
|
<description>SOT0B input/output select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIN0S" -->
|
|
<field>
|
|
<name>SIN0S</name>
|
|
<description>SIN0S input select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR08" -->
|
|
<register>
|
|
<name>EPFR08</name>
|
|
<description>Extended pin function setting register 08</description>
|
|
<addressOffset>0x620</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x0000FC00</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SCK5B" -->
|
|
<field>
|
|
<name>SCK5B</name>
|
|
<description>SCK5 input/output select bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOT5B" -->
|
|
<field>
|
|
<name>SOT5B</name>
|
|
<description>SOT5B input/output select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIN5S" -->
|
|
<field>
|
|
<name>SIN5S</name>
|
|
<description>SIN5S input select bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EPFR09" -->
|
|
<register>
|
|
<name>EPFR09</name>
|
|
<description>Extended pin function setting register 09</description>
|
|
<addressOffset>0x624</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x000FF03F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ADTRG1S" -->
|
|
<field>
|
|
<name>ADTRG1S</name>
|
|
<description>ADTRG1 input select bit</description>
|
|
<lsb>16</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ADTRG0S" -->
|
|
<field>
|
|
<name>ADTRG0S</name>
|
|
<description>ADTRG0 input select bit</description>
|
|
<lsb>12</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QZIN0S" -->
|
|
<field>
|
|
<name>QZIN0S</name>
|
|
<description>QZIN0S input select bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QBIN0S" -->
|
|
<field>
|
|
<name>QBIN0S</name>
|
|
<description>QBIN0S input select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "QAIN0S" -->
|
|
<field>
|
|
<name>QAIN0S</name>
|
|
<description>QAIN0S input select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "PZR0" -->
|
|
<register derivedFrom="DDR0">
|
|
<name>PZR0</name>
|
|
<description>Port Pseudo Open Drain Setting Register 0</description>
|
|
<addressOffset>0x700</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR1" -->
|
|
<register derivedFrom="DDR1">
|
|
<name>PZR1</name>
|
|
<description>Port Pseudo Open Drain Setting Register 1</description>
|
|
<addressOffset>0x704</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR2" -->
|
|
<register derivedFrom="DDR2">
|
|
<name>PZR2</name>
|
|
<description>Port Pseudo Open Drain Setting Register 2</description>
|
|
<addressOffset>0x708</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR3" -->
|
|
<register derivedFrom="DDR3">
|
|
<name>PZR3</name>
|
|
<description>Port Pseudo Open Drain Setting Register 3</description>
|
|
<addressOffset>0x70C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR4" -->
|
|
<register derivedFrom="DDR4">
|
|
<name>PZR4</name>
|
|
<description>Port Pseudo Open Drain Setting Register 4</description>
|
|
<addressOffset>0x710</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR5" -->
|
|
<register derivedFrom="DDR5">
|
|
<name>PZR5</name>
|
|
<description>Port Pseudo Open Drain Setting Register 5</description>
|
|
<addressOffset>0x714</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR6" -->
|
|
<register derivedFrom="DDR6">
|
|
<name>PZR6</name>
|
|
<description>Port Pseudo Open Drain Setting Register 6</description>
|
|
<addressOffset>0x718</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZR8" -->
|
|
<register derivedFrom="DDR8">
|
|
<name>PZR8</name>
|
|
<description>Port Pseudo Open Drain Setting Register 8</description>
|
|
<addressOffset>0x720</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "PZRE" -->
|
|
<register derivedFrom="DDRE">
|
|
<name>PZRE</name>
|
|
<description>Port Pseudo Open Drain Setting Register E</description>
|
|
<addressOffset>0x738</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "LVD" -->
|
|
<peripheral>
|
|
<name>LVD</name>
|
|
<description>Low-voltage Detection</description>
|
|
<groupName>LVD</groupName>
|
|
<baseAddress>0x40035000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "LVD" -->
|
|
<interrupt>
|
|
<name>LVD</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "LVD_CTL" -->
|
|
<register>
|
|
<name>LVD_CTL</name>
|
|
<description>Low-voltage Detection Voltage Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xBC</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDIE" -->
|
|
<field>
|
|
<name>LVDIE</name>
|
|
<description>Low-voltage detection interrupt enable bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SVHI" -->
|
|
<field>
|
|
<name>SVHI</name>
|
|
<description>Low-voltage detection interrupt voltage setting bits</description>
|
|
<lsb>2</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LVD_STR" -->
|
|
<register>
|
|
<name>LVD_STR</name>
|
|
<description>Low-voltage Detection Interrupt Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDIR" -->
|
|
<field>
|
|
<name>LVDIR</name>
|
|
<description>Low-voltage detection interrupt bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LVD_CLR" -->
|
|
<register>
|
|
<name>LVD_CLR</name>
|
|
<description>Low-voltage Detection Interrupt Clear Register </description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDCL" -->
|
|
<field>
|
|
<name>LVDCL</name>
|
|
<description>Low-voltage detection interrupt clear bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LVD_RLR" -->
|
|
<register>
|
|
<name>LVD_RLR</name>
|
|
<description>Low-voltage Detection Voltage Protection Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDLCK" -->
|
|
<field>
|
|
<name>LVDLCK</name>
|
|
<description>Low-voltage Detection Voltage Control Register protection bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LVD_STR2" -->
|
|
<register>
|
|
<name>LVD_STR2</name>
|
|
<description>Low-voltage Detection Circuit Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LVDIRDY" -->
|
|
<field>
|
|
<name>LVDIRDY</name>
|
|
<description>Low-voltage detection interrupt status flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "DS" -->
|
|
<peripheral>
|
|
<name>DS</name>
|
|
<description>Low Power Consumption Mode</description>
|
|
<groupName>DS</groupName>
|
|
<baseAddress>0x40035800</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x100</offset>
|
|
<size>0x16</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "PMD_CTL" -->
|
|
<register>
|
|
<name>PMD_CTL</name>
|
|
<description>RTC Mode Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RTCE" -->
|
|
<field>
|
|
<name>RTCE</name>
|
|
<description>RTC mode control bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WRFSR" -->
|
|
<register>
|
|
<name>WRFSR</name>
|
|
<description>Deep Standby Return Cause Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WLVDH" -->
|
|
<field>
|
|
<name>WLVDH</name>
|
|
<description>Low-voltage detection reset return bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WINITX" -->
|
|
<field>
|
|
<name>WINITX</name>
|
|
<description>INITX pin input reset return bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WIFSR" -->
|
|
<register>
|
|
<name>WIFSR</name>
|
|
<description>Deep Standby Return Cause Register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WUI3" -->
|
|
<field>
|
|
<name>WUI3</name>
|
|
<description>WKUP pin input return bit 3</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WUI2" -->
|
|
<field>
|
|
<name>WUI2</name>
|
|
<description>WKUP pin input return bit 2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WUI1" -->
|
|
<field>
|
|
<name>WUI1</name>
|
|
<description>WKUP pin input return bit 1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WUI0" -->
|
|
<field>
|
|
<name>WUI0</name>
|
|
<description>WKUP pin input return bit 0</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WLVDI" -->
|
|
<field>
|
|
<name>WLVDI</name>
|
|
<description>LVD interrupt return bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WRTCI" -->
|
|
<field>
|
|
<name>WRTCI</name>
|
|
<description>RTC interrupt return bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WIER" -->
|
|
<register>
|
|
<name>WIER</name>
|
|
<description>Deep Standby Return Enable Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3B</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WUI3E" -->
|
|
<field>
|
|
<name>WUI3E</name>
|
|
<description>WKUP pin input return enable bit 3</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUI2E" -->
|
|
<field>
|
|
<name>WUI2E</name>
|
|
<description>WKUP pin input return enable bit 2</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUI1E" -->
|
|
<field>
|
|
<name>WUI1E</name>
|
|
<description>WKUP pin input return enable bit 1</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WLVDE" -->
|
|
<field>
|
|
<name>WLVDE</name>
|
|
<description>LVD interrupt return enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WRTCE" -->
|
|
<field>
|
|
<name>WRTCE</name>
|
|
<description>RTC interrupt return enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WILVR" -->
|
|
<register>
|
|
<name>WILVR</name>
|
|
<description>WKUP Pin Input Level Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x07</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WUI3LV" -->
|
|
<field>
|
|
<name>WUI3LV</name>
|
|
<description>WKUP pin input level select bit 3</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUI2LV" -->
|
|
<field>
|
|
<name>WUI2LV</name>
|
|
<description>WKUP pin input level select bit 2</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUI1LV" -->
|
|
<field>
|
|
<name>WUI1LV</name>
|
|
<description>WKUP pin input level select bit 1</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DSRAMR" -->
|
|
<register>
|
|
<name>DSRAMR</name>
|
|
<description>Deep Standby RAM Retention Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SRAMR" -->
|
|
<field>
|
|
<name>SRAMR</name>
|
|
<description>On-chip SRAM retention control bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "BUR01" -->
|
|
<register>
|
|
<name>BUR01</name>
|
|
<description>Backup Registers from 1</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR02" -->
|
|
<register>
|
|
<name>BUR02</name>
|
|
<description>Backup Registers from 2</description>
|
|
<addressOffset>0x101</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR03" -->
|
|
<register>
|
|
<name>BUR03</name>
|
|
<description>Backup Registers from 3</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR04" -->
|
|
<register>
|
|
<name>BUR04</name>
|
|
<description>Backup Registers from 4</description>
|
|
<addressOffset>0x103</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR05" -->
|
|
<register>
|
|
<name>BUR05</name>
|
|
<description>Backup Registers from 5</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR06" -->
|
|
<register>
|
|
<name>BUR06</name>
|
|
<description>Backup Registers from 6</description>
|
|
<addressOffset>0x105</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR07" -->
|
|
<register>
|
|
<name>BUR07</name>
|
|
<description>Backup Registers from 7</description>
|
|
<addressOffset>0x106</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR08" -->
|
|
<register>
|
|
<name>BUR08</name>
|
|
<description>Backup Registers from 8</description>
|
|
<addressOffset>0x107</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR09" -->
|
|
<register>
|
|
<name>BUR09</name>
|
|
<description>Backup Registers from 9</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR10" -->
|
|
<register>
|
|
<name>BUR10</name>
|
|
<description>Backup Registers from 10</description>
|
|
<addressOffset>0x109</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR11" -->
|
|
<register>
|
|
<name>BUR11</name>
|
|
<description>Backup Registers from 11</description>
|
|
<addressOffset>0x10A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR12" -->
|
|
<register>
|
|
<name>BUR12</name>
|
|
<description>Backup Registers from 12</description>
|
|
<addressOffset>0x10B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR13" -->
|
|
<register>
|
|
<name>BUR13</name>
|
|
<description>Backup Registers from 13</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR14" -->
|
|
<register>
|
|
<name>BUR14</name>
|
|
<description>Backup Registers from 14</description>
|
|
<addressOffset>0x10D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR15" -->
|
|
<register>
|
|
<name>BUR15</name>
|
|
<description>Backup Registers from 15</description>
|
|
<addressOffset>0x10E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "BUR16" -->
|
|
<register>
|
|
<name>BUR16</name>
|
|
<description>Backup Registers from 16</description>
|
|
<addressOffset>0x10F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFS0" -->
|
|
<peripheral>
|
|
<name>MFS0</name>
|
|
<description>Multi-function Serial Interface 0</description>
|
|
<groupName>MFS0</groupName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "MFS0RX" -->
|
|
<interrupt>
|
|
<name>MFS0RX</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "MFS0TX" -->
|
|
<interrupt>
|
|
<name>MFS0TX</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "UART_SCR" -->
|
|
<register>
|
|
<name>UART_SCR</name>
|
|
<description>Serial Control Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x9F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCL" -->
|
|
<field>
|
|
<name>UPCL</name>
|
|
<description>Programmable Clear bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RIE" -->
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Received interrupt enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIE" -->
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit interrupt enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TBIE" -->
|
|
<field>
|
|
<name>TBIE</name>
|
|
<description>Transmit bus idle interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RXE" -->
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Received operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TXE" -->
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmission operation enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_SMR" -->
|
|
<register>
|
|
<name>UART_SMR</name>
|
|
<description>Serial Mode Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFD</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MD" -->
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Operation mode set bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUCR" -->
|
|
<field>
|
|
<name>WUCR</name>
|
|
<description>Wake-up control bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SBL" -->
|
|
<field>
|
|
<name>SBL</name>
|
|
<description>Stop bit length select bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDS" -->
|
|
<field>
|
|
<name>BDS</name>
|
|
<description>Transfer direction select bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOE" -->
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Serial data output enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_SSR" -->
|
|
<register>
|
|
<name>UART_SSR</name>
|
|
<description>Serial Status Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xBF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "REC" -->
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Received error flag clear bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PE" -->
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity error flag bit (only functions in operation mode 0) </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FRE" -->
|
|
<field>
|
|
<name>FRE</name>
|
|
<description>Framing error flag bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ORE" -->
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>Overrun error flag bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RDRF" -->
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Received data full flag bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TDRE" -->
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit data empty flag bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TBI" -->
|
|
<field>
|
|
<name>TBI</name>
|
|
<description>Transmit bus idle flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_ESCR" -->
|
|
<register>
|
|
<name>UART_ESCR</name>
|
|
<description>Extended Communication Control Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLWEN" -->
|
|
<field>
|
|
<name>FLWEN</name>
|
|
<description>Flow control enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ESBL" -->
|
|
<field>
|
|
<name>ESBL</name>
|
|
<description>Extension stop bit length select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INV" -->
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Inverted serial data format bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PEN" -->
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>Parity enable bit (only functions in operation mode 0) </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "P" -->
|
|
<field>
|
|
<name>P</name>
|
|
<description>Parity select bit (only functions in operation mode 0)</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "L" -->
|
|
<field>
|
|
<name>L</name>
|
|
<description>Data length select bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_RDR" -->
|
|
<register>
|
|
<name>UART_RDR</name>
|
|
<description>Received Data Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x01FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "UART_TDR" -->
|
|
<register>
|
|
<name>UART_TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x01FF</resetValue>
|
|
<resetMask>0x01FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "UART_BGR" -->
|
|
<register>
|
|
<name>UART_BGR</name>
|
|
<description>Baud Rate Generator Registers</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EXT" -->
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External clock select bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR1" -->
|
|
<field>
|
|
<name>BGR1</name>
|
|
<description>Baud Rate Generator Registers 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR0" -->
|
|
<field>
|
|
<name>BGR0</name>
|
|
<description>Baud Rate Generator Registers 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_FCR1" -->
|
|
<register>
|
|
<name>UART_FCR1</name>
|
|
<description>FIFO Control Register 1</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLSTE" -->
|
|
<field>
|
|
<name>FLSTE</name>
|
|
<description>Re-transmission data lost detect enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRIIE" -->
|
|
<field>
|
|
<name>FRIIE</name>
|
|
<description>Received FIFO idle detection enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FDRQ" -->
|
|
<field>
|
|
<name>FDRQ</name>
|
|
<description>Transmit FIFO data request bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FTIE" -->
|
|
<field>
|
|
<name>FTIE</name>
|
|
<description>Transmit FIFO interrupt enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSEL" -->
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>FIFO select bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_FCR0" -->
|
|
<register>
|
|
<name>UART_FCR0</name>
|
|
<description>FIFO Control Register 0</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLST" -->
|
|
<field>
|
|
<name>FLST</name>
|
|
<description>FIFO re-transmit data lost flag bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FLD" -->
|
|
<field>
|
|
<name>FLD</name>
|
|
<description>FIFO pointer reload bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSET" -->
|
|
<field>
|
|
<name>FSET</name>
|
|
<description>FIFO pointer save bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL2" -->
|
|
<field>
|
|
<name>FCL2</name>
|
|
<description>FIFO2 reset bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL1" -->
|
|
<field>
|
|
<name>FCL1</name>
|
|
<description>FIFO1 reset bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE2" -->
|
|
<field>
|
|
<name>FE2</name>
|
|
<description>FIFO2 operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE1" -->
|
|
<field>
|
|
<name>FE1</name>
|
|
<description>FIFO1 operation enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UART_FBYTE1" -->
|
|
<register>
|
|
<name>UART_FBYTE1</name>
|
|
<description>FIFO Byte Register 1</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "UART_FBYTE2" -->
|
|
<register>
|
|
<name>UART_FBYTE2</name>
|
|
<description>FIFO Byte Register 2</description>
|
|
<alternateGroup>UART</alternateGroup>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "CSIO_SCR" -->
|
|
<register>
|
|
<name>CSIO_SCR</name>
|
|
<description>Serial Control Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCL" -->
|
|
<field>
|
|
<name>UPCL</name>
|
|
<description>Programmable clear bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MS" -->
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave function select bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPI" -->
|
|
<field>
|
|
<name>SPI</name>
|
|
<description>SPI corresponding bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RIE" -->
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Received interrupt enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIE" -->
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit interrupt enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TBIE" -->
|
|
<field>
|
|
<name>TBIE</name>
|
|
<description>Transmit bus idle interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RXE" -->
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Data received enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TXE" -->
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Data transmission enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_SMR" -->
|
|
<register>
|
|
<name>CSIO_SMR</name>
|
|
<description>Serial Mode Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MD" -->
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Operation mode set bits</description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUCR" -->
|
|
<field>
|
|
<name>WUCR</name>
|
|
<description>Wake-up control bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCINV" -->
|
|
<field>
|
|
<name>SCINV</name>
|
|
<description>Serial clock invert bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BDS" -->
|
|
<field>
|
|
<name>BDS</name>
|
|
<description>Transfer direction select bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCKE" -->
|
|
<field>
|
|
<name>SCKE</name>
|
|
<description>Master mode serial clock output enable bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOE" -->
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Serial data output enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_SSR" -->
|
|
<register>
|
|
<name>CSIO_SSR</name>
|
|
<description>Serial Status Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0x8F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "REC" -->
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Received error flag clear bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ORE" -->
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>Overrun error flag bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RDRF" -->
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Received data full flag bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TDRE" -->
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit data empty flag bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TBI" -->
|
|
<field>
|
|
<name>TBI</name>
|
|
<description>Transmit bus idle flag bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_ESCR" -->
|
|
<register>
|
|
<name>CSIO_ESCR</name>
|
|
<description>Extended Communication Control Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x9F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SOP" -->
|
|
<field>
|
|
<name>SOP</name>
|
|
<description>Serial output pin set bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WT" -->
|
|
<field>
|
|
<name>WT</name>
|
|
<description>Data transmit/received wait select bits</description>
|
|
<lsb>3</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "L" -->
|
|
<field>
|
|
<name>L</name>
|
|
<description>Data length select bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_RDR" -->
|
|
<register>
|
|
<name>CSIO_RDR</name>
|
|
<description>Received Data Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x01FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "CSIO_TDR" -->
|
|
<register>
|
|
<name>CSIO_TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x01FF</resetValue>
|
|
<resetMask>0x01FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "CSIO_BGR" -->
|
|
<register>
|
|
<name>CSIO_BGR</name>
|
|
<description>Baud Rate Generator Registers</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7FFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BGR1" -->
|
|
<field>
|
|
<name>BGR1</name>
|
|
<description>Baud Rate Generator Registers 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR0" -->
|
|
<field>
|
|
<name>BGR0</name>
|
|
<description>Baud Rate Generator Registers 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_FCR1" -->
|
|
<register>
|
|
<name>CSIO_FCR1</name>
|
|
<description>FIFO Control Register 1</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLSTE" -->
|
|
<field>
|
|
<name>FLSTE</name>
|
|
<description>Re-transmission data lost detect enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRIIE" -->
|
|
<field>
|
|
<name>FRIIE</name>
|
|
<description>Received FIFO idle detection enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FDRQ" -->
|
|
<field>
|
|
<name>FDRQ</name>
|
|
<description>Transmit FIFO data request bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FTIE" -->
|
|
<field>
|
|
<name>FTIE</name>
|
|
<description>Transmit FIFO interrupt enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSEL" -->
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>FIFO select bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_FCR0" -->
|
|
<register>
|
|
<name>CSIO_FCR0</name>
|
|
<description>FIFO Control Register 0</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLST" -->
|
|
<field>
|
|
<name>FLST</name>
|
|
<description>FIFO re-transmit data lost flag bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FLD" -->
|
|
<field>
|
|
<name>FLD</name>
|
|
<description>FIFO pointer reload bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSET" -->
|
|
<field>
|
|
<name>FSET</name>
|
|
<description>FIFO pointer save bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL2" -->
|
|
<field>
|
|
<name>FCL2</name>
|
|
<description>FIFO2 reset bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL1" -->
|
|
<field>
|
|
<name>FCL1</name>
|
|
<description>FIFO1 reset bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE2" -->
|
|
<field>
|
|
<name>FE2</name>
|
|
<description>FIFO2 operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE1" -->
|
|
<field>
|
|
<name>FE1</name>
|
|
<description>FIFO1 operation enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CSIO_FBYTE1" -->
|
|
<register>
|
|
<name>CSIO_FBYTE1</name>
|
|
<description>FIFO Byte Register 1</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "CSIO_FBYTE2" -->
|
|
<register>
|
|
<name>CSIO_FBYTE2</name>
|
|
<description>FIFO Byte Register 2</description>
|
|
<alternateGroup>CSIO</alternateGroup>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "LIN_SCR" -->
|
|
<register>
|
|
<name>LIN_SCR</name>
|
|
<description>Serial Control Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCL" -->
|
|
<field>
|
|
<name>UPCL</name>
|
|
<description>Programmable clear bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MS" -->
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave function select bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LBR" -->
|
|
<field>
|
|
<name>LBR</name>
|
|
<description>LIN Break Field setting bit (valid in master mode only) </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RIE" -->
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Received interrupt enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIE" -->
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit interrupt enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TBIE" -->
|
|
<field>
|
|
<name>TBIE</name>
|
|
<description>Transmit bus idle interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RXE" -->
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Data reception enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TXE" -->
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Data transmission enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_SMR" -->
|
|
<register>
|
|
<name>LIN_SMR</name>
|
|
<description>Serial Mode Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xF9</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MD" -->
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Operation mode setting bits </description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUCR" -->
|
|
<field>
|
|
<name>WUCR</name>
|
|
<description>Wake-up control bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SBL" -->
|
|
<field>
|
|
<name>SBL</name>
|
|
<description>Stop bit length select bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOE" -->
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Serial data output enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_SSR" -->
|
|
<register>
|
|
<name>LIN_SSR</name>
|
|
<description>Serial Status Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xBF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "REC" -->
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Received Error flag clear bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LBD" -->
|
|
<field>
|
|
<name>LBD</name>
|
|
<description>LIN Break field detection flag bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRE" -->
|
|
<field>
|
|
<name>FRE</name>
|
|
<description>Framing error flag bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ORE" -->
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>Overrun error flag bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RDRF" -->
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Received data full flag bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TDRE" -->
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit data empty flag bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TBI" -->
|
|
<field>
|
|
<name>TBI</name>
|
|
<description>Transmit bus idle flag bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_ESCR" -->
|
|
<register>
|
|
<name>LIN_ESCR</name>
|
|
<description>Extended Communication Control Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xDF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ESBL" -->
|
|
<field>
|
|
<name>ESBL</name>
|
|
<description>Extended stop bit length select bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LBIE" -->
|
|
<field>
|
|
<name>LBIE</name>
|
|
<description>LIN Break field detect interrupt enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LBL" -->
|
|
<field>
|
|
<name>LBL</name>
|
|
<description>LIN Break field length select bits (valid in master mode only) </description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DEL" -->
|
|
<field>
|
|
<name>DEL</name>
|
|
<description>LIN Break delimiter length select bits (valid in master mode only) </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_RDR" -->
|
|
<register>
|
|
<name>LIN_RDR</name>
|
|
<description>Received Data Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x00FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "LIN_TDR" -->
|
|
<register>
|
|
<name>LIN_TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00FF</resetValue>
|
|
<resetMask>0x00FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "LIN_BGR" -->
|
|
<register>
|
|
<name>LIN_BGR</name>
|
|
<description>Baud Rate Generator Registers</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EXT" -->
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External clock select bit </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR1" -->
|
|
<field>
|
|
<name>BGR1</name>
|
|
<description>Baud Rate Generator Registers 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR0" -->
|
|
<field>
|
|
<name>BGR0</name>
|
|
<description>Baud Rate Generator Registers 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_FCR1" -->
|
|
<register>
|
|
<name>LIN_FCR1</name>
|
|
<description>FIFO Control Register 1</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLSTE" -->
|
|
<field>
|
|
<name>FLSTE</name>
|
|
<description>Re-transmission data lost detect enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRIIE" -->
|
|
<field>
|
|
<name>FRIIE</name>
|
|
<description>Received FIFO idle detection enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FDRQ" -->
|
|
<field>
|
|
<name>FDRQ</name>
|
|
<description>Transmit FIFO data request bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FTIE" -->
|
|
<field>
|
|
<name>FTIE</name>
|
|
<description>Transmit FIFO interrupt enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSEL" -->
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>FIFO select bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_FCR0" -->
|
|
<register>
|
|
<name>LIN_FCR0</name>
|
|
<description>FIFO Control Register 0</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLST" -->
|
|
<field>
|
|
<name>FLST</name>
|
|
<description>FIFO re-transmit data lost flag bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FLD" -->
|
|
<field>
|
|
<name>FLD</name>
|
|
<description>FIFO pointer reload bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSET" -->
|
|
<field>
|
|
<name>FSET</name>
|
|
<description>FIFO pointer save bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL2" -->
|
|
<field>
|
|
<name>FCL2</name>
|
|
<description>FIFO2 reset bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL1" -->
|
|
<field>
|
|
<name>FCL1</name>
|
|
<description>FIFO1 reset bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE2" -->
|
|
<field>
|
|
<name>FE2</name>
|
|
<description>FIFO2 operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE1" -->
|
|
<field>
|
|
<name>FE1</name>
|
|
<description>FIFO1 operation enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "LIN_FBYTE1" -->
|
|
<register>
|
|
<name>LIN_FBYTE1</name>
|
|
<description>FIFO Byte Register 1</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "LIN_FBYTE2" -->
|
|
<register>
|
|
<name>LIN_FBYTE2</name>
|
|
<description>FIFO Byte Register 2</description>
|
|
<alternateGroup>LIN</alternateGroup>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "I2C_IBCR" -->
|
|
<register>
|
|
<name>I2C_IBCR</name>
|
|
<description>I2C Bus Control Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MSS" -->
|
|
<field>
|
|
<name>MSS</name>
|
|
<description>Master/slave select bit </description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ACT_SCC" -->
|
|
<field>
|
|
<name>ACT_SCC</name>
|
|
<description>Operation flag/iteration start condition generation bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ACKE" -->
|
|
<field>
|
|
<name>ACKE</name>
|
|
<description>Data byte acknowledge enable bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WSEL" -->
|
|
<field>
|
|
<name>WSEL</name>
|
|
<description>Wait selection bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CNDE" -->
|
|
<field>
|
|
<name>CNDE</name>
|
|
<description>Condition detection interrupt enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTE" -->
|
|
<field>
|
|
<name>INTE</name>
|
|
<description>Interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BER" -->
|
|
<field>
|
|
<name>BER</name>
|
|
<description>Bus error flag bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "INT" -->
|
|
<field>
|
|
<name>INT</name>
|
|
<description>interrupt flag bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_SMR" -->
|
|
<register>
|
|
<name>I2C_SMR</name>
|
|
<description>Serial Mode Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFC</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MD" -->
|
|
<field>
|
|
<name>MD</name>
|
|
<description>operation mode set bits</description>
|
|
<lsb>5</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WUCR" -->
|
|
<field>
|
|
<name>WUCR</name>
|
|
<description>Wake-up control bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RIE" -->
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Received interrupt enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TIE" -->
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit interrupt enable bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_IBSR" -->
|
|
<register>
|
|
<name>I2C_IBSR</name>
|
|
<description>I2C Bus Status Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FBT" -->
|
|
<field>
|
|
<name>FBT</name>
|
|
<description>First byte bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RACK" -->
|
|
<field>
|
|
<name>RACK</name>
|
|
<description>Acknowledge flag bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RSA" -->
|
|
<field>
|
|
<name>RSA</name>
|
|
<description>Reserved address detection bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TRX" -->
|
|
<field>
|
|
<name>TRX</name>
|
|
<description>Data direction bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "AL" -->
|
|
<field>
|
|
<name>AL</name>
|
|
<description>Arbitration lost bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RSC" -->
|
|
<field>
|
|
<name>RSC</name>
|
|
<description>Iteration start condition check bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPC" -->
|
|
<field>
|
|
<name>SPC</name>
|
|
<description>Stop condition check bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BB" -->
|
|
<field>
|
|
<name>BB</name>
|
|
<description>Bus state bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_SSR" -->
|
|
<register>
|
|
<name>I2C_SSR</name>
|
|
<description>Serial Status Register </description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "REC" -->
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Received error flag clear bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TSET" -->
|
|
<field>
|
|
<name>TSET</name>
|
|
<description>Transmit empty flag set bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DMA" -->
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA mode enable bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TBIE" -->
|
|
<field>
|
|
<name>TBIE</name>
|
|
<description>Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ORE" -->
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>Overrun error flag bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "RDRF" -->
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Received data full flag bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TDRE" -->
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit data empty flag bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TBI" -->
|
|
<field>
|
|
<name>TBI</name>
|
|
<description>Transmit bus idle flag bit (Effective only when DMA mode is enabled) </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_RDR" -->
|
|
<register>
|
|
<name>I2C_RDR</name>
|
|
<description>Received Data Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x00FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "I2C_TDR" -->
|
|
<register>
|
|
<name>I2C_TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00FF</resetValue>
|
|
<resetMask>0x00FF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "I2C_ISMK" -->
|
|
<register>
|
|
<name>I2C_ISMK</name>
|
|
<description>7-bit Slave Address Mask Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7F</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EN" -->
|
|
<field>
|
|
<name>EN</name>
|
|
<description>I2C interface operation enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SM" -->
|
|
<field>
|
|
<name>SM</name>
|
|
<description>Slave address mask bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_ISBA" -->
|
|
<register>
|
|
<name>I2C_ISBA</name>
|
|
<description>7-bit Slave Address Register</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SAEN" -->
|
|
<field>
|
|
<name>SAEN</name>
|
|
<description>Slave address enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SA" -->
|
|
<field>
|
|
<name>SA</name>
|
|
<description>7-bit slave address</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_BGR" -->
|
|
<register>
|
|
<name>I2C_BGR</name>
|
|
<description>Baud Rate Generator Registers</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x7FFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BGR1" -->
|
|
<field>
|
|
<name>BGR1</name>
|
|
<description>Baud Rate Generator Registers 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BGR0" -->
|
|
<field>
|
|
<name>BGR0</name>
|
|
<description>Baud Rate Generator Registers 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_FCR1" -->
|
|
<register>
|
|
<name>I2C_FCR1</name>
|
|
<description>FIFO Control Register 1</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLSTE" -->
|
|
<field>
|
|
<name>FLSTE</name>
|
|
<description>Re-transmission data lost detect enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRIIE" -->
|
|
<field>
|
|
<name>FRIIE</name>
|
|
<description>Received FIFO idle detection enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FDRQ" -->
|
|
<field>
|
|
<name>FDRQ</name>
|
|
<description>Transmit FIFO data request bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FTIE" -->
|
|
<field>
|
|
<name>FTIE</name>
|
|
<description>Transmit FIFO interrupt enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSEL" -->
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>FIFO select bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_FCR0" -->
|
|
<register>
|
|
<name>I2C_FCR0</name>
|
|
<description>FIFO Control Register 0</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FLST" -->
|
|
<field>
|
|
<name>FLST</name>
|
|
<description>FIFO re-transmit data lost flag bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "FLD" -->
|
|
<field>
|
|
<name>FLD</name>
|
|
<description>FIFO pointer reload bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FSET" -->
|
|
<field>
|
|
<name>FSET</name>
|
|
<description>FIFO pointer save bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL2" -->
|
|
<field>
|
|
<name>FCL2</name>
|
|
<description>FIFO2 reset bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FCL1" -->
|
|
<field>
|
|
<name>FCL1</name>
|
|
<description>FIFO1 reset bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE2" -->
|
|
<field>
|
|
<name>FE2</name>
|
|
<description>FIFO2 operation enable bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FE1" -->
|
|
<field>
|
|
<name>FE1</name>
|
|
<description>FIFO1 operation enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "I2C_FBYTE1" -->
|
|
<register>
|
|
<name>I2C_FBYTE1</name>
|
|
<description>FIFO Byte Register 1</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "I2C_FBYTE2" -->
|
|
<register>
|
|
<name>I2C_FBYTE2</name>
|
|
<description>FIFO Byte Register 2</description>
|
|
<alternateGroup>I2C</alternateGroup>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFS1" -->
|
|
<peripheral derivedFrom="MFS0">
|
|
<name>MFS1</name>
|
|
<baseAddress>0x40038100</baseAddress>
|
|
<!-- INTERRUPT "MFS1RX" -->
|
|
<interrupt>
|
|
<name>MFS1RX</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "MFS1TX" -->
|
|
<interrupt>
|
|
<name>MFS1TX</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFS3" -->
|
|
<peripheral derivedFrom="MFS0">
|
|
<name>MFS3</name>
|
|
<baseAddress>0x40038300</baseAddress>
|
|
<!-- INTERRUPT "MFS3RX" -->
|
|
<interrupt>
|
|
<name>MFS3RX</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "MFS3TX" -->
|
|
<interrupt>
|
|
<name>MFS3TX</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFS5" -->
|
|
<peripheral derivedFrom="MFS0">
|
|
<name>MFS5</name>
|
|
<baseAddress>0x40038500</baseAddress>
|
|
<!-- INTERRUPT "MFS5RX" -->
|
|
<interrupt>
|
|
<name>MFS5RX</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "MFS5TX" -->
|
|
<interrupt>
|
|
<name>MFS5TX</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "MFS_NFC" -->
|
|
<peripheral>
|
|
<name>MFS_NFC</name>
|
|
<description>I2C Auxiliary Noise Filter Setting Register</description>
|
|
<groupName>MFS_NFC</groupName>
|
|
<baseAddress>0x40038800</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "I2CDNF" -->
|
|
<register>
|
|
<name>I2CDNF</name>
|
|
<description>I2C Auxiliary Noise Filter Setting Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "I2CDNF7" -->
|
|
<field>
|
|
<name>I2CDNF7</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.7</description>
|
|
<lsb>14</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF6" -->
|
|
<field>
|
|
<name>I2CDNF6</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.6</description>
|
|
<lsb>12</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF5" -->
|
|
<field>
|
|
<name>I2CDNF5</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.5</description>
|
|
<lsb>10</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF4" -->
|
|
<field>
|
|
<name>I2CDNF4</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.4</description>
|
|
<lsb>8</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF3" -->
|
|
<field>
|
|
<name>I2CDNF3</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.3</description>
|
|
<lsb>6</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF2" -->
|
|
<field>
|
|
<name>I2CDNF2</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.2</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF1" -->
|
|
<field>
|
|
<name>I2CDNF1</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.1</description>
|
|
<lsb>2</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "I2CDNF0" -->
|
|
<field>
|
|
<name>I2CDNF0</name>
|
|
<description>Auxiliary noise filter additional step select bits for I2C ch.0</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "RTC" -->
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>REAL-TIME CLOCK</description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x4003B000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x13</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x15</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x19</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "WTCR1" -->
|
|
<register>
|
|
<name>WTCR1</name>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFF1F7D</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "INTCRIE" -->
|
|
<field>
|
|
<name>INTCRIE</name>
|
|
<description>Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTERIE" -->
|
|
<field>
|
|
<name>INTERIE</name>
|
|
<description>Time rewrite error interrupt enable bit </description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTALIE" -->
|
|
<field>
|
|
<name>INTALIE</name>
|
|
<description>Alarm interrupt enable bit </description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTTMIE" -->
|
|
<field>
|
|
<name>INTTMIE</name>
|
|
<description>Timer interrupt enable bit</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTHIE" -->
|
|
<field>
|
|
<name>INTHIE</name>
|
|
<description>1-hour interrupt enable bit </description>
|
|
<lsb>27</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTMIE" -->
|
|
<field>
|
|
<name>INTMIE</name>
|
|
<description>1-minute interrupt enable bit </description>
|
|
<lsb>26</lsb>
|
|
<msb>26</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSIE" -->
|
|
<field>
|
|
<name>INTSIE</name>
|
|
<description>1-second interrupt enable bit</description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSSIE" -->
|
|
<field>
|
|
<name>INTSSIE</name>
|
|
<description>0.5-second interrupt enable bit</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTCRI" -->
|
|
<field>
|
|
<name>INTCRI</name>
|
|
<description>Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTERI" -->
|
|
<field>
|
|
<name>INTERI</name>
|
|
<description>Time rewrite error interrupt flag bit </description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTALI" -->
|
|
<field>
|
|
<name>INTALI</name>
|
|
<description>Alarm interrupt flag bit</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTTMI" -->
|
|
<field>
|
|
<name>INTTMI</name>
|
|
<description>Timer interrupt flag bit </description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTHI" -->
|
|
<field>
|
|
<name>INTHI</name>
|
|
<description>1-hour interrupt flag bit </description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTMI" -->
|
|
<field>
|
|
<name>INTMI</name>
|
|
<description>1-minute interrupt flag bit</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSI" -->
|
|
<field>
|
|
<name>INTSI</name>
|
|
<description>1-second interrupt flag bit </description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INTSSI" -->
|
|
<field>
|
|
<name>INTSSI</name>
|
|
<description>0.5-second interrupt flag bit</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "YEN" -->
|
|
<field>
|
|
<name>YEN</name>
|
|
<description>Alarm year register enable bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MOEN" -->
|
|
<field>
|
|
<name>MOEN</name>
|
|
<description>Alarm month register enable bit </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DEN" -->
|
|
<field>
|
|
<name>DEN</name>
|
|
<description>Alarm date register enable bit </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "HEN" -->
|
|
<field>
|
|
<name>HEN</name>
|
|
<description>Alarm hour register enable bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MIEN" -->
|
|
<field>
|
|
<name>MIEN</name>
|
|
<description>Alarm minute register enable bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BUSY" -->
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "SCRST" -->
|
|
<field>
|
|
<name>SCRST</name>
|
|
<description>Sub second generation/1-second generation counter reset bit </description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SCST" -->
|
|
<field>
|
|
<name>SCST</name>
|
|
<description>1-second clock output stop bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SRST" -->
|
|
<field>
|
|
<name>SRST</name>
|
|
<description>RTC reset bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RUN" -->
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>RTC count block operation bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "ST" -->
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTCR2" -->
|
|
<register>
|
|
<name>WTCR2</name>
|
|
<description>Control Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000701</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TMRUN" -->
|
|
<field>
|
|
<name>TMRUN</name>
|
|
<description>Timer counter operation bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "TMEN" -->
|
|
<field>
|
|
<name>TMEN</name>
|
|
<description>Timer counter control bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMST" -->
|
|
<field>
|
|
<name>TMST</name>
|
|
<description>Timer counter start bit </description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CREAD" -->
|
|
<field>
|
|
<name>CREAD</name>
|
|
<description>Year/month/date/hour/minute/second/day of the week counter value read control bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTBR" -->
|
|
<register>
|
|
<name>WTBR</name>
|
|
<description>Counter Cycle Setting Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BR23" -->
|
|
<field>
|
|
<name>BR23</name>
|
|
<description>Bit23 of WTBR</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR22" -->
|
|
<field>
|
|
<name>BR22</name>
|
|
<description>Bit22 of WTBR</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR21" -->
|
|
<field>
|
|
<name>BR21</name>
|
|
<description>Bit21 of WTBR</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR20" -->
|
|
<field>
|
|
<name>BR20</name>
|
|
<description>Bit20 of WTBR</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR19" -->
|
|
<field>
|
|
<name>BR19</name>
|
|
<description>Bit19 of WTBR</description>
|
|
<lsb>19</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR18" -->
|
|
<field>
|
|
<name>BR18</name>
|
|
<description>Bit18 of WTBR</description>
|
|
<lsb>18</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR17" -->
|
|
<field>
|
|
<name>BR17</name>
|
|
<description>Bit17 of WTBR</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR16" -->
|
|
<field>
|
|
<name>BR16</name>
|
|
<description>Bit16 of WTBR</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR15" -->
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Bit15 of WTBR</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR14" -->
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Bit14 of WTBR</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR13" -->
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Bit13 of WTBR</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR12" -->
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Bit12 of WTBR</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR11" -->
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Bit11 of WTBR</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR10" -->
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Bit10 of WTBR</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR9" -->
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Bit9 of WTBR</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR8" -->
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Bit8 of WTBR</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR7" -->
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Bit7 of WTBR</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR6" -->
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Bit6 of WTBR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR5" -->
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Bit5 of WTBR</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR4" -->
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Bit4 of WTBR</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR3" -->
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Bit3 of WTBR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR2" -->
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Bit2 of WTBR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR1" -->
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Bit1 of WTBR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BR0" -->
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Bit0 of WTBR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTDR" -->
|
|
<register>
|
|
<name>WTDR</name>
|
|
<description>Date Register</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TD" -->
|
|
<field>
|
|
<name>TD</name>
|
|
<description>the second digit of the date</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "D" -->
|
|
<field>
|
|
<name>D</name>
|
|
<description>the first digit of the date</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTHR" -->
|
|
<register>
|
|
<name>WTHR</name>
|
|
<description>Hour register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TH" -->
|
|
<field>
|
|
<name>TH</name>
|
|
<description>the second digit of the hour</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "H" -->
|
|
<field>
|
|
<name>H</name>
|
|
<description>the first digit of the hour</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTMIR" -->
|
|
<register>
|
|
<name>WTMIR</name>
|
|
<description>Minute Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TMI" -->
|
|
<field>
|
|
<name>TMI</name>
|
|
<description>the second digit of the minute</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MI" -->
|
|
<field>
|
|
<name>MI</name>
|
|
<description>the first digit of the minute</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTSR" -->
|
|
<register>
|
|
<name>WTSR</name>
|
|
<description>Second Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TS" -->
|
|
<field>
|
|
<name>TS</name>
|
|
<description>the second digit of the second</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "S" -->
|
|
<field>
|
|
<name>S</name>
|
|
<description>the first digit of the second</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTYR" -->
|
|
<register>
|
|
<name>WTYR</name>
|
|
<description>Year Register</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TY" -->
|
|
<field>
|
|
<name>TY</name>
|
|
<description>the second digit of the year</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "Y" -->
|
|
<field>
|
|
<name>Y</name>
|
|
<description>the first digit of the year</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTMOR" -->
|
|
<register>
|
|
<name>WTMOR</name>
|
|
<description>Month Register</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TMO" -->
|
|
<field>
|
|
<name>TMO</name>
|
|
<description>the second digit in the month</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "MO" -->
|
|
<field>
|
|
<name>MO</name>
|
|
<description>the first digit of the month</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTDW" -->
|
|
<register>
|
|
<name>WTDW</name>
|
|
<description>Day of the Week Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DW" -->
|
|
<field>
|
|
<name>DW</name>
|
|
<description>Day of the week</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ALDR" -->
|
|
<register>
|
|
<name>ALDR</name>
|
|
<description>Alarm Date Register</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TAD" -->
|
|
<field>
|
|
<name>TAD</name>
|
|
<description>the second digit of the alarm-set date</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AD" -->
|
|
<field>
|
|
<name>AD</name>
|
|
<description>the first digit of the alarm-set date</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ALHR" -->
|
|
<register>
|
|
<name>ALHR</name>
|
|
<description>Alarm Hour Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TAH" -->
|
|
<field>
|
|
<name>TAH</name>
|
|
<description>the second digit of the alarm-set hour</description>
|
|
<lsb>4</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AH" -->
|
|
<field>
|
|
<name>AH</name>
|
|
<description>the first digit of the alarm-set hour</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ALMIR" -->
|
|
<register>
|
|
<name>ALMIR</name>
|
|
<description>Alarm Minute Register</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TAMI" -->
|
|
<field>
|
|
<name>TAMI</name>
|
|
<description>the second digit of the alarm-set minute</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AMI" -->
|
|
<field>
|
|
<name>AMI</name>
|
|
<description>the first digit of the alarm-set minute</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ALYR" -->
|
|
<register>
|
|
<name>ALYR</name>
|
|
<description>Alarm Years Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TAY" -->
|
|
<field>
|
|
<name>TAY</name>
|
|
<description>the second digit of the alarm-set year</description>
|
|
<lsb>4</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AY" -->
|
|
<field>
|
|
<name>AY</name>
|
|
<description>the first digit of the alarm-set year</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "ALMOR" -->
|
|
<register>
|
|
<name>ALMOR</name>
|
|
<description>Alarm Month Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TAMO" -->
|
|
<field>
|
|
<name>TAMO</name>
|
|
<description>the second digit of the alarm-set month</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "AMO" -->
|
|
<field>
|
|
<name>AMO</name>
|
|
<description>the first digit of the alarm-set month</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTTR" -->
|
|
<register>
|
|
<name>WTTR</name>
|
|
<description>Timer Setting Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TM17" -->
|
|
<field>
|
|
<name>TM17</name>
|
|
<description>Bit17 of WTTR</description>
|
|
<lsb>17</lsb>
|
|
<msb>17</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM16" -->
|
|
<field>
|
|
<name>TM16</name>
|
|
<description>Bit16 of WTTR</description>
|
|
<lsb>16</lsb>
|
|
<msb>16</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM15" -->
|
|
<field>
|
|
<name>TM15</name>
|
|
<description>Bit15 of WTTR</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM14" -->
|
|
<field>
|
|
<name>TM14</name>
|
|
<description>Bit14 of WTTR</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM13" -->
|
|
<field>
|
|
<name>TM13</name>
|
|
<description>Bit13 of WTTR</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM12" -->
|
|
<field>
|
|
<name>TM12</name>
|
|
<description>Bit12 of WTTR</description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM11" -->
|
|
<field>
|
|
<name>TM11</name>
|
|
<description>Bit11 of WTTR</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM10" -->
|
|
<field>
|
|
<name>TM10</name>
|
|
<description>Bit10 of WTTR</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM9" -->
|
|
<field>
|
|
<name>TM9</name>
|
|
<description>Bit9 of WTTR</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM8" -->
|
|
<field>
|
|
<name>TM8</name>
|
|
<description>Bit8 of WTTR</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM7" -->
|
|
<field>
|
|
<name>TM7</name>
|
|
<description>Bit7 of WTTR</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM6" -->
|
|
<field>
|
|
<name>TM6</name>
|
|
<description>Bit6 of WTTR</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM5" -->
|
|
<field>
|
|
<name>TM5</name>
|
|
<description>Bit5 of WTTR</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM4" -->
|
|
<field>
|
|
<name>TM4</name>
|
|
<description>Bit4 of WTTR</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM3" -->
|
|
<field>
|
|
<name>TM3</name>
|
|
<description>Bit3 of WTTR</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM2" -->
|
|
<field>
|
|
<name>TM2</name>
|
|
<description>Bit2 of WTTR</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM1" -->
|
|
<field>
|
|
<name>TM1</name>
|
|
<description>Bit1 of WTTR</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TM0" -->
|
|
<field>
|
|
<name>TM0</name>
|
|
<description>Bit0 of WTTR</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTCLKS" -->
|
|
<register>
|
|
<name>WTCLKS</name>
|
|
<description>Clock Selection Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTCLKS" -->
|
|
<field>
|
|
<name>WTCLKS</name>
|
|
<description>Input clock selection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTCLKM" -->
|
|
<register>
|
|
<name>WTCLKM</name>
|
|
<description>Selection Clock Status Register</description>
|
|
<addressOffset>0x21</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTCLKM" -->
|
|
<field>
|
|
<name>WTCLKM</name>
|
|
<description>Clock selection status bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTCAL" -->
|
|
<register>
|
|
<name>WTCAL</name>
|
|
<description>Frequency Correction Value Setting Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTCAL" -->
|
|
<field>
|
|
<name>WTCAL</name>
|
|
<description>Frequency correction value</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTCALEN" -->
|
|
<register>
|
|
<name>WTCALEN</name>
|
|
<description>Frequency Correction Enable Register</description>
|
|
<addressOffset>0x25</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTCALEN" -->
|
|
<field>
|
|
<name>WTCALEN</name>
|
|
<description>Frequency correction enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTDIV" -->
|
|
<register>
|
|
<name>WTDIV</name>
|
|
<description>Divider Ratio Setting Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x0F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTDIV" -->
|
|
<field>
|
|
<name>WTDIV</name>
|
|
<description>Divider ratio</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "WTDIVEN" -->
|
|
<register>
|
|
<name>WTDIVEN</name>
|
|
<description>Divider Output Enable Register</description>
|
|
<addressOffset>0x29</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "WTDIVRDY" -->
|
|
<field>
|
|
<name>WTDIVRDY</name>
|
|
<description>Divider status bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "WTDIVEN" -->
|
|
<field>
|
|
<name>WTDIVEN</name>
|
|
<description>Divider enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "CRC" -->
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>CRC Registers</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "CRCCR" -->
|
|
<register>
|
|
<name>CRCCR</name>
|
|
<description>CRC Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FXOR" -->
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>Initialization bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CRCLSF" -->
|
|
<field>
|
|
<name>CRCLSF</name>
|
|
<description>Final XOR control bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CRCLTE" -->
|
|
<field>
|
|
<name>CRCLTE</name>
|
|
<description>CRC result bit-order setting bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LSBFST" -->
|
|
<field>
|
|
<name>LSBFST</name>
|
|
<description>CRC result byte-order setting bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "LTLEND" -->
|
|
<field>
|
|
<name>LTLEND</name>
|
|
<description>Bit-order setting bit </description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CRC32" -->
|
|
<field>
|
|
<name>CRC32</name>
|
|
<description>Byte-order setting bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "INIT" -->
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>CRC mode selection bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CRCINIT" -->
|
|
<register>
|
|
<name>CRCINIT</name>
|
|
<description>Initial Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "D" -->
|
|
<field>
|
|
<name>D</name>
|
|
<description>Initial value</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CRCIN" -->
|
|
<register>
|
|
<name>CRCIN</name>
|
|
<description>Input Data Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "D" -->
|
|
<field>
|
|
<name>D</name>
|
|
<description>Input data</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "CRCR" -->
|
|
<register>
|
|
<name>CRCR</name>
|
|
<description>CRC Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "D" -->
|
|
<field>
|
|
<name>D</name>
|
|
<description>CRC Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>31</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "USBCLK" -->
|
|
<peripheral>
|
|
<name>USBCLK</name>
|
|
<description>USB Clock</description>
|
|
<groupName>USBCLK</groupName>
|
|
<baseAddress>0x40036000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xC</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x30</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "UCCR" -->
|
|
<register>
|
|
<name>UCCR</name>
|
|
<description>USB Clock Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UCSEL" -->
|
|
<field>
|
|
<name>UCSEL</name>
|
|
<description>USB clock selection bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UCEN" -->
|
|
<field>
|
|
<name>UCEN</name>
|
|
<description>USB clock output enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPCR1" -->
|
|
<register>
|
|
<name>UPCR1</name>
|
|
<description>USB-PLL Control Register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPINC" -->
|
|
<field>
|
|
<name>UPINC</name>
|
|
<description>USB-PLL input clock selection bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "UPLLEN" -->
|
|
<field>
|
|
<name>UPLLEN</name>
|
|
<description>USB-PLL oscillation enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPCR2" -->
|
|
<register>
|
|
<name>UPCR2</name>
|
|
<description>USB-PLL Control Register 2</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x07</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPOWT" -->
|
|
<field>
|
|
<name>UPOWT</name>
|
|
<description>USB-PLL oscillation stabilization wait time setting bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPCR3" -->
|
|
<register>
|
|
<name>UPCR3</name>
|
|
<description>USB-PLL Control Register 3</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x1F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPLLK" -->
|
|
<field>
|
|
<name>UPLLK</name>
|
|
<description>Frequency division ratio (K) setting bit of the USB-PLL clock </description>
|
|
<lsb>0</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPCR4" -->
|
|
<register>
|
|
<name>UPCR4</name>
|
|
<description>USB-PLL Control Register 4</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3B</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPLLN" -->
|
|
<field>
|
|
<name>UPLLN</name>
|
|
<description>Frequency division ratio (N) setting bit of the USB-PLL clock </description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPCR5" -->
|
|
<register>
|
|
<name>UPCR5</name>
|
|
<description>USB-PLL Control Register 5</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0x0F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPLLM" -->
|
|
<field>
|
|
<name>UPLLM</name>
|
|
<description>Frequency division ratio (M) setting bit of the USB-PLL clock</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UP_STR" -->
|
|
<register>
|
|
<name>UP_STR</name>
|
|
<description>USB-PLL Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPRDY" -->
|
|
<field>
|
|
<name>UPRDY</name>
|
|
<description>USB-PLL oscillation stabilization bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPINT_ENR" -->
|
|
<register>
|
|
<name>UPINT_ENR</name>
|
|
<description>USB-PLL Interrupt Source Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCSE" -->
|
|
<field>
|
|
<name>UPCSE</name>
|
|
<description>USB-PLL oscillation stabilization wait complete interrupt enable bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPINT_STR" -->
|
|
<register>
|
|
<name>UPINT_STR</name>
|
|
<description>USB-PLL Interrupt Source Status Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCSI" -->
|
|
<field>
|
|
<name>UPCSI</name>
|
|
<description>USB-PLL interrupt source status bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UPINT_CLR" -->
|
|
<register>
|
|
<name>UPINT_CLR</name>
|
|
<description>USB-PLL Interrupt Source Clear Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "UPCSC" -->
|
|
<field>
|
|
<name>UPCSC</name>
|
|
<description>USB-PLL oscillation stabilization interrupt source clear bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "USBEN" -->
|
|
<register>
|
|
<name>USBEN</name>
|
|
<description>USB Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x01</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "USBEN" -->
|
|
<field>
|
|
<name>USBEN</name>
|
|
<description>USB enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "USB0" -->
|
|
<peripheral>
|
|
<name>USB0</name>
|
|
<description>USB0 Function</description>
|
|
<groupName>USB0</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x2100</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2104</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2108</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x210C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2110</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2114</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2118</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x211C</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2120</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2124</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2128</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x212C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2130</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2134</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2138</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x213C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2140</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2144</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2148</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x214C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2150</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2154</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2158</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x215C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2160</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2164</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2168</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x216C</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2170</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x2174</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "USB0F" -->
|
|
<interrupt>
|
|
<name>USB0F</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "USB0F_USB0H" -->
|
|
<interrupt>
|
|
<name>USB0F_USB0H</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "UDCC" -->
|
|
<register>
|
|
<name>UDCC</name>
|
|
<description>UDC Control Register</description>
|
|
<addressOffset>0x2120</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00A0</resetValue>
|
|
<resetMask>0x00FB</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RST" -->
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Function Reset bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RESUM" -->
|
|
<field>
|
|
<name>RESUM</name>
|
|
<description>Resume Setting bit </description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "HCONX" -->
|
|
<field>
|
|
<name>HCONX</name>
|
|
<description>Host Connection bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "USTP" -->
|
|
<field>
|
|
<name>USTP</name>
|
|
<description>USB Operating Clock Stop bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STALCLREN" -->
|
|
<field>
|
|
<name>STALCLREN</name>
|
|
<description>Endpoint 1 to 5 STAL bit Clear Select bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RFBK" -->
|
|
<field>
|
|
<name>RFBK</name>
|
|
<description>Data Toggle Mode Select bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PWC" -->
|
|
<field>
|
|
<name>PWC</name>
|
|
<description>Power Control bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP0C" -->
|
|
<register>
|
|
<name>EP0C</name>
|
|
<description>EP0 Control Register</description>
|
|
<addressOffset>0x2124</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0040</resetValue>
|
|
<resetMask>0x027F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "STAL" -->
|
|
<field>
|
|
<name>STAL</name>
|
|
<description>Endpoint 0 Stall Setting bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PKS0" -->
|
|
<field>
|
|
<name>PKS0</name>
|
|
<description>Packet Size Endpoint 0 Setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP1C" -->
|
|
<register>
|
|
<name>EP1C</name>
|
|
<description>EP1 Control Register</description>
|
|
<addressOffset>0x2128</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6100</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EPEN" -->
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint Enable bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TYPE" -->
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Endpoint Transfer Type Select bits</description>
|
|
<lsb>13</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DIR" -->
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Endpoint Transfer Direction Select bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DMAE" -->
|
|
<field>
|
|
<name>DMAE</name>
|
|
<description>DMA Automatic Transfer Enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "NULE" -->
|
|
<field>
|
|
<name>NULE</name>
|
|
<description>Null Automatic Transfer Enable bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STAL" -->
|
|
<field>
|
|
<name>STAL</name>
|
|
<description>Endpoint Stall Setting bit </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PKS" -->
|
|
<field>
|
|
<name>PKS</name>
|
|
<description>Packet Size Setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP2C" -->
|
|
<register>
|
|
<name>EP2C</name>
|
|
<description>EP2 Control Register</description>
|
|
<addressOffset>0x212C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6040</resetValue>
|
|
<resetMask>0xFE7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EPEN" -->
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint Enable bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TYPE" -->
|
|
<field>
|
|
<name>TYPE</name>
|
|
<description>Endpoint Transfer Type Select bits</description>
|
|
<lsb>13</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DIR" -->
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Endpoint Transfer Direction Select bit </description>
|
|
<lsb>12</lsb>
|
|
<msb>12</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DMAE" -->
|
|
<field>
|
|
<name>DMAE</name>
|
|
<description>DMA Automatic Transfer Enable bit</description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "NULE" -->
|
|
<field>
|
|
<name>NULE</name>
|
|
<description>Null Automatic Transfer Enable bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STAL" -->
|
|
<field>
|
|
<name>STAL</name>
|
|
<description>Endpoint Stall Setting bit </description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PKS" -->
|
|
<field>
|
|
<name>PKS</name>
|
|
<description>Packet Size Setting bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP3C" -->
|
|
<register derivedFrom="EP2C">
|
|
<name>EP3C</name>
|
|
<description>EP3 Control Register</description>
|
|
<addressOffset>0x2130</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP4C" -->
|
|
<register derivedFrom="EP2C">
|
|
<name>EP4C</name>
|
|
<description>EP4 Control Register</description>
|
|
<addressOffset>0x2134</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP5C" -->
|
|
<register derivedFrom="EP2C">
|
|
<name>EP5C</name>
|
|
<description>EP5 Control Register</description>
|
|
<addressOffset>0x2138</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "TMSP" -->
|
|
<register>
|
|
<name>TMSP</name>
|
|
<description>Time Stamp Register</description>
|
|
<addressOffset>0x213C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x07FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TMSP" -->
|
|
<field>
|
|
<name>TMSP</name>
|
|
<description>Time Stamp bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>10</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UDCS" -->
|
|
<register>
|
|
<name>UDCS</name>
|
|
<description>UDC Status Register</description>
|
|
<addressOffset>0x2140</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SUSP" -->
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend detection bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOF" -->
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>SOF Detection bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BRST" -->
|
|
<field>
|
|
<name>BRST</name>
|
|
<description>Bus Reset Detection bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WKUP" -->
|
|
<field>
|
|
<name>WKUP</name>
|
|
<description>Wake-up Detection bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SETP" -->
|
|
<field>
|
|
<name>SETP</name>
|
|
<description>Setup Stage Detection bit </description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CONF" -->
|
|
<field>
|
|
<name>CONF</name>
|
|
<description>Configuration Detection bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "UDCIE" -->
|
|
<register>
|
|
<name>UDCIE</name>
|
|
<description>UDC Interrupt Enable Register</description>
|
|
<addressOffset>0x2141</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SUSPIE" -->
|
|
<field>
|
|
<name>SUSPIE</name>
|
|
<description>Suspend Interrupt Enable bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOFIE" -->
|
|
<field>
|
|
<name>SOFIE</name>
|
|
<description>SOF Reception Interrupt Enable bit </description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BRSTIE" -->
|
|
<field>
|
|
<name>BRSTIE</name>
|
|
<description>Bus Reset Enable bit </description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "WKUPIE" -->
|
|
<field>
|
|
<name>WKUPIE</name>
|
|
<description>Wake-up Interrupt Enable bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CONFN" -->
|
|
<field>
|
|
<name>CONFN</name>
|
|
<description>Configuration Number Indication bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CONFIE" -->
|
|
<field>
|
|
<name>CONFIE</name>
|
|
<description>Configuration Interrupt Enable bit </description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP0IS" -->
|
|
<register>
|
|
<name>EP0IS</name>
|
|
<description>EP0I Status Register</description>
|
|
<addressOffset>0x2144</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8400</resetValue>
|
|
<resetMask>0xC400</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BFINI" -->
|
|
<field>
|
|
<name>BFINI</name>
|
|
<description>Send Buffer Initialization bit </description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQIIE" -->
|
|
<field>
|
|
<name>DRQIIE</name>
|
|
<description>Send Data Interrupt Enable bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQI" -->
|
|
<field>
|
|
<name>DRQI</name>
|
|
<description>Send/Receive Data Interrupt Request bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP0OS" -->
|
|
<register>
|
|
<name>EP0OS</name>
|
|
<description>EP0O Status Register</description>
|
|
<addressOffset>0x2148</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xE67F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BFINI" -->
|
|
<field>
|
|
<name>BFINI</name>
|
|
<description>Receive Buffer Initialization bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQOIE" -->
|
|
<field>
|
|
<name>DRQOIE</name>
|
|
<description>Receive Data Interrupt Enable bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPKIE" -->
|
|
<field>
|
|
<name>SPKIE</name>
|
|
<description>Short Packet Interrupt Enable bit </description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQO" -->
|
|
<field>
|
|
<name>DRQO</name>
|
|
<description>Receive Data Interrupt Request bit </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPK" -->
|
|
<field>
|
|
<name>SPK</name>
|
|
<description>Short Packet Interrupt Request bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIZE" -->
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Packet Size Indication bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP1S" -->
|
|
<register>
|
|
<name>EP1S</name>
|
|
<description>EP1 Status Register</description>
|
|
<addressOffset>0x214C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xEFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BFINI" -->
|
|
<field>
|
|
<name>BFINI</name>
|
|
<description>Send/Receive Buffer Initialization bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQIE" -->
|
|
<field>
|
|
<name>DRQIE</name>
|
|
<description>Packet Transfer Interrupt Enable bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPKIE" -->
|
|
<field>
|
|
<name>SPKIE</name>
|
|
<description>Short Packet Interrupt Enable bit</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BUSY" -->
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy Flag bit </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "DRQ" -->
|
|
<field>
|
|
<name>DRQ</name>
|
|
<description>Packet Transfer Interrupt Request bit </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPK" -->
|
|
<field>
|
|
<name>SPK</name>
|
|
<description>Short Packet Interrupt Request bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIZE" -->
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>packet SIZE</description>
|
|
<lsb>0</lsb>
|
|
<msb>8</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP2S" -->
|
|
<register>
|
|
<name>EP2S</name>
|
|
<description>EP2 Status Register</description>
|
|
<addressOffset>0x2150</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<resetMask>0xEFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BFINI" -->
|
|
<field>
|
|
<name>BFINI</name>
|
|
<description>Send/Receive Buffer Initialization bit</description>
|
|
<lsb>15</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DRQIE" -->
|
|
<field>
|
|
<name>DRQIE</name>
|
|
<description>Packet Transfer Interrupt Enable bit</description>
|
|
<lsb>14</lsb>
|
|
<msb>14</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPKIE" -->
|
|
<field>
|
|
<name>SPKIE</name>
|
|
<description>Short Packet Interrupt Enable bit</description>
|
|
<lsb>13</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BUSY" -->
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy Flag bit </description>
|
|
<lsb>11</lsb>
|
|
<msb>11</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "DRQ" -->
|
|
<field>
|
|
<name>DRQ</name>
|
|
<description>Packet Transfer Interrupt Request bit </description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SPK" -->
|
|
<field>
|
|
<name>SPK</name>
|
|
<description>Short Packet Interrupt Request bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SIZE" -->
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>packet SIZE</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP3S" -->
|
|
<register derivedFrom="EP2S">
|
|
<name>EP3S</name>
|
|
<description>EP3 Status Register</description>
|
|
<addressOffset>0x2154</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP4S" -->
|
|
<register derivedFrom="EP2S">
|
|
<name>EP4S</name>
|
|
<description>EP4 Status Register</description>
|
|
<addressOffset>0x2158</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP5S" -->
|
|
<register derivedFrom="EP2S">
|
|
<name>EP5S</name>
|
|
<description>EP5 Status Register</description>
|
|
<addressOffset>0x215C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP0DT" -->
|
|
<register>
|
|
<name>EP0DT</name>
|
|
<description>EP0 Data Register</description>
|
|
<addressOffset>0x2160</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x0000</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "BFDT" -->
|
|
<field>
|
|
<name>BFDT</name>
|
|
<description>Endpoint Send/Receive Buffer Data</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "EP1DT" -->
|
|
<register derivedFrom="EP0DT">
|
|
<name>EP1DT</name>
|
|
<description>EP1 Data Register</description>
|
|
<addressOffset>0x2164</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP2DT" -->
|
|
<register derivedFrom="EP0DT">
|
|
<name>EP2DT</name>
|
|
<description>EP2 Data Register</description>
|
|
<addressOffset>0x2168</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP3DT" -->
|
|
<register derivedFrom="EP0DT">
|
|
<name>EP3DT</name>
|
|
<description>EP3 Data Register</description>
|
|
<addressOffset>0x216C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP4DT" -->
|
|
<register derivedFrom="EP0DT">
|
|
<name>EP4DT</name>
|
|
<description>EP4 Data Register</description>
|
|
<addressOffset>0x2170</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "EP5DT" -->
|
|
<register derivedFrom="EP0DT">
|
|
<name>EP5DT</name>
|
|
<description>EP5 Data Register</description>
|
|
<addressOffset>0x2174</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "HCNT" -->
|
|
<register>
|
|
<name>HCNT</name>
|
|
<description>Host Control Register</description>
|
|
<addressOffset>0x2100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0100</resetValue>
|
|
<resetMask>0x07FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "SOFSTEP" -->
|
|
<field>
|
|
<name>SOFSTEP</name>
|
|
<description>SOF interrupt occurrence selection bit</description>
|
|
<lsb>10</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CANCEL" -->
|
|
<field>
|
|
<name>CANCEL</name>
|
|
<description>token cancellation enable bit</description>
|
|
<lsb>9</lsb>
|
|
<msb>9</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RETRY" -->
|
|
<field>
|
|
<name>RETRY</name>
|
|
<description>retry enable bit</description>
|
|
<lsb>8</lsb>
|
|
<msb>8</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RWKIRE" -->
|
|
<field>
|
|
<name>RWKIRE</name>
|
|
<description>resume interrupt enable bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "URIRE" -->
|
|
<field>
|
|
<name>URIRE</name>
|
|
<description>bus reset interrupt enable bit</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMPIRE" -->
|
|
<field>
|
|
<name>CMPIRE</name>
|
|
<description>token completion interrupt enable bit</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CNNIRE" -->
|
|
<field>
|
|
<name>CNNIRE</name>
|
|
<description>device connection detection interrupt enable bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DIRE" -->
|
|
<field>
|
|
<name>DIRE</name>
|
|
<description>device disconnection detection interrupt enable bit</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOFIRE" -->
|
|
<field>
|
|
<name>SOFIRE</name>
|
|
<description>SOF interrupt enable bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "URST" -->
|
|
<field>
|
|
<name>URST</name>
|
|
<description>bus reset bit</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "HOST" -->
|
|
<field>
|
|
<name>HOST</name>
|
|
<description>host mode bit</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HIRQ" -->
|
|
<register>
|
|
<name>HIRQ</name>
|
|
<description>Host Interrupt Register</description>
|
|
<addressOffset>0x2104</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xBF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TCAN" -->
|
|
<field>
|
|
<name>TCAN</name>
|
|
<description>token cancellation flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RWKIRQ" -->
|
|
<field>
|
|
<name>RWKIRQ</name>
|
|
<description>remote Wake-up end flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "URIRQ" -->
|
|
<field>
|
|
<name>URIRQ</name>
|
|
<description>bus reset end flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CMPIRQ" -->
|
|
<field>
|
|
<name>CMPIRQ</name>
|
|
<description>token completion flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CNNIRQ" -->
|
|
<field>
|
|
<name>CNNIRQ</name>
|
|
<description>device connection detection flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DIRQ" -->
|
|
<field>
|
|
<name>DIRQ</name>
|
|
<description>device disconnection detection flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOFIRQ" -->
|
|
<field>
|
|
<name>SOFIRQ</name>
|
|
<description>SOF starting flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HERR" -->
|
|
<register>
|
|
<name>HERR</name>
|
|
<description>Host Error Status Register</description>
|
|
<addressOffset>0x2105</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x03</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "LSTSOF" -->
|
|
<field>
|
|
<name>LSTSOF</name>
|
|
<description>lost SOF flag</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RERR" -->
|
|
<field>
|
|
<name>RERR</name>
|
|
<description>receive error flag</description>
|
|
<lsb>6</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TOUT" -->
|
|
<field>
|
|
<name>TOUT</name>
|
|
<description>timeout flag</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CRC" -->
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>CRC error flag</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TGERR" -->
|
|
<field>
|
|
<name>TGERR</name>
|
|
<description>toggle error flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "STUFF" -->
|
|
<field>
|
|
<name>STUFF</name>
|
|
<description>stuffing error flag</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "HS" -->
|
|
<field>
|
|
<name>HS</name>
|
|
<description>handshake status flags</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HSTATE" -->
|
|
<register>
|
|
<name>HSTATE</name>
|
|
<description>Host Status Register</description>
|
|
<addressOffset>0x2108</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12</resetValue>
|
|
<resetMask>0x3F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ALIVE" -->
|
|
<field>
|
|
<name>ALIVE</name>
|
|
<description>specify the keep-alive function in the low-speed mode</description>
|
|
<lsb>5</lsb>
|
|
<msb>5</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "CLKSEL" -->
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>USB operation clock selection bit</description>
|
|
<lsb>4</lsb>
|
|
<msb>4</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SOFBUSY" -->
|
|
<field>
|
|
<name>SOFBUSY</name>
|
|
<description>SOF busy flag</description>
|
|
<lsb>3</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SUSP" -->
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>suspend setting bit</description>
|
|
<lsb>2</lsb>
|
|
<msb>2</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TMODE" -->
|
|
<field>
|
|
<name>TMODE</name>
|
|
<description>transmission mode flag</description>
|
|
<lsb>1</lsb>
|
|
<msb>1</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<!-- FIELD "CSTAT" -->
|
|
<field>
|
|
<name>CSTAT</name>
|
|
<description>connection status flag</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HFCOMP" -->
|
|
<register>
|
|
<name>HFCOMP</name>
|
|
<description>SOF Interrupt Frame Compare Register</description>
|
|
<addressOffset>0x2109</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FRAMECOMP" -->
|
|
<field>
|
|
<name>FRAMECOMP</name>
|
|
<description>frame compare data</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HRTIMER" -->
|
|
<register>
|
|
<name>HRTIMER</name>
|
|
<description>Retry Timer Setup Register</description>
|
|
<addressOffset>0x210C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RTIMER1" -->
|
|
<field>
|
|
<name>RTIMER1</name>
|
|
<description>retry timer setting 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RTIMER0" -->
|
|
<field>
|
|
<name>RTIMER0</name>
|
|
<description>retry timer setting 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HRTIMER2" -->
|
|
<register>
|
|
<name>HRTIMER2</name>
|
|
<description>Retry Timer Setup Register 2</description>
|
|
<addressOffset>0x2110</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x03</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "RTIMER2" -->
|
|
<field>
|
|
<name>RTIMER2</name>
|
|
<description>retry timer setting 2</description>
|
|
<lsb>0</lsb>
|
|
<msb>1</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HADR" -->
|
|
<register>
|
|
<name>HADR</name>
|
|
<description>Host Address Register</description>
|
|
<addressOffset>0x2111</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "ADDRESS" -->
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Host Address</description>
|
|
<lsb>0</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HEOF" -->
|
|
<register>
|
|
<name>HEOF</name>
|
|
<description>EOF Setup Register</description>
|
|
<addressOffset>0x2114</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x3FFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EOF1" -->
|
|
<field>
|
|
<name>EOF1</name>
|
|
<description>End Frame 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>13</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EOF0" -->
|
|
<field>
|
|
<name>EOF0</name>
|
|
<description>End Frame 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HFRAME" -->
|
|
<register>
|
|
<name>HFRAME</name>
|
|
<description>Frame Setup Register</description>
|
|
<addressOffset>0x2118</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0x07FF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "FRAME1" -->
|
|
<field>
|
|
<name>FRAME1</name>
|
|
<description>Frame Setup 1</description>
|
|
<lsb>8</lsb>
|
|
<msb>10</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FRAME0" -->
|
|
<field>
|
|
<name>FRAME0</name>
|
|
<description>Frame Setup 0</description>
|
|
<lsb>0</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "HTOKEN" -->
|
|
<register>
|
|
<name>HTOKEN</name>
|
|
<description>Host Token Endpoint Register</description>
|
|
<addressOffset>0x211C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "TGGL" -->
|
|
<field>
|
|
<name>TGGL</name>
|
|
<description>toggle bit</description>
|
|
<lsb>7</lsb>
|
|
<msb>7</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TKNEN" -->
|
|
<field>
|
|
<name>TKNEN</name>
|
|
<description>token enable bits</description>
|
|
<lsb>4</lsb>
|
|
<msb>6</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ENDPT" -->
|
|
<field>
|
|
<name>ENDPT</name>
|
|
<description>endpoint bits</description>
|
|
<lsb>0</lsb>
|
|
<msb>3</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<!-- PERIPHERAL "DMAC" -->
|
|
<peripheral>
|
|
<name>DMAC</name>
|
|
<description>DMAC Registers</description>
|
|
<groupName>DMAC</groupName>
|
|
<baseAddress>0x40060000</baseAddress>
|
|
<!-- ADDRESS BLOCK -->
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<!-- INTERRUPT "DMAC0" -->
|
|
<interrupt>
|
|
<name>DMAC0</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "DMAC1" -->
|
|
<interrupt>
|
|
<name>DMAC1</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "DMAC2" -->
|
|
<interrupt>
|
|
<name>DMAC2</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<!-- INTERRUPT "DMAC3" -->
|
|
<interrupt>
|
|
<name>DMAC3</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<!-- REGISTERS -->
|
|
<registers>
|
|
<!-- REGISTER "DMACR" -->
|
|
<register>
|
|
<name>DMACR</name>
|
|
<description>Entire DMAC Configuration Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xDF000000</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "DE" -->
|
|
<field>
|
|
<name>DE</name>
|
|
<description>DMA Enable (all-channel operation enable bit) </description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DS" -->
|
|
<field>
|
|
<name>DS</name>
|
|
<description>DMA Stop</description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PR" -->
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Priority Rotation</description>
|
|
<lsb>28</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "DH" -->
|
|
<field>
|
|
<name>DH</name>
|
|
<description>DMA Halt (All-channel pause bit) </description>
|
|
<lsb>24</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DMACA0" -->
|
|
<register>
|
|
<name>DMACA0</name>
|
|
<description>Configuration A Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFF9FFFFF</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "EB" -->
|
|
<field>
|
|
<name>EB</name>
|
|
<description>Enable bit (individual-channel operation enable bit)</description>
|
|
<lsb>31</lsb>
|
|
<msb>31</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "PB" -->
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Pause bit (individual-channel pause bit) </description>
|
|
<lsb>30</lsb>
|
|
<msb>30</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "ST" -->
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Software Trigger</description>
|
|
<lsb>29</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "IS" -->
|
|
<field>
|
|
<name>IS</name>
|
|
<description>Input Select </description>
|
|
<lsb>23</lsb>
|
|
<msb>28</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "BC" -->
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Block Count </description>
|
|
<lsb>16</lsb>
|
|
<msb>19</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TC" -->
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transfer Count</description>
|
|
<lsb>0</lsb>
|
|
<msb>15</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DMACB0" -->
|
|
<register>
|
|
<name>DMACB0</name>
|
|
<description>Configuration B Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3FFF0001</resetMask>
|
|
<!-- FIELDS -->
|
|
<fields>
|
|
<!-- FIELD "MS" -->
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Mode Select</description>
|
|
<lsb>28</lsb>
|
|
<msb>29</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "TW" -->
|
|
<field>
|
|
<name>TW</name>
|
|
<description>Transfer Width </description>
|
|
<lsb>26</lsb>
|
|
<msb>27</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FS" -->
|
|
<field>
|
|
<name>FS</name>
|
|
<description>Fixed Source </description>
|
|
<lsb>25</lsb>
|
|
<msb>25</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "FD" -->
|
|
<field>
|
|
<name>FD</name>
|
|
<description>Fixed Destination</description>
|
|
<lsb>24</lsb>
|
|
<msb>24</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RC" -->
|
|
<field>
|
|
<name>RC</name>
|
|
<description>Reload Count (BC/TC reload)</description>
|
|
<lsb>23</lsb>
|
|
<msb>23</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RS" -->
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Reload Source</description>
|
|
<lsb>22</lsb>
|
|
<msb>22</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "RD" -->
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Reload Destination</description>
|
|
<lsb>21</lsb>
|
|
<msb>21</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EI" -->
|
|
<field>
|
|
<name>EI</name>
|
|
<description>Error Interrupt (unsuccessful transfer completion interrupt enable)</description>
|
|
<lsb>20</lsb>
|
|
<msb>20</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "SS" -->
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Stop Status (stop status notification)</description>
|
|
<lsb>16</lsb>
|
|
<msb>18</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<!-- FIELD "EM" -->
|
|
<field>
|
|
<name>EM</name>
|
|
<description>Enable bit Mask (EB bit clear mask)</description>
|
|
<lsb>0</lsb>
|
|
<msb>0</msb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!-- REGISTER "DMACSA0" -->
|
|
<register>
|
|
<name>DMACSA0</name>
|
|
<description>Transfer Source Address Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "DMACDA0" -->
|
|
<register>
|
|
<name>DMACDA0</name>
|
|
<description>Transfer Destination Address Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<!-- REGISTER "DMACA1" -->
|
|
<register derivedFrom="DMACA0">
|
|
<name>DMACA1</name>
|
|
<description>Configuration A Register 1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACB1" -->
|
|
<register derivedFrom="DMACB0">
|
|
<name>DMACB1</name>
|
|
<description>Configuration B Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACSA1" -->
|
|
<register derivedFrom="DMACSA0">
|
|
<name>DMACSA1</name>
|
|
<description>Transfer Source Address Register 1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACDA1" -->
|
|
<register derivedFrom="DMACDA0">
|
|
<name>DMACDA1</name>
|
|
<description>Transfer Destination Address Register 1</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACA2" -->
|
|
<register derivedFrom="DMACA0">
|
|
<name>DMACA2</name>
|
|
<description>Configuration A Register 2</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACB2" -->
|
|
<register derivedFrom="DMACB0">
|
|
<name>DMACB2</name>
|
|
<description>Configuration B Register 2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACSA2" -->
|
|
<register derivedFrom="DMACSA0">
|
|
<name>DMACSA2</name>
|
|
<description>Transfer Source Address Register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACDA2" -->
|
|
<register derivedFrom="DMACDA0">
|
|
<name>DMACDA2</name>
|
|
<description>Transfer Destination Address Register 2</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACA3" -->
|
|
<register derivedFrom="DMACA0">
|
|
<name>DMACA3</name>
|
|
<description>Configuration A Register 3</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACB3" -->
|
|
<register derivedFrom="DMACB0">
|
|
<name>DMACB3</name>
|
|
<description>Configuration B Register 3</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACSA3" -->
|
|
<register derivedFrom="DMACSA0">
|
|
<name>DMACSA3</name>
|
|
<description>Transfer Source Address Register 3</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
</register>
|
|
<!-- REGISTER "DMACDA3" -->
|
|
<register derivedFrom="DMACDA0">
|
|
<name>DMACDA3</name>
|
|
<description>Transfer Destination Address Register 3</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|