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RMUL2025/lib/cmsis_svd/data/STMicro/STM32W108.svd

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<?xml version="1.0" encoding="utf-8" standalone="no"?>
<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32W108</name>
<version>1.0</version>
<description>STM32W108</description>
<!--Bus Interface Properties-->
<!--Cortex-M3 is byte addressable-->
<addressUnitBits>8</addressUnitBits>
<!--the maximum data bit width accessible within a single transfer-->
<width>32</width>
<!--Register Default Properties-->
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>TIM1</name>
<description>General purpose timer 1</description>
<groupName>TIM</groupName>
<baseAddress>0x4000A800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3851</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM1_IRQ</name>
<description>Timer 1 Interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>TIM1_ISR</name>
<displayName>TIM1_ISR</displayName>
<description>TIM Interrupt Status Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSVD</name>
<description>RSVD</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIF</name>
<description>TIF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC4IF</name>
<description>CC4IF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC3IF</name>
<description>CC3IF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC2IF</name>
<description>CC2IF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC1IF</name>
<description>CC1IF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIF</name>
<description>UIF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TIM1_MISSR</name>
<displayName>TIM1_MISSR</displayName>
<description>TIM interrupt missed register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4IM</name>
<description>CC4IM</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC3IM</name>
<description>CC3IM</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC2IM</name>
<description>CC2IM</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC1IM</name>
<description>CC1IM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RSVD</name>
<description>RSVD</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TIM1_CR1</name>
<displayName>TIM1_CR1</displayName>
<description>control register 1</description>
<addressOffset>0x3800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARBE</name>
<description>ARBE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>CMS</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>OPM</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>URS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>UDIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>CEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_IER</name>
<displayName>TIM1_IER</displayName>
<description>TIM Interrupt Enable Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>TIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>CC4IE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>CC3IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>CC2IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>CC1IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>UIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CR2</name>
<displayName>TIM1_CR2</displayName>
<description>control register 2</description>
<addressOffset>0x3804</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1S</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>MMS</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_SMCR</name>
<displayName>TIM1_SMCR</displayName>
<description>slave Mode Control register</description>
<addressOffset>0x3808</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>ETP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>ECE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>ETPS</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>ETF</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>MSM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>TS</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMS</name>
<description>SMS</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_EGR</name>
<displayName>TIM1_EGR</displayName>
<description>TIM event generation register</description>
<addressOffset>0x3814</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TG</name>
<description>TG</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>CC4G</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>CC3G</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>CC2G</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>CC1G</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>UG</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCMR1_Input</name>
<displayName>TIM1_CCMR1_Input</displayName>
<description>capture/compare mode register 1 (Input
mode)</description>
<addressOffset>0x3818</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>IC1PSC</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>IC1F</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>IC2PSC</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2F</name>
<description>IC2F</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCMR1_Output</name>
<displayName>TIM1_CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<alternateRegister>TIM1_CCMR1_Input</alternateRegister>
<addressOffset>0x3818</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCMR2_Input</name>
<displayName>TIM1_CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<addressOffset>0x381C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>IC3PSC</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>IC3F</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>IC4PSC</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC4F</name>
<description>IC4F</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCMR2_Output</name>
<displayName>TIM1_CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<alternateRegister>TIM1_CCMR2_Input</alternateRegister>
<addressOffset>0x381C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCER</name>
<displayName>TIM1_CCER</displayName>
<description>TIM capture/compare enable
register</description>
<addressOffset>0x3820</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4P</name>
<description>CC4P</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>CC4E</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>CC3P</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>CC3E</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>CC2P</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>CC2E</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>CC1P</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>CC1E</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CNT</name>
<displayName>TIM1_CNT</displayName>
<description>TIM counter register</description>
<addressOffset>0x3824</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_PSC</name>
<displayName>TIM1_PSC</displayName>
<description>TIM prescaler register</description>
<addressOffset>0x3828</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>PSC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_ARR</name>
<displayName>TIM1_ARR</displayName>
<description>TIM auto-reload register</description>
<addressOffset>0x382C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>ARR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCR1</name>
<displayName>TIM1_CCR1</displayName>
<description>IM capture/compare register 1</description>
<addressOffset>0x3834</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCR2</name>
<displayName>TIM1_CCR2</displayName>
<description>TIM capture/compare register 2</description>
<addressOffset>0x3838</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCR3</name>
<displayName>TIM1_CCR3</displayName>
<description>TIM capture/compare register 3</description>
<addressOffset>0x383C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_CCR4</name>
<displayName>TIM1_CCR4</displayName>
<description>TIM capture/compare register 4</description>
<addressOffset>0x3840</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM1_OR</name>
<displayName>TIM1_OR</displayName>
<description>TIM option register</description>
<addressOffset>0x3850</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ORRSVD</name>
<description>ORRSVD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKMSKEN</name>
<description>CLKMSKEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTRIGSEL</name>
<description>EXTRIGSEL</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM2</name>
<description>General purpose timer 2</description>
<groupName>TIM</groupName>
<baseAddress>0x4000A804</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x484D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM2_IRQ</name>
<description>Timer 2 Interrupt</description>
<value>1</value>
</interrupt>
<registers>
<register>
<name>TIM2_ISR</name>
<displayName>TIM2_ISR</displayName>
<description>TIM Interrupt Status Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSVD</name>
<description>RSVD</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIF</name>
<description>TIF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC4IF</name>
<description>CC4IF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC3IF</name>
<description>CC3IF</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC2IF</name>
<description>CC2IF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC1IF</name>
<description>CC1IF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIF</name>
<description>UIF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TIM2_MISSR</name>
<displayName>TIM2_MISSR</displayName>
<description>TIM interrupt missed register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4IM</name>
<description>CC4IM</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC3IM</name>
<description>CC3IM</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC2IM</name>
<description>CC2IM</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CC1IM</name>
<description>CC1IM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RSVD</name>
<description>RSVD</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TIM2_CR1</name>
<displayName>TIM2_CR1</displayName>
<description>control register 1</description>
<addressOffset>0x47FC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARBE</name>
<description>ARBE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>CMS</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>DIR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>OPM</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>URS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>UDIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>CEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_IER</name>
<displayName>TIM2_IER</displayName>
<description>TIM Interrupt Enable Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>TIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>CC4IE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>CC3IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>CC2IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>CC1IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>UIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CR2</name>
<displayName>TIM2_CR2</displayName>
<description>control register 1</description>
<addressOffset>0x4800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1S</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>MMS</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_SMCR</name>
<displayName>TIM2_SMCR</displayName>
<description>TIM slave Mode Control
register</description>
<addressOffset>0x4804</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>ETP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>ECE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>ETPS</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>ETF</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>MSM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>TS</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMS</name>
<description>SMS</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_EGR</name>
<displayName>TIM2_EGR</displayName>
<description>TIM event generation register</description>
<addressOffset>0x4810</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TG</name>
<description>TG</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>CC4G</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>CC3G</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>CC2G</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>CC1G</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>UG</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCMR1_Input</name>
<displayName>TIM2_CCMR1_Input</displayName>
<description>capture/compare mode register 1 (Input
mode)</description>
<addressOffset>0x4814</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>IC1PSC</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>IC1F</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>IC2PSC</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2F</name>
<description>IC2F</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCMR1_Output</name>
<displayName>TIM2_CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<alternateRegister>TIM2_CCMR1_Input</alternateRegister>
<addressOffset>0x4814</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCMR2_Input</name>
<displayName>TIM2_CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<addressOffset>0x4818</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>IC4F</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>IC4PSC</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>IC3F</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>IC3PSC</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCMR2_Output</name>
<displayName>TIM2_CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<alternateRegister>TIM2_CCMR2_Input</alternateRegister>
<addressOffset>0x4818</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCER</name>
<displayName>TIM2_CCER</displayName>
<description>TIM capture/compare enable
register</description>
<addressOffset>0x481C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4P</name>
<description>CC4P</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>CC4E</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>CC3P</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>CC3E</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>CC2P</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>CC2E</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>CC1P</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>CC1E</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CNT</name>
<displayName>TIM2_CNT</displayName>
<description>TIM counter register</description>
<addressOffset>0x4820</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_PSC</name>
<displayName>TIM2_PSC</displayName>
<description>TIM prescaler register</description>
<addressOffset>0x4824</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>PSC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_ARR</name>
<displayName>TIM2_ARR</displayName>
<description>TIM auto-reload register</description>
<addressOffset>0x4828</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>ARR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCR1</name>
<displayName>TIM2_CCR1</displayName>
<description>TIM capture/compare register 1</description>
<addressOffset>0x4830</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCR2</name>
<displayName>TIM2_CCR2</displayName>
<description>TIM capture/compare register 2</description>
<addressOffset>0x4834</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCR3</name>
<displayName>TIM2_CCR3</displayName>
<description>TIM capture/compare register 3</description>
<addressOffset>0x4838</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_CCR4</name>
<displayName>TIM2_CCR4</displayName>
<description>TIM capture/compare register 4</description>
<addressOffset>0x483C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>CCR</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM2_OR</name>
<displayName>TIM2_OR</displayName>
<description>TIM option register</description>
<addressOffset>0x484C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REMAPC4</name>
<description>REMAPC4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REMAPC3</name>
<description>REMAPC3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REMAPC2</name>
<description>REMAPC2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REMAPC1</name>
<description>REMAPC1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORRSVD</name>
<description>ORRSVD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKMSKEN</name>
<description>CLKMSKEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTRIGSEL</name>
<description>EXTRIGSEL</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC1</name>
<description>Serial controller 1</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000A808</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x205D</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SC1_IRQ</name>
<description>Serial Controller 1 Interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>SC1_ISR</name>
<displayName>SC1_ISR</displayName>
<description>Serial controller interrupt status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODB</name>
<description>TXULODB</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODA</name>
<description>TXULODA</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODB</name>
<description>RXULODB</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODA</name>
<description>RXULODA</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDFIN</name>
<description>CMDFIN</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTF</name>
<description>BTF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRF</name>
<description>BRF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>UDR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>OVR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_IER</name>
<displayName>SC1_IER</displayName>
<description>Serial controller interrupt enable
register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEIE</name>
<description>PEIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIE</name>
<description>FEIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODBIE</name>
<description>TXULODBIE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODAIE</name>
<description>TXULODAIE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODBIE</name>
<description>RXULODBIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODAIE</name>
<description>RXULODAIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>NACKIE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDFINIE</name>
<description>CMDFINIE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTFIE</name>
<description>BTFIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRFIE</name>
<description>BRFIE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRIE</name>
<description>UDRIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>OVRIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLEIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>TXEIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNEIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_ICR</name>
<displayName>SC1_ICR</displayName>
<description>Serial controller interrupt control
register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLELEVEL</name>
<description>IDLELEVEL</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXELEVEL</name>
<description>TXELEVEL</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNELEVEL</name>
<description>RXNELEVEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DR</name>
<displayName>SC1_DR</displayName>
<description>Serial control Data register</description>
<addressOffset>0x2034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>DR</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_CR</name>
<displayName>SC1_CR</displayName>
<description>Serial controller control
register</description>
<addressOffset>0x204C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>MODE</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_CRR1</name>
<displayName>SC1_CRR1</displayName>
<description>Serial controller clock rate
register</description>
<addressOffset>0x2058</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LIN</name>
<description>LIN</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_CRR2</name>
<displayName>SC1_CRR2</displayName>
<description>Serial controller clock rate register
2</description>
<addressOffset>0x205C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXP</name>
<description>EXP</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC2</name>
<description>Serial controller 2</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000A80C</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1859</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SC2_IRQ</name>
<description>Serial Controller 2 Interrupt</description>
<value>6</value>
</interrupt>
<registers>
<register>
<name>SC2_ISR</name>
<displayName>SC2_ISR</displayName>
<description>Serial controller interrupt status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODB</name>
<description>TXULODB</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODA</name>
<description>TXULODA</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODB</name>
<description>RXULODB</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODA</name>
<description>RXULODA</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDFIN</name>
<description>CMDFIN</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTF</name>
<description>BTF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRF</name>
<description>BRF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>UDR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>OVR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_IER</name>
<displayName>SC2_IER</displayName>
<description>Serial controller interrupt enable
register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEIE</name>
<description>PEIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIE</name>
<description>FEIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODBIE</name>
<description>TXULODBIE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXULODAIE</name>
<description>TXULODAIE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODBIE</name>
<description>RXULODBIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXULODAIE</name>
<description>RXULODAIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>NACKIE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDFINIE</name>
<description>CMDFINIE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTFIE</name>
<description>BTFIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRFIE</name>
<description>BRFIE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRIE</name>
<description>UDRIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>OVRIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLEIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>TXEIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNEIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_ICR</name>
<displayName>SC2_ICR</displayName>
<description>Serial controller interrupt control
register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLELEVEL</name>
<description>IDLELEVEL</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXELEVEL</name>
<description>TXELEVEL</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNELEVEL</name>
<description>RXNELEVEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DR</name>
<displayName>SC2_DR</displayName>
<description>Serial controller data
register</description>
<addressOffset>0x1830</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>DR</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_CR</name>
<displayName>SC2_CR</displayName>
<description>Serial controller control
register</description>
<addressOffset>0x1848</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>MODE</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_CRR1</name>
<displayName>SC2_CRR1</displayName>
<description>Serial controller clock rate register
1</description>
<addressOffset>0x1854</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LIN</name>
<description>LIN</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_CRR2</name>
<displayName>SC2_CRR2</displayName>
<description>Serial controller clock rate register
2</description>
<addressOffset>0x1858</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXP</name>
<description>EXP</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC</name>
<description>Analog to Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x4000A810</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x2815</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC_IRQ</name>
<description>ADC Interrupt</description>
<value>11</value>
</interrupt>
<registers>
<register>
<name>ADC_ISR</name>
<displayName>ADC_ISR</displayName>
<description>ADC interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAOVF</name>
<description>DMAOVF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAT</name>
<description>SAT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMABF</name>
<description>DMABF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMABHF</name>
<description>DMABHF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_IER</name>
<displayName>ADC_IER</displayName>
<description>ADC interrupt enable register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAOVFIE</name>
<description>DMAOVFIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SATIE</name>
<description>SATIE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMABFIE</name>
<description>DMABFIE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMABHFIE</name>
<description>DMABHFIE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_CR</name>
<displayName>ADC_CR</displayName>
<description>ADC control register</description>
<addressOffset>0x27F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00001800</resetValue>
<fields>
<field>
<name>SMP</name>
<description>SMP</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>HVSELP</name>
<description>HVSELP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HVSELN</name>
<description>HVSELN</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHSELP</name>
<description>CHSELP</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHSELN</name>
<description>CHSELN</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLK</name>
<description>CLK</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADON</name>
<description>ADON</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_OFFSETR</name>
<displayName>ADC_OFFSETR</displayName>
<description>ADC offset register</description>
<addressOffset>0x27F8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET</name>
<description>OFFSET</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_GAINR</name>
<displayName>ADC_GAINR</displayName>
<description>ADC gain register</description>
<addressOffset>0x27FC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00008000</resetValue>
<fields>
<field>
<name>GAIN</name>
<description>GAIN</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_DMACR</name>
<displayName>ADC_DMACR</displayName>
<description>ADC DMA control register</description>
<addressOffset>0x2800</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RST</name>
<description>Write 1 to reset the ADC
DMA</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>AUTOWRAP</name>
<description>Selects DMA mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOAD</name>
<description>Loads the DMA buffer</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADC_DMASR</name>
<displayName>ADC_DMASR</displayName>
<description>ADC DMA status register</description>
<addressOffset>0x2804</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AOVF</name>
<description>AOVF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACT</name>
<description>ACT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_DMAMSAR</name>
<displayName>ADC_DMAMSAR</displayName>
<description>ADC DMA memory start address
register</description>
<addressOffset>0x2808</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>MSA</name>
<description>MSA</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_DMANDTR</name>
<displayName>ADC_DMANDTR</displayName>
<description>ADC DMA number of data to transfer
register</description>
<addressOffset>0x280C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>NDT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_DMAMNAR</name>
<displayName>ADC_DMAMNAR</displayName>
<description>ADC DMA memory next address
register</description>
<addressOffset>0x2810</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>MNA</name>
<description>MNA</description>
<bitOffset>1</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_DMACNDTR</name>
<displayName>ADC_DMACNDTR</displayName>
<description>ADC DMA count number of data transferred
register</description>
<addressOffset>0x2814</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNDT</name>
<description>CNDT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EXTI</name>
<description>External interrupt/event
controller</description>
<groupName>EXTI</groupName>
<baseAddress>0x4000A814</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1405</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EXTIA_IRQ</name>
<description>EXTI port A interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>EXTIB_IRQ</name>
<description>EXTI port B interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>EXTIC_IRQ</name>
<description>EXTI port C interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>EXTID_IRQ</name>
<description>EXTI port D interrupt</description>
<value>15</value>
</interrupt>
<registers>
<register>
<name>EXTI_PR</name>
<displayName>EXTI_PR</displayName>
<description>EXTI pending register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>EXTIA_TSR</name>
<displayName>EXTIA_TSR</displayName>
<description>EXTIA trigger source register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FILTEN</name>
<description>FILTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTMOD</name>
<description>INTMOD</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTIB_TSR</name>
<displayName>EXTIB_TSR</displayName>
<description>EXTIB trigger source register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FILTEN</name>
<description>FILTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTMOD</name>
<description>INTMOD</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTIC_TSR</name>
<displayName>EXTIC_TSR</displayName>
<description>EXTIC trigger source register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FILTEN</name>
<description>FILTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTMOD</name>
<description>INTMOD</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTIC_CR</name>
<displayName>EXTIC_CR</displayName>
<description>EXTIC configuration register</description>
<addressOffset>0x1400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000000F</resetValue>
<fields>
<field>
<name>GPIO_SEL</name>
<description>GPIO_SEL</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTID_TSR</name>
<displayName>EXTID_TSR</displayName>
<description>EXTID trigger source register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FILTEN</name>
<description>FILTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTMOD</name>
<description>INTMOD</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTID_CR</name>
<displayName>EXTID_CR</displayName>
<description>EXTID configuration register</description>
<addressOffset>0x1404</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>GPIO_SEL</name>
<description>GPIO_SEL</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x4000B000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>GPIOA_CRL</name>
<displayName>GPIOA_CRL</displayName>
<description>Port A configuration register
(Low)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE3</name>
<description>CNFMODE3</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE2</name>
<description>CNFMODE2</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE1</name>
<description>CNFMODE1</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE0</name>
<description>CNFMODE0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOA_CRH</name>
<displayName>GPIOA_CRH</displayName>
<description>Port A configuration register
(High)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE7</name>
<description>CNFMODE7</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE6</name>
<description>CNFMODE6</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE5</name>
<description>CNFMODE5</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE4</name>
<description>CNFMODE4</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOA_IDR</name>
<displayName>GPIOA_IDR</displayName>
<description>Port A input data register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR7</name>
<description>IDR7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>IDR6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>IDR5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>IDR4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>IDR3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>IDR2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>IDR1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>IDR0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOA_ODR</name>
<displayName>GPIOA_ODR</displayName>
<description>Port A output data register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR7</name>
<description>ODR7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>ODR6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>ODR5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>ODR4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>ODR3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>ODR2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>ODR1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>ODR0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOA_BSR</name>
<displayName>GPIOA_BSR</displayName>
<description>Port A bit set register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BS7</name>
<description>BS7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>BS6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>BS5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>BS4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>BS3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>BS2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>BS1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>BS0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOA_BRR</name>
<displayName>GPIOA_BRR</displayName>
<description>Port A output clear register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR7</name>
<description>BR7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>BR6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>BR5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>BR4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>BR3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>BR2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>BR1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>BR0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x4000B400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>GPIOB_CRL</name>
<displayName>GPIOB_CRL</displayName>
<description>Port B configuration register
(Low)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE3</name>
<description>CNFMODE3</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE2</name>
<description>CNFMODE2</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE1</name>
<description>CNFMODE1</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE0</name>
<description>CNFMODE0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOB_CRH</name>
<displayName>GPIOB_CRH</displayName>
<description>Port B configuration register
(High)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE7</name>
<description>CNFMODE7</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE6</name>
<description>CNFMODE6</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE5</name>
<description>CNFMODE5</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE4</name>
<description>CNFMODE4</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOB_IDR</name>
<displayName>GPIOB_IDR</displayName>
<description>Port B input data register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ID7</name>
<description>ID7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID6</name>
<description>ID6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID5</name>
<description>ID5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID4</name>
<description>ID4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID3</name>
<description>ID3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID2</name>
<description>ID2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID1</name>
<description>ID1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID0</name>
<description>ID0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOB_ODR</name>
<displayName>GPIOB_ODR</displayName>
<description>Port B output data register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OD7</name>
<description>OD7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD6</name>
<description>OD6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD5</name>
<description>OD5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD4</name>
<description>OD4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD3</name>
<description>OD3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD2</name>
<description>OD2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD1</name>
<description>OD1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD0</name>
<description>OD0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOB_BSR</name>
<displayName>GPIOB_BSR</displayName>
<description>Port B bit set register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BS7</name>
<description>BS7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>BS6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>BS5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>BS4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>BS3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>BS2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>BS1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>BS0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOB_BRR</name>
<displayName>GPIOB_BRR</displayName>
<description>Port B output clear register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR7</name>
<description>BR7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>BR6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>BR5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>BR4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>BR3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>BR2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>BR1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>BR0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOC</name>
<description>General purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x4000B800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>GPIOC_CRL</name>
<displayName>GPIOC_CRL</displayName>
<description>Port C configuration register
(Low)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE3</name>
<description>CNFMODE3</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE2</name>
<description>CNFMODE2</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE1</name>
<description>CNFMODE1</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE0</name>
<description>CNFMODE0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOC_CRH</name>
<displayName>GPIOC_CRH</displayName>
<description>Port C configuration register
(High)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00004444</resetValue>
<fields>
<field>
<name>CNFMODE7</name>
<description>CNFMODE7</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE6</name>
<description>CNFMODE6</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE5</name>
<description>CNFMODE5</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CNFMODE4</name>
<description>CNFMODE4</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOC_IDR</name>
<displayName>GPIOC_IDR</displayName>
<description>Port C input data register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ID7</name>
<description>ID7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID6</name>
<description>ID6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID5</name>
<description>ID5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID4</name>
<description>ID4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID3</name>
<description>ID3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID2</name>
<description>ID2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID1</name>
<description>ID1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID0</name>
<description>ID0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOC_ODR</name>
<displayName>GPIOC_ODR</displayName>
<description>Port C output data register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OD7</name>
<description>OD7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD6</name>
<description>OD6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD5</name>
<description>OD5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD4</name>
<description>OD4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD3</name>
<description>OD3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD2</name>
<description>OD2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD1</name>
<description>OD1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD0</name>
<description>OD0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOC_BSR</name>
<displayName>GPIOC_BSR</displayName>
<description>Port B bit set register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BS7</name>
<description>BS7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>BS6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>BS5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>BS4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>BS3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>BS2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>BS1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>BS0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIOC_BRR</name>
<displayName>GPIOC_BRR</displayName>
<description>Port C output clear register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR7</name>
<description>BR7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>BR6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>BR5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>BR4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>BR3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>BR2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>BR1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>BR0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIO_DBG</name>
<description>General purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x40004028</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x7BDD</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>GPIO_DBGCR</name>
<displayName>GPIO_DBGCR</displayName>
<description>GPIO debug configuration
register</description>
<addressOffset>0x7BD8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>DBGDIS</name>
<description>DBGDIS</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTREGEN</name>
<description>EXTREGEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO_DBGSR</name>
<displayName>GPIO_DBGSR</displayName>
<description>GPIO debug status register</description>
<addressOffset>0x7BDC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BOOTMODE</name>
<description>BOOTMODE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCEDBG</name>
<description>FORCEDBG</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEN</name>
<description>SWEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO_PCTRACECR</name>
<displayName>GPIO_PCTRACECR</displayName>
<description>Clock PC trace register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEL</name>
<description>selects PC_TRACE source on bb_debug GPIO
pins</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDG</name>
<description>Watchdog timer</description>
<groupName>WDG</groupName>
<baseAddress>0x40006000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>WDG_CR</name>
<displayName>WDG_CR</displayName>
<description>WDG configuration register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>WDGDIS</name>
<description>WDGDIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDGEN</name>
<description>WDGEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDG_KR</name>
<displayName>WDG_KR</displayName>
<description>WDG key register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>KEY</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDG_KICKSR</name>
<displayName>WDG_KICKSR</displayName>
<description>WDG kick-start register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KS</name>
<description>KS</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CLK</name>
<description>Clock</description>
<groupName>CLK</groupName>
<baseAddress>0x40000008</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x4025</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CLK_SLEEPCR</name>
<displayName>CLK_SLEEPCR</displayName>
<description>Sleep timer control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>LSEEN</name>
<description>Enables 32kHz external
XTAL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSI10KEN</name>
<description>Enables 10kHz internal RC during
deep</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_LSI10KCR</name>
<displayName>CLK_LSI10KCR</displayName>
<description>LSI Clock (10KHz) control
register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TUNE</name>
<description>Tune value for clkrc</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_LSI1KCR</name>
<displayName>CLK_LSI1KCR</displayName>
<description>LSI Clock (1KHz) control
register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00005000</resetValue>
<fields>
<field>
<name>CLKFRAC</name>
<description>Divider value fractional
portion</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>CALINT</name>
<description>Divider value integer
portion</description>
<bitOffset>11</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_HSECR1</name>
<displayName>CLK_HSECR1</displayName>
<description>HSE Clock (24MHz) control register
1</description>
<addressOffset>0x3FFC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000000F</resetValue>
<fields>
<field>
<name>BIASTRIM</name>
<description>Bias trim setting for 24MHz
oscillator</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_HSICR</name>
<displayName>CLK_HSICR</displayName>
<description>HSI Clock (12MHz) trim
register</description>
<addressOffset>0x4000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000017</resetValue>
<fields>
<field>
<name>TUNE</name>
<description>Frequency trim setting for HF RC
oscillator</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_PERIODCR</name>
<displayName>CLK_PERIODCR</displayName>
<description>Clock period control register</description>
<addressOffset>0x4008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>MODE</name>
<description>Sets clock to be measured by
CLK_PERIOD</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_PERIODSR</name>
<displayName>CLK_PERIODSR</displayName>
<description>Clock period status register</description>
<addressOffset>0x400C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERIOD</name>
<description>Clock period measurement</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_DITHERCR</name>
<displayName>CLK_DITHERCR</displayName>
<description>Clock dither control register</description>
<addressOffset>0x4010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIS</name>
<description>Dither disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_HSECR2</name>
<displayName>CLK_HSECR2</displayName>
<description>HSE Clock (24MHz) control register
2</description>
<addressOffset>0x4014</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SW1</name>
<description>OSCHF/XTAL is selected</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>MHz crystal oscillator is main
clock</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_CPUCR</name>
<displayName>CLK_CPUCR</displayName>
<description>Clock source select register</description>
<addressOffset>0x4018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SW2</name>
<description>12MHz/24MHz is selected</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RST</name>
<description>Reset event</description>
<groupName>RST</groupName>
<baseAddress>0x4000002C</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>RST_SR</name>
<displayName>RST_SR</displayName>
<description>Reset Status Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>LKUP</name>
<description>LKUP</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OBFAIL</name>
<description>OBFAIL</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUP</name>
<description>WKUP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWRST</name>
<description>SWRST</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDG</name>
<description>WDG</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIN</name>
<description>PIN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWRLV</name>
<description>PWRLV</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWRHV</name>
<description>PWRHV</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASH</name>
<description>FLASH</description>
<groupName>FLASH</groupName>
<baseAddress>0x4000402C</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x43D4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FLASH_ACR</name>
<displayName>FLASH_ACR</displayName>
<description>FLASH access control register</description>
<addressOffset>0x3FD4</addressOffset>
<size>32</size>
<resetValue>0x00000031</resetValue>
<fields>
<field>
<name>PRFTBS</name>
<description>Prefetch Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRFTBE</name>
<description>PRFTBE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HLFCYA</name>
<description>HLFCYA</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LATENCY</name>
<description>LATENCY</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLASH_KEYR</name>
<displayName>FLASH_KEYR</displayName>
<description>FLASH key register</description>
<addressOffset>0x3FD8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FKEYR</name>
<description>FKEYR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_OPTKEYR</name>
<displayName>FLASH_OPTKEYR</displayName>
<description>FLASH OPT key register</description>
<addressOffset>0x3FDC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>OPTKEYR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_SR</name>
<displayName>FLASH_SR</displayName>
<description>FLASH status register</description>
<addressOffset>0x3FE0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>EOP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WRPRTERR</name>
<description>WRPRTERR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGERR</name>
<description>PGERR</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BSY</name>
<description>BSY</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>FLASH_CR</name>
<displayName>FLASH_CR</displayName>
<description>FLASH control register</description>
<addressOffset>0x3FE4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>EOPIE</name>
<description>EOPIE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>ERRIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTWRE</name>
<description>OPTWRE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>LOCK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT</name>
<description>STRT</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTER</name>
<description>OPTER</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTPG</name>
<description>OPTPG</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>MER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PG</name>
<description>PG</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_AR</name>
<displayName>FLASH_AR</displayName>
<description>FLASH address register</description>
<addressOffset>0x3FE8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FAR</name>
<description>FAR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_OBR</name>
<displayName>FLASH_OBR</displayName>
<description>FLASH option bytes register</description>
<addressOffset>0x3FF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x03FFFFFC</resetValue>
<fields>
<field>
<name>RDPRT</name>
<description>RDPRT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTERR</name>
<description>OPTERR</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_WRPR</name>
<displayName>FLASH_WRPR</displayName>
<description>FLASH write protection
register</description>
<addressOffset>0x3FF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>WRP</name>
<description>WRP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_CLKER</name>
<displayName>FLASH_CLKER</displayName>
<description>FLASH controller clock enable
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLASH_CLKSR</name>
<displayName>FLASH_CLKSR</displayName>
<description>FLASH controller clock status
register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BSY</name>
<description>BSY</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SLPTMR</name>
<description>Sleep timer</description>
<groupName>SLPTMR</groupName>
<baseAddress>0x4000600C</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x4049</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SLPTIM_IRQ</name>
<description>Sleep Timer Interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>SLPTMR_CR</name>
<displayName>SLPTMR_CR</displayName>
<description>SLPTMR configuration register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000400</resetValue>
<fields>
<field>
<name>REVERSE</name>
<description>REVERSE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBGP</name>
<description>DBGP</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSC</name>
<description>PSC</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKSEL</name>
<description>CLKSEL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CNTH</name>
<displayName>SLPTMR_CNTH</displayName>
<description>SLPTMR counter high register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTH</name>
<description>CNTH</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CNTL</name>
<displayName>SLPTMR_CNTL</displayName>
<description>SLPTMR counter high register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTL</name>
<description>CNTL</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CMPAH</name>
<displayName>SLPTMR_CMPAH</displayName>
<description>SLPTMR compare A high register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>CMPAH</name>
<description>CMPAH</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CMPAL</name>
<displayName>SLPTMR_CMPAL</displayName>
<description>SLPTMR compare A low register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>CMPAL</name>
<description>CMPAL</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CMPBH</name>
<displayName>SLPTMR_CMPBH</displayName>
<description>SLPTMR compare B high register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>CMPBH</name>
<description>CMPBH</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_CMPBL</name>
<displayName>SLPTMR_CMPBL</displayName>
<description>SLPTMR compare B low register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>CMPBL</name>
<description>CMPBL</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_ISR</name>
<displayName>SLPTMR_ISR</displayName>
<description>SLPTMR interrupt status
register</description>
<addressOffset>0x4008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMPB</name>
<description>CMPB</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPA</name>
<description>CMPA</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OW</name>
<description>OW</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_IFR</name>
<displayName>SLPTMR_IFR</displayName>
<description>SLPTMR force interrupts
register</description>
<addressOffset>0x4014</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMPB</name>
<description>CMPB</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPA</name>
<description>CMPA</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OW</name>
<description>OW</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLPTMR_IER</name>
<displayName>SLPTMR_IER</displayName>
<description>SLPTMR interrupt enable
register</description>
<addressOffset>0x4048</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRAP</name>
<description>WRAP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPA</name>
<description>CMPA</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPB</name>
<description>CMPB</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWR</name>
<description>Power control</description>
<groupName>PWR</groupName>
<baseAddress>0x40000004</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xBC19</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PWR_DSLEEPCR1</name>
<displayName>PWR_DSLEEPCR1</displayName>
<description>PWR_DSLEEPCR1</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWR_CSYSPWRUPACKCR</name>
<description>PWR_CSYSPWRUPACKCR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_DSLEEPCR2</name>
<displayName>PWR_DSLEEPCR2</displayName>
<description>PWR_DSLEEPCR2</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>MODE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_VREGCR</name>
<displayName>PWR_VREGCR</displayName>
<description>Voltage regulator Control
register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000207</resetValue>
<fields>
<field>
<name>PWR_VREGCR_1V2TRIM</name>
<description>1V2 regulator trim value</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PWR_VREGCR_1V2EN</name>
<description>1V2 direct controle of regulator
on/off</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWR_VREGCR_1V8TRIM</name>
<description>1V8 regulator trim value</description>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PWR_VREGCR_1V8EN</name>
<description>1V8 direct controle of regulator
on/off</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWR_VREGCR_VREFEN</name>
<description>VREF on/off</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKECR1</name>
<displayName>PWR_WAKECR1</displayName>
<description>PWR_WAKECR1</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>WAKEEN</name>
<description>WAKEEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC1</name>
<description>SC1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC2</name>
<description>SC2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRQD</name>
<description>IRQD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPA</name>
<description>COMPA</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPB</name>
<description>COMPB</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRAP</name>
<description>WRAP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CORE</name>
<description>CORE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPWRRUPREQ</name>
<description>CPWRRUPREQ</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSYSPWRUPREQ</name>
<description>CSYSPWRUPREQ</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKECR2</name>
<displayName>PWR_WAKECR2</displayName>
<description>PWR_WAKECR2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COREWAKE</name>
<description>COREWAKE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKESR</name>
<displayName>PWR_WAKESR</displayName>
<description>PWR_WAKESR</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GPIOPIN</name>
<description>GPIOPIN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC1</name>
<description>SC1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC2</name>
<description>SC2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRQD</name>
<description>IRQD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPA</name>
<description>COMPA</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMPB</name>
<description>COMPB</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRAP</name>
<description>WRAP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CORE</name>
<description>CORE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPWRRUPREQ</name>
<description>CPWRRUPREQ</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSYSPWRUPREQ</name>
<description>CSYSPWRUPREQ</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CPWRUPREQSR</name>
<displayName>PWR_CPWRUPREQSR</displayName>
<description>PWR_CPWRUPREQSR</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REQ</name>
<description>REQ</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CSYSPWRUPREQSR</name>
<displayName>PWR_CSYSPWRUPREQSR</displayName>
<description>PWR_CSYSPWRUPREQSR</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REQ</name>
<description>REQ</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CSYSPWRUPACKSR</name>
<displayName>PWR_CSYSPWRUPACKSR</displayName>
<description>PWR_CSYSPWRUPACKSR</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CSYSPWRUPACKCR</name>
<displayName>PWR_CSYSPWRUPACKCR</displayName>
<description>PWR_CSYSPWRUPACKCR</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INHIBIT</name>
<description>INHIBIT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKEPAR</name>
<displayName>PWR_WAKEPAR</displayName>
<description>Wake GPIO Port A register</description>
<addressOffset>0xBC04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA0</name>
<description>PA0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA1</name>
<description>PA1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA2</name>
<description>PA2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA3</name>
<description>PA3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA4</name>
<description>PA4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA5</name>
<description>PA5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA6</name>
<description>PA6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA7</name>
<description>PA7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKEPBR</name>
<displayName>PWR_WAKEPBR</displayName>
<description>Wake GPIO Port B register</description>
<addressOffset>0xBC08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PB0</name>
<description>PB0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB1</name>
<description>PB1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB2</name>
<description>PB2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB3</name>
<description>PB3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB4</name>
<description>PB4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB5</name>
<description>PB5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB6</name>
<description>PB6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB7</name>
<description>PB7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKEPCR</name>
<displayName>PWR_WAKEPCR</displayName>
<description>Wake GPIO Port C register</description>
<addressOffset>0xBC0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PC0</name>
<description>PC0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC1</name>
<description>PC1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC2</name>
<description>PC2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC3</name>
<description>PC3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC4</name>
<description>PC4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC5</name>
<description>PC5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC6</name>
<description>PC6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC7</name>
<description>PC7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WAKEFILTR</name>
<displayName>PWR_WAKEFILTR</displayName>
<description>Wake filter register</description>
<addressOffset>0xBC18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GPIO</name>
<description>Enable filter on GPIO wakeup sources
enabled by the PWR_WAKEPxR registers</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC1</name>
<description>Enable filter on GPIO wakeup source SC1
(PB2)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SC2</name>
<description>Enable filter on GPIO wakeup source SC2
(PA2)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRQD</name>
<description>Enable filter on GPIO wakeup source EXTI
D</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt
Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1001</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ICTR</name>
<displayName>ICTR</displayName>
<description>Interrupt Controller Type
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTLINESNUM</name>
<description>Total number of interrupt lines in
groups</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software Triggered Interrupt
Register</description>
<addressOffset>0xF00</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>interrupt to be triggered</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x280</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x400</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x404</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x408</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x40C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x410</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MEM</name>
<description>Memory Control registers</description>
<groupName>RAM</groupName>
<baseAddress>0x40005000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x29</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>RAMPROTR1</name>
<displayName>RAMPROTR1</displayName>
<description>Memory protection register1</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT1</name>
<description>RAMPROT1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR2</name>
<displayName>RAMPROTR2</displayName>
<description>Memory protection register2</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT2</name>
<description>RAMPROT2</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR3</name>
<displayName>RAMPROTR3</displayName>
<description>Memory protection register3</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT3</name>
<description>RAMPROT1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR4</name>
<displayName>RAMPROTR4</displayName>
<description>Memory protection register4</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT4</name>
<description>RAMPROT4</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR5</name>
<displayName>RAMPROTR5</displayName>
<description>Memory protection register5</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT5</name>
<description>RAMPROT5</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR6</name>
<displayName>RAMPROTR6</displayName>
<description>Memory protection register6</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT6</name>
<description>RAMPROT6</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR7</name>
<displayName>RAMPROTR7</displayName>
<description>Memory protection register7</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT7</name>
<description>RAMPROT7</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMPROTR8</name>
<displayName>RAMPROTR8</displayName>
<description>Memory protection register8</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RAMPROT8</name>
<description>RAMPROT8</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAPROTR1</name>
<displayName>DMAPROTR1</displayName>
<description>DMA protection register1</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>DMA protection fault, faulting
address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>OFFSET</name>
<description>offset in RAM</description>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAPROTR2</name>
<displayName>DMAPROTR2</displayName>
<description>DMA protection register2</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHANNEL</name>
<description>DMA protection fault, faulting
channel</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAMCR</name>
<displayName>RAMCR</displayName>
<description>Memory configuration register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WEN</name>
<description>Makes all RAM write access</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC1_DMA</name>
<description>Serial controller 1 (Direct memory
access)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x71</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC1_DMARXBEGADDAR</name>
<displayName>SC1_DMARXBEGADDAR</displayName>
<description>Serial controller receive DMA begin address
channel A register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXENDADDAR</name>
<displayName>SC1_DMARXENDADDAR</displayName>
<description>Serial controller receive DMA end address
channel A register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXBEGADDBR</name>
<displayName>SC1_DMARXBEGADDBR</displayName>
<description>Serial controller receive DMA begin address
channel B register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXENDADDBR</name>
<displayName>SC1_DMARXENDADDBR</displayName>
<description>Serial controller receive DMA end address
channel B register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMATXBEGADDAR</name>
<displayName>SC1_DMATXBEGADDAR</displayName>
<description>Serial controller transmit DMA begin address
channel A register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMATXENDADDAR</name>
<displayName>SC1_DMATXENDADDAR</displayName>
<description>Serial controller transmit DMA end address
channel A register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMATXBEGADDBR</name>
<displayName>SC1_DMATXBEGADDBR</displayName>
<description>Serial controller transmit DMA begin address
channel B register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMATXENDADDBR</name>
<displayName>SC1_DMATXENDADDBR</displayName>
<description>Serial controller transmit DMA end address
channel B</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXCNTAR</name>
<displayName>SC1_DMARXCNTAR</displayName>
<description>Serial controller receive DMA counter
channel A register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXCNTBR</name>
<displayName>SC1_DMARXCNTBR</displayName>
<description>Serial controller receive DMA count channel
B register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMATXCNTR</name>
<displayName>SC1_DMATXCNTR</displayName>
<description>Serial controller transmit DMA counter
register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMASR</name>
<displayName>SC1_DMASR</displayName>
<description>Serial controller DMA status
register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NSSS</name>
<description>NSSS</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FEB</name>
<description>FEB</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEA</name>
<description>FEA</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEB</name>
<description>PEB</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>PEA</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRB</name>
<description>OVRB</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRA</name>
<description>OVRA</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBACK</name>
<description>TXBACK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXAACK</name>
<description>TXAACK</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBACK</name>
<description>RXBACK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXAACK</name>
<description>RXAACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMACR</name>
<displayName>SC1_DMACR</displayName>
<description>Serial controller DMA control
register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXRST</name>
<description>TXRST</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXRST</name>
<description>RXRST</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXLODB</name>
<description>TXLODB</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXLODA</name>
<description>TXLODA</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXLODB</name>
<description>RXLODB</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXLODA</name>
<description>RXLODA</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXERRAR</name>
<displayName>SC1_DMARXERRAR</displayName>
<description>Serial controller receive DMA channel A
first error register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXERRBR</name>
<displayName>SC1_DMARXERRBR</displayName>
<description>Serial controller receive DMA channel B
first error register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_DMARXCNTSAVEDR</name>
<displayName>SC1_DMARXCNTSAVEDR</displayName>
<description>Serial controller receive DMA saved counter
channel B register</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC1_UART</name>
<description>Serial controller 1 (Universal Asynchronous
Receiver/Transmitter)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C848</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x25</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC1_UARTSR</name>
<displayName>SC1_UARTSR</displayName>
<description>Serial controller UART status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>OVR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_UARTCR</name>
<displayName>SC1_UARTCR</displayName>
<description>Serial controller UART control
register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHFCE</name>
<description>AHFCE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFCE</name>
<description>HFCE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>PS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>PCE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M</name>
<description>M</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRTS</name>
<description>nRTS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_UARTBRR1</name>
<displayName>SC1_UARTBRR1</displayName>
<description>Serial controller UART baud rate register
1</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>N</name>
<description>N</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_UARTBRR2</name>
<displayName>SC1_UARTBRR2</displayName>
<description>Serial controller UART baud rate register
2</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F</name>
<description>F</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC1_I2C</name>
<description>Serial controller 1 (Serial peripheral
interface)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C844</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC1_I2CSR</name>
<displayName>SC1_I2CSR</displayName>
<description>Serial controller I2C status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMDFIN</name>
<description>CMDFIN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRF</name>
<description>BRF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTF</name>
<description>BTF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_I2CCR1</name>
<displayName>SC1_I2CCR1</displayName>
<description>Serial controller I2C control register
1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STOP</name>
<description>STOP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTE</name>
<description>BTE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRE</name>
<description>BRE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_I2CCR2</name>
<displayName>SC1_I2CCR2</displayName>
<description>Serial controller I2C control register
2</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC1_SPI</name>
<description>Serial controller 1 (Serial peripheral
interface)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C840</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x19</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC1_SPISR</name>
<displayName>SC1_SPISR</displayName>
<description>Serial controller SPI status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVF</name>
<description>OVF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC1_SPICR</name>
<displayName>SC1_SPICR</displayName>
<description>Serial controller SPI control
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXMODE</name>
<description>RXMODE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTR</name>
<description>MSTR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPTEN</name>
<description>RPTEN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>LSBFIRST</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>CPHA</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>CPOL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC2_DMA</name>
<description>Serial controller 2 (Direct memory
access)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x71</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC2_DMARXBEGADDAR</name>
<displayName>SC2_DMARXBEGADDAR</displayName>
<description>Serial controller receive DMA begin address
channel A register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXENDADDAR</name>
<displayName>SC2_DMARXENDADDAR</displayName>
<description>Serial controller receive DMA end address
channel A register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXBEGADDBR</name>
<displayName>SC2_DMARXBEGADDBR</displayName>
<description>Serial controller receive DMA begin address
channel B register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXENDADDBR</name>
<displayName>SC2_DMARXENDADDBR</displayName>
<description>Serial controller receive DMA end address
channel B register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMATXBEGADDAR</name>
<displayName>SC2_DMATXBEGADDAR</displayName>
<description>Serial controller transmit DMA begin address
channel A register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMATXENDADDAR</name>
<displayName>SC2_DMATXENDADDAR</displayName>
<description>Serial controller transmit DMA end address
channel A register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMATXBEGADDBR</name>
<displayName>SC2_DMATXBEGADDBR</displayName>
<description>Serial controller transmit DMA begin address
channel B register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMATXENDADDBR</name>
<displayName>SC2_DMATXENDADDBR</displayName>
<description>Serial controller transmit DMA end address
channel B register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXCNTAR</name>
<displayName>SC2_DMARXCNTAR</displayName>
<description>Serial controller receive DMA counter
channel A register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXCNTBR</name>
<displayName>SC2_DMARXCNTBR</displayName>
<description>Serial controller receive DMA count channel
B register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMATXCNTR</name>
<displayName>SC2_DMATXCNTR</displayName>
<description>Serial controller transmit DMA counter
register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMASR</name>
<displayName>SC2_DMASR</displayName>
<description>Serial controller DMA status
register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NSSS</name>
<description>NSSS</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FEB</name>
<description>FEB</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEA</name>
<description>FEA</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEB</name>
<description>PEB</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>PEA</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRB</name>
<description>OVRB</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRA</name>
<description>OVRA</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBACK</name>
<description>TXBACK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXAACK</name>
<description>TXAACK</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBACK</name>
<description>RXBACK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXAACK</name>
<description>RXAACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMACR</name>
<displayName>SC2_DMACR</displayName>
<description>Serial controller DMA control
register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXRST</name>
<description>TXRST</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXRST</name>
<description>RXRST</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXLODB</name>
<description>TXLODB</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXLODA</name>
<description>TXLODA</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXLODB</name>
<description>RXLODB</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXLODA</name>
<description>RXLODA</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXERRAR</name>
<displayName>SC2_DMARXERRAR</displayName>
<description>Serial controller receive DMA channel A
first error register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXERRBR</name>
<displayName>SC2_DMARXERRBR</displayName>
<description>Serial controller receive DMA channel B
first error register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>ADD</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_DMARXCNTSAVEDR</name>
<displayName>SC2_DMARXCNTSAVEDR</displayName>
<description>Serial controller receive DMA saved counter
channel B register</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>CNT</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC2_I2C</name>
<description>Serial controller 2 (Serial peripheral
interface)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C044</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC2_I2CSR</name>
<displayName>SC2_I2CSR</displayName>
<description>Serial controller I2C status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMDFIN</name>
<description>CMDFIN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRF</name>
<description>BRF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTF</name>
<description>BTF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_I2CCR1</name>
<displayName>SC2_I2CCR1</displayName>
<description>Serial controller I2C control register
1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STOP</name>
<description>STOP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTE</name>
<description>BTE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRE</name>
<description>BRE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_I2CCR2</name>
<displayName>SC2_I2CCR2</displayName>
<description>Serial controller I2C control register
2</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SC2_SPI</name>
<description>Serial controller 2 (Serial peripheral
interface)</description>
<groupName>SerialControll</groupName>
<baseAddress>0x4000C040</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x19</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SC2_SPISR</name>
<displayName>SC2_SPISR</displayName>
<description>Serial controller SPI status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVF</name>
<description>OVF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SC2_SPICR</name>
<displayName>SC2_SPICR</displayName>
<description>Serial controller SPI control
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXMODE</name>
<description>RXMODE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTR</name>
<description>MSTR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPTEN</name>
<description>RPTEN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>LSBFIRST</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>CPHA</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>CPOL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MAC_TIM</name>
<description>MAC timer</description>
<groupName>TIM</groupName>
<baseAddress>0x40002038</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x55</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MAC_TIM_IRQ</name>
<description>MAC Timer Interrupt</description>
<value>8</value>
</interrupt>
<registers>
<register>
<name>MACTMR_CNTR</name>
<displayName>MACTMR_CNTR</displayName>
<description>MACTMR counter register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>MAC timer count</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>MACTMR_CR</name>
<displayName>MACTMR_CR</displayName>
<description>MACTMR configuration register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>MAC timer enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>MAC timer reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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