RMUL2025/lib/cmsis_svd/data/STMicro/STM32L15xxxA.svd

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"><name>STM32L15xxxA</name><version>1.0</version><description>STM32L15xxxA</description><!--Bus Interface Properties--><!--Cortex-M3 is byte addressable--><addressUnitBits>8</addressUnitBits><!--the maximum data bit width accessible within a single transfer--><width>32</width><!--Register Default Properties--><size>0x20</size><resetValue>0x0</resetValue><resetMask>0xFFFFFFFF</resetMask><peripherals><peripheral><name>C_ADC</name><description>Common ADC registers</description><groupName>ADC</groupName><baseAddress>0x40012700</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>CSR</name><displayName>CSR</displayName><description>ADC Common status register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>ADONS1</name><description>ADON Status of ADC</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>OVR1</name><description>Overrun flag of ADC 1</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>STRT1</name><description>Regular channel Start flag of ADC               1</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>JSTRT1</name><description>Injected channel Start flag of ADC               1</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>JEOC1</name><description>Injected channel end of conversion of               ADC 1</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>EOC1</name><description>End of conversion of ADC 1</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>AWD1</name><description>Analog watchdog flag of ADC               1</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCR</name><displayName>CCR</displayName><description>ADC common control register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>TSVREFE</name><description>Temperature sensor and VREFINT               enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>ADCPRE</name><description>ADC prescaler</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field></fields></register></registers></peripheral><peripheral><name>COMP</name><description>Comparators</description><groupName>COMP</groupName><baseAddress>0x40007C00</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>COMP_CA</name><description>Comparator wakeup through EXTI line (21 and
        22) interrupt/Channel acquisition interrupt</description><value>22</value></interrupt><interrupt><name>COMP_ACQ</name><description>Comparator Channel Acquisition</description><value>53</value></interrupt><registers><register><name>CSR</name><displayName>CSR</displayName><description>comparator control and status           register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>TSUSP</name><description>Suspend Timer Mode</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CAIF</name><description>Channel acquisition interrupt               flag</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>CAIE</name><description>Channel Acquisition Interrupt Enable /               Clear</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RCH13</name><description>Select GPIO port PC3 as re-routed ADC               input channel CH13.</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>FCH8</name><description>Select GPIO port PB0 as fast ADC input               channel CH8.</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>FCH3</name><description>Select GPIO port PA3 as fast ADC input               channel CH3.</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>OUTSEL</name><description>Comparator 2 output               selection</description><bitOffset>21</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>INSEL</name><description>Inverted input selection</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>WNDWE</name><description>Window mode enable</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>VREFOUTEN</name><description>VREFINT output enable</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CMP2OUT</name><description>Comparator 2 output</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>SPEED</name><description>Comparator 2 speed mode</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CMP1OUT</name><description>Comparator 1 output</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>SW1</name><description>SW1 analog switch enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CMP1EN</name><description>Comparator 1 enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PD400K</name><description>400 kO pull-down resistor</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PD10K</name><description>10 kO pull-down resistor</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PU400K</name><description>400 kO pull-up resistor</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PU10K</name><description>10 kO pull-up resistor</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register></registers></peripheral><peripheral><name>CRC</name><description>CRC calculation unit</description><groupName>CRC</groupName><baseAddress>0x40023000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>DR</name><displayName>DR</displayName><description>Data register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0xFFFFFFFF</resetValue><fields><field><name>Data_register</name><description>Data Register</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>IDR</name><displayName>IDR</displayName><description>Independent data register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>Independent_data_register</name><description>Independent data register</description><bitOffset>0</bitOffset><bitWidth>7</bitWidth></field></fields></register><register><name>CR</name><displayName>CR</displayName><description>Control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>RESET</name><description>RESET</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral><peripheral><name>DAC</name><description>Digital-to-analog converter</description><groupName>DAC</groupName><baseAddress>0x40007400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>DAC</name><description>DAC interrupt</description><value>21</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DMAUDRIE2</name><description>DAC channel2 DMA underrun interrupt               enable</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAEN2</name><description>DAC channel2 DMA enable</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>MAMP2</name><description>DAC channel2 mask/amplitude               selector</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>WAVE2</name><description>DAC channel2 noise/triangle wave               generation enable</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>TSEL2</name><description>DAC channel2 trigger               selection</description><bitOffset>19</bitOffset><bitWidth>3</bitWidth></field><field><name>TEN2</name><description>DAC channel2 trigger               enable</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>BOFF2</name><description>DAC channel2 output buffer               disable</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>EN2</name><description>DAC channel2 enable</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAUDRIE1</name><description>DAC channel1 DMA Underrun Interrupt               enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAEN1</name><description>DAC channel1 DMA enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>MAMP1</name><description>DAC channel1 mask/amplitude               selector</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>WAVE1</name><description>DAC channel1 noise/triangle wave               generation enable</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>TSEL1</name><description>DAC channel1 trigger               selection</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth></field><field><name>TEN1</name><description>DAC channel1 trigger               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>BOFF1</name><description>DAC channel1 output buffer               disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN1</name><description>DAC channel1 enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SWTRIGR</name><displayName>SWTRIGR</displayName><description>software trigger register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>SWTRIG2</name><description>DAC channel2 software               trigger</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>SWTRIG1</name><description>DAC channel1 software               trigger</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DHR12R1</name><displayName>DHR12R1</displayName><description>channel1 12-bit right-aligned data holding           register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC1DHR</name><description>DAC channel1 12-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR12L1</name><displayName>DHR12L1</displayName><description>channel1 12-bit left aligned data holding           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC1DHR</name><description>DAC channel1 12-bit left-aligned               data</description><bitOffset>4</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR8R1</name><displayName>DHR8R1</displayName><description>channel1 8-bit right aligned data holding           register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC1DHR</name><description>DAC channel1 8-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>DHR12R2</name><displayName>DHR12R2</displayName><description>channel2 12-bit right aligned data holding           register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 12-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR12L2</name><displayName>DHR12L2</displayName><description>channel2 12-bit left aligned data holding           register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 12-bit left-aligned               data</description><bitOffset>4</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR8R2</name><displayName>DHR8R2</displayName><description>channel2 8-bit right-aligned data holding           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 8-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>DHR12RD</name><displayName>DHR12RD</displayName><description>Dual DAC 12-bit right-aligned data holding           register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 12-bit right-aligned               data</description><bitOffset>16</bitOffset><bitWidth>12</bitWidth></field><field><name>DACC1DHR</name><description>DAC channel1 12-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR12LD</name><displayName>DHR12LD</displayName><description>DUAL DAC 12-bit left aligned data holding           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 12-bit left-aligned               data</description><bitOffset>20</bitOffset><bitWidth>12</bitWidth></field><field><name>DACC1DHR</name><description>DAC channel1 12-bit left-aligned               data</description><bitOffset>4</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DHR8RD</name><displayName>DHR8RD</displayName><description>DUAL DAC 8-bit right aligned data holding           register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DHR</name><description>DAC channel2 8-bit right-aligned               data</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>DACC1DHR</name><description>DAC channel1 8-bit right-aligned               data</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>DOR1</name><displayName>DOR1</displayName><description>channel1 data output register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>DACC1DOR</name><description>DAC channel1 data output</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>DOR2</name><displayName>DOR2</displayName><description>channel2 data output register</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>DACC2DOR</name><description>DAC channel2 data output</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DMAUDR2</name><description>DAC channel2 DMA underrun               flag</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAUDR1</name><description>DAC channel1 DMA underrun               flag</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral><peripheral><name>DMA1</name><description>Direct memory access controller</description><groupName>DMA</groupName><baseAddress>0x40026000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>DMA1_Channel1</name><description>DMA1 Channel1 global interrupt</description><value>11</value></interrupt><interrupt><name>DMA1_Channel2</name><description>DMA1 Channel2 global interrupt</description><value>12</value></interrupt><interrupt><name>DMA1_Channel3</name><description>DMA1 Channel3 global interrupt</description><value>13</value></interrupt><interrupt><name>DMA1_Channel4</name><description>DMA1 Channel4 global interrupt</description><value>14</value></interrupt><interrupt><name>DMA1_Channel5</name><description>DMA1 Channel5 global interrupt</description><value>15</value></interrupt><interrupt><name>DMA1_Channel6</name><description>DMA1 Channel6 global interrupt</description><value>16</value></interrupt><interrupt><name>DMA1_Channel7</name><description>DMA1 Channel7 global interrupt</description><value>17</value></interrupt><registers><register><name>ISR</name><displayName>ISR</displayName><description>interrupt status register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>TEIF7</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF7</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF7</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF7</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF6</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF6</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF6</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF6</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF5</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF5</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF5</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF5</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF4</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF4</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF4</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF4</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF3</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF3</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF3</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF3</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF2</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF2</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF2</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF2</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF1</name><description>Channel x transfer error flag (x = 1               ..7)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF1</name><description>Channel x half transfer flag (x = 1               ..7)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF1</name><description>Channel x transfer complete flag (x = 1               ..7)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF1</name><description>Channel x global interrupt flag (x = 1               ..7)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>IFCR</name><displayName>IFCR</displayName><description>interrupt flag clear register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>CTEIF7</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF7</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF7</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF7</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF6</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF6</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF6</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF6</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF5</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF5</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF5</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF5</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF4</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF4</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF4</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF4</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF3</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF3</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF3</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF3</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF2</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF2</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF2</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF2</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CTEIF1</name><description>Channel x transfer error clear (x = 1               ..7)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CHTIF1</name><description>Channel x half transfer clear (x = 1               ..7)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CTCIF1</name><description>Channel x transfer complete clear (x = 1               ..7)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CGIF1</name><description>Channel x global interrupt clear (x = 1               ..7)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCR1</name><displayName>CCR1</displayName><description>channel x configuration           register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR1</name><displayName>CNDTR1</displayName><description>channel x number of data           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR1</name><displayName>CPAR1</displayName><description>channel x peripheral address           register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR1</name><displayName>CMAR1</displayName><description>channel x memory address           register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR2</name><displayName>CCR2</displayName><description>channel x configuration           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR2</name><displayName>CNDTR2</displayName><description>channel x number of data           register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR2</name><displayName>CPAR2</displayName><description>channel x peripheral address           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR2</name><displayName>CMAR2</displayName><description>channel x memory address           register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR3</name><displayName>CCR3</displayName><description>channel x configuration           register</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR3</name><displayName>CNDTR3</displayName><description>channel x number of data           register</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR3</name><displayName>CPAR3</displayName><description>channel x peripheral address           register</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR3</name><displayName>CMAR3</displayName><description>channel x memory address           register</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR4</name><displayName>CCR4</displayName><description>channel x configuration           register</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR4</name><displayName>CNDTR4</displayName><description>channel x number of data           register</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR4</name><displayName>CPAR4</displayName><description>channel x peripheral address           register</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR4</name><displayName>CMAR4</displayName><description>channel x memory address           register</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR5</name><displayName>CCR5</displayName><description>channel x configuration           register</description><addressOffset>0x58</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR5</name><displayName>CNDTR5</displayName><description>channel x number of data           register</description><addressOffset>0x5C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR5</name><displayName>CPAR5</displayName><description>channel x peripheral address           register</description><addressOffset>0x60</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR5</name><displayName>CMAR5</displayName><description>channel x memory address           register</description><addressOffset>0x64</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR6</name><displayName>CCR6</displayName><description>channel x configuration           register</description><addressOffset>0x6C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR6</name><displayName>CNDTR6</displayName><description>channel x number of data           register</description><addressOffset>0x70</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR6</name><displayName>CPAR6</displayName><description>channel x peripheral address           register</description><addressOffset>0x74</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR6</name><displayName>CMAR6</displayName><description>channel x memory address           register</description><addressOffset>0x78</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CCR7</name><displayName>CCR7</displayName><description>channel x configuration           register</description><addressOffset>0x80</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MEM2MEM</name><description>Memory to memory mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>PL</name><description>Channel priority level</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MSIZE</name><description>Memory size</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PSIZE</name><description>Peripheral size</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MINC</name><description>Memory increment mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>PINC</name><description>Peripheral increment mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CIRC</name><description>Circular mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Data transfer direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIE</name><description>Transfer error interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIE</name><description>Half transfer interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transfer complete interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Channel enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNDTR7</name><displayName>CNDTR7</displayName><description>channel x number of data           register</description><addressOffset>0x84</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NDT</name><description>Number of data to transfer</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CPAR7</name><displayName>CPAR7</displayName><description>channel x peripheral address           register</description><addressOffset>0x88</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Peripheral address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>CMAR7</name><displayName>CMAR7</displayName><description>channel x memory address           register</description><addressOffset>0x8C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MA</name><description>Memory address</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>EXTI</name><description>External interrupt/event       controller</description><groupName>EXTI</groupName><baseAddress>0x40010400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>DMA2_CH1</name><description>DMA2 Channel 1 interrupt</description><value>47</value></interrupt><interrupt><name>DMA2_CH2</name><description>DMA2 Channel 2 interrupt</description><value>48</value></interrupt><interrupt><name>DMA2_CH3</name><description>DMA2 Channel 3 interrupt</description><value>49</value></interrupt><interrupt><name>DMA2_CH4</name><description>DMA2 Channel 4 interrupt</description><value>50</value></interrupt><interrupt><name>DMA2_CH5</name><description>DMA2 Channel 5 interrupt</description><value>51</value></interrupt><registers><register><name>IMR</name><displayName>IMR</displayName><description>IMR</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MR</name><description>Interrupt mask on line x</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register><register><name>EMR</name><displayName>EMR</displayName><description>EMR</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MR</name><description>Event mask on line x</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register><register><name>RTSR</name><displayName>RTSR</displayName><description>RTSR</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>TR</name><description>Rising edge trigger event configuration               bit of line x</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register><register><name>FTSR</name><displayName>FTSR</displayName><description>FTSR</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>TR</name><description>Falling edge trigger event configuration               bit of line x</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register><register><name>SWIER</name><displayName>SWIER</displayName><description>SWIER</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SWIER</name><description>Software interrupt on line               x</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register><register><name>PR</name><displayName>PR</displayName><description>PR</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PR</name><description>Pending bit</description><bitOffset>0</bitOffset><bitWidth>23</bitWidth></field></fields></register></registers></peripheral><peripheral><name>Flash</name><description>Flash</description><groupName>Flash</groupName><baseAddress>0x40023C00</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TAMPER_STAMP</name><description>Tamper and TimeStamp through EXTI line
        interrupts</description><value>2</value></interrupt><interrupt><name>EXTI0</name><description>EXTI Line0 interrupt</description><value>6</value></interrupt><interrupt><name>EXTI1</name><description>EXTI Line1 interrupt</description><value>7</value></interrupt><interrupt><name>EXTI2</name><description>EXTI Line2 interrupt</description><value>8</value></interrupt><interrupt><name>EXTI3</name><description>EXTI Line3 interrupt</description><value>9</value></interrupt><interrupt><name>EXTI4</name><description>EXTI Line4 interrupt</description><value>10</value></interrupt><interrupt><name>EXTI9_5</name><description>EXTI Line[9:5] interrupts</description><value>23</value></interrupt><interrupt><name>EXTI15_10</name><description>EXTI Line[15:10] interrupts</description><value>40</value></interrupt><registers><register><name>ACR</name><displayName>ACR</displayName><description>Access control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LATENCY</name><description>Latency</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>PRFTEN</name><description>Prefetch enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>ACC64</name><description>64-bit access</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>SLEEP_PD</name><description>Flash mode during Sleep</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>RUN_PD</name><description>Flash mode during Run</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>PECR</name><displayName>PECR</displayName><description>Program/erase control register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000007</resetValue><fields><field><name>PELOCK</name><description>FLASH_PECR and data EEPROM               lock</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>PRGLOCK</name><description>Program memory lock</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>OPTLOCK</name><description>Option bytes block lock</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>PROG</name><description>Program memory selection</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>DATA</name><description>Data EEPROM selection</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>FTDW</name><description>Fixed time data write for Byte, Half               Word and Word programming</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>ERASE</name><description>Page or Double Word erase               mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>FPRG</name><description>Half Page/Double Word programming               mode</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>PARALLELBANK</name><description>Parallel bank mode</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>EOPIE</name><description>End of programming interrupt               enable</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>ERRIE</name><description>Error interrupt enable</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>OBL_LAUNCH</name><description>Launch the option byte               loading</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>PDKEYR</name><displayName>PDKEYR</displayName><description>Power down key register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>PDKEYR</name><description>RUN_PD in FLASH_ACR key</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>PEKEYR</name><displayName>PEKEYR</displayName><description>Program/erase key register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>PEKEYR</name><description>FLASH_PEC and data EEPROM               key</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>PRGKEYR</name><displayName>PRGKEYR</displayName><description>Program memory key register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>PRGKEYR</name><description>Program memory key</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>OPTKEYR</name><displayName>OPTKEYR</displayName><description>Option byte key register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>OPTKEYR</name><description>Option byte key</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>Status register</description><addressOffset>0x18</addressOffset><size>0x20</size><resetValue>0x00000004</resetValue><fields><field><name>BSY</name><description>Write/erase operations in               progress</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>EOP</name><description>End of operation</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ENDHV</name><description>End of high voltage</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>READY</name><description>Flash memory module ready after low               power mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>WRPERR</name><description>Write protected error</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PGAERR</name><description>Programming alignment               error</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>SIZERR</name><description>Size error</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>OPTVERR</name><description>Option validity error</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>OPTVERRUSR</name><description>Option UserValidity Error</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register><register><name>OBR</name><displayName>OBR</displayName><description>Option byte register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00F80000</resetValue><fields><field><name>RDPRT</name><description>Read protection</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>BOR_LEV</name><description>BOR_LEV</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>IWDG_SW</name><description>IWDG_SW</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>nRTS_STOP</name><description>nRTS_STOP</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>nRST_STDBY</name><description>nRST_STDBY</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>BFB2</name><description>Boot From Bank 2</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>WRPR1</name><displayName>WRPR1</displayName><description>Write protection register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>WRP1</name><description>Write protection</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>WRPR2</name><displayName>WRPR2</displayName><description>Write protection register</description><addressOffset>0x80</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>WRP2</name><description>WRP2</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>WRPR3</name><displayName>WRPR3</displayName><description>Write protection register</description><addressOffset>0x84</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>WRP3</name><description>WRP3</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>GPIOA</name><description>General-purpose I/Os</description><groupName>GPIO</groupName><baseAddress>0x40020000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>FLASH</name><description>Flash global interrupt</description><value>4</value></interrupt><registers><register><name>MODER</name><displayName>MODER</displayName><description>GPIO port mode register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0xA8000000</resetValue><fields><field><name>MODER15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>OTYPER</name><displayName>OTYPER</displayName><description>GPIO port output type register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OT15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OT14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>OT13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>OT12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>OT11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OT10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>OT9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>OT8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OT7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OT6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>OT5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>OT4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>OT3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OT2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>OT1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>OT0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>OSPEEDER</name><displayName>OSPEEDER</displayName><description>GPIO port output speed           register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OSPEEDR15</name><description>OSPEEDR15</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR14</name><description>OSPEEDR14</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR13</name><description>OSPEEDR13</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR12</name><description>OSPEEDR12</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR11</name><description>OSPEEDR11</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR10</name><description>OSPEEDR10</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR9</name><description>OSPEEDR9</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR8</name><description>OSPEEDR8</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR7</name><description>OSPEEDR7</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR6</name><description>OSPEEDR6</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR5</name><description>OSPEEDR5</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR4</name><description>OSPEEDR4</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR3</name><description>OSPEEDR3</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR2</name><description>OSPEEDR2</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR1</name><description>OSPEEDR1</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR0</name><description>OSPEEDR0</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>PUPDR</name><displayName>PUPDR</displayName><description>GPIO port pull-up/pull-down           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x64000000</resetValue><fields><field><name>PUPDR15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>IDR</name><displayName>IDR</displayName><description>GPIO port input data register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>IDR15</name><description>Port input data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR14</name><description>Port input data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR13</name><description>Port input data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR12</name><description>Port input data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR11</name><description>Port input data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR10</name><description>Port input data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR9</name><description>Port input data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR8</name><description>Port input data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR7</name><description>Port input data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR6</name><description>Port input data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR5</name><description>Port input data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR4</name><description>Port input data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR3</name><description>Port input data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR2</name><description>Port input data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR1</name><description>Port input data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR0</name><description>Port input data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ODR</name><displayName>ODR</displayName><description>GPIO port output data register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ODR15</name><description>Port output data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR14</name><description>Port output data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR13</name><description>Port output data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR12</name><description>Port output data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR11</name><description>Port output data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR10</name><description>Port output data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR9</name><description>Port output data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR8</name><description>Port output data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR7</name><description>Port output data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR6</name><description>Port output data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR5</name><description>Port output data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR4</name><description>Port output data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR3</name><description>Port output data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR2</name><description>Port output data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR1</name><description>Port output data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR0</name><description>Port output data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>BSRR</name><displayName>BSRR</displayName><description>GPIO port bit set/reset           register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>BR15</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>BR14</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>BR13</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>BR12</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>BR11</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>BR10</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>BR9</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>BR8</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>BR7</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>BR6</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>BR5</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>BR4</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>BR3</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>BR2</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>BR1</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>BR0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>BS15</name><description>Port x set bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>BS14</name><description>Port x set bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>BS13</name><description>Port x set bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>BS12</name><description>Port x set bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>BS11</name><description>Port x set bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>BS10</name><description>Port x set bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>BS9</name><description>Port x set bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>BS8</name><description>Port x set bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>BS7</name><description>Port x set bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>BS6</name><description>Port x set bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>BS5</name><description>Port x set bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>BS4</name><description>Port x set bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>BS3</name><description>Port x set bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>BS2</name><description>Port x set bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>BS1</name><description>Port x set bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>BS0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>LCKR</name><displayName>LCKR</displayName><description>GPIO port configuration lock           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LCKK</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK15</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK14</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK13</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK12</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK11</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK10</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK9</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK8</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK7</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK6</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK5</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK4</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK3</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK2</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK1</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK0</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>AFRL</name><displayName>AFRL</displayName><description>AFRL</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRL7</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL6</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL5</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL4</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL3</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL2</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL1</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL0</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>AFRH</name><displayName>AFRH</displayName><description>GPIO alternate function high           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRH15</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH14</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH13</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH12</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH11</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH10</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH9</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH8</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register></registers></peripheral><peripheral><name>GPIOB</name><description>General-purpose I/Os</description><groupName>GPIO</groupName><baseAddress>0x40020400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>MODER</name><displayName>MODER</displayName><description>GPIO port mode register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000280</resetValue><fields><field><name>MODER15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>OTYPER</name><displayName>OTYPER</displayName><description>GPIO port output type register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OT15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OT14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>OT13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>OT12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>OT11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OT10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>OT9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>OT8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OT7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OT6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>OT5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>OT4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>OT3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OT2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>OT1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>OT0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>OSPEEDER</name><displayName>OSPEEDER</displayName><description>GPIO port output speed           register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x000000C0</resetValue><fields><field><name>OSPEEDR15</name><description>OSPEEDR15</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR14</name><description>OSPEEDR14</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR13</name><description>OSPEEDR13</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR12</name><description>OSPEEDR12</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR11</name><description>OSPEEDR11</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR10</name><description>OSPEEDR10</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR9</name><description>OSPEEDR9</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR8</name><description>OSPEEDR8</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR7</name><description>OSPEEDR7</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR6</name><description>OSPEEDR6</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR5</name><description>OSPEEDR5</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR4</name><description>OSPEEDR4</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR3</name><description>OSPEEDR3</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR2</name><description>OSPEEDR2</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR1</name><description>OSPEEDR1</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR0</name><description>OSPEEDR0</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>PUPDR</name><displayName>PUPDR</displayName><description>GPIO port pull-up/pull-down           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000100</resetValue><fields><field><name>PUPDR15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>IDR</name><displayName>IDR</displayName><description>GPIO port input data register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>IDR15</name><description>Port input data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR14</name><description>Port input data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR13</name><description>Port input data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR12</name><description>Port input data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR11</name><description>Port input data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR10</name><description>Port input data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR9</name><description>Port input data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR8</name><description>Port input data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR7</name><description>Port input data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR6</name><description>Port input data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR5</name><description>Port input data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR4</name><description>Port input data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR3</name><description>Port input data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR2</name><description>Port input data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR1</name><description>Port input data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR0</name><description>Port input data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ODR</name><displayName>ODR</displayName><description>GPIO port output data register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ODR15</name><description>Port output data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR14</name><description>Port output data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR13</name><description>Port output data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR12</name><description>Port output data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR11</name><description>Port output data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR10</name><description>Port output data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR9</name><description>Port output data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR8</name><description>Port output data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR7</name><description>Port output data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR6</name><description>Port output data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR5</name><description>Port output data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR4</name><description>Port output data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR3</name><description>Port output data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR2</name><description>Port output data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR1</name><description>Port output data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR0</name><description>Port output data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>BSRR</name><displayName>BSRR</displayName><description>GPIO port bit set/reset           register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>BR15</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>BR14</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>BR13</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>BR12</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>BR11</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>BR10</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>BR9</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>BR8</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>BR7</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>BR6</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>BR5</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>BR4</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>BR3</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>BR2</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>BR1</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>BR0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>BS15</name><description>Port x set bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>BS14</name><description>Port x set bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>BS13</name><description>Port x set bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>BS12</name><description>Port x set bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>BS11</name><description>Port x set bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>BS10</name><description>Port x set bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>BS9</name><description>Port x set bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>BS8</name><description>Port x set bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>BS7</name><description>Port x set bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>BS6</name><description>Port x set bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>BS5</name><description>Port x set bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>BS4</name><description>Port x set bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>BS3</name><description>Port x set bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>BS2</name><description>Port x set bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>BS1</name><description>Port x set bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>BS0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>LCKR</name><displayName>LCKR</displayName><description>GPIO port configuration lock           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LCKK</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK15</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK14</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK13</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK12</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK11</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK10</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK9</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK8</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK7</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK6</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK5</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK4</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK3</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK2</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK1</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK0</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>AFRL</name><displayName>AFRL</displayName><description>AFRL</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRL7</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL6</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL5</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL4</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL3</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL2</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL1</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL0</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>AFRH</name><displayName>AFRH</displayName><description>GPIO alternate function high           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRH15</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH14</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH13</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH12</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH11</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH10</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH9</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH8</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register></registers></peripheral><peripheral><name>GPIOC</name><description>General-purpose I/Os</description><groupName>GPIO</groupName><baseAddress>0x40020800</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>MODER</name><displayName>MODER</displayName><description>GPIO port mode register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MODER15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>MODER0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>OTYPER</name><displayName>OTYPER</displayName><description>GPIO port output type register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OT15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OT14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>OT13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>OT12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>OT11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OT10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>OT9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>OT8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OT7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OT6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>OT5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>OT4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>OT3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OT2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>OT1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>OT0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>OSPEEDER</name><displayName>OSPEEDER</displayName><description>GPIO port output speed           register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OSPEEDR15</name><description>OSPEEDR15</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR14</name><description>OSPEEDR14</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR13</name><description>OSPEEDR13</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR12</name><description>OSPEEDR12</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR11</name><description>OSPEEDR11</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR10</name><description>OSPEEDR10</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR9</name><description>OSPEEDR9</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR8</name><description>OSPEEDR8</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR7</name><description>OSPEEDR7</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR6</name><description>OSPEEDR6</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR5</name><description>OSPEEDR5</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR4</name><description>OSPEEDR4</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR3</name><description>OSPEEDR3</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR2</name><description>OSPEEDR2</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR1</name><description>OSPEEDR1</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>OSPEEDR0</name><description>OSPEEDR0</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>PUPDR</name><displayName>PUPDR</displayName><description>GPIO port pull-up/pull-down           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PUPDR15</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR14</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR13</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR12</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR11</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR10</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR9</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR8</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR7</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR6</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR5</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR4</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR3</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR2</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR1</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>PUPDR0</name><description>Port x configuration bits (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>IDR</name><displayName>IDR</displayName><description>GPIO port input data register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>IDR15</name><description>Port input data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR14</name><description>Port input data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR13</name><description>Port input data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR12</name><description>Port input data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR11</name><description>Port input data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR10</name><description>Port input data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR9</name><description>Port input data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR8</name><description>Port input data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR7</name><description>Port input data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR6</name><description>Port input data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR5</name><description>Port input data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR4</name><description>Port input data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR3</name><description>Port input data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR2</name><description>Port input data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR1</name><description>Port input data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>IDR0</name><description>Port input data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ODR</name><displayName>ODR</displayName><description>GPIO port output data register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ODR15</name><description>Port output data (y =               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR14</name><description>Port output data (y =               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR13</name><description>Port output data (y =               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR12</name><description>Port output data (y =               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR11</name><description>Port output data (y =               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR10</name><description>Port output data (y =               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR9</name><description>Port output data (y =               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR8</name><description>Port output data (y =               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR7</name><description>Port output data (y =               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR6</name><description>Port output data (y =               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR5</name><description>Port output data (y =               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR4</name><description>Port output data (y =               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR3</name><description>Port output data (y =               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR2</name><description>Port output data (y =               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR1</name><description>Port output data (y =               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>ODR0</name><description>Port output data (y =               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>BSRR</name><displayName>BSRR</displayName><description>GPIO port bit set/reset           register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>BR15</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>BR14</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>BR13</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>BR12</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>BR11</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>BR10</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>BR9</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>BR8</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>BR7</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>BR6</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>BR5</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>BR4</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>BR3</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>BR2</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>BR1</name><description>Port x reset bit y (y =               0..15)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>BR0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>BS15</name><description>Port x set bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>BS14</name><description>Port x set bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>BS13</name><description>Port x set bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>BS12</name><description>Port x set bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>BS11</name><description>Port x set bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>BS10</name><description>Port x set bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>BS9</name><description>Port x set bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>BS8</name><description>Port x set bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>BS7</name><description>Port x set bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>BS6</name><description>Port x set bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>BS5</name><description>Port x set bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>BS4</name><description>Port x set bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>BS3</name><description>Port x set bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>BS2</name><description>Port x set bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>BS1</name><description>Port x set bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>BS0</name><description>Port x set bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>LCKR</name><displayName>LCKR</displayName><description>GPIO port configuration lock           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LCKK</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK15</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK14</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK13</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK12</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK11</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK10</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK9</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK8</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK7</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK6</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK5</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK4</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK3</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK2</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK1</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LCK0</name><description>Port x lock bit y (y=               0..15)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>AFRL</name><displayName>AFRL</displayName><description>AFRL</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRL7</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL6</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL5</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL4</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL3</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL2</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL1</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRL0</name><description>Alternate function selection for port x               bit y (y = 0..7)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>AFRH</name><displayName>AFRH</displayName><description>GPIO alternate function high           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>AFRH15</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>28</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH14</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH13</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH12</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH11</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH10</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH9</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>AFRH8</name><description>Alternate function selection for port x               bit y (y = 8..15)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="GPIOC"><name>GPIOD</name><baseAddress>0x40020C00</baseAddress></peripheral><peripheral derivedFrom="GPIOC"><name>GPIOE</name><baseAddress>0x40021000</baseAddress></peripheral><peripheral derivedFrom="GPIOC"><name>GPIOH</name><baseAddress>0x40021400</baseAddress></peripheral><peripheral><name>I2C1</name><description>Inter-integrated circuit</description><groupName>I2C</groupName><baseAddress>0x40005400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>CR1</name><displayName>CR1</displayName><description>CR1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>SWRST</name><description>Software reset</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ALERT</name><description>SMBus alert</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>PEC</name><description>Packet error checking</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>POS</name><description>Acknowledge/PEC Position (for data               reception)</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ACK</name><description>Acknowledge enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>STOP</name><description>Stop generation</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>START</name><description>Start generation</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>NOSTRETCH</name><description>Clock stretching disable (Slave               mode)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ENGC</name><description>General call enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ENPEC</name><description>PEC enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>ENARP</name><description>ARP enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>SMBTYPE</name><description>SMBus type</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>SMBUS</name><description>SMBus mode</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>PE</name><description>Peripheral enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>CR2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>LAST</name><description>DMA last transfer</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAEN</name><description>DMA requests enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ITBUFEN</name><description>Buffer interrupt enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ITEVTEN</name><description>Event interrupt enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ITERREN</name><description>Error interrupt enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>FREQ</name><description>Peripheral clock frequency</description><bitOffset>0</bitOffset><bitWidth>6</bitWidth></field></fields></register><register><name>OAR1</name><displayName>OAR1</displayName><description>OAR1</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ADDMODE</name><description>ADDMODE</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ADD_8_9</name><description>Interface address</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>ADD_1_7</name><description>Interface address</description><bitOffset>1</bitOffset><bitWidth>7</bitWidth></field><field><name>ADD_0</name><description>Interface address</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>OAR2</name><displayName>OAR2</displayName><description>OAR2</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ADD2</name><description>Interface address</description><bitOffset>1</bitOffset><bitWidth>7</bitWidth></field><field><name>ENDUAL</name><description>Dual addressing mode               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>DR</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>DR</name><description>-bit data register</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>SR1</name><displayName>SR1</displayName><description>SR1</description><addressOffset>0x14</addressOffset><size>0x20</size><resetValue>0x0000</resetValue><fields><field><name>SMBALERT</name><description>SMBus alert</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TIMEOUT</name><description>Timeout or Tlow error</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PECERR</name><description>PEC Error in reception</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>OVR</name><description>Overrun/Underrun</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>AF</name><description>Acknowledge failure</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>ARLO</name><description>Arbitration lost (master               mode)</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>BERR</name><description>Bus error</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TxE</name><description>Data register empty               (transmitters)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>RxNE</name><description>Data register not empty               (receivers)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>STOPF</name><description>Stop detection (slave               mode)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ADD10</name><description>10-bit header sent (Master               mode)</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>BTF</name><description>Byte transfer finished</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ADDR</name><description>Address sent (master mode)/matched               (slave mode)</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>SB</name><description>Start bit (Master mode)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>SR2</name><displayName>SR2</displayName><description>SR2</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x0000</resetValue><fields><field><name>PEC</name><description>acket error checking               register</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>DUALF</name><description>Dual flag (Slave mode)</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>SMBHOST</name><description>SMBus host header (Slave               mode)</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>SMBDEFAULT</name><description>SMBus device default address (Slave               mode)</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GENCALL</name><description>General call address (Slave               mode)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TRA</name><description>Transmitter/receiver</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>BUSY</name><description>Bus busy</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>MSL</name><description>Master/slave</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCR</name><displayName>CCR</displayName><description>CCR</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>F_S</name><description>I2C master mode selection</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>DUTY</name><description>Fast mode duty cycle</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CCR</name><description>Clock control register in Fast/Standard               mode (Master mode)</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>TRISE</name><displayName>TRISE</displayName><description>TRISE</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0002</resetValue><fields><field><name>TRISE</name><description>Maximum rise time in Fast/Standard mode               (Master mode)</description><bitOffset>0</bitOffset><bitWidth>6</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="I2C1"><name>I2C2</name><baseAddress>0x40005800</baseAddress></peripheral><peripheral><name>IWDG</name><description>Independent watchdog</description><groupName>IWDG</groupName><baseAddress>0x40003000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>KR</name><displayName>KR</displayName><description>Key register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>KEY</name><description>Key value (write only, read               0000h)</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>PR</name><displayName>PR</displayName><description>Prescaler register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PR</name><description>Prescaler divider</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>RLR</name><displayName>RLR</displayName><description>Reload register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000FFF</resetValue><fields><field><name>RL</name><description>Watchdog counter reload               value</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>Status register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>RVU</name><description>Watchdog counter reload value               update</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>PVU</name><description>Watchdog prescaler value               update</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral><peripheral><name>LCD</name><description>Liquid crystal display controller</description><groupName>LCD</groupName><baseAddress>0x40002400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>I2C1_EV</name><description>I2C1 event interrupt</description><value>31</value></interrupt><interrupt><name>I2C1_ER</name><description>I2C1 error interrupt</description><value>32</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MUX_SEG</name><description>Mux segment enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>BIAS</name><description>Bias selector</description><bitOffset>5</bitOffset><bitWidth>2</bitWidth></field><field><name>DUTY</name><description>Duty selection</description><bitOffset>2</bitOffset><bitWidth>3</bitWidth></field><field><name>VSEL</name><description>Voltage source selection</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LCDEN</name><description>LCD controller enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>FCR</name><displayName>FCR</displayName><description>frame control register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PS</name><description>PS 16-bit prescaler</description><bitOffset>22</bitOffset><bitWidth>4</bitWidth></field><field><name>DIV</name><description>DIV clock divider</description><bitOffset>18</bitOffset><bitWidth>4</bitWidth></field><field><name>BLINK</name><description>Blink mode selection</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>BLINKF</name><description>Blink frequency selection</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth></field><field><name>CC</name><description>Contrast control</description><bitOffset>10</bitOffset><bitWidth>3</bitWidth></field><field><name>DEAD</name><description>Dead time duration</description><bitOffset>7</bitOffset><bitWidth>3</bitWidth></field><field><name>PON</name><description>Pulse ON duration</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>UDDIE</name><description>Update display done interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>SOFIE</name><description>Start of frame interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>HD</name><description>High drive enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x8</addressOffset><size>0x20</size><resetValue>0x00000020</resetValue><fields><field><name>FCRSF</name><description>LCD Frame Control Register               Synchronization flag</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>RDY</name><description>Ready flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>UDD</name><description>Update Display Done</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>UDR</name><description>Update display request</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>SOF</name><description>Start of frame flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ENS</name><description>LCD enabled status</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>CLR</name><displayName>CLR</displayName><description>clear register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>UDDC</name><description>Update display done clear</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>SOFC</name><description>Start of frame flag clear</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM0</name><displayName>RAM_COM0</displayName><description>display memory</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM1</name><displayName>RAM_COM1</displayName><description>display memory</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM2</name><displayName>RAM_COM2</displayName><description>display memory</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM3</name><displayName>RAM_COM3</displayName><description>display memory</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM4</name><displayName>RAM_COM4</displayName><description>display memory</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM5</name><displayName>RAM_COM5</displayName><description>display memory</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM6</name><displayName>RAM_COM6</displayName><description>display memory</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RAM_COM7</name><displayName>RAM_COM7</displayName><description>display memory</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>S31</name><description>S31</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>S30</name><description>S30</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>S29</name><description>S29</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>S28</name><description>S28</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>S27</name><description>S27</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>S26</name><description>S26</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>S25</name><description>S25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>S24</name><description>S24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>S23</name><description>S23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>S22</name><description>S22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>S21</name><description>S21</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>S20</name><description>S20</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>S19</name><description>S19</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>S18</name><description>S18</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>S17</name><description>S17</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>S16</name><description>S16</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>S15</name><description>S15</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>S14</name><description>S14</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>S13</name><description>S13</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>S12</name><description>S12</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>S11</name><description>S11</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>S10</name><description>S10</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>S09</name><description>S09</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>S08</name><description>S08</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>S07</name><description>S07</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>S06</name><description>S06</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>S05</name><description>S05</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>S04</name><description>S04</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>S03</name><description>S03</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>S02</name><description>S02</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>S01</name><description>S01</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>S00</name><description>S00</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral><peripheral><name>PWR</name><description>Power control</description><groupName>PWR</groupName><baseAddress>0x40007000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>I2C2_EV</name><description>I2C2 event interrupt</description><value>33</value></interrupt><interrupt><name>I2C2_ER</name><description>I2C2 error interrupt</description><value>34</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>power control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00001000</resetValue><fields><field><name>LPRUN</name><description>Low power run mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>VOS</name><description>Voltage scaling range               selection</description><bitOffset>11</bitOffset><bitWidth>2</bitWidth></field><field><name>FWU</name><description>Fast wakeup</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ULP</name><description>Ultralow power mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>DBP</name><description>Disable backup domain write               protection</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>PLS</name><description>PVD level selection</description><bitOffset>5</bitOffset><bitWidth>3</bitWidth></field><field><name>PVDE</name><description>Power voltage detector               enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CSBF</name><description>Clear standby flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CWUF</name><description>Clear wakeup flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>PDDS</name><description>Power down deepsleep</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LPSDSR</name><description>Low-power deep sleep</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CSR</name><displayName>CSR</displayName><description>power control/status register</description><addressOffset>0x4</addressOffset><size>0x20</size><resetValue>0x00000008</resetValue><fields><field><name>EWUP3</name><description>Enable WKUP pin 3</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>EWUP2</name><description>Enable WKUP pin 2</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>EWUP1</name><description>Enable WKUP pin 1</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>REGLPF</name><description>Regulator LP flag</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>VOSF</name><description>Voltage Scaling select               flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>VREFINTRDYF</name><description>Internal voltage reference (VREFINT)               ready flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>PVDO</name><description>PVD output</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>SBF</name><description>Standby flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>WUF</name><description>Wakeup flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register></registers></peripheral><peripheral><name>RCC</name><description>Reset and clock control</description><groupName>RCC</groupName><baseAddress>0x40023800</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>CR</name><displayName>CR</displayName><description>Clock control register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00000300</resetValue><fields><field><name>RTCPRE1</name><description>TC/LCD prescaler</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RTCPRE0</name><description>RTCPRE0</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CSSON</name><description>Clock security system               enable</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PLLRDY</name><description>PLL clock ready flag</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>PLLON</name><description>PLL enable</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>HSEBYP</name><description>HSE clock bypass</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>HSERDY</name><description>HSE clock ready flag</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>HSEON</name><description>HSE clock enable</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>MSIRDY</name><description>MSI clock ready flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>MSION</name><description>MSI clock enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>HSIRDY</name><description>Internal high-speed clock ready               flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>HSION</name><description>Internal high-speed clock               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register><register><name>ICSCR</name><displayName>ICSCR</displayName><description>Internal clock sources calibration           register</description><addressOffset>0x4</addressOffset><size>0x20</size><resetValue>0x0000B000</resetValue><fields><field><name>MSITRIM</name><description>MSI clock trimming</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth><access>read-write</access></field><field><name>MSICAL</name><description>MSI clock calibration</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth><access>read-only</access></field><field><name>MSIRANGE</name><description>MSI clock ranges</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>HSITRIM</name><description>High speed internal clock               trimming</description><bitOffset>8</bitOffset><bitWidth>5</bitWidth><access>read-write</access></field><field><name>HSICAL</name><description>nternal high speed clock               calibration</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth><access>read-only</access></field></fields></register><register><name>CFGR</name><displayName>CFGR</displayName><description>Clock configuration register</description><addressOffset>0x8</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>MCOPRE</name><description>Microcontroller clock output               prescaler</description><bitOffset>28</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>MCOSEL</name><description>Microcontroller clock output               selection</description><bitOffset>24</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>PLLDIV</name><description>PLL output division</description><bitOffset>22</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>PLLMUL</name><description>PLL multiplication factor</description><bitOffset>18</bitOffset><bitWidth>4</bitWidth><access>read-write</access></field><field><name>PLLSRC</name><description>PLL entry clock source</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PPRE2</name><description>APB high-speed prescaler               (APB2)</description><bitOffset>11</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>PPRE1</name><description>APB low-speed prescaler               (APB1)</description><bitOffset>8</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>HPRE</name><description>AHB prescaler</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth><access>read-write</access></field><field><name>SWS</name><description>System clock switch status</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth><access>read-only</access></field><field><name>SW</name><description>System clock switch</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field></fields></register><register><name>CIR</name><displayName>CIR</displayName><description>Clock interrupt register</description><addressOffset>0xC</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>CSSC</name><description>Clock security system interrupt               clear</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>LSECSSC</name><description>LSE CSS interrupt clear</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>MSIRDYC</name><description>MSI ready interrupt clear</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>PLLRDYC</name><description>PLL ready interrupt clear</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>HSERDYC</name><description>HSE ready interrupt clear</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>HSIRDYC</name><description>HSI ready interrupt clear</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>LSERDYC</name><description>LSE ready interrupt clear</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>LSIRDYC</name><description>LSI ready interrupt clear</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>LSECSSIE</name><description>LSE CSS interrupt enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>MSIRDYIE</name><description>MSI ready interrupt enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PLLRDYIE</name><description>PLL ready interrupt enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>HSERDYIE</name><description>HSE ready interrupt enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>HSIRDYIE</name><description>HSI ready interrupt enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LSERDYIE</name><description>LSE ready interrupt enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LSIRDYIE</name><description>LSI ready interrupt enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CSSF</name><description>Clock security system interrupt               flag</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSECSSF</name><description>LSE CSS Interrupt flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>MSIRDYF</name><description>MSI ready interrupt flag</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>PLLRDYF</name><description>PLL ready interrupt flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>HSERDYF</name><description>HSE ready interrupt flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>HSIRDYF</name><description>HSI ready interrupt flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSERDYF</name><description>LSE ready interrupt flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSIRDYF</name><description>LSI ready interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>AHBRSTR</name><displayName>AHBRSTR</displayName><description>AHB peripheral reset register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DMA2RST</name><description>DMA2 reset</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>DMA1RST</name><description>DMA1 reset</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>FLITFRST</name><description>FLITF reset</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CRCRST</name><description>CRC reset</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOGRST</name><description>IO port G reset</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOFRST</name><description>IO port F reset</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOHRST</name><description>IO port H reset</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOERST</name><description>IO port E reset</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIODRST</name><description>IO port D reset</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOCRST</name><description>IO port C reset</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOBRST</name><description>IO port B reset</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOARST</name><description>IO port A reset</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB2RSTR</name><displayName>APB2RSTR</displayName><description>APB2 peripheral reset register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>USART1RST</name><description>USART1RST</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI1RST</name><description>SPI1RST</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ADC1RST</name><description>ADC1RST</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TM11RST</name><description>TM11RST</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TM10RST</name><description>TM10RST</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM9RST</name><description>TIM9RST</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>SYSCFGRST</name><description>SYSCFGRST</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB1RSTR</name><displayName>APB1RSTR</displayName><description>APB1 peripheral reset register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>COMPRST</name><description>COMP interface reset</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>DACRST</name><description>DAC interface reset</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>PWRRST</name><description>Power interface reset</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>USBRST</name><description>USB reset</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C2RST</name><description>I2C 2 reset</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C1RST</name><description>I2C 1 reset</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>USART3RST</name><description>USART 3 reset</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>USART2RST</name><description>USART 2 reset</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI3RST</name><description>SPI 3 reset</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI2RST</name><description>SPI 2 reset</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>WWDRST</name><description>Window watchdog reset</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCDRST</name><description>LCD reset</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM7RST</name><description>Timer 7 reset</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM6RST</name><description>Timer 6reset</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM5RST</name><description>Timer 5 reset</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM4RST</name><description>Timer 4 reset</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM3RST</name><description>Timer 3 reset</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM2RST</name><description>Timer 2 reset</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>AHBENR</name><displayName>AHBENR</displayName><description>AHB peripheral clock enable           register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00008000</resetValue><fields><field><name>DMA2EN</name><description>DMA2 clock enable</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>DMA1EN</name><description>DMA1 clock enable</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>FLITFEN</name><description>FLITF clock enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CRCEN</name><description>CRC clock enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPGEN</name><description>IO port G clock enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPFEN</name><description>IO port F clock enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPHEN</name><description>IO port H clock enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPEEN</name><description>IO port E clock enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPDEN</name><description>IO port D clock enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPCEN</name><description>IO port C clock enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPBEN</name><description>IO port B clock enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOPAEN</name><description>IO port A clock enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB2ENR</name><displayName>APB2ENR</displayName><description>APB2 peripheral clock enable           register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>USART1EN</name><description>USART1 clock enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI1EN</name><description>SPI 1 clock enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ADC1EN</name><description>ADC1 interface clock               enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM11EN</name><description>TIM11 timer clock enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM10EN</name><description>TIM10 timer clock enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM9EN</name><description>TIM9 timer clock enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>SYSCFGEN</name><description>System configuration controller clock               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB1ENR</name><displayName>APB1ENR</displayName><description>APB1 peripheral clock enable           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>COMPEN</name><description>COMP interface clock               enable</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>DACEN</name><description>DAC interface clock enable</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>PWREN</name><description>Power interface clock               enable</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>USBEN</name><description>USB clock enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C2EN</name><description>I2C 2 clock enable</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C1EN</name><description>I2C 1 clock enable</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>USART3EN</name><description>USART 3 clock enable</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>USART2EN</name><description>USART 2 clock enable</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI3EN</name><description>SPI 3 clock enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI2EN</name><description>SPI 2 clock enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>WWDGEN</name><description>Window watchdog clock               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCDEN</name><description>LCD clock enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM7EN</name><description>Timer 7 clock enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM6EN</name><description>Timer 6 clock enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM5EN</name><description>Timer 5 clock enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM4EN</name><description>Timer 4 clock enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM3EN</name><description>Timer 3 clock enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM2EN</name><description>Timer 2 clock enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>AHBLPENR</name><displayName>AHBLPENR</displayName><description>AHB peripheral clock enable in low power           mode register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0101903F</resetValue><fields><field><name>DMA2LPEN</name><description>DMA2 clock enable during Sleep               mode</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>DMA1LPEN</name><description>DMA1 clock enable during Sleep               mode</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>SRAMLPEN</name><description>SRAM clock enable during Sleep               mode</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>FLITFLPEN</name><description>FLITF clock enable during Sleep               mode</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CRCLPEN</name><description>CRC clock enable during Sleep               mode</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOGLPEN</name><description>IO port G clock enable during Sleep               mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOFLPEN</name><description>IO port F clock enable during Sleep               mode</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOHLPEN</name><description>IO port H clock enable during Sleep               mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOELPEN</name><description>IO port E clock enable during Sleep               mode</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIODLPEN</name><description>IO port D clock enable during Sleep               mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOCLPEN</name><description>IO port C clock enable during Sleep               mode</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOBLPEN</name><description>IO port B clock enable during Sleep               mode</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>GPIOALPEN</name><description>IO port A clock enable during Sleep               mode</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB2LPENR</name><displayName>APB2LPENR</displayName><description>APB2 peripheral clock enable in low power           mode register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>USART1LPEN</name><description>USART1 clock enable during Sleep               mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI1LPEN</name><description>SPI 1 clock enable during Sleep               mode</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ADC1LPEN</name><description>ADC1 interface clock enable during Sleep               mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM11LPEN</name><description>TIM11 timer clock enable during Sleep               mode</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM10LPEN</name><description>TIM10 timer clock enable during Sleep               mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM9LPEN</name><description>TIM9 timer clock enable during Sleep               mode</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>SYSCFGLPEN</name><description>System configuration controller clock               enable during Sleep mode</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>APB1LPENR</name><displayName>APB1LPENR</displayName><description>APB1 peripheral clock enable in low power           mode register</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>COMPLPEN</name><description>COMP interface clock enable during Sleep               mode</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>DACLPEN</name><description>DAC interface clock enable during Sleep               mode</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>PWRLPEN</name><description>Power interface clock enable during               Sleep mode</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>USBLPEN</name><description>USB clock enable during Sleep               mode</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C2LPEN</name><description>I2C 2 clock enable during Sleep               mode</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>I2C1LPEN</name><description>I2C 1 clock enable during Sleep               mode</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>USART3LPEN</name><description>USART 3 clock enable during Sleep               mode</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>USART2LPEN</name><description>USART 2 clock enable during Sleep               mode</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>SPI2LPEN</name><description>SPI 2 clock enable during Sleep               mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>WWDGLPEN</name><description>Window watchdog clock enable during               Sleep mode</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>LCDLPEN</name><description>LCD clock enable during Sleep               mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM7LPEN</name><description>Timer 7 clock enable during Sleep               mode</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM6LPEN</name><description>Timer 6 clock enable during Sleep               mode</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM4LPEN</name><description>Timer 4 clock enable during Sleep               mode</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM3LPEN</name><description>Timer 3 clock enable during Sleep               mode</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM2LPEN</name><description>Timer 2 clock enable during Sleep               mode</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CSR</name><displayName>CSR</displayName><description>Control/status register</description><addressOffset>0x34</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>LPWRSTF</name><description>Low-power reset flag</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>WWDGRSTF</name><description>Window watchdog reset flag</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>IWDGRSTF</name><description>Independent watchdog reset               flag</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>SFTRSTF</name><description>Software reset flag</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PORRSTF</name><description>POR/PDR reset flag</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>PINRSTF</name><description>PIN reset flag</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>OBLRSTF</name><description>Options bytes loading reset               flag</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RMVF</name><description>Remove reset flag</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RTCRST</name><description>RTC software reset</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RTCEN</name><description>RTC clock enable</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RTCSEL</name><description>RTC and LCD clock source               selection</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>LSECSSD</name><description>CSS on LSE failure               Detection</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSECSSON</name><description>CSS on LSE enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LSEBYP</name><description>External low-speed oscillator               bypass</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LSERDY</name><description>External low-speed oscillator               ready</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSEON</name><description>External low-speed oscillator               enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LSIRDY</name><description>Internal low-speed oscillator               ready</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>LSION</name><description>Internal low-speed oscillator               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register></registers></peripheral><peripheral><name>RI</name><description>Routing interface</description><groupName>RI</groupName><baseAddress>0x40007C04</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>LCD</name><description>LCD global interrupt</description><value>24</value></interrupt><registers><register><name>ICR</name><displayName>ICR</displayName><description>RI input capture register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IC4</name><description>IC4</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>IC3</name><description>IC3</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>IC2</name><description>IC2</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>IC1</name><description>IC1</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>TIM</name><description>Timer select bits</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth></field><field><name>IC4IOS</name><description>Input capture 4 select               bits</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>IC3IOS</name><description>Input capture 3 select               bits</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>IC2IOS</name><description>Input capture 2 select               bits</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>IC1IOS</name><description>Input capture 1 select               bits</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>ASCR1</name><displayName>ASCR1</displayName><description>RI analog switches control register           1</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SCM</name><description>Switch control mode</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>CH30GR11_4</name><description>Analog switch control</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>CH29GR11_3</name><description>Analog switch control</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>CH28GR11_2</name><description>Analog switch control</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>CH27GR11_1</name><description>Analog switch control</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>VCOMP</name><description>ADC analog switch selection for internal               node to comparator 1</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>CH25</name><description>Analog I/O switch control of channel               CH25</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>CH24</name><description>Analog I/O switch control of channel               CH24</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>CH23</name><description>Analog I/O switch control of channel               CH23</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>CH22</name><description>Analog I/O switch control of channel               CH22</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>CH21GR7_4</name><description>Analog switch control</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>CH20GR7_3</name><description>Analog switch control</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>CH19GR7_2</name><description>Analog switch control</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>CH18GR7_1</name><description>Analog switch control</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>CH31GR7_1</name><description>Analog switch control</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>CH15GR9_2</name><description>Analog switch control</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CH14GR9_1</name><description>Analog switch control</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CH13GR8_4</name><description>Analog switch control</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>CH12GR8_3</name><description>Analog switch control</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>CH11GR8_2</name><description>Analog switch control</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CH10GR8_1</name><description>Analog switch control</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CH9GR3_2</name><description>Analog switch control</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>CH8GR3_1</name><description>Analog switch control</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>CH7GR2_2</name><description>Analog switch control</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>CH6GR2_1</name><description>Analog switch control</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>COMP1_SW1</name><description>Comparator 1 analog switch</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>CH31GR11_5</name><description>Analog switch control</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CH3GR1_4</name><description>Analog switch control</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CH2GR1_3</name><description>Analog switch control</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CH1GR1_2</name><description>Analog switch control</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CH0GR1_1</name><description>Analog switch control</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ASCR2</name><displayName>ASCR2</displayName><description>RI analog switches control register           2</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>GR5_4</name><description>GR5_4 analog switch               control</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth></field><field><name>GR6_4</name><description>GR6_4 analog switch               control</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth></field><field><name>GR6_3</name><description>GR6_3 analog switch               control</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>GR7_7</name><description>GR7_7 analog switch               control</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>GR7_6</name><description>GR7_6 analog switch               control</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>GR7_5</name><description>GR7_5 analog switch               control</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>GR2_5</name><description>GR2_5 analog switch               control</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>GR2_4</name><description>GR2_4 analog switch               control</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>GR2_3</name><description>GR2_3 analog switch               control</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>GR9_4</name><description>GR9_4 analog switch               control</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>GR9_3</name><description>GR9_3 analog switch               control</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>GR3_5</name><description>GR3_5 analog switch               control</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>GR3_4</name><description>GR3_4 analog switch               control</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>GR3_3</name><description>GR3_3 analog switch               control</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>GR4_3</name><description>GR4_3 analog switch               control</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>GR4_2</name><description>GR4_2 analog switch               control</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>GR4_1</name><description>GR4_1 analog switch               control</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>GR5_3</name><description>GR5_3 analog switch               control</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>GR5_2</name><description>GR5_2 analog switch               control</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>GR5_1</name><description>GR5_1 analog switch               control</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>GR6_2</name><description>GR6_2 analog switch               control</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>GR6_1</name><description>GR6_1 analog switch               control</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>GR10_4</name><description>GR10_4 analog switch               control</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>GR10_3</name><description>GR10_3 analog switch               control</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>GR10_2</name><description>GR10_2 analog switch               control</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>GR10_1</name><description>GR10_1 analog switch               control</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>HYSCR1</name><displayName>HYSCR1</displayName><description>RI hysteresis control register           1</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PB</name><description>Port B hysteresis control               on/off</description><bitOffset>16</bitOffset><bitWidth>16</bitWidth></field><field><name>PA</name><description>Port A hysteresis control               on/off</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>HYSCR2</name><displayName>HYSCR2</displayName><description>RI hysteresis control register           2</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PD</name><description>Port D hysteresis control               on/off</description><bitOffset>16</bitOffset><bitWidth>16</bitWidth></field><field><name>PC</name><description>Port C hysteresis control               on/off</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>HYSCR3</name><displayName>HYSCR3</displayName><description>RI hysteresis control register           3</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PF</name><description>Port F hysteresis control               on/off</description><bitOffset>16</bitOffset><bitWidth>16</bitWidth></field><field><name>PE</name><description>Port E hysteresis control               on/off</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>HYSCR4</name><displayName>HYSCR4</displayName><description>Hysteresis control register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PG</name><description>Port G hysteresis control               on/off</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ASMR1</name><displayName>ASMR1</displayName><description>Analog switch mode register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Port A analog switch mode               selection</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CMR1</name><displayName>CMR1</displayName><description>Channel mask register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Port A channel masking</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CICR1</name><displayName>CICR1</displayName><description>Channel identification for capture           register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PA</name><description>Port A channel identification for               capture</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ASMR2</name><displayName>ASMR2</displayName><description>Analog switch mode register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PB</name><description>Port B analog switch mode               selection</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CMR2</name><displayName>CMR2</displayName><description>Channel mask register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PB</name><description>Port B channel masking</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CICR2</name><displayName>CICR2</displayName><description>Channel identification for capture           register</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PB</name><description>Port B channel identification for               capture</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ASMR3</name><displayName>ASMR3</displayName><description>Analog switch mode register</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PC</name><description>Port C analog switch mode               selection</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CMR3</name><displayName>CMR3</displayName><description>Channel mask register</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PC</name><description>Port C channel masking</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CICR3</name><displayName>CICR3</displayName><description>Channel identification for capture           register</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PC</name><description>Port C channel identification for               capture</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ASMR4</name><displayName>ASMR4</displayName><description>Analog switch mode register</description><addressOffset>0x40</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PF</name><description>Port F analog switch mode               selection</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CMR4</name><displayName>CMR4</displayName><description>Channel mask register</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PF</name><description>Port F channel masking</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CICR4</name><displayName>CICR4</displayName><description>Channel identification for capture           register</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PF</name><description>Port F channel identification for               capture</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ASMR5</name><displayName>ASMR5</displayName><description>Analog switch mode register</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PG</name><description>Port G analog switch mode               selection</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CMR5</name><displayName>CMR5</displayName><description>Channel mask register</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PG</name><description>Port G channel masking</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CICR5</name><displayName>CICR5</displayName><description>Channel identification for capture           register</description><addressOffset>0x54</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PG</name><description>Port G channel identification for               capture</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register></registers></peripheral><peripheral><name>RTC</name><description>Real-time clock</description><groupName>RTC</groupName><baseAddress>0x40002800</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>TR</name><displayName>TR</displayName><description>time register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PM</name><description>AM/PM notation</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>HT</name><description>Hour tens in BCD format</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>HU</name><description>Hour units in BCD format</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>MNT</name><description>Minute tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>MNU</name><description>Minute units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>ST</name><description>Second tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SU</name><description>Second units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>date register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00002101</resetValue><fields><field><name>YT</name><description>Year tens in BCD format</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>YU</name><description>Year units in BCD format</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>WDU</name><description>Week day units</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth></field><field><name>MT</name><description>Month tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>MU</name><description>Month units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>DT</name><description>Date tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DU</name><description>Date units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>COE</name><description>Calibration output enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>OSEL</name><description>Output selection</description><bitOffset>21</bitOffset><bitWidth>2</bitWidth></field><field><name>POL</name><description>Output polarity</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>COSEL</name><description>Calibration output               selection</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>BKP</name><description>Backup</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>SUB1H</name><description>Subtract 1 hour</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>ADD1H</name><description>Add 1 hour</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>TSIE</name><description>Time-stamp interrupt               enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>WUTIE</name><description>Wakeup timer interrupt               enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRBIE</name><description>Alarm B interrupt enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRAIE</name><description>Alarm A interrupt enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>TSE</name><description>Time stamp enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>WUTE</name><description>Wakeup timer enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRBE</name><description>Alarm B enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRAE</name><description>Alarm A enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>DCE</name><description>Coarse digital calibration               enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>FMT</name><description>Hour format</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>BYPSHAD</name><description>Bypass the shadow               registers</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>REFCKON</name><description>Reference clock detection               enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TSEDGE</name><description>Time-stamp event active               edge</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>WCKSEL</name><description>WCKSEL</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>ISR</name><displayName>ISR</displayName><description>initialization and status           register</description><addressOffset>0xC</addressOffset><size>0x20</size><resetValue>0x00000007</resetValue><fields><field><name>RECALPF</name><description>Recalibration pending Flag</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>TAMP3F</name><description>TAMPER3 detection flag</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TAMP2F</name><description>TAMPER2 detection flag</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TAMP1F</name><description>Tamper detection flag</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TSOVF</name><description>Timestamp overflow flag</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TSF</name><description>Timestamp flag</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>WUTF</name><description>Wakeup timer flag</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>ALRBF</name><description>Alarm B flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>ALRAF</name><description>Alarm A flag</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>INIT</name><description>Initialization mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>INITF</name><description>Initialization flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RSF</name><description>Registers synchronization               flag</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>INITS</name><description>Initialization status flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>SHPF</name><description>Shift operation pending</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>WUTWF</name><description>Wakeup timer write flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ALRBWF</name><description>Alarm B write flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ALRAWF</name><description>Alarm A write flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>PRER</name><displayName>PRER</displayName><description>prescaler register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x007F00FF</resetValue><fields><field><name>PREDIV_A</name><description>Asynchronous prescaler               factor</description><bitOffset>16</bitOffset><bitWidth>7</bitWidth></field><field><name>PREDIV_S</name><description>Synchronous prescaler               factor</description><bitOffset>0</bitOffset><bitWidth>15</bitWidth></field></fields></register><register><name>WUTR</name><displayName>WUTR</displayName><description>wakeup timer register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000FFFF</resetValue><fields><field><name>WUT</name><description>Wakeup auto-reload value               bits</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CALIBR</name><displayName>CALIBR</displayName><description>calibration register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DCS</name><description>Digital calibration sign</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>DC</name><description>Digital calibration</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>ALRMAR</name><displayName>ALRMAR</displayName><description>alarm A register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MSK4</name><description>Alarm A date mask</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>WDSEL</name><description>Week day selection</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>DT</name><description>Date tens in BCD format.</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>DU</name><description>Date units or day in BCD               format.</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK3</name><description>Alarm A hours mask</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>PM</name><description>AM/PM notation</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>HT</name><description>Hour tens in BCD format.</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>HU</name><description>Hour units in BCD format.</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK2</name><description>Alarm A minutes mask</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>MNT</name><description>Minute tens in BCD format.</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>MNU</name><description>Minute units in BCD               format.</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK1</name><description>Alarm A seconds mask</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ST</name><description>Second tens in BCD format.</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SU</name><description>Second units in BCD               format.</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>ALRMBR</name><displayName>ALRMBR</displayName><description>alarm B register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MSK4</name><description>Alarm B date mask</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>WDSEL</name><description>Week day selection</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>DT</name><description>Date tens in BCD format</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>DU</name><description>Date units or day in BCD               format</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK3</name><description>Alarm B hours mask</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>PM</name><description>AM/PM notation</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>HT</name><description>Hour tens in BCD format</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>HU</name><description>Hour units in BCD format</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK2</name><description>Alarm B minutes mask</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>MNT</name><description>Minute tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>MNU</name><description>Minute units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>MSK1</name><description>Alarm B seconds mask</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>ST</name><description>Second tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SU</name><description>Second units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>WPR</name><displayName>WPR</displayName><description>write protection register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>KEY</name><description>Write protection key</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>SSR</name><displayName>SSR</displayName><description>sub second register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>SS</name><description>Sub second value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>SHIFTR</name><displayName>SHIFTR</displayName><description>shift control register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>ADD1S</name><description>ADD1S</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field><field><name>SUBFS</name><description>Subtract a fraction of a               second</description><bitOffset>0</bitOffset><bitWidth>15</bitWidth></field></fields></register><register><name>TSTR</name><displayName>TSTR</displayName><description>TSTR</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>PM</name><description>AM/PM notation</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>HT</name><description>Hour tens in BCD format.</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>HU</name><description>Hour units in BCD format.</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>MNT</name><description>Minute tens in BCD format.</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>MNU</name><description>Minute units in BCD               format.</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>ST</name><description>Second tens in BCD format.</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SU</name><description>Second units in BCD               format.</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>TSDR</name><displayName>TSDR</displayName><description>time stamp date register</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>WDU</name><description>Week day units</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth></field><field><name>MT</name><description>Month tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>MU</name><description>Month units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>DT</name><description>Date tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DU</name><description>Date units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>TSSSR</name><displayName>TSSSR</displayName><description>timestamp sub second register</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>SS</name><description>Sub second value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CALR</name><displayName>CALR</displayName><description>calibration register</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CALP</name><description>Use an 8-second calibration cycle               period</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CALW8</name><description>Use a 16-second calibration cycle               period</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CALW16</name><description>CALW16</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>CALM</name><description>Calibration minus</description><bitOffset>0</bitOffset><bitWidth>9</bitWidth></field></fields></register><register><name>TAFCR</name><displayName>TAFCR</displayName><description>tamper and alternate function configuration           register</description><addressOffset>0x40</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ALARMOUTTYPE</name><description>AFO_ALARM output type</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMPPUDIS</name><description>TAMPER pull-up disable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMPPRCH</name><description>Tamper precharge duration</description><bitOffset>13</bitOffset><bitWidth>2</bitWidth></field><field><name>TAMPFLT</name><description>Tamper filter count</description><bitOffset>11</bitOffset><bitWidth>2</bitWidth></field><field><name>TAMPFREQ</name><description>Tamper sampling frequency</description><bitOffset>8</bitOffset><bitWidth>3</bitWidth></field><field><name>TAMPTS</name><description>Activate timestamp on tamper detection               event</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP3TRG</name><description>TAMPER1 mapping</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP3E</name><description>TIMESTAMP mapping</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP2TRG</name><description>Active level for tamper 2</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP2E</name><description>Tamper 2 detection enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMPIE</name><description>Tamper interrupt enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP1ETRG</name><description>Active level for tamper 1</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>TAMP1E</name><description>Tamper 1 detection enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ALRMASSR</name><displayName>ALRMASSR</displayName><description>alarm A sub second register</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MASKSS</name><description>Mask the most-significant bits starting               at this bit</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>SS</name><description>Sub seconds value</description><bitOffset>0</bitOffset><bitWidth>15</bitWidth></field></fields></register><register><name>ALRMBSSR</name><displayName>ALRMBSSR</displayName><description>alarm B sub second register</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>MASKSS</name><description>Mask the most-significant bits starting               at this bit</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>SS</name><description>Sub seconds value</description><bitOffset>0</bitOffset><bitWidth>15</bitWidth></field></fields></register><register><name>BKP0R</name><displayName>BKP0R</displayName><description>backup register</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP1R</name><displayName>BKP1R</displayName><description>backup register</description><addressOffset>0x54</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP2R</name><displayName>BKP2R</displayName><description>backup register</description><addressOffset>0x58</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP3R</name><displayName>BKP3R</displayName><description>backup register</description><addressOffset>0x5C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP4R</name><displayName>BKP4R</displayName><description>backup register</description><addressOffset>0x60</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP5R</name><displayName>BKP5R</displayName><description>backup register</description><addressOffset>0x64</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP6R</name><displayName>BKP6R</displayName><description>backup register</description><addressOffset>0x68</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP7R</name><displayName>BKP7R</displayName><description>backup register</description><addressOffset>0x6C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP8R</name><displayName>BKP8R</displayName><description>backup register</description><addressOffset>0x70</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP9R</name><displayName>BKP9R</displayName><description>backup register</description><addressOffset>0x74</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP10R</name><displayName>BKP10R</displayName><description>backup register</description><addressOffset>0x78</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP11R</name><displayName>BKP11R</displayName><description>backup register</description><addressOffset>0x7C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP12R</name><displayName>BKP12R</displayName><description>backup register</description><addressOffset>0x80</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP13R</name><displayName>BKP13R</displayName><description>backup register</description><addressOffset>0x84</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP14R</name><displayName>BKP14R</displayName><description>backup register</description><addressOffset>0x88</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP15R</name><displayName>BKP15R</displayName><description>backup register</description><addressOffset>0x8C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP16R</name><displayName>BKP16R</displayName><description>backup register</description><addressOffset>0x90</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP17R</name><displayName>BKP17R</displayName><description>backup register</description><addressOffset>0x94</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP18R</name><displayName>BKP18R</displayName><description>backup register</description><addressOffset>0x98</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP19R</name><displayName>BKP19R</displayName><description>backup register</description><addressOffset>0x9C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP20R</name><displayName>BKP20R</displayName><description>backup register</description><addressOffset>0xA0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP21R</name><displayName>BKP21R</displayName><description>backup register</description><addressOffset>0xA4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP22R</name><displayName>BKP22R</displayName><description>backup register</description><addressOffset>0xA8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP23R</name><displayName>BKP23R</displayName><description>backup register</description><addressOffset>0xAC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP24R</name><displayName>BKP24R</displayName><description>backup register</description><addressOffset>0xB0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP25R</name><displayName>BKP25R</displayName><description>backup register</description><addressOffset>0xB4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP26R</name><displayName>BKP26R</displayName><description>backup register</description><addressOffset>0xB8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP27R</name><displayName>BKP27R</displayName><description>backup register</description><addressOffset>0xBC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP28R</name><displayName>BKP28R</displayName><description>backup register</description><addressOffset>0xC0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP29R</name><displayName>BKP29R</displayName><description>backup register</description><addressOffset>0xC4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP30R</name><displayName>BKP30R</displayName><description>backup register</description><addressOffset>0xC8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>BKP31R</name><displayName>BKP31R</displayName><description>backup register</description><addressOffset>0xCC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>BKP</name><description>BKP</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>SPI1</name><description>Serial peripheral interface</description><groupName>SPI</groupName><baseAddress>0x40013000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>PVD</name><description>PVD through EXTI Line detection
        interrupt</description><value>1</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>BIDIMODE</name><description>Bidirectional data mode               enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>BIDIOE</name><description>Output enable in bidirectional               mode</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CRCEN</name><description>Hardware CRC calculation               enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>CRCNEXT</name><description>CRC transfer next</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>DFF</name><description>Data frame format</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>RXONLY</name><description>Receive only</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>SSM</name><description>Software slave management</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>SSI</name><description>Internal slave select</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>LSBFIRST</name><description>Frame format</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>SPE</name><description>SPI enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>BR</name><description>Baud rate control</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth></field><field><name>MSTR</name><description>Master selection</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CPOL</name><description>Clock polarity</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CPHA</name><description>Clock phase</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TXEIE</name><description>Tx buffer empty interrupt               enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>RXNEIE</name><description>RX buffer not empty interrupt               enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ERRIE</name><description>Error interrupt enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>FRF</name><description>Frame format</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>SSOE</name><description>SS output enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TXDMAEN</name><description>Tx buffer DMA enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>RXDMAEN</name><description>Rx buffer DMA enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x8</addressOffset><size>0x20</size><resetValue>0x0002</resetValue><fields><field><name>TIFRFE</name><description>TI frame format error</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>BSY</name><description>Busy flag</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>OVR</name><description>Overrun flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>MODF</name><description>Mode fault</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>CRCERR</name><description>CRC error flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>UDR</name><description>Underrun flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>CHSIDE</name><description>Channel side</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>TXE</name><description>Transmit buffer empty</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>RXNE</name><description>Receive buffer not empty</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>data register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>DR</name><description>Data register</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CRCPR</name><displayName>CRCPR</displayName><description>CRC polynomial register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0007</resetValue><fields><field><name>CRCPOLY</name><description>CRC polynomial register</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>RXCRCR</name><displayName>RXCRCR</displayName><description>RX CRC register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x0000</resetValue><fields><field><name>RxCRC</name><description>Rx CRC register</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>TXCRCR</name><displayName>TXCRCR</displayName><description>TX CRC register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x0000</resetValue><fields><field><name>TxCRC</name><description>Tx CRC register</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>I2SCFGR</name><displayName>I2SCFGR</displayName><description>I2S configuration register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>I2SMOD</name><description>I2S mode selection</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>I2SE</name><description>I2S Enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>I2SCFG</name><description>I2S configuration mode</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>PCMSYNC</name><description>PCM frame synchronization</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>I2SSTD</name><description>I2S standard selection</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>CKPOL</name><description>Steady state clock               polarity</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>DATLEN</name><description>Data length to be               transferred</description><bitOffset>1</bitOffset><bitWidth>2</bitWidth></field><field><name>CHLEN</name><description>Channel length (number of bits per audio               channel)</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>I2SPR</name><displayName>I2SPR</displayName><description>I2S prescaler register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000002</resetValue><fields><field><name>MCKOE</name><description>Master clock output enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ODD</name><description>Odd factor for the               prescaler</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>I2SDIV</name><description>I2S Linear prescaler</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="SPI1"><name>SPI2</name><baseAddress>0x40003800</baseAddress><interrupt><name>RCC</name><description>RCC global interrupt</description><value>5</value></interrupt></peripheral><peripheral><name>SYSCFG</name><description>System configuration controller</description><groupName>SYSCFG</groupName><baseAddress>0x40010000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><registers><register><name>MEMRMP</name><displayName>MEMRMP</displayName><description>memory remap register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>MEM_MODE</name><description>MEM_MODE</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>BOOT_MODE</name><description>BOOT_MODE</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth><access>read-only</access></field></fields></register><register><name>PMC</name><displayName>PMC</displayName><description>peripheral mode configuration           register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>USB_PU</name><description>USB pull-up</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EXTICR1</name><displayName>EXTICR1</displayName><description>external interrupt configuration register           1</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>EXTI3</name><description>EXTI x configuration (x = 0 to               3)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI2</name><description>EXTI x configuration (x = 0 to               3)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI1</name><description>EXTI x configuration (x = 0 to               3)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI0</name><description>EXTI x configuration (x = 0 to               3)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>EXTICR2</name><displayName>EXTICR2</displayName><description>external interrupt configuration register           2</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>EXTI7</name><description>EXTI x configuration (x = 4 to               7)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI6</name><description>EXTI x configuration (x = 4 to               7)</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI5</name><description>EXTI x configuration (x = 4 to               7)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI4</name><description>EXTI x configuration (x = 4 to               7)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>EXTICR3</name><displayName>EXTICR3</displayName><description>external interrupt configuration register           3</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>EXTI11</name><description>EXTI x configuration (x = 8 to               11)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI10</name><description>EXTI10</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI9</name><description>EXTI x configuration (x = 8 to               11)</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI8</name><description>EXTI x configuration (x = 8 to               11)</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>EXTICR4</name><displayName>EXTICR4</displayName><description>external interrupt configuration register           4</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>EXTI15</name><description>EXTI x configuration (x = 12 to               15)</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI14</name><description>EXTI14</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI13</name><description>EXTI13</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>EXTI12</name><description>EXTI12</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register></registers></peripheral><peripheral><name>TIM10</name><description>General-purpose timers</description><groupName>TIM</groupName><baseAddress>0x40010C00</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>RTC_WKUP</name><description>RTC Wakeup through EXTI line
        interrupt</description><value>3</value></interrupt><interrupt><name>RTC_Alarm</name><description>RTC Alarms (A and B) through EXTI line
        interrupt</description><value>41</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CKD</name><description>Clock division</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DIER</name><displayName>DIER</displayName><description>Interrupt enable register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x0000</resetValue><fields><field><name>CC1IE</name><description>Capture/Compare 1 interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIE</name><description>Update interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC1OF</name><description>Capture/compare 1 overcapture               flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1IF</name><description>Capture/Compare 1 interrupt               flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIF</name><description>Update interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EGR</name><displayName>EGR</displayName><description>event generation register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC1G</name><description>Capture/Compare 1               generation</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UG</name><description>Update generation</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCMR1_Output</name><displayName>CCMR1_Output</displayName><description>capture/compare mode register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>OC1M</name><description>Output compare 1 mode</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>OC1PE</name><description>Output compare 1 preload               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1FE</name><description>Output compare 1 fast               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCMR1_Input</name><displayName>CCMR1_Input</displayName><description>capture/compare mode register 1 (input           mode)</description><alternateRegister>CCMR1_Output</alternateRegister><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IC1F</name><description>Input capture 1 filter</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>ICPCS</name><description>Input capture 1 prescaler</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCER</name><displayName>CCER</displayName><description>capture/compare enable           register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC1NP</name><description>Capture/Compare 1 complementary output               Polarity</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1P</name><description>Capture/Compare 1 output               Polarity</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1E</name><description>Capture/Compare 1 output               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNT</name><displayName>CNT</displayName><description>counter</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CNT</name><description>TIM10 counter</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>PSC</name><displayName>PSC</displayName><description>prescaler</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>PSC</name><description>TIM9 prescaler</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ARR</name><displayName>ARR</displayName><description>auto-reload register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR1</name><displayName>CCR1</displayName><description>capture/compare register 1</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CCR1</name><description>Capture/Compare 1 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>OR</name><displayName>OR</displayName><description>option register</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TI1_RMP</name><description>TIM11 Input 1 remapping               capability</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="TIM10"><name>TIM11</name><baseAddress>0x40011000</baseAddress><interrupt><name>SPI1</name><description>SPI1 global interrupt</description><value>35</value></interrupt></peripheral><peripheral><name>TIM2</name><description>General-purpose timers</description><groupName>TIM</groupName><baseAddress>0x40000000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>SPI2</name><description>SPI2 global interrupt</description><value>36</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CKD</name><description>Clock division</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>CMS</name><description>Center-aligned mode               selection</description><bitOffset>5</bitOffset><bitWidth>2</bitWidth></field><field><name>DIR</name><description>Direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TI1S</name><description>TI1 selection</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>MMS</name><description>Master mode selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>CCDS</name><description>Capture/compare DMA               selection</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SMCR</name><displayName>SMCR</displayName><description>slave mode control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ETP</name><description>External trigger polarity</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>ECE</name><description>External clock enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>ETPS</name><description>External trigger prescaler</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>ETF</name><description>External trigger filter</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>MSM</name><description>Master/Slave mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>TS</name><description>Trigger selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>OCCS</name><description>OCREF clear selection</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>SMS</name><description>Slave mode selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>DIER</name><displayName>DIER</displayName><description>Interrupt enable register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x0000</resetValue><fields><field><name>TDE</name><description>Trigger DMA request enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4DE</name><description>Capture/Compare 4 DMA request               enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3DE</name><description>Capture/Compare 3 DMA request               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2DE</name><description>Capture/Compare 2 DMA request               enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1DE</name><description>Capture/Compare 1 DMA request               enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>UDE</name><description>Update DMA request enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>TIE</name><description>Trigger interrupt enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4IE</name><description>Capture/Compare 4 interrupt               enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3IE</name><description>Capture/Compare 3 interrupt               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2IE</name><description>Capture/Compare 2 interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1IE</name><description>Capture/Compare 1 interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIE</name><description>Update interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC4OF</name><description>Capture/compare 1 overcapture               flag</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3OF</name><description>Capture/compare 3 overcapture               flag</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2OF</name><description>Capture/compare 2 overcapture               flag</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1OF</name><description>Capture/compare 1 overcapture               flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIF</name><description>Trigger interrupt flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4IF</name><description>Capture/Compare 4 interrupt               flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3IF</name><description>Capture/Compare 3 interrupt               flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2IF</name><description>Capture/Compare 2 interrupt               flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1IF</name><description>Capture/Compare 1 interrupt               flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIF</name><description>Update interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EGR</name><displayName>EGR</displayName><description>event generation register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TG</name><description>Trigger generation</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4G</name><description>Capture/compare 4               generation</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3G</name><description>Capture/compare 3               generation</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2G</name><description>Capture/compare 2               generation</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1G</name><description>Capture/compare 1               generation</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UG</name><description>Update generation</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCMR1_Output</name><displayName>CCMR1_Output</displayName><description>capture/compare mode register           1</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>OC2CE</name><description>Output compare 2 clear               enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OC2M</name><description>Output compare 2 mode</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>OC2PE</name><description>Output compare 2 preload               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OC2FE</name><description>Output compare 2 fast               enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2S</name><description>Capture/Compare 2               selection</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1CE</name><description>Output compare 1 clear               enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1M</name><description>Output compare 1 mode</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>OC1PE</name><description>Output compare 1 preload               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1FE</name><description>Output compare 1 fast               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCMR1_Input</name><displayName>CCMR1_Input</displayName><description>capture/compare mode register 1 (input           mode)</description><alternateRegister>CCMR1_Output</alternateRegister><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IC2F</name><description>Input capture 2 filter</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>IC2PCS</name><description>Input capture 2 prescaler</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>CC2S</name><description>Capture/Compare 2               selection</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>IC1F</name><description>Input capture 1 filter</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>ICPCS</name><description>Input capture 1 prescaler</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCMR2_Output</name><displayName>CCMR2_Output</displayName><description>capture/compare mode register           2</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>OC4CE</name><description>Output compare 4 clear               enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OC4M</name><description>Output compare 4 mode</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>OC4PE</name><description>Output compare 4 preload               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OC4FE</name><description>Output compare 4 fast               enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4S</name><description>Capture/Compare 4               selection</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OC3CE</name><description>Output compare 3 clear               enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OC3M</name><description>Output compare 3 mode</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>OC3PE</name><description>Output compare 3 preload               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OC3FE</name><description>Output compare 3 fast               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3S</name><description>Capture/Compare 3               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCMR2_Input</name><displayName>CCMR2_Input</displayName><description>capture/compare mode register 2 (input           mode)</description><alternateRegister>CCMR2_Output</alternateRegister><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IC4F</name><description>Input capture 4 filter</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>IC4PSC</name><description>Input capture 4 prescaler</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>CC4S</name><description>Capture/Compare 4               selection</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>IC3F</name><description>Input capture 3 filter</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>IC3PSC</name><description>Input capture 3 prescaler</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>CC3S</name><description>Capture/compare 3               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCER</name><displayName>CCER</displayName><description>capture/compare enable           register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC4NP</name><description>Capture/Compare 4 output               Polarity</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4P</name><description>Capture/Compare 4 output               Polarity</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>CC4E</name><description>Capture/Compare 4 output               enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3NP</name><description>Capture/Compare 3 output               Polarity</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3P</name><description>Capture/Compare 3 output               Polarity</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>CC3E</name><description>Capture/Compare 3 output               enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2NP</name><description>Capture/Compare 2 output               Polarity</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2P</name><description>Capture/Compare 2 output               Polarity</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2E</name><description>Capture/Compare 2 output               enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1NP</name><description>Capture/Compare 1 complementary output               Polarity</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1P</name><description>Capture/Compare 1 output               Polarity</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1E</name><description>Capture/Compare 1 output               enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNT</name><displayName>CNT</displayName><description>counter</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CNT</name><description>TIM2 counter</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>PSC</name><displayName>PSC</displayName><description>prescaler</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>PSC</name><description>TIM2 prescaler</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ARR</name><displayName>ARR</displayName><description>auto-reload register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR1</name><displayName>CCR1</displayName><description>capture/compare register 1</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CCR1</name><description>Capture/Compare 1 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR2</name><displayName>CCR2</displayName><description>capture/compare register 1</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CCR2</name><description>Capture/Compare 2 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR3</name><displayName>CCR3</displayName><description>capture/compare register 1</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CCR1</name><description>Capture/Compare 1 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR4</name><displayName>CCR4</displayName><description>capture/compare register 1</description><addressOffset>0x40</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CCR4</name><description>Capture/Compare 4 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>DCR</name><displayName>DCR</displayName><description>DMA control register</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>DBL</name><description>DMA burst length</description><bitOffset>8</bitOffset><bitWidth>5</bitWidth></field><field><name>DBA</name><description>DMA base address</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>DMAR</name><displayName>DMAR</displayName><description>DMA address for full transfer</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>DMAB</name><description>DMA register for burst               accesses</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="TIM2"><name>TIM3</name><baseAddress>0x40000400</baseAddress><interrupt><name>SPI3</name><description>SPI3 global interrupt</description><value>46</value></interrupt></peripheral><peripheral derivedFrom="TIM2"><name>TIM4</name><baseAddress>0x40000800</baseAddress></peripheral><peripheral><name>TIM6</name><description>Basic timers</description><groupName>TIM</groupName><baseAddress>0x40001000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TIM10</name><description>TIM10 global interrupt</description><value>26</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>TIM6 control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>TIM6 control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>MMS</name><description>Master mode selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>DIER</name><displayName>DIER</displayName><description>TIM6 DMA/Interrupt enable           register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>UDE</name><description>Update DMA request enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>UIE</name><description>Update interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>TIM6 status register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>UIF</name><description>Update interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EGR</name><displayName>EGR</displayName><description>TIM6 event generation register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x0000</resetValue><fields><field><name>UG</name><description>Update generation</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CNT</name><displayName>CNT</displayName><description>TIM6 counter</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CNT</name><description>CNT</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>PSC</name><displayName>PSC</displayName><description>TIM6 prescaler</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>PSC</name><description>Prescaler valueThe counter clock               frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] +               1).</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ARR</name><displayName>ARR</displayName><description>TIM6 auto-reload register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ARR</name><description>Prescaler value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="TIM6"><name>TIM7</name><baseAddress>0x40001400</baseAddress><interrupt><name>TIM11</name><description>TIM11 global interrupt</description><value>27</value></interrupt></peripheral><peripheral><name>TIM9</name><description>General-purpose timers</description><groupName>TIM</groupName><baseAddress>0x40010800</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TIM2</name><description>TIM2 global interrupt</description><value>28</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CKD</name><description>Clock division</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OMP</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>MMS</name><description>Master mode selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>SMCR</name><displayName>SMCR</displayName><description>slave mode control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>MSM</name><description>Master/Slave mode</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>TS</name><description>Trigger selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SMS</name><description>Slave mode selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>DIER</name><displayName>DIER</displayName><description>Interrupt enable register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x0000</resetValue><fields><field><name>TIE</name><description>Trigger interrupt enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2IE</name><description>Capture/Compare 2 interrupt               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1IE</name><description>Capture/Compare 1 interrupt               enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIE</name><description>Update interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CC2OF</name><description>Capture/compare 2 overcapture               flag</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1OF</name><description>Capture/compare 1 overcapture               flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>TIF</name><description>Trigger interrupt flag</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2IF</name><description>Capture/Compare 2 interrupt               flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1IF</name><description>Capture/Compare 1 interrupt               flag</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UIF</name><description>Update interrupt flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EGR</name><displayName>EGR</displayName><description>event generation register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TG</name><description>Trigger generation</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2G</name><description>Capture/Compare 2               generation</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1G</name><description>Capture/Compare 1               generation</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>UG</name><description>Update generation</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CCMR1_Output</name><displayName>CCMR1_Output</displayName><description>capture/compare mode register           1</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>OC2CE</name><description>Output compare 2 clear               enable</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>OC2M</name><description>Output compare 2 mode</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>OC2PE</name><description>Output compare 2 preload               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OC2FE</name><description>Output compare 2 fast               enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CC2S</name><description>Capture/Compare 2               selection</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1CE</name><description>Output compare 1 clear               enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1M</name><description>Output compare 1 mode</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>OC1PE</name><description>Output compare 1 preload               enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>OC1FE</name><description>Output compare 1 fast               enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CCMR1_Input</name><displayName>CCMR1_Input</displayName><description>capture/compare mode register 1 (input           mode)</description><alternateRegister>CCMR1_Output</alternateRegister><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IC2F</name><description>Input capture 2 filter</description><bitOffset>12</bitOffset><bitWidth>4</bitWidth></field><field><name>IC2PCS</name><description>Input capture 2 prescaler</description><bitOffset>10</bitOffset><bitWidth>2</bitWidth></field><field><name>CC2S</name><description>Capture/Compare 2               selection</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>IC1F</name><description>Input capture 1 filter</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field><field><name>ICPCS</name><description>Input capture 1 prescaler</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth></field><field><name>CC1S</name><description>Capture/Compare 1               selection</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>CNT</name><displayName>CNT</displayName><description>counter</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CNT</name><description>TIM9 counter</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>PSC</name><displayName>PSC</displayName><description>prescaler</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>PSC</name><description>TIM9 prescaler</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>ARR</name><displayName>ARR</displayName><description>auto-reload register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR1</name><displayName>CCR1</displayName><description>capture/compare register 1</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CCR1</name><description>Capture/Compare 1 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>CCR2</name><displayName>CCR2</displayName><description>capture/compare register 2</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CCR2</name><description>Capture/Compare 2 value</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>OR</name><displayName>OR</displayName><description>option register</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>TI1_RMP</name><description>TIM9 Input 1 remapping               capability</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth></field></fields></register></registers></peripheral><peripheral><name>USART1</name><description>Universal synchronous asynchronous receiver       transmitter</description><groupName>USART</groupName><baseAddress>0x40013800</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TIM3</name><description>TIM3 global interrupt</description><value>29</value></interrupt><registers><register><name>SR</name><displayName>SR</displayName><description>Status register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00C00000</resetValue><fields><field><name>CTS</name><description>CTS flag</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>LBD</name><description>LIN break detection flag</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>TXE</name><description>Transmit data register               empty</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>TC</name><description>Transmission complete</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>RXNE</name><description>Read data register not               empty</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>IDLE</name><description>IDLE line detected</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ORE</name><description>Overrun error</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>NF</name><description>Noise detected flag</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>FE</name><description>Framing error</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>PE</name><description>Parity error</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>Data register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DR</name><description>Data value</description><bitOffset>0</bitOffset><bitWidth>9</bitWidth></field></fields></register><register><name>BRR</name><displayName>BRR</displayName><description>Baud rate register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DIV_Mantissa</name><description>mantissa of USARTDIV</description><bitOffset>4</bitOffset><bitWidth>12</bitWidth></field><field><name>DIV_Fraction</name><description>fraction of USARTDIV</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>CR1</name><displayName>CR1</displayName><description>Control register 1</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OVER8</name><description>Oversampling mode</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>UE</name><description>USART enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>M</name><description>Word length</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>WAKE</name><description>Wakeup method</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>PCE</name><description>Parity control enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>PS</name><description>Parity selection</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>PEIE</name><description>PE interrupt enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>TXEIE</name><description>TXE interrupt enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIE</name><description>Transmission complete interrupt               enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>RXNEIE</name><description>RXNE interrupt enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>IDLEIE</name><description>IDLE interrupt enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>TE</name><description>Transmitter enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>RE</name><description>Receiver enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>RWU</name><description>Receiver wakeup</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>SBK</name><description>Send break</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>Control register 2</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LINEN</name><description>LIN mode enable</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>STOP</name><description>STOP bits</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>CLKEN</name><description>Clock enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CPOL</name><description>Clock polarity</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CPHA</name><description>Clock phase</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>LBCL</name><description>Last bit clock pulse</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>LBDIE</name><description>LIN break detection interrupt               enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>LBDL</name><description>lin break detection length</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>ADD</name><description>Address of the USART node</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>CR3</name><displayName>CR3</displayName><description>Control register 3</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ONEBIT</name><description>One sample bit method               enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>CTSIE</name><description>CTS interrupt enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CTSE</name><description>CTS enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>RTSE</name><description>RTS enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAT</name><description>DMA enable transmitter</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAR</name><description>DMA enable receiver</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>SCEN</name><description>Smartcard mode enable</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>NACK</name><description>Smartcard NACK enable</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>HDSEL</name><description>Half-duplex selection</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>IRLP</name><description>IrDA low-power</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>IREN</name><description>IrDA mode enable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EIE</name><description>Error interrupt enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>GTPR</name><displayName>GTPR</displayName><description>Guard time and prescaler           register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>GT</name><description>Guard time value</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>PSC</name><description>Prescaler value</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="USART1"><name>USART2</name><baseAddress>0x40004400</baseAddress><interrupt><name>TIM4</name><description>TIM4 global interrupt</description><value>30</value></interrupt></peripheral><peripheral derivedFrom="USART1"><name>USART3</name><baseAddress>0x40004800</baseAddress><interrupt><name>TIM5</name><description>TIM5 global interrupt</description><value>45</value></interrupt></peripheral><peripheral><name>USB</name><description>Universal serial bus full-speed device       interface</description><groupName>USB</groupName><baseAddress>0x40005C00</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TIM6</name><description>TIM6 global interrupt</description><value>43</value></interrupt><registers><register><name>USB_EP0R</name><displayName>USB_EP0R</displayName><description>endpoint 0 register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP1R</name><displayName>USB_EP1R</displayName><description>endpoint 1 register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP2R</name><displayName>USB_EP2R</displayName><description>endpoint 2 register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP3R</name><displayName>USB_EP3R</displayName><description>endpoint 3 register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP4R</name><displayName>USB_EP4R</displayName><description>endpoint 4 register</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP5R</name><displayName>USB_EP5R</displayName><description>endpoint 5 register</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP6R</name><displayName>USB_EP6R</displayName><description>endpoint 6 register</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_EP7R</name><displayName>USB_EP7R</displayName><description>endpoint 7 register</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission               transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission               transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for               transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction               completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception               transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception               transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for               reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>USB_CNTR</name><displayName>USB_CNTR</displayName><description>control register</description><addressOffset>0x40</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000003</resetValue><fields><field><name>FRES</name><description>Force USB Reset</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>PDWN</name><description>Power down</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>LPMODE</name><description>Low-power mode</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>FSUSP</name><description>Force suspend</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>RESUME</name><description>Resume request</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>ESOFM</name><description>Expected start of frame interrupt               mask</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>SOFM</name><description>Start of frame interrupt               mask</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>RESETM</name><description>USB reset interrupt mask</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>SUSPM</name><description>Suspend mode interrupt               mask</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>WKUPM</name><description>Wakeup interrupt mask</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ERRM</name><description>Error interrupt mask</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>PMAOVRM</name><description>Packet memory area over / underrun               interrupt mask</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTRM</name><description>Correct transfer interrupt               mask</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>ISTR</name><displayName>ISTR</displayName><description>interrupt status register</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EP_ID</name><description>Endpoint Identifier</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>DIR</name><description>Direction of transaction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>ESOF</name><description>Expected start frame</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>SOF</name><description>start of frame</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>RESET</name><description>reset request</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>SUSP</name><description>Suspend mode request</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>WKUP</name><description>Wakeup</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ERR</name><description>Error</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>PMAOVR</name><description>Packet memory area over /               underrun</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR</name><description>Correct transfer</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>FNR</name><displayName>FNR</displayName><description>frame number register</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x0000</resetValue><fields><field><name>FN</name><description>Frame number</description><bitOffset>0</bitOffset><bitWidth>11</bitWidth></field><field><name>LSOF</name><description>Lost SOF</description><bitOffset>11</bitOffset><bitWidth>2</bitWidth></field><field><name>LCK</name><description>Locked</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>RXDM</name><description>Receive data - line status</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>RXDP</name><description>Receive data + line status</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DADDR</name><displayName>DADDR</displayName><description>device address</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>ADD</name><description>Device address</description><bitOffset>0</bitOffset><bitWidth>7</bitWidth></field><field><name>EF</name><description>Enable function</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>BTABLE</name><displayName>BTABLE</displayName><description>Buffer table address</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>BTABLE</name><description>Buffer table</description><bitOffset>3</bitOffset><bitWidth>13</bitWidth></field></fields></register></registers></peripheral><peripheral derivedFrom="USB"><name>USB_SRAM</name><baseAddress>0x40006000</baseAddress><interrupt><name>TIM7</name><description>TIM7 global interrupt</description><value>44</value></interrupt></peripheral><peripheral><name>WWDG</name><description>Window watchdog</description><groupName>WWDG</groupName><baseAddress>0x40002C00</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>TIM9</name><description>TIM9 global interrupt</description><value>25</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>Control register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x0000007F</resetValue><fields><field><name>WDGA</name><description>Activation bit</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>T</name><description>7-bit counter (MSB to LSB)</description><bitOffset>0</bitOffset><bitWidth>7</bitWidth><access>read-write</access></field></fields></register><register><name>CFR</name><displayName>CFR</displayName><description>Configuration register</description><addressOffset>0x4</addressOffset><size>0x20</size><resetValue>0x0000007F</resetValue><fields><field><name>EWI</name><description>Early wakeup interrupt</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>write-only</access></field><field><name>WDGTB1</name><description>Timer base</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>WDGTB0</name><description>WDGTB0</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>W</name><description>7-bit window value</description><bitOffset>0</bitOffset><bitWidth>7</bitWidth><access>read-write</access></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>SR</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EWIF</name><description>EWIF</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral><peripheral><name>ADC</name><description>Analog-to-digital converter</description><groupName>ADC</groupName><baseAddress>0x40012400</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>USART1</name><description>USART1 global interrupt</description><value>37</value></interrupt><registers><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>JCNR</name><description>Injected channel not ready</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>RCNR</name><description>Regular channel not ready</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>ADONS</name><description>ADC ON status</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>OVR</name><description>Overrun</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>STRT</name><description>Regular channel start flag</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>JSTRT</name><description>Injected channel start               flag</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>JEOC</name><description>Injected channel end of               conversion</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>EOC</name><description>Regular channel end of               conversion</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>AWD</name><description>Analog watchdog flag</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>OVRIE</name><description>Overrun interrupt enable</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>RES</name><description>Resolution</description><bitOffset>24</bitOffset><bitWidth>2</bitWidth></field><field><name>AWDEN</name><description>Analog watchdog enable on regular               channels</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>JAWDEN</name><description>Analog watchdog enable on injected               channels</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>PDI</name><description>Power down during the idle               phase</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>PDD</name><description>Power down during the delay               phase</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>DISCNUM</name><description>Discontinuous mode channel               count</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth></field><field><name>JDISCEN</name><description>Discontinuous mode on injected               channels</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>DISCEN</name><description>Discontinuous mode on regular               channels</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>JAUTO</name><description>Automatic injected group               conversion</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>AWDSGL</name><description>Enable the watchdog on a single channel               in scan mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>SCAN</name><description>Scan mode</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>JEOCIE</name><description>Interrupt enable for injected               channels</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>AWDIE</name><description>Analog watchdog interrupt               enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>EOCIE</name><description>Interrupt enable for EOC</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>AWDCH</name><description>Analog watchdog channel select               bits</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>control register 2</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SWSTART</name><description>Start conversion of regular               channels</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth></field><field><name>EXTEN</name><description>External trigger enable for regular               channels</description><bitOffset>28</bitOffset><bitWidth>2</bitWidth></field><field><name>EXTSEL</name><description>External event select for regular               group</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth></field><field><name>JSWSTART</name><description>Start conversion of injected               channels</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>JEXTEN</name><description>External trigger enable for injected               channels</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>JEXTSEL</name><description>External event select for injected               group</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>ALIGN</name><description>Data alignment</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>EOCS</name><description>End of conversion               selection</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>DDS</name><description>DMA disable selection</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>DMA</name><description>Direct memory access mode</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>DELS</name><description>Delay selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>ADC_CFG</name><description>ADC configuration</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CONT</name><description>Continuous conversion</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>ADON</name><description>A/D Converter ON / OFF</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SMPR1</name><displayName>SMPR1</displayName><description>sample time register 1</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SampletimebitsSMPx_x</name><description>Reserved</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>SMPR2</name><displayName>SMPR2</displayName><description>sample time register 2</description><addressOffset>0x10</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SampletimebitsSMPx_x</name><description>Reserved</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>SMPR3</name><displayName>SMPR3</displayName><description>sample time register 3</description><addressOffset>0x14</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SampletimebitsSMPx_x</name><description>Reserved</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>JOFR1</name><displayName>JOFR1</displayName><description>injected channel data offset register           x</description><addressOffset>0x18</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>JOFFSET1</name><description>Data offset for injected channel               x</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>JOFR2</name><displayName>JOFR2</displayName><description>injected channel data offset register           x</description><addressOffset>0x1C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>JOFFSET2</name><description>Data offset for injected channel               x</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>JOFR3</name><displayName>JOFR3</displayName><description>injected channel data offset register           x</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>JOFFSET3</name><description>Data offset for injected channel               x</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>JOFR4</name><displayName>JOFR4</displayName><description>injected channel data offset register           x</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>JOFFSET4</name><description>Data offset for injected channel               x</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>HTR</name><displayName>HTR</displayName><description>watchdog higher threshold           register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000FFF</resetValue><fields><field><name>HT</name><description>Analog watchdog higher               threshold</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>LTR</name><displayName>LTR</displayName><description>watchdog lower threshold           register</description><addressOffset>0x2C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>LT</name><description>Analog watchdog lower               threshold</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field></fields></register><register><name>SQR1</name><displayName>SQR1</displayName><description>regular sequence register 1</description><addressOffset>0x30</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>L</name><description>Regular channel sequence               length</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>SQ28</name><description>28th conversion in regular               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ27</name><description>27th conversion in regular               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ26</name><description>26th conversion in regular               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ25</name><description>25th conversion in regular               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>SQR2</name><displayName>SQR2</displayName><description>regular sequence register 2</description><addressOffset>0x34</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SQ24</name><description>24th conversion in regular               sequence</description><bitOffset>25</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ23</name><description>23rd conversion in regular               sequence</description><bitOffset>20</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ22</name><description>22nd conversion in regular               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ21</name><description>21st conversion in regular               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ20</name><description>20th conversion in regular               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ19</name><description>19th conversion in regular               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>SQR3</name><displayName>SQR3</displayName><description>regular sequence register 3</description><addressOffset>0x38</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SQ18</name><description>18th conversion in regular               sequence</description><bitOffset>25</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ17</name><description>17th conversion in regular               sequence</description><bitOffset>20</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ16</name><description>16th conversion in regular               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ15</name><description>15th conversion in regular               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ14</name><description>14th conversion in regular               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ13</name><description>13th conversion in regular               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>SQR4</name><displayName>SQR4</displayName><description>regular sequence register 4</description><addressOffset>0x3C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SQ12</name><description>12th conversion in regular               sequence</description><bitOffset>25</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ11</name><description>11th conversion in regular               sequence</description><bitOffset>20</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ10</name><description>10th conversion in regular               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ9</name><description>9th conversion in regular               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ8</name><description>8th conversion in regular               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ7</name><description>7th conversion in regular               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>SQR5</name><displayName>SQR5</displayName><description>regular sequence register 5</description><addressOffset>0x40</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SQ6</name><description>6th conversion in regular               sequence</description><bitOffset>25</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ5</name><description>5th conversion in regular               sequence</description><bitOffset>20</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ4</name><description>4th conversion in regular               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ3</name><description>3rd conversion in regular               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ2</name><description>2nd conversion in regular               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>SQ1</name><description>1st conversion in regular               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>JSQR</name><displayName>JSQR</displayName><description>injected sequence register</description><addressOffset>0x44</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>JL</name><description>Injected sequence length</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>JSQ4</name><description>4th conversion in injected               sequence</description><bitOffset>15</bitOffset><bitWidth>5</bitWidth></field><field><name>JSQ3</name><description>3rd conversion in injected               sequence</description><bitOffset>10</bitOffset><bitWidth>5</bitWidth></field><field><name>JSQ2</name><description>2nd conversion in injected               sequence</description><bitOffset>5</bitOffset><bitWidth>5</bitWidth></field><field><name>JSQ1</name><description>1st conversion in injected               sequence</description><bitOffset>0</bitOffset><bitWidth>5</bitWidth></field></fields></register><register><name>JDR1</name><displayName>JDR1</displayName><description>injected data register x</description><addressOffset>0x48</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>JDATA</name><description>Injected data</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>JDR2</name><displayName>JDR2</displayName><description>injected data register x</description><addressOffset>0x4C</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>JDATA</name><description>Injected data</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>JDR3</name><displayName>JDR3</displayName><description>injected data register x</description><addressOffset>0x50</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>JDATA</name><description>Injected data</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>JDR4</name><displayName>JDR4</displayName><description>injected data register x</description><addressOffset>0x54</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>JDATA</name><description>Injected data</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>regular data register</description><addressOffset>0x58</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>RegularDATA</name><description>Regular data</description><bitOffset>0</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>SMPR0</name><displayName>SMPR0</displayName><description>sample time register 0</description><addressOffset>0x5C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SampletimebitsSMPx_x</name><description>Reserved</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>NVIC</name><description>Nested Vectored Interrupt       Controller</description><groupName>NVIC</groupName><baseAddress>0xE000E000</baseAddress><addressBlock><offset>0x0</offset><size>0x1001</size><usage>registers</usage></addressBlock><interrupt><name>USART2</name><description>USART2 global interrupt</description><value>38</value></interrupt><registers><register><name>ICTR</name><displayName>ICTR</displayName><description>Interrupt Controller Type           Register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>INTLINESNUM</name><description>Total number of interrupt lines in               groups</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>STIR</name><displayName>STIR</displayName><description>Software Triggered Interrupt           Register</description><addressOffset>0xF00</addressOffset><size>0x20</size><access>write-only</access><resetValue>0x00000000</resetValue><fields><field><name>INTID</name><description>interrupt to be triggered</description><bitOffset>0</bitOffset><bitWidth>9</bitWidth></field></fields></register><register><name>ISER0</name><displayName>ISER0</displayName><description>Interrupt Set-Enable Register</description><addressOffset>0x100</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SETENA</name><description>SETENA</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ISER1</name><displayName>ISER1</displayName><description>Interrupt Set-Enable Register</description><addressOffset>0x104</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SETENA</name><description>SETENA</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ICER0</name><displayName>ICER0</displayName><description>Interrupt Clear-Enable           Register</description><addressOffset>0x180</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CLRENA</name><description>CLRENA</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ICER1</name><displayName>ICER1</displayName><description>Interrupt Clear-Enable           Register</description><addressOffset>0x184</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CLRENA</name><description>CLRENA</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ISPR0</name><displayName>ISPR0</displayName><description>Interrupt Set-Pending Register</description><addressOffset>0x200</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SETPEND</name><description>SETPEND</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ISPR1</name><displayName>ISPR1</displayName><description>Interrupt Set-Pending Register</description><addressOffset>0x204</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SETPEND</name><description>SETPEND</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ICPR0</name><displayName>ICPR0</displayName><description>Interrupt Clear-Pending           Register</description><addressOffset>0x280</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CLRPEND</name><description>CLRPEND</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>ICPR1</name><displayName>ICPR1</displayName><description>Interrupt Clear-Pending           Register</description><addressOffset>0x284</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>CLRPEND</name><description>CLRPEND</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>IABR0</name><displayName>IABR0</displayName><description>Interrupt Active Bit Register</description><addressOffset>0x300</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>ACTIVE</name><description>ACTIVE</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>IABR1</name><displayName>IABR1</displayName><description>Interrupt Active Bit Register</description><addressOffset>0x304</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>ACTIVE</name><description>ACTIVE</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>IPR0</name><displayName>IPR0</displayName><description>Interrupt Priority Register</description><addressOffset>0x400</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR1</name><displayName>IPR1</displayName><description>Interrupt Priority Register</description><addressOffset>0x404</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR2</name><displayName>IPR2</displayName><description>Interrupt Priority Register</description><addressOffset>0x408</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR3</name><displayName>IPR3</displayName><description>Interrupt Priority Register</description><addressOffset>0x40C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR4</name><displayName>IPR4</displayName><description>Interrupt Priority Register</description><addressOffset>0x410</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR5</name><displayName>IPR5</displayName><description>Interrupt Priority Register</description><addressOffset>0x414</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR6</name><displayName>IPR6</displayName><description>Interrupt Priority Register</description><addressOffset>0x418</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR7</name><displayName>IPR7</displayName><description>Interrupt Priority Register</description><addressOffset>0x41C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR8</name><displayName>IPR8</displayName><description>Interrupt Priority Register</description><addressOffset>0x420</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR9</name><displayName>IPR9</displayName><description>Interrupt Priority Register</description><addressOffset>0x424</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR10</name><displayName>IPR10</displayName><description>Interrupt Priority Register</description><addressOffset>0x428</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR11</name><displayName>IPR11</displayName><description>Interrupt Priority Register</description><addressOffset>0x42C</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR12</name><displayName>IPR12</displayName><description>Interrupt Priority Register</description><addressOffset>0x430</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register><register><name>IPR13</name><displayName>IPR13</displayName><description>Interrupt Priority Register</description><addressOffset>0x434</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>IPR_N0</name><description>IPR_N0</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N1</name><description>IPR_N1</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N2</name><description>IPR_N2</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth></field><field><name>IPR_N3</name><description>IPR_N3</description><bitOffset>24</bitOffset><bitWidth>8</bitWidth></field></fields></register></registers></peripheral><peripheral><name>DBG</name><description>Debug support</description><groupName>DBG</groupName><baseAddress>0xE0042000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>USART3</name><description>USART3 global interrupt</description><value>39</value></interrupt><registers><register><name>DBGMCU_IDCODE</name><displayName>DBGMCU_IDCODE</displayName><description>IDCODE</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x10006411</resetValue><fields><field><name>DEV_ID</name><description>DEV_ID</description><bitOffset>0</bitOffset><bitWidth>12</bitWidth></field><field><name>REV_ID</name><description>REV_ID</description><bitOffset>16</bitOffset><bitWidth>16</bitWidth></field></fields></register><register><name>DBGMCU_CR</name><displayName>DBGMCU_CR</displayName><description>Control Register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DBG_SLEEP</name><description>DBG_SLEEP</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_STOP</name><description>DBG_STOP</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_STANDBY</name><description>DBG_STANDBY</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>TRACE_IOEN</name><description>TRACE_IOEN</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>TRACE_MODE</name><description>TRACE_MODE</description><bitOffset>6</bitOffset><bitWidth>2</bitWidth></field><field><name>DBG_I2C2_SMBUS_TIMEOUT</name><description>DBG_I2C2_SMBUS_TIMEOUT</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM8_STOP</name><description>DBG_TIM8_STOP</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM5_STOP</name><description>DBG_TIM5_STOP</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM6_STOP</name><description>DBG_TIM6_STOP</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM7_STOP</name><description>DBG_TIM7_STOP</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DBGMCU_APB1_FZ</name><displayName>DBGMCU_APB1_FZ</displayName><description>Debug MCU APB1 Freeze registe</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DBG_TIM2_STOP</name><description>DBG_TIM2_STOP</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM3_STOP</name><description>DBG_TIM3 _STOP</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM4_STOP</name><description>DBG_TIM4_STOP</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM5_STOP</name><description>DBG_TIM5_STOP</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM6_STOP</name><description>DBG_TIM6_STOP</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM7_STOP</name><description>DBG_TIM7_STOP</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM12_STOP</name><description>DBG_TIM12_STOP</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM13_STOP</name><description>DBG_TIM13_STOP</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM14_STOP</name><description>DBG_TIM14_STOP</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_WWDG_STOP</name><description>DBG_WWDG_STOP</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_IWDEG_STOP</name><description>DBG_IWDEG_STOP</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_J2C1_SMBUS_TIMEOUT</name><description>DBG_J2C1_SMBUS_TIMEOUT</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_J2C2_SMBUS_TIMEOUT</name><description>DBG_J2C2_SMBUS_TIMEOUT</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_J2C3SMBUS_TIMEOUT</name><description>DBG_J2C3SMBUS_TIMEOUT</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_CAN1_STOP</name><description>DBG_CAN1_STOP</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_CAN2_STOP</name><description>DBG_CAN2_STOP</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>DBGMCU_APB2_FZ</name><displayName>DBGMCU_APB2_FZ</displayName><description>Debug MCU APB2 Freeze registe</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>DBG_TIM1_STOP</name><description>TIM1 counter stopped when core is               halted</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM8_STOP</name><description>TIM8 counter stopped when core is               halted</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM9_STOP</name><description>TIM9 counter stopped when core is               halted</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM10_STOP</name><description>TIM10 counter stopped when core is               halted</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>DBG_TIM11_STOP</name><description>TIM11 counter stopped when core is               halted</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field></fields></register></registers></peripheral></peripherals></device>