27878 lines
1.1 MiB
27878 lines
1.1 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>LPC15xx</name>
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<version>0.7</version>
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<description>LPC15xx Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM</description>
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<cpu>
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<name>CM3</name>
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<revision>r2p1</revision>
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<endian>little</endian>
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<mpuPresent>0</mpuPresent>
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<fpuPresent>0</fpuPresent>
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<nvicPrioBits>3</nvicPrioBits>
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<vendorSystickConfig>0</vendorSystickConfig>
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</cpu>
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<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<!--
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Software that is described herein is for illustrative purposes only
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which provides customers with programming information regarding the
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products. This software is supplied "AS IS" without any warranties.
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NXP Semiconductors assumes no responsibility or liability for the
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use of the software, conveys no license or title under any patent,
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copyright, or mask work right to the product. NXP Semiconductors
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reserves the right to make changes in the software without
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notification. NXP Semiconductors also make no representation or
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warranty that such application will be suitable for the specified
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use without further testing or modification.
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-->
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<!--
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v0.3 changes
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PINMUX changed to INPUT MUX; register names changed to INMUX
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part name canged to LPC15xx
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v0.4 changes
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CAN prefix removed from CAN registers
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iocon updated with glitch filter registers
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v0.5 changes
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USART register map updated with minUSART v2 IP version
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v0.6 changes
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C_CAN register map corrected - IF2_DAx and IF2_DBx registers added
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-->
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<peripherals>
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<peripheral>
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<name>GPIO_PORT</name>
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<description>General Purpose I/O (GPIO) </description>
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<groupName>GPIO</groupName>
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<baseAddress>0x1C000000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x3FFFF</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<dim>76</dim>
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<dimIncrement>0x1</dimIncrement>
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<dimIndex>0-75</dimIndex>
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<name>B[%s]</name>
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<displayName>B[%s]</displayName>
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<description>Byte pin registers</description>
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<addressOffset>0x0000</addressOffset>
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<size>8</size>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>PBYTE</name>
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<description>Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<dim>76</dim>
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<dimIncrement>0x4</dimIncrement>
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<dimIndex>0-75</dimIndex>
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<name>W[%s]</name>
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<displayName>W[%s]</displayName>
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<description>Word pin registers </description>
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<addressOffset>0x1000</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>PWORD</name>
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<description>Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<dim>3</dim>
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<dimIncrement>0x4</dimIncrement>
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<dimIndex>0-2</dimIndex>
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<name>DIR[%s]</name>
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<displayName>DIR[%s]</displayName>
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<description>Port Direction registers </description>
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<addressOffset>0x2000</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>DIRP0</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>DIRP1</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>DIRP2</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>DIRP3</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>DIRP4</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>DIRP5</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[5:5]</bitRange>
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</field>
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<field>
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<name>DIRP6</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[6:6]</bitRange>
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</field>
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<field>
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<name>DIRP7</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[7:7]</bitRange>
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</field>
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<field>
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<name>DIRP8</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[8:8]</bitRange>
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</field>
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<field>
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<name>DIRP9</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[9:9]</bitRange>
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</field>
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<field>
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<name>DIRP10</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[10:10]</bitRange>
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</field>
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<field>
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<name>DIRP11</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[11:11]</bitRange>
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</field>
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<field>
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<name>DIRP12</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[12:12]</bitRange>
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</field>
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<field>
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<name>DIRP13</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[13:13]</bitRange>
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</field>
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<field>
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<name>DIRP14</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[14:14]</bitRange>
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</field>
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<field>
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<name>DIRP15</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[15:15]</bitRange>
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</field>
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<field>
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<name>DIRP16</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[16:16]</bitRange>
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</field>
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<field>
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<name>DIRP17</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[17:17]</bitRange>
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</field>
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<field>
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<name>DIRP18</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[18:18]</bitRange>
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</field>
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<field>
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<name>DIRP19</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[19:19]</bitRange>
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</field>
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<field>
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<name>DIRP20</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[20:20]</bitRange>
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</field>
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<field>
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<name>DIRP21</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[21:21]</bitRange>
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</field>
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<field>
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<name>DIRP22</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[22:22]</bitRange>
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</field>
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<field>
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<name>DIRP23</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[23:23]</bitRange>
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</field>
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<field>
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<name>DIRP24</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[24:24]</bitRange>
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</field>
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<field>
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<name>DIRP25</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[25:25]</bitRange>
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</field>
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<field>
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<name>DIRP26</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[26:26]</bitRange>
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</field>
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<field>
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<name>DIRP27</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[27:27]</bitRange>
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</field>
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<field>
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<name>DIRP28</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[28:28]</bitRange>
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</field>
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<field>
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<name>DIRP29</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[29:29]</bitRange>
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</field>
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<field>
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<name>DIRP30</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[30:30]</bitRange>
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</field>
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<field>
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<name>DIRP31</name>
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<description>Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output.</description>
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<bitRange>[31:31]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<dim>3</dim>
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<dimIncrement>0x4</dimIncrement>
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<dimIndex>0-2</dimIndex>
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<name>MASK[%s]</name>
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<displayName>MASK[%s]</displayName>
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<description>Port Mask register </description>
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<addressOffset>0x2080</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>MASKP0</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>MASKP1</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>MASKP2</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>MASKP3</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>MASKP4</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>MASKP5</name>
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<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
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<bitRange>[5:5]</bitRange>
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</field>
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<field>
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<name>MASKP6</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP7</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP8</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP9</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP10</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP11</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP12</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP13</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP14</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP15</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP16</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP17</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP18</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP19</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP20</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP21</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP22</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP23</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP24</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP25</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP26</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP27</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP28</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP29</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP30</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP31</name>
|
|
<description>Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>PIN[%s]</name>
|
|
<displayName>PIN[%s]</displayName>
|
|
<description>Port pin register </description>
|
|
<addressOffset>0x2100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORT0</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT1</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT2</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT3</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT4</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT5</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT6</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT7</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT8</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT9</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT10</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT11</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT12</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT13</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT14</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT15</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT16</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT17</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT18</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT19</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT20</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT21</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT22</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT23</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT24</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT25</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT26</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT27</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT28</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT29</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT30</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT31</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>MPIN[%s]</name>
|
|
<displayName>MPIN[%s]</displayName>
|
|
<description>Masked port register </description>
|
|
<addressOffset>0x2180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPORTP0</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP1</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP2</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP3</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP4</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP5</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP6</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP7</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP8</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP9</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP10</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP11</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP12</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP13</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP14</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP15</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP16</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP17</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP18</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP19</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP20</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP21</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP22</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP23</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP24</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP25</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP26</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP27</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP28</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP29</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP30</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP31</name>
|
|
<description>Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SET[%s]</name>
|
|
<displayName>SET[%s]</displayName>
|
|
<description>Write: Set port register Read: port output bits </description>
|
|
<addressOffset>0x2200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETP00</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP01</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP02</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP03</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP04</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP05</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP06</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP07</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP08</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP09</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP010</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP011</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP012</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP013</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP014</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP015</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP016</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP017</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP018</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP019</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP020</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP021</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP022</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP023</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP024</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP025</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP026</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP027</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP028</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP029</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP030</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP031</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>CLR[%s]</name>
|
|
<displayName>CLR[%s]</displayName>
|
|
<description>Clear port</description>
|
|
<addressOffset>0x2280</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRP00</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP01</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP02</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP03</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP04</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP05</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP06</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP07</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP08</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP09</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP010</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP011</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP012</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP013</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP014</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP015</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP016</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP017</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP018</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP019</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP020</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP021</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP022</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP023</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP024</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP025</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP026</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP027</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP028</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP029</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP030</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP031</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>NOT[%s]</name>
|
|
<displayName>NOT[%s]</displayName>
|
|
<description>Toggle port </description>
|
|
<addressOffset>0x2300</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOTP00</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP01</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP02</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP03</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP04</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP05</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP06</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP07</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP08</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP09</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP010</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP011</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP012</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP013</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP014</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP015</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP016</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP017</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP018</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP019</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP020</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP021</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP022</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP023</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP024</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP025</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP026</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP027</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP028</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP029</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP030</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP031</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>DMA controller</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x1C004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DMA control.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>DMA controller master enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The DMA controller is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt status.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEINT</name>
|
|
<description>Summarizes whether any enabled interrupts are pending.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. No enabled interrupts are pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. At least one enabled interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEERRINT</name>
|
|
<description>Summarizes whether any error interrupts are pending.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. No error interrupts are pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. At least one error interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRAMBASE</name>
|
|
<description>SRAM address of the channel configuration table.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET</name>
|
|
<description>Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLESET0</name>
|
|
<description>Channel Enable read and Set for all DMA channels.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA0</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA1</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA2</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA3</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA4</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA5</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA6</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA7</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA8</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA9</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA10</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA11</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA12</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA13</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA14</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA15</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA16</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA17</name>
|
|
<description>Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLECLR0</name>
|
|
<description>Channel Enable Clear for all DMA channels.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR0</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR1</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR2</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR3</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR4</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR5</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR6</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR7</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR8</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR9</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR10</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR11</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR12</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR13</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR14</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR15</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR16</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR17</name>
|
|
<description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTIVE0</name>
|
|
<description>Channel Active status for all DMA channels.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACT0</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT1</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT2</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT3</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT4</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT5</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT6</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT7</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT8</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT9</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT10</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT11</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT12</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT13</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT14</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT15</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT16</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT17</name>
|
|
<description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUSY0</name>
|
|
<description>Channel Busy status for all DMA channels.</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BSY0</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY1</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY2</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY3</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY4</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY5</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY6</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY7</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY8</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY9</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY10</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY11</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY12</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY13</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY14</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY15</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY16</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY17</name>
|
|
<description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRINT0</name>
|
|
<description>Error Interrupt status for all DMA channels.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR0</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR1</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR2</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR3</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR4</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR5</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR6</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR7</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR8</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR9</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR10</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR11</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR12</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR13</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR14</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR15</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR16</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR17</name>
|
|
<description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET0</name>
|
|
<description>Interrupt Enable read and Set for all DMA channels.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET0</name>
|
|
<description>0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET1</name>
|
|
<description>0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET2</name>
|
|
<description>0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET3</name>
|
|
<description>0</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET4</name>
|
|
<description>0</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET5</name>
|
|
<description>0</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET6</name>
|
|
<description>0</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET7</name>
|
|
<description>0</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET8</name>
|
|
<description>0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET9</name>
|
|
<description>0</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET10</name>
|
|
<description>0</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET11</name>
|
|
<description>0</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET12</name>
|
|
<description>0</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET13</name>
|
|
<description>0</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET14</name>
|
|
<description>0</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET15</name>
|
|
<description>0</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET16</name>
|
|
<description>0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET17</name>
|
|
<description>0</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR0</name>
|
|
<description>Interrupt Enable Clear for all DMA channels.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR0</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR1</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR2</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR3</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR4</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR5</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR6</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR7</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR8</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR9</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR10</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR11</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR12</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR13</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR14</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR15</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR16</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR17</name>
|
|
<description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTA0</name>
|
|
<description>Interrupt A status for all DMA channels.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IA0</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA1</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA2</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA3</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA4</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA5</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA6</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA7</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA8</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA9</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA10</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA11</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA12</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA13</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA14</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA15</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA16</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IA17</name>
|
|
<description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTB0</name>
|
|
<description>Interrupt B status for all DMA channels.</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IB0</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB1</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB2</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB3</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB4</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB5</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB6</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB7</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB8</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB9</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB10</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB11</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB12</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB13</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB14</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB15</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB16</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IB17</name>
|
|
<description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETVALID0</name>
|
|
<description>Set ValidPending control bits for all DMA channels.</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SV0</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV1</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV2</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV3</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV4</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV5</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV6</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV7</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV8</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV9</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV10</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV11</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV12</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV13</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV14</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV15</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV16</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SV17</name>
|
|
<description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETTRIG0</name>
|
|
<description>Set Trigger control bits for all DMA channels.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETTRIG0</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG1</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG2</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG3</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG4</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG5</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG6</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG7</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG8</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG9</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG10</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG11</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG12</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG13</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG14</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG15</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG16</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETTRIG17</name>
|
|
<description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ABORT0</name>
|
|
<description>Channel Abort control for all DMA channels.</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AORTCTRL0</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL1</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL2</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL3</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL4</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL5</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL6</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL7</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL8</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL9</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL10</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL11</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL12</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL13</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL14</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL15</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL16</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AORTCTRL17</name>
|
|
<description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>18</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-17</dimIndex>
|
|
<name>CFG%s</name>
|
|
<description>Configuration register for DMA channel 0.</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHREQEN</name>
|
|
<description>Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Peripheral DMA requests are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Peripheral DMA requests are enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWTRIGEN</name>
|
|
<description>Hardware Triggering Enable for this channel.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Hardware triggering is not used.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Use hardware triggering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIGPOL</name>
|
|
<description>Trigger Polarity. Selects the polarity of a hardware trigger for this channel.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_LOW__FALLING</name>
|
|
<description>Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH__RISING</name>
|
|
<description>Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGTYPE</name>
|
|
<description>Trigger Type. Selects hardware trigger as edge triggered or level triggered.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Edge. Hardware trigger is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGBURST</name>
|
|
<description>Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_TRANSFER</name>
|
|
<description>Single transfer. Hardware trigger causes a single transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST_TRANSFER</name>
|
|
<description>Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURSTPOWER</name>
|
|
<description>Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRCBURSTWRAP</name>
|
|
<description>Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Source burst wrapping is not enabled for this DMA channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Source burst wrapping is enabled for this DMA channel.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSTBURSTWRAP</name>
|
|
<description>Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Destination burst wrapping is not enabled for this DMA channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Destination burst wrapping is enabled for this DMA channel.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHPRIORITY</name>
|
|
<description>Priority of this channel when multiple DMA requests are pending. This description reflects a 3-bit priority field giving 8 priority levels. A specific instance of the SDMA might have anywhere from 2 to 16 priority levels (1 to 4 bits for the CH_PRIORITY field). 0x0 = highest priority. 0x7 = lowest priority.</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>18</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-17</dimIndex>
|
|
<name>CTLSTAT%s</name>
|
|
<description>Control and status register for DMA channel 0.</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALIDPENDING</name>
|
|
<description>Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT_ON_DMA_OPE</name>
|
|
<description>No effect on DMA operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID_PENDING</name>
|
|
<description>Valid pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_TRIGGERED</name>
|
|
<description>Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGERED</name>
|
|
<description>Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>18</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-17</dimIndex>
|
|
<name>XFERCFG%s</name>
|
|
<description>Transfer configuration register for DMA channel 0.</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CFGVALID</name>
|
|
<description>Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_VALID</name>
|
|
<description>Not valid. The current channel descriptor is not considered valid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Valid. The current channel descriptor is considered valid.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Reload the channels' control structure when the current descriptor is exhausted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WHEN_WRITTEN_BY_SOFT</name>
|
|
<description>When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WHEN_WRITTEN_BY_SOFT</name>
|
|
<description>When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRTRIG</name>
|
|
<description>Clear Trigger.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_CLEARED</name>
|
|
<description>Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEARED</name>
|
|
<description>Cleared. The trigger is cleared when this descriptor is exhausted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETINTA</name>
|
|
<description>Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. The INTA flag for this channel will be set when the current descriptor is exhausted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETINTB</name>
|
|
<description>Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. The INTB flag for this channel will be set when the current descriptor is exhausted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Transfer width used for this DMA channel.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_TRANSFERS_ARE</name>
|
|
<description>8-bit transfers are performed (8-bit source reads and destination writes).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_TRANSFERS_ARE</name>
|
|
<description>16-bit transfers are performed (16-bit source reads and destination writes).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_BIT_TRANSFERS_ARE</name>
|
|
<description>32-bit transfers are performed (32-bit source reads and destination writes).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved setting, do not use.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRCINC</name>
|
|
<description>Determines whether the source address is incremented for each DMA transfer.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INCREMENT</name>
|
|
<description>No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_X_WIDTH</name>
|
|
<description>1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_X_WIDTH</name>
|
|
<description>2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_X_WIDTH</name>
|
|
<description>4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSTINC</name>
|
|
<description>Determines whether the destination address is incremented for each DMA transfer.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INCREMENT</name>
|
|
<description>No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_X_WIDTH</name>
|
|
<description>1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_X_WIDTH</name>
|
|
<description>2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_X_WIDTH</name>
|
|
<description>4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XFERCOUNT</name>
|
|
<description>Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description>USB device controller</description>
|
|
<groupName>USB</groupName>
|
|
<baseAddress>0x1C00C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB_IRQ</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_FIQ</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBWAKEUP</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DEVCMDSTAT</name>
|
|
<description>USB Device Command/Status register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_ADDR</name>
|
|
<description>USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DEV_EN</name>
|
|
<description>USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PLL_ON</name>
|
|
<description>USB Clock/PLL control.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USB_NEEDCLK_FUNCTION</name>
|
|
<description>USB_NeedClk functional</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_NEEDCLK_ALWAYS_1</name>
|
|
<description>USB_NeedClk always 1. Clock will not be stopped in case of suspend.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_SUP</name>
|
|
<description>LPM Support.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LPM_NOT_SUPPORTED</name>
|
|
<description>LPM not supported.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_SUPPORTED</name>
|
|
<description>LPM supported.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_AO</name>
|
|
<description>Interrupt on NAK for interrupt and bulk OUT EP</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ONLY_ACKNOWLEDGED_PA</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_ACKNOWLEDGED_AN</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_AI</name>
|
|
<description>Interrupt on NAK for interrupt and bulk IN EP</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ONLY_ACKNOWLEDGED_PA</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_ACKNOWLEDGED_AN</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_CO</name>
|
|
<description>Interrupt on NAK for control OUT EP</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ONLY_ACKNOWLEDGED_PA</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_ACKNOWLEDGED_AN</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_CI</name>
|
|
<description>Interrupt on NAK for control IN EP</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ONLY_ACKNOWLEDGED_PA</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_ACKNOWLEDGED_AN</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCON</name>
|
|
<description>Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSUS</name>
|
|
<description>Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_SUS</name>
|
|
<description>Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_REWP</name>
|
|
<description>LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCON_C</name>
|
|
<description>Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSUS_C</name>
|
|
<description>Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DRES_C</name>
|
|
<description>Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VBUSDEBOUNCED</name>
|
|
<description>This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INFO</name>
|
|
<description>USB Info register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAME_NR</name>
|
|
<description>Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERR_CODE</name>
|
|
<description>The error code which last occurred:</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PID_ENCODING_ERROR</name>
|
|
<description>PID encoding error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PID_UNKNOWN</name>
|
|
<description>PID unknown</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET_UNEXPECTED</name>
|
|
<description>Packet unexpected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOKEN_CRC_ERROR</name>
|
|
<description>Token CRC error</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_CRC_ERROR</name>
|
|
<description>Data CRC error</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIME_OUT</name>
|
|
<description>Time out</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BABBLE</name>
|
|
<description>Babble</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRUNCATED_EOP</name>
|
|
<description>Truncated EOP</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENT_RECEIVED_NAK</name>
|
|
<description>Sent/Received NAK</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENT_STALL</name>
|
|
<description>Sent Stall</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENT_EMPTY_PACKET</name>
|
|
<description>Sent empty packet</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BITSTUFF_ERROR</name>
|
|
<description>Bitstuff error</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC_ERROR</name>
|
|
<description>Sync error</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRONG_DATA_TOGGLE</name>
|
|
<description>Wrong data toggle</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPLISTSTART</name>
|
|
<description>USB EP Command/Status List start address</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_LIST</name>
|
|
<description>Start address of the USB EP Command/Status List.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATABUFSTART</name>
|
|
<description>USB Data buffer start address</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[21:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DA_BUF</name>
|
|
<description>Start address of the buffer pointer page where all endpoint data buffers are located.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPM</name>
|
|
<description>Link Power Management register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HIRD_HW</name>
|
|
<description>Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIRD_SW</name>
|
|
<description>Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_PENDING</name>
|
|
<description>As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPSKIP</name>
|
|
<description>USB Endpoint skip</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SKIP</name>
|
|
<description>Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINUSE</name>
|
|
<description>USB Endpoint Buffer in use</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUF</name>
|
|
<description>Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1.</description>
|
|
<bitRange>[9:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPBUFCFG</name>
|
|
<description>USB Endpoint Buffer Configuration register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUF_SB</name>
|
|
<description>Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer.</description>
|
|
<bitRange>[9:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>USB interrupt status register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP0OUT</name>
|
|
<description>Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP0IN</name>
|
|
<description>Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP1OUT</name>
|
|
<description>Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP1IN</name>
|
|
<description>Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP2OUT</name>
|
|
<description>Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP2IN</name>
|
|
<description>Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP3OUT</name>
|
|
<description>Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP3IN</name>
|
|
<description>Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP4OUT</name>
|
|
<description>Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP4IN</name>
|
|
<description>Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_INT</name>
|
|
<description>Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_INT</name>
|
|
<description>Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>USB interrupt enable register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSETSTAT</name>
|
|
<description>USB set interrupt status register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTROUTING</name>
|
|
<description>USB interrupt routing register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ROUTE_INT9_0</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROUTE_INT30</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROUTE_INT31</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPTOGGLE</name>
|
|
<description>USB Endpoint toggle register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Cyclic Redundancy Check (CRC) engine</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x1C010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>CRC mode register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_POLY</name>
|
|
<description>CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BIT_RVS_WR</name>
|
|
<description>Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMPL_WR</name>
|
|
<description>Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BIT_RVS_SUM</name>
|
|
<description>CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMPL_SUM</name>
|
|
<description>CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Reserved</name>
|
|
<description>Always 0 when read</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEED</name>
|
|
<description>CRC seed register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_SEED</name>
|
|
<description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUM</name>
|
|
<description>CRC checksum register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_SUM</name>
|
|
<description>The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WR_DATA</name>
|
|
<description>CRC data register</description>
|
|
<alternateRegister>SUM</alternateRegister>
|
|
<addressOffset>0x08</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_WR_DATA</name>
|
|
<description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>SCT0</name>
|
|
<description>Large State Configurable Timers 0/1 (SCT0/1)</description>
|
|
<groupName>SCT0</groupName>
|
|
<baseAddress>0x1C018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SCT0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>SCT configuration register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00007E00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNIFY</name>
|
|
<description>SCT operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SCT_OPERATES_AS</name>
|
|
<description>The SCT operates as two 16-bit counters named L and H.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SCT_OPERATES_AS</name>
|
|
<description>The SCT operates as a unified 32-bit counter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKMODE</name>
|
|
<description>SCT clock mode</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_CLOCK</name>
|
|
<description>System clock. The system clock clocks the SCT and prescalers.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALED_SYSTEM_CLO</name>
|
|
<description>Prescaled system clock. The SCT clock is the system clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_INPUT</name>
|
|
<description>SCT input. The input selected by CLKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALED_SCT_INPUT</name>
|
|
<description>Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CLKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can the same or faster than the system clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>SCT clock select</description>
|
|
<bitRange>[6:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 3.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 4.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 4.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 5.</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 5.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 6.</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 6.</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 7.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 7.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NORELAOD_L</name>
|
|
<description>A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NORELOAD_H</name>
|
|
<description>A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INSYNC</name>
|
|
<description>Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.</description>
|
|
<bitRange>[16:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOLIMIT_L</name>
|
|
<description>A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOLIMIT_H</name>
|
|
<description>A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>SCT control register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00040004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOWN_L</name>
|
|
<description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP_L</name>
|
|
<description>When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HALT_L</name>
|
|
<description>When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLRCTR_L</name>
|
|
<description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIDIR_L</name>
|
|
<description>L or unified counter direction select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_COUNTS_U</name>
|
|
<description>The counter counts up to its limit condition, then is cleared to zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_COUNTS_U</name>
|
|
<description>The counter counts up to its limit, then counts down to a limit condition or to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_L</name>
|
|
<description>Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
|
|
<bitRange>[12:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOWN_H</name>
|
|
<description>This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP_H</name>
|
|
<description>When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HALT_H</name>
|
|
<description>When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLRCTR_H</name>
|
|
<description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIDIR_H</name>
|
|
<description>Direction select</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_H_COUNTER_COUNTS</name>
|
|
<description>The H counter counts up to its limit condition, then is cleared to zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_H_COUNTER_COUNTS</name>
|
|
<description>The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_H</name>
|
|
<description>Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMIT</name>
|
|
<description>SCT limit register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMMSK_L</name>
|
|
<description>If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LIMMSK_H</name>
|
|
<description>If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HALT</name>
|
|
<description>SCT halt condition register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALTMSK_L</name>
|
|
<description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HALTMSK_H</name>
|
|
<description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STOP</name>
|
|
<description>SCT stop condition register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPMSK_L</name>
|
|
<description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STOPMSK_H</name>
|
|
<description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>START</name>
|
|
<description>SCT start condition register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTMSK_L</name>
|
|
<description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTMSK_H</name>
|
|
<description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DITHER</name>
|
|
<description>SCT dither condition register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DITHMSK_L</name>
|
|
<description>If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DITHMSK_H</name>
|
|
<description>If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>SCT counter register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTR_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CTR_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>SCT state register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE_L</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATE_H</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>SCT input register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AIN0</name>
|
|
<description>Real-time status of input 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN1</name>
|
|
<description>Real-time status of input 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN2</name>
|
|
<description>Real-time status of input 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN3</name>
|
|
<description>Real-time status of input 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN4</name>
|
|
<description>Real-time status of input 4.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN5</name>
|
|
<description>Real-time status of input 5.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN6</name>
|
|
<description>Real-time status of input 6.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN7</name>
|
|
<description>Real-time status of input 7.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN0</name>
|
|
<description>Input 0 state synchronized to the SCT clock.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN1</name>
|
|
<description>Input 1 state synchronized to the SCT clock.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN2</name>
|
|
<description>Input 2 state synchronized to the SCT clock.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN3</name>
|
|
<description>Input 3 state synchronized to the SCT clock.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN4</name>
|
|
<description>Input 4 state synchronized to the SCT clock.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN5</name>
|
|
<description>Input 5 state synchronized to the SCT clock.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN6</name>
|
|
<description>Input 6 state synchronized to the SCT clock.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN7</name>
|
|
<description>Input 7 state synchronized to the SCT clock.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGMODE</name>
|
|
<description>SCT match/capture registers mode register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGMOD_L</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REGMOD_H</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT</name>
|
|
<description>SCT output register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUTDIRCTRL</name>
|
|
<description>SCT output counter direction control register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETCLR0</name>
|
|
<description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR1</name>
|
|
<description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR2</name>
|
|
<description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR3</name>
|
|
<description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR4</name>
|
|
<description>Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR5</name>
|
|
<description>Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR6</name>
|
|
<description>Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR7</name>
|
|
<description>Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR8</name>
|
|
<description>Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR9</name>
|
|
<description>Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RES</name>
|
|
<description>SCT conflict resolution register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>O0RES</name>
|
|
<description>Effect of simultaneous set and clear on output 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR0 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR0 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O1RES</name>
|
|
<description>Effect of simultaneous set and clear on output 1.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR1 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR1 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O2RES</name>
|
|
<description>Effect of simultaneous set and clear on output 2.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR2 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_N_OR_S</name>
|
|
<description>Clear output n (or set based on the SETCLR2 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O3RES</name>
|
|
<description>Effect of simultaneous set and clear on output 3.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR3 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR3 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O4RES</name>
|
|
<description>Effect of simultaneous set and clear on output 4.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR4 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR4 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O5RES</name>
|
|
<description>Effect of simultaneous set and clear on output 5.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR5 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR5 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O6RES</name>
|
|
<description>Effect of simultaneous set and clear on output 6.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR6 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR6 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O7RES</name>
|
|
<description>Effect of simultaneous set and clear on output 7.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR7 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR7 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O8RES</name>
|
|
<description>Effect of simultaneous set and clear on output 8.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR8 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR8 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O9RES</name>
|
|
<description>Effect of simultaneous set and clear on output 9.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR9 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR9 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ0</name>
|
|
<description>SCT DMA request 0 register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_0</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL0</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ0</name>
|
|
<description>This read-only bit indicates the state of DMA Request 0</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ1</name>
|
|
<description>SCT DMA request 1 register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_1</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL1</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ1</name>
|
|
<description>This read-only bit indicates the state of DMA Request 1.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVEN</name>
|
|
<description>SCT event enable register</description>
|
|
<addressOffset>0x0F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IEN</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVFLAG</name>
|
|
<description>SCT event flag register</description>
|
|
<addressOffset>0x0F4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLAG</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONEN</name>
|
|
<description>SCT conflict enable register</description>
|
|
<addressOffset>0x0F8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCEN</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFLAG</name>
|
|
<description>SCT conflict flag register</description>
|
|
<addressOffset>0x0FC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCFLAG</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 9 = bit 9).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRL</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRH</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>MATCH%s</name>
|
|
<description>SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCHn_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MATCHn_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>FRACMAT%s</name>
|
|
<description>Fractional match registers 0 to 5 for SCT match value registers 0 to 5.</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACMAT_L</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRACMAT_H</name>
|
|
<description>When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>CAP%s</name>
|
|
<description>SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1</description>
|
|
<alternateRegister>MATCH%s</alternateRegister>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPn_L</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPn_H</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>MATCHREL%s</name>
|
|
<description>SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOADn_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RELOADn_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>FRACMATREL%s</name>
|
|
<description>Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELFRAC_L</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RELFRAC_H</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>CAPCTRL%s</name>
|
|
<description>SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1</description>
|
|
<alternateRegister>MATCHREL%s</alternateRegister>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPCONn_L</name>
|
|
<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPCONn_H</name>
|
|
<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>EV%s_STATE</name>
|
|
<description>SCT event state register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATEMSKn</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>EV%s_CTRL</name>
|
|
<description>SCT event control register 0</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCHSEL</name>
|
|
<description>Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HEVENT</name>
|
|
<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_L_STATE</name>
|
|
<description>Selects the L state and the L match register selected by MATCHSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_H_STATE</name>
|
|
<description>Selects the H state and the H match register selected by MATCHSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTSEL</name>
|
|
<description>Input/output select</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_INPUT_SE</name>
|
|
<description>Selects the input selected by IOSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_OUTPUT_S</name>
|
|
<description>Selects the output selected by IOSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOSEL</name>
|
|
<description>Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOCOND</name>
|
|
<description>Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>LOW</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rise</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Fall</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>HIGH</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBMODE</name>
|
|
<description>Selects how the specified match and I/O condition are used and combined.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR</name>
|
|
<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>MATCH. Uses the specified match only.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>IO. Uses the specified I/O condition only.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND</name>
|
|
<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATELD</name>
|
|
<description>This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_ADDE</name>
|
|
<description>STATEV value is added into STATE (the carry-out is ignored).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_LOAD</name>
|
|
<description>STATEV value is loaded into STATE.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATEV</name>
|
|
<description>This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.</description>
|
|
<bitRange>[19:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MATCHMEM</name>
|
|
<description>If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTION</name>
|
|
<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECTION_INDEPENDEN</name>
|
|
<description>Direction independent. This event is triggered regardless of the count direction.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_UP</name>
|
|
<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_DOWN</name>
|
|
<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:23]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>10</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>OUT%s_SET</name>
|
|
<description>SCT output 0 set register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>10</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>OUT%s_CLR</name>
|
|
<description>SCT output 0 clear register</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="SCT0">
|
|
<name>SCT1</name>
|
|
<description>SCT1</description>
|
|
<baseAddress>0x1C01C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SCT1</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCT2</name>
|
|
<description>Small State Configurable Timers 2/3 (SCT2/3) </description>
|
|
<groupName>SCT2</groupName>
|
|
<baseAddress>0x1C020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SCT2</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>SCT configuration register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00007E00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNIFY</name>
|
|
<description>SCT operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SCT_OPERATES_AS</name>
|
|
<description>The SCT operates as two 16-bit counters named L and H.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SCT_OPERATES_AS</name>
|
|
<description>The SCT operates as a unified 32-bit counter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKMODE</name>
|
|
<description>SCT clock mode</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_BUS_CLOCK_CLOCKS</name>
|
|
<description>The bus clock clocks the SCT and prescalers.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SCT_CLOCK_IS_THE</name>
|
|
<description>The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_INPUT_SELECTED_B</name>
|
|
<description>The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.This is not reserved on the LPC15xx. Need to add back in from spec.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>SCT clock select</description>
|
|
<bitRange>[6:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGES_ON_INPU</name>
|
|
<description>Rising edges on input 3.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGES_ON_INP</name>
|
|
<description>Falling edges on input 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NORELAOD_L</name>
|
|
<description>A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NORELOAD_H</name>
|
|
<description>A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INSYNC</name>
|
|
<description>Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.</description>
|
|
<bitRange>[16:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOLIMIT_L</name>
|
|
<description>A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOLIMIT_H</name>
|
|
<description>A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>SCT control register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00040004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOWN_L</name>
|
|
<description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP_L</name>
|
|
<description>When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HALT_L</name>
|
|
<description>When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLRCTR_L</name>
|
|
<description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIDIR_L</name>
|
|
<description>L or unified counter direction select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_COUNTS_U</name>
|
|
<description>The counter counts up to its limit condition, then is cleared to zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_COUNTS_U</name>
|
|
<description>The counter counts up to its limit, then counts down to a limit condition or to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_L</name>
|
|
<description>Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
|
|
<bitRange>[12:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOWN_H</name>
|
|
<description>This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP_H</name>
|
|
<description>When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HALT_H</name>
|
|
<description>When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLRCTR_H</name>
|
|
<description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIDIR_H</name>
|
|
<description>Direction select</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_H_COUNTER_COUNTS</name>
|
|
<description>The H counter counts up to its limit condition, then is cleared to zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_H_COUNTER_COUNTS</name>
|
|
<description>The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_H</name>
|
|
<description>Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMIT</name>
|
|
<description>SCT limit register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMMSK_L</name>
|
|
<description>If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LIMMSK_H</name>
|
|
<description>If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HALT</name>
|
|
<description>SCT halt condition register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALTMSK_L</name>
|
|
<description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HALTMSK_H</name>
|
|
<description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STOP</name>
|
|
<description>SCT stop condition register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPMSK_L</name>
|
|
<description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STOPMSK_H</name>
|
|
<description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>START</name>
|
|
<description>SCT start condition register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTMSK_L</name>
|
|
<description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTMSK_H</name>
|
|
<description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>SCT counter register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTR_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CTR_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>SCT state register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE_L</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATE_H</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>SCT input register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AIN0</name>
|
|
<description>Real-time status of input 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN1</name>
|
|
<description>Real-time status of input 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN2</name>
|
|
<description>Real-time status of input 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN3</name>
|
|
<description>Real-time status of input 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN0</name>
|
|
<description>Input 0 state synchronized to the SCT clock.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN1</name>
|
|
<description>Input 1 state synchronized to the SCT clock.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN2</name>
|
|
<description>Input 2 state synchronized to the SCT clock.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN3</name>
|
|
<description>Input 3 state synchronized to the SCT clock.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGMODE</name>
|
|
<description>SCT match/capture registers mode register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGMOD_L</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REGMOD_H</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT</name>
|
|
<description>SCT output register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 5 = bit 5).</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUTDIRCTRL</name>
|
|
<description>SCT output counter direction control register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETCLR0</name>
|
|
<description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR1</name>
|
|
<description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR2</name>
|
|
<description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR3</name>
|
|
<description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR4</name>
|
|
<description>Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR5</name>
|
|
<description>Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_DO_NOT</name>
|
|
<description>Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_AND_CLEAR_ARE_RE</name>
|
|
<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RES</name>
|
|
<description>SCT conflict resolution register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>O0RES</name>
|
|
<description>Effect of simultaneous set and clear on output 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR0 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR0 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O1RES</name>
|
|
<description>Effect of simultaneous set and clear on output 1.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR1 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR1 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O2RES</name>
|
|
<description>Effect of simultaneous set and clear on output 2.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR2 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_N_OR_S</name>
|
|
<description>Clear output n (or set based on the SETCLR2 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O3RES</name>
|
|
<description>Effect of simultaneous set and clear on output 3.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR3 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR3 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O4RES</name>
|
|
<description>Effect of simultaneous set and clear on output 4.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR4 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR4 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O5RES</name>
|
|
<description>Effect of simultaneous set and clear on output 5.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR5 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR5 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ0</name>
|
|
<description>SCT DMA request 0 register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_0</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL0</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ0</name>
|
|
<description>This read-only bit indicates the state of DMA Request 0</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ1</name>
|
|
<description>SCT DMA request 1 register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_1</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL1</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ1</name>
|
|
<description>This read-only bit indicates the state of DMA Request 1.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVEN</name>
|
|
<description>SCT event enable register</description>
|
|
<addressOffset>0x0F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IEN</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVFLAG</name>
|
|
<description>SCT event flag register</description>
|
|
<addressOffset>0x0F4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLAG</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONEN</name>
|
|
<description>SCT conflict enable register</description>
|
|
<addressOffset>0x0F8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCEN</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFLAG</name>
|
|
<description>SCT conflict flag register</description>
|
|
<addressOffset>0x0FC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCFLAG</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 5 = bit 5).</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRL</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRH</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MATCH%s</name>
|
|
<description>SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCHn_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MATCHn_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CAP%s</name>
|
|
<description>SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 = 1</description>
|
|
<alternateRegister>MATCH%s</alternateRegister>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPn_L</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPn_H</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MATCHREL%s</name>
|
|
<description>SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOADn_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RELOADn_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CAPCTRL%s</name>
|
|
<description>SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 = 1</description>
|
|
<alternateRegister>MATCHREL%s</alternateRegister>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPCONn_L</name>
|
|
<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPCONn_H</name>
|
|
<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 9 = bit 24).</description>
|
|
<bitRange>[24:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:25]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>10</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>EV%s_STATE</name>
|
|
<description>SCT event state register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATEMSKn</name>
|
|
<description>If bit m is one, event n (n= 0 to 9) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 9 = bit 9).</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>10</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-9</dimIndex>
|
|
<name>EV%s_CTRL</name>
|
|
<description>SCT event control register 0</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCHSEL</name>
|
|
<description>Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HEVENT</name>
|
|
<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_L_STATE</name>
|
|
<description>Selects the L state and the L match register selected by MATCHSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_H_STATE</name>
|
|
<description>Selects the H state and the H match register selected by MATCHSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTSEL</name>
|
|
<description>Input/output select</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_INPUTS_E</name>
|
|
<description>Selects the inputs elected by IOSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_THE_OUTPUTS</name>
|
|
<description>Selects the outputs selected by IOSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOSEL</name>
|
|
<description>Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOCOND</name>
|
|
<description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>LOW</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rise</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Fall</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>HIGH</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBMODE</name>
|
|
<description>Selects how the specified match and I/O condition are used and combined.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR</name>
|
|
<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>MATCH. Uses the specified match only.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>IO. Uses the specified I/O condition only.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND</name>
|
|
<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATELD</name>
|
|
<description>This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_ADDE</name>
|
|
<description>STATEV value is added into STATE (the carry-out is ignored).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_LOAD</name>
|
|
<description>STATEV value is loaded into STATE.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATEV</name>
|
|
<description>This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.</description>
|
|
<bitRange>[19:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MATCHMEM</name>
|
|
<description>If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTION</name>
|
|
<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECTION_INDEPENDEN</name>
|
|
<description>Direction independent. This event is triggered regardless of the count direction.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_UP</name>
|
|
<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_DOWN</name>
|
|
<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:23]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>OUT%s_SET</name>
|
|
<description>SCT output 0 set register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>OUT%s_CLR</name>
|
|
<description>SCT output 0 clear register</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 9 = bit 9.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="SCT2">
|
|
<name>SCT3</name>
|
|
<description>SCT3</description>
|
|
<baseAddress>0x1C024000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SCT3</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>12-bit ADC controller ADC0/1 </description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0_SEQA</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC0_SEQB</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC0_THCMP</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC0_OVR</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode). Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASYNMODE</name>
|
|
<description>Select clock mode.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_MODE</name>
|
|
<description>Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit set, sampling of the A/D input and start of conversion will initiate exactly 2 system clocks after the leading edge of a (synchronous) trigger pulse.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS_MODE</name>
|
|
<description>Asynchronous mode. The ADC clock is based on the output of the asynchronous ADC clock divider ADCASYNCCLKSEL in the SYSCON block. The frequency of this clock is limited to 50 MHz max (100 MHz in 10-bit mode). In addition, the ADC clock must never be faster than 10x the system clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10BIT</name>
|
|
<description>Select 10-bit conversion. In 10-bit mode higher conversion rates of up to 100 MHz are supported. A/D resolution is reduced to ten bits, but the clock rate (set via the CLKDIV field) can be increased up to 100 MHz to achieve a conversion rate of up to four million samples per second. The two LSBs of the result data are forced to zero.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The 10-bit/high-conversion rate mode is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The 10-bit/high-conversion rate is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPWRMODE</name>
|
|
<description>Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The low-power ADC mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CALMODE</name>
|
|
<description>Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INSEL</name>
|
|
<description>A/D Input Select Register: Selects between external pin and internal source for various channels</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD0SEL</name>
|
|
<description>This field selects the input source for channel 0. All other values are reserved.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ADCN_0_PIN</name>
|
|
<description>ADCn_0 pin. Voltage on ADC channel 0 input.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CORE_VOLTAGE_REGULAT</name>
|
|
<description>Core voltage regulator output (1.2V to 1.8V). If the WRAPEN field is 0x2, the core voltage regulator output is also is output on the ADC0/1_0 pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_VOLTAGE_REF</name>
|
|
<description>Internal voltage reference. If the WRAPEN field is 0x2, the internal voltage reference is also is output on the ADCn_0 pin.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMPERATURE_SENSOR</name>
|
|
<description>Temperature Sensor. If the WRAPEN field is 0x2, the temperature sensor voltage is also is output on the ADCn_0 pin.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDADIV2</name>
|
|
<description>VDDA/2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CONNECTION_OR_LOA</name>
|
|
<description>No connection or load</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQA_CTRL</name>
|
|
<description>A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNELS</name>
|
|
<description>Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER</name>
|
|
<description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIGPOL</name>
|
|
<description>Select the polarity of the selected input trigger for this conversion sequence.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE_EDGE</name>
|
|
<description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE_EDGE</name>
|
|
<description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCBYPASS</name>
|
|
<description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SYNCHRONIZATI</name>
|
|
<description>Enable synchronization. The hardware trigger bypass is not enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS_SYNCHRONIZATI</name>
|
|
<description>Bypass synchronization. The hardware trigger bypass is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[25:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SINGLESTEP</name>
|
|
<description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LOWPRIO</name>
|
|
<description>Set priority for sequence A.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW_PRIORITY</name>
|
|
<description>Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_PRIORITY</name>
|
|
<description>High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below:</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>END_OF_CONVERSION</name>
|
|
<description>End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END_OF_SEQUENCE</name>
|
|
<description>End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEQA_ENA</name>
|
|
<description>Sequence Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Sequence A is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQB_CTRL</name>
|
|
<description>A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNELS</name>
|
|
<description>Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER</name>
|
|
<description>Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIGPOL</name>
|
|
<description>Select the polarity of the selected input trigger for this conversion sequence.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE_EDGE</name>
|
|
<description>Negative edge. A negative edge launches the conversion sequence on the selected trigger input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE_EDGE</name>
|
|
<description>Positive edge. A positive edge launches the conversion sequence on the selected trigger input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCBYPASS</name>
|
|
<description>Setting this bit allows the hardware trigger input to bypass synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SYNCHRONIZATI</name>
|
|
<description>Enable synchronization. The hardware trigger bypass is not enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS_SYNCHRONIZATI</name>
|
|
<description>Bypass synchronization. The hardware trigger bypass is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[25:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SINGLESTEP</name>
|
|
<description>When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below:</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>END_OF_CONVERSION</name>
|
|
<description>End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END_OF_SEQUENCE</name>
|
|
<description>End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEQB_ENA</name>
|
|
<description>Sequence Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Sequence B is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQA_GDAT</name>
|
|
<description>A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is the a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPRANGE</name>
|
|
<description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPCROSS</name>
|
|
<description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[25:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...).</description>
|
|
<bitRange>[29:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled).</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAVALID</name>
|
|
<description>This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEQB_GDAT</name>
|
|
<description>A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register. This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP. DATAVALID = 1 indicates that this result has not yet been read.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPRANGE</name>
|
|
<description>Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH). Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPCROSS</name>
|
|
<description>Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[25:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...).</description>
|
|
<bitRange>[29:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled).</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAVALID</name>
|
|
<description>This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-11</dimIndex>
|
|
<name>DAT[%s]</name>
|
|
<displayName>DAT[%s]</displayName>
|
|
<description>A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPRANGE</name>
|
|
<description>Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMPCROSS</name>
|
|
<description>Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[25:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL</name>
|
|
<description>This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)</description>
|
|
<bitRange>[29:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAVALID</name>
|
|
<description>This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR0_LOW</name>
|
|
<description>A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRLOW</name>
|
|
<description>Low threshold value against which A/D results will be compared</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR1_LOW</name>
|
|
<description>A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRLOW</name>
|
|
<description>Low threshold value against which A/D results will be compared</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR0_HIGH</name>
|
|
<description>A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRHIGH</name>
|
|
<description>High threshold value against which A/D results will be compared</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR1_HIGH</name>
|
|
<description>A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRHIGH</name>
|
|
<description>High threshold value against which A/D results will be compared</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHAN_THRSEL</name>
|
|
<description>A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11_THRSEL</name>
|
|
<description>Threshold select by channel.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_0</name>
|
|
<description>Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD_1</name>
|
|
<description>Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEQA_INTEN</name>
|
|
<description>Sequence A interrupt enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The sequence A interrupt/DMA request is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEQB_INTEN</name>
|
|
<description>Sequence B interrupt enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The sequence B interrupt/DMA request is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVR_INTEN</name>
|
|
<description>Overrun interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The overrun interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN0</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN1</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN2</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN3</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN4</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN5</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN6</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[16:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN7</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN8</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[20:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN9</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN10</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[24:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCMPINTEN11</name>
|
|
<description>Threshold comparison interrupt enable.</description>
|
|
<bitRange>[26:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTSIDE_THRESHOLD</name>
|
|
<description>Outside threshold.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CROSSING_THRESHOLD</name>
|
|
<description>Crossing threshold.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLAGS</name>
|
|
<description>A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THCMP0</name>
|
|
<description>Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP1</name>
|
|
<description>Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP2</name>
|
|
<description>Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP3</name>
|
|
<description>Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP4</name>
|
|
<description>Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP5</name>
|
|
<description>Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP6</name>
|
|
<description>Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP7</name>
|
|
<description>Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP8</name>
|
|
<description>Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP9</name>
|
|
<description>Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP10</name>
|
|
<description>Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP11</name>
|
|
<description>Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN0</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 0</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN1</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 1</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN2</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 2</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN3</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 3</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN4</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 4</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN5</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN6</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 6</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN7</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 7</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN8</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 8</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN9</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 9</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN10</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 10</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN11</name>
|
|
<description>Mirrors the OVERRRUN status flag from the result register for A/D channel 11</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SEQA_OVR</name>
|
|
<description>Mirrors the global OVERRUN status flag in the SEQA_GDAT register</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SEQB_OVR</name>
|
|
<description>Mirrors the global OVERRUN status flag in the SEQB_GDAT register</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SEQA_INT</name>
|
|
<description>Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SEQB_INT</name>
|
|
<description>Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_INT</name>
|
|
<description>Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVR_INT</name>
|
|
<description>Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRM</name>
|
|
<description>ADC trim register.</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000F00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VRANGE</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HIGH_VOLTAGE</name>
|
|
<description>High voltage. VDDA = 2.7 V to 3.6 V.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_VOLTAGE</name>
|
|
<description>Low voltage. VDDA = 2.4 V to 2.7 V.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>12-bit DAC Modification </description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VAL</name>
|
|
<description>D/A Converter Value Register. This register contains the digital value to be converted to analog.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write zeros to unused bits.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>The voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/4096) + VREFN. This voltage will be stable the selected settling time (specified by the BIAS field in the DAC Control Register) after this field is modified.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write zeros to unused bits.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DAC Control register. This register contains bits to configure DAC operation and the interrupt/dma request flag.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_DMA_FLAG</name>
|
|
<description>Interrupt/DMA request flag. This bit is read-only. 0 = This bit is cleared upon any write to the DACVAL register. 1 = This bit is set by hardware only if a hardware trigger has been selected as follows: - If the internal timer is selected, this bit will be set when the timer times-out. - If an external trigger input is selected, this bit will be set when a transition of the specified polarity is detected on the selected input.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TRIG_SRC</name>
|
|
<description>Hardware Trigger Source: If anyof these hardware trigger sources are selected, an interrupt/dma request will be generated when the specified trigger occurs. In addition, if double-buffering is enabled (the DBLBUF_ENA' bit is set), the DACVAL register will be loaded from the pre-buffer at the same time.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>Internal. Selects the internal timer as the trigger source provided the timer is enabled (the TIMER_ENA bit is set). Otherwise (if the timer is not enabled), hardware triggering is disabled. If hardware triggering is disabled no interrupt or DMA requests will be generated. Double-buffering of the DAC VAL register is not useful and cannot be enabled when hardware triggering is disabled.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN</name>
|
|
<description>Pin. External DAC_TRIG port input is selected. Also select this function in the PINASSIGN11 register in the switchmatrix.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLARITY</name>
|
|
<description>Specifies the polarity of the selected external trigger input. Does not apply if the TRIG_SRC field is set to 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. A trigger will be asserted when a RISING edge is detected on the selected external trigger input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. A trigger will be asserted when a FALLING edge is detected on the selected external trigger input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_BYPASS</name>
|
|
<description>Permits bypassing of one synchronization flip-flop, if not required. Does not apply if the TRIG_SRC field is set to 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONIZE</name>
|
|
<description>Synchronize. The selected trigger input will be synchronized to the system clock prior to edge-detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_SYNCHRONIZE</name>
|
|
<description>Not synchronize. The selected trigger input will not be synchronized to the system clock prior to edge-detection. This will save one clock of latency. This bit should only be set f the selected hardware input trigger is from a source that is guaranteeed to already be synchronous to the system clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ENA</name>
|
|
<description>Timer Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The internal timer is disabled. If the TRIG_SEL field is also set to 000 then hardware triggering is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The internal timer is enabled and counting. Note: This bit should only be set after a valid count value has been programmed into the DACCNTVAL register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLBUF_ENA</name>
|
|
<description>Double-Buffer Enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Double-buffering of the DACVAL register is disabled. Software writes to the DACVAL address will directly modify the DAC data presented to the D/A converter. Hardware trigger events, if selected, will not affect the DACVAL contents.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The double-buffering feature in the DACVAL register is enabled. Writes to the DACVAL register are written to a pre-buffer and then transferred to the DACVAL when the specified hardware trigger occurs. Setting this bit will have no effect if hardware triggering is disabled. Double-buffering is of no value under this condition.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHUTOFF_ENA</name>
|
|
<description>Shutoff Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The hardware DAC-shutoff feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The hardware DAC-shutoff feature is enabled. Whenever the DAC_SHUTOFF (port pin) input is high, the DAC output voltage will be forced to zero. The DAC output will return to the value specifed in the DACVAL register once the input pin returns to the low state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHUTOFF_FLAG</name>
|
|
<description>Shutoff Flag. This is a read-only bit. Reflects the state of the DAC_SHUTOFF input if the Shutoff feature is enabled. 0 = DAC_SHUTOFF (port pin) input is low. DAC is outputting the voltage specified in the DAC VAL register. 1 = DAC_SHUTOFF (port pin) input is high. The DAC output is forced to zero. This bit serves as a flag only, If a processor interrupt is desired when a DAC shutoff condition occurrs, that can be accomplished by enabling the port pin selected as the DAC_SHUTOFF pin to directly generate a port interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIAS</name>
|
|
<description>These bits permit trading-off longer DAC settling times to achieve reduced power consumption. The default setting provides maximum speed but also maximum power.</description>
|
|
<bitRange>[12:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write zeros to unused bits.</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTVAL</name>
|
|
<description>DAC Counter Value register. This register contains the reload value for the internal DAC DMA/Interrupt timer.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTVAL</name>
|
|
<description>16-bit reload value for the internal DAC interrupt/DMA timer. The timer will overflow at the fixed rate of the system clock divided by CNTVAL+1. Upon each overflow an interrupt/dma request will be generated and the DAC VAL register contents will be updated if double-buffering is enabled.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write zeros to unused bits.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>ACMP</name>
|
|
<description>Analog comparators ACMP0/1/2/3</description>
|
|
<groupName>ACMP</groupName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CMP1</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CMP2</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CMP3</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Comparator block control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ROSCCTL</name>
|
|
<description>Selects the which comparators set and reset the ROSC output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACMP1_ACMP0</name>
|
|
<description>ACMP1/ACMP0. The ROSC output is set by ACMP1 and reset by ACMP0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_ACMP1</name>
|
|
<description>ACMP0/ACMP1. The ROSC output is set by ACMP0 and reset by ACMP1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXT_RESET</name>
|
|
<description>Selects the reset source for the ROSC output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>Internal. The ROSC output is reset by the internal chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FROM_PIN_ROSC_RESET</name>
|
|
<description>From pin ROSC_RESET. The ROSC output is reset by the ROSC_RESET input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP0</name>
|
|
<description>Comparator 0 source control</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator enable control.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Comparator disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Comparator is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts are disabled..</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAT</name>
|
|
<description>Comparator status. This bit reflects the comparator output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VM</name>
|
|
<description>VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_0</name>
|
|
<description>Vref divider 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_I3</name>
|
|
<description>ACMP0_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_I4</name>
|
|
<description>ACMP0_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP_SENSOR</name>
|
|
<description>Temp sensor.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_2</name>
|
|
<description>ADC0_2. Input for ADC0 channel 2.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VP</name>
|
|
<description>VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_0</name>
|
|
<description>Vref divider 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_I3</name>
|
|
<description>ACMP0_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_I4</name>
|
|
<description>ACMP0_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEMP_SENSOR</name>
|
|
<description>Temp sensor.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_2</name>
|
|
<description>ADC0_2. Input for ADC0 channel 2.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_IS_TURNED</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPOL</name>
|
|
<description>Selects the polarity of the CMP output for purposes of generating level interrupts.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted. The output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTTYPE</name>
|
|
<description>Select interrupt type.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Edge. Comparator interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Level. Comparator interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. Comparator interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. Comparator interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Both edges. Comparator Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. The Comparator interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The Comparator voltage ladder is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The Comparator voltage ladder is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VLADREF</name>
|
|
<description>Voltage reference select for comparator 0 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VSEL</name>
|
|
<description>Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1</name>
|
|
<description>Comparator 1 source control</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator enable control.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Comparator disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Comparator is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts are disabled..</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAT</name>
|
|
<description>Comparator status. This bit reflects the comparator output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VM</name>
|
|
<description>VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_1</name>
|
|
<description>Vref divider 1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1_I3</name>
|
|
<description>ACMP1_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1_I4</name>
|
|
<description>ACMP1_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_1</name>
|
|
<description>ADC0_1. Input for ADC0 channel 1.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_3</name>
|
|
<description>ADC0_3. Input for ADC0 channel 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VP</name>
|
|
<description>VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_1</name>
|
|
<description>Vref divider 1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1_I3</name>
|
|
<description>ACMP1_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1_I4</name>
|
|
<description>ACMP1_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_1</name>
|
|
<description>ADC0_1. Input for ADC0 channel 1.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_3</name>
|
|
<description>ADC0_3. Input for ADC0 channel 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_IS_TURNED</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPOL</name>
|
|
<description>Selects the polarity of the CMP output for purposes of generating level interrupts.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted. The output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTTYPE</name>
|
|
<description>Select interrupt type.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Edge. Comparator interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Level. Comparator interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. Comparator interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. Comparator interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Both edges. Comparator Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. The Comparator interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 1.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The Comparator voltage ladder is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The Comparator voltage ladder is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VLADREF</name>
|
|
<description>Voltage reference select for comparator 1 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VSEL</name>
|
|
<description>Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2</name>
|
|
<description>Comparator 2 source control</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator enable control.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Comparator disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Comparator is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts are disabled..</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAT</name>
|
|
<description>Comparator status. This bit reflects the comparator output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VM</name>
|
|
<description>VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_2</name>
|
|
<description>Vref divider 2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP2_I3</name>
|
|
<description>ACMP2_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP2_I4</name>
|
|
<description>ACMP2_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_0</name>
|
|
<description>ADC0_0. Input for ADC0 channel 0.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_2</name>
|
|
<description>ADC1_2. Input for ADC1 channel 2.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VP</name>
|
|
<description>VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_2</name>
|
|
<description>Vref divider 2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP2_I3</name>
|
|
<description>ACMP2_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP2_I4</name>
|
|
<description>ACMP2_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_0</name>
|
|
<description>ADC0_0. Input for ADC0 channel 0.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_2</name>
|
|
<description>ADC1_2. Input for ADC1 channel 2.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_IS_TURNED</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPOL</name>
|
|
<description>Selects the polarity of the CMP output for purposes of generating level interrupts.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted. The output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTTYPE</name>
|
|
<description>Select interrupt type.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Edge. Comparator interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Level. Comparator interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. Comparator interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. Comparator interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Both edges. Comparator Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. The Comparator interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 2.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The Comparator voltage ladder is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The Comparator voltage ladder is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VLADREF</name>
|
|
<description>Voltage reference select for comparator 2 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VSEL</name>
|
|
<description>Voltage ladder value for comparator 2. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3</name>
|
|
<description>Comparator 3 source control</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator enable control.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Comparator disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Comparator is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts are disabled..</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled.. Must set to 1 for interrupts to propagate to the NVIC and start-up logic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAT</name>
|
|
<description>Comparator status. This bit reflects the comparator output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VM</name>
|
|
<description>VM input select.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_3</name>
|
|
<description>Vref divider 3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP3_I3</name>
|
|
<description>ACMP3_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP3_I4</name>
|
|
<description>ACMP3_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_1</name>
|
|
<description>ADC1_1. Input for ADC1 channel 1.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_3</name>
|
|
<description>ADC1_3. Input for ADC1 channel 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VP</name>
|
|
<description>VP input select.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_DIVIDER_3</name>
|
|
<description>Vref divider 3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP_I1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP_I2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP3_I3</name>
|
|
<description>ACMP3_I3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP3_I4</name>
|
|
<description>ACMP3_I4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_0</name>
|
|
<description>Internal 0.9 V band gap reference.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_1</name>
|
|
<description>ADC1_1. Input for ADC1 channel 1.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_3</name>
|
|
<description>ADC1_3. Input for ADC1 channel 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_IS_TURNED</name>
|
|
<description>Hysteresis is turned off, comparator output will change as the input voltages cross.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_5_MV</name>
|
|
<description>Hysteresis = 5 mV.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_10_MV</name>
|
|
<description>Hysteresis = 10 mV.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYSTERESIS_EQ_15_MV</name>
|
|
<description>Hysteresis = 15 mV.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPOL</name>
|
|
<description>Selects the polarity of the CMP output for purposes of generating level interrupts.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted. The output is used as-is for generating interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The output is used inverted for generating interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTTYPE</name>
|
|
<description>Select interrupt type.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Edge. Comparator interrupt is edge triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Level. Comparator interrupt is level triggered.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTEDGE</name>
|
|
<description>Select edge triggered interrupt to be active on either high or low transitions, when INTTYPE = 0.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. Comparator interrupt is active on falling edges.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. Comparator interrupt is active on rising edges.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>Both edges. Comparator Interrupt is active on both edges.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTFLAG</name>
|
|
<description>Interrupt flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. The Comparator interrupt is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Comparator interrupt is pending. Writing a 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLADEN</name>
|
|
<description>Voltage ladder enable for comparator 3.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The Comparator voltage ladder is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The Comparator voltage ladder is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VLADREF</name>
|
|
<description>Voltage reference select for comparator 3 voltage ladder.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VREF_CMP_PIN</name>
|
|
<description>VREF_CMP pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDA_PIN</name>
|
|
<description>VDDA pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VSEL</name>
|
|
<description>Voltage ladder value for comparator 3. The reference voltage Vref depends on the setting of VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref / 31. 00010 = 2 x Vref / 31. ... 11111 = Vref</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Configure the propagation delay. A shorter propagation delay means higher power consumption. Use values from 0x0 (shortest propagation delay and highest power consumption) to 0x2 (longest propagation delay and lowest power consumption). See the data sheet for details.</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>CMPFILTR%s</name>
|
|
<description>Comparator 0 pin filter set-up</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select clock divider for comparator clock CMP_PCLK.</description>
|
|
<bitRange>[4:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>INMUX</name>
|
|
<description>Input multiplexing (INMUX) </description>
|
|
<groupName>INMUX</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>SCT0_INMUX[%s]</name>
|
|
<displayName>SCT0_INMUX[%s]</displayName>
|
|
<description>Pinmux register for SCT0 input 0</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP_N</name>
|
|
<description>Input number (decimal value) to SCT0 inputs 0 to 6. 0 = PIO0_2 (external pin) 1 = PIO0_3 (external pin) 2 = PIO0_17 (external pin) 3 = PIO0_30 (external pin) 4 = PIO1_6 (external pin) 5 = PIO1_7 (external pin) 6 = PIO1_12 (external pin) 7 = PIO1_13 (external pin) 8 = SCT1_OUT4 (large SCT1 output 4) 9 = SCT2_OUT4 (companion small SCT2 output 4) 10 = SCT2_OUT5 (companion small SCT2 output 5) 11 = ADC0_THCMP_IRQ () 12 = ADC1_THCMP_IRQ () 13 = COMP0_OUT (One output from each analog comparator) 14 = COMP1_OUT 15 = COMP2_OUT 16 = COMP3_OUT 17 = SCTIPU_ABORT 18 = SCTIPU_SAMPLE0 19 = SCTIPU_SAMPLE1 20 = SCTIPU_SAMPLE2 21 = SCTIPU_SAMPLE3 22 = DEBUG_HALTED (from ARM Cortex CoreSight Debugger)</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIO0_2</name>
|
|
<description>PIO0_2 (external pin)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_3</name>
|
|
<description>PIO0_3 (external pin)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_17</name>
|
|
<description>PIO0_17 (external pin)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_30</name>
|
|
<description>PIO0_30 (external pin)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO1_6</name>
|
|
<description>PIO1_6 (external pin)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO1_7</name>
|
|
<description>PIO1_7 (external pin)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO1_12</name>
|
|
<description>PIO1_12 (external pin)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO1_13</name>
|
|
<description>PIO1_13 (external pin)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT1_OUT4</name>
|
|
<description>SCT1_OUT4 (large SCT1 output 4)</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT2_OUT4</name>
|
|
<description>SCT2_OUT4 (small SCT2 output 4)</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT2_OUT5</name>
|
|
<description>SCT2_OUT5 (small SCT2 output 5)</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0_THCMP_IRQ</name>
|
|
<description>ADC0_THCMP_IRQ (ADC0 threshold compare interrupt)</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC1_THCMP_IRQ</name>
|
|
<description>ADC1_THCMP_IRQ (ADC1 threshold compare interrupt)</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0_OUT</name>
|
|
<description>ACMP0_OUT (One output from each analog comparator)</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1_OUT</name>
|
|
<description>ACMP1_OUT (One output from each analog comparator)</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP2_OUT</name>
|
|
<description>ACMP2_OUT (One output from each analog comparator)</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP3_OUT</name>
|
|
<description>ACMP3_OUT (One output from each analog comparator)</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCTIPU_ABORT</name>
|
|
<description>SCTIPU_ABORT</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCTIPU_SAMPLE0</name>
|
|
<description>SCTIPU_SAMPLE0</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCTIPU_SAMPLE1</name>
|
|
<description>SCTIPU_SAMPLE1</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCTIPU_SAMPLE2</name>
|
|
<description>SCTIPU_SAMPLE2</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCTIPU_SAMPLE3</name>
|
|
<description>SCTIPU_SAMPLE3</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUG_HALTED</name>
|
|
<description>ARM DEBUG HALTED</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>SCT1_INMUX[%s]</name>
|
|
<displayName>SCT1_INMUX[%s]</displayName>
|
|
<description>Pinmux register for SCT1 input 0</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP_N</name>
|
|
<description>Input number (decimal value) to SCT1 inputs 0 to 6. 0 = PIO0_15 (external pin) 1 = PIO0_16 (external pin) 2 = PIO0_21 (external pin) 3 = PIO0_31 (external pin) 4 = PIO1_4 (external pin) 5 = PIO1_5 (external pin) 6 = PIO1_15 (external pin) 7 = PIO1_16 (external pin) 8 = SCT0_OUT4 (large SCT0 output 4) 9 = SCT3_OUT4 (small companion SCT3 output 4) 10 = SCT3_OUT5 (small companion SCT3 output 5) 11 = ADC0_THCMP_IRQ 12 = ADC1_THCMP_IRQ 13 = COMP0_OUT (One output from each analog comparator) 14 = COMP1_OUT 15 = COMP2_OUT 16 = A COMP3_OUT 17 = SCTIPU_ABORT 18 = SCTIPU_SAMPLE0 19 = SCTIPU_SAMPLE1 20 = SCTIPU_SAMPLE2 21 = SCTIPU_SAMPLE3 22 = DEBUG_HALTED DEBUG_HALTED (from ARM Cortex CoreSight Debugger)</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SCT2_INMUX[%s]</name>
|
|
<displayName>SCT2_INMUX[%s]</displayName>
|
|
<description>Pinmux register for SCT2 input 0</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP_N</name>
|
|
<description>Input number (decimal value) to SCT2 inputs 0 to 2. 0 = P0_4 (external pin) 1 = P0_27 (external pin) 2 = P1_18 (external pin) 3 = P1_19 (external pin) 4 = SCT0_OUT4 5 = SCT0_OUT5 6 = SCT0_OUT7 7 = SCT0_OUT8 8 = ADC0_THCMP_IRQ 9 = ADC1_THCMP_IRQ 10 = COMP0_OUT (One output from each analog comparator) 11 = COMP1_OUT 12 = COMP2_OUT 13 = COMP3_OUT 14 = SCTIPU_ABORT 15 = SCTIPU_SAMPLE0 16 = SCTIPU_SAMPLE1 17 = SCTIPU_SAMPLE2 18 = SCTIPU_SAMPLE3 19 = USB_FRAME_TOGGLE 20 = DEBUG_HALTED</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SCT3_INMUX[%s]</name>
|
|
<displayName>SCT3_INMUX[%s]</displayName>
|
|
<description>Pinmux register for SCT3 input 0</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP_N</name>
|
|
<description>Input number (decimal value) to SCT3 inputs 0 to 2. 0 = PIO0_7 1 = PIO1_11 2 = PIO1_21 3 = PIO1_22 4 = SCT1_OUT4 5 = SCT1_OUT5 6 = SCT1_OUT7 7 = SCT1_OUT8 8 = ADC0_THCMP_IRQ 9 = ADC1_THCMP_IRQ 10 = COMP0_OUT 11 = COMP1_OUT 12 = COMP2_OUT 13 = COMP3_OUT 14 = SCTIPU_ABORT3 15 = SCTIPU_SAMPLE0 16 = SCTIPU_SAMPLE1 17 = SCTIPU_SAMPLE2 18 = SCTIPU_SAMPLE3 19 = USB_FRAME_TOGGLE 20 = DEBUG_HALTED</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>PINTSEL[%s]</name>
|
|
<displayName>PINTSEL[%s]</displayName>
|
|
<description>Pin interrupt select register 0</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPIN</name>
|
|
<description>Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>18</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-17</dimIndex>
|
|
<name>DMA_ITRIG_INMUX[%s]</name>
|
|
<displayName>DMA_ITRIG_INMUX[%s]</displayName>
|
|
<description>Trigger input for DMA channel 0 select register.</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP_N</name>
|
|
<description>Trigger input number (decimal value) to DMA channel n. 0 = ADC0_SEQA_IRQ 1 = ADC0_SEQB_IRQ 2 = ADC1_SEQA_IRQ 3 = ADC1_SEQB_IRQ 4 = SCT0_DMA0 5 = SCT0_DMA1 6 = SCT1_DMA0 7 = SCT1_DMA1 8 = SCT2_DMA0 9 = SCT2_DMA1 10 = SCT3_DMA0 11 = SCT3_DMA1 12 = COMP0_OUT (One output from each analog comparator) 13 = COMP1_OUT 14 = COMP2_OUT 15 = COMP3_OUT 16 = SDMA_TRIGOUT_A 17 = SDMA_TRIGOUT_B 18 = SDMA_TRIGOUT_C 19 = SDMA_TRIGOUT_D</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>DMA_INMUX_INMUX[%s]</name>
|
|
<displayName>DMA_INMUX_INMUX[%s]</displayName>
|
|
<description>DMA trigger input select register.</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INP</name>
|
|
<description>DMA trigger output number</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQMEAS_REF</name>
|
|
<description>Clock selection for frequency measurement function reference clock</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKIN</name>
|
|
<description>Clock source number (decimal value) for frequency measure function target clock: 0 = System oscilator (MAIN_OSC) 1 = IRC 2 = WDOSC 3 = 32KHZOSC 4 = USB_FTOGGLE 5 = PIO0_5 6 = PIO0_19 7 = PIO0_30 8 = PIO1_27</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREQMEAS_TARGET</name>
|
|
<description>Clock selection for frequency measurement function target clock</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKIN</name>
|
|
<description>Clock source number (decimal value) for frequency measure function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC 2 = WDOSC 3 = 32KHZOSC 4 = USB_FTOGGLE 5 = PIO0_5 6 = PIO0_19 7 = PIO0_30 8 = PIO1_27</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real-Time Clock (RTC)</description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC_ALARM</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTC_WAKE</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>RTC control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWRESET</name>
|
|
<description>Software reset control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_IN_RESET</name>
|
|
<description>Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN_RESET</name>
|
|
<description>In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFD</name>
|
|
<description>Oscillator fail detect status.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Run. The RTC oscillator is running properly. Writing a 0 has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAIL</name>
|
|
<description>Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALARM1HZ</name>
|
|
<description>RTC 1 Hz timer alarm flag status.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_MATCH</name>
|
|
<description>No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE1KHZ</name>
|
|
<description>RTC 1 kHz timer wake-up flag status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIME_OUT</name>
|
|
<description>Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALARMDPD_EN</name>
|
|
<description>RTC 1 Hz timer alarm enable for Deep power-down.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEDPD_EN</name>
|
|
<description>RTC 1 kHz timer wake-up enable for Deep power-down.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC1KHZ_EN</name>
|
|
<description>RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. The 1 kHz RTC timer is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_EN</name>
|
|
<description>RTC enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCH</name>
|
|
<description>RTC match register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATVAL</name>
|
|
<description>Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>RTC counter register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKE</name>
|
|
<description>RTC high-resolution/wake-up timer control register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WWDT</name>
|
|
<description>Windowed Watchdog Timer (WWDT)</description>
|
|
<groupName>WWDT</groupName>
|
|
<baseAddress>0x4002C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDT</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDEN</name>
|
|
<description>Watchdog enable bit. Once this bit has been written with a 1, it cannot be re-written with a 0. Once this bit is set to one and performing a watchdog feed, the watchdog timer starts running permanently.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. The watchdog timer is stopped.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Run. The watchdog timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDRESET</name>
|
|
<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT</name>
|
|
<description>Interrupt. A watchdog time-out will not cause a chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. A watchdog time-out will cause a chip reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOF</name>
|
|
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDINT</name>
|
|
<description>Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDPROTECT</name>
|
|
<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FLEXIBLE</name>
|
|
<description>Flexible. The watchdog time-out value (TC) can be changed at any time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRESHOLD</name>
|
|
<description>Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Watchdog time-out value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEED</name>
|
|
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEED</name>
|
|
<description>Feed value should be 0xAA followed by 0x55.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TV</name>
|
|
<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter timer value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog Warning Interrupt compare value.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog warning interrupt compare value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog Window compare value.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog window value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>SWM</name>
|
|
<description>Switch Matrix (SWM)</description>
|
|
<groupName>SWM</groupName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PINASSIGN0</name>
|
|
<description>Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART0_TXD_O</name>
|
|
<description>UART0_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_RXD_I</name>
|
|
<description>UART0_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_RTS_O</name>
|
|
<description>UART0_RTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_CTS_I</name>
|
|
<description>UART0_CTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN1</name>
|
|
<description>Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART0_SCLK_IO</name>
|
|
<description>UART0_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_TXD_O</name>
|
|
<description>UART1_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RXD_I</name>
|
|
<description>UART1_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RTS_O</name>
|
|
<description>UART1_RTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN2</name>
|
|
<description>Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART1_CTS_I</name>
|
|
<description>UART1_CTS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_SCLK_IO</name>
|
|
<description>UART1_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2_TXD_O</name>
|
|
<description>UART2_TXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2_RXD_I</name>
|
|
<description>UART2_RXD function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN3</name>
|
|
<description>Pin assign register 3. Assign movable function .</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART2_SCLK_IO</name>
|
|
<description>UART2_SCLK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_SCK_IO</name>
|
|
<description>SSP0_SCK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_MOSI_IO</name>
|
|
<description>SSP0_MOSI function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_MISO_IO</name>
|
|
<description>SSP0_MISO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN4</name>
|
|
<description>Pin assign register 4. Assign movable functions</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSP0_SSELSN_0_IO</name>
|
|
<description>SSP0_SSELSN_0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_SSELSN_1_IO</name>
|
|
<description>SSP0_SSELSN_1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_SSELSN_2_IO</name>
|
|
<description>SSP0_SSELSN_2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_SSELSN_3_IO</name>
|
|
<description>SSP0_SSELSN_3 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN5</name>
|
|
<description>Pin assign register 5. Assign movable functions</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSP1_SCK_IO</name>
|
|
<description>SSP1_SCK function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_MOSI_IO</name>
|
|
<description>SSP1_MOSI function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_MISO_IO</name>
|
|
<description>SSP1_MISO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_SSELSN_0_IO</name>
|
|
<description>SSP1_SSELSN_0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN6</name>
|
|
<description>Pin assign register 6. Assign movable functions</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSP1_SSELSN_1_IO</name>
|
|
<description>SSP1_SSELSN_1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_TD1_O</name>
|
|
<description>CAN_TD1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_RD1_I</name>
|
|
<description>CAN_RD1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_CONNECTN_O</name>
|
|
<description>USB_CONNECTN function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN7</name>
|
|
<description>Pin assign register 7. Assign movable functions</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VBUS_I</name>
|
|
<description>USB_VBUS function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT0_O</name>
|
|
<description>SCT0_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT1_O</name>
|
|
<description>SCT0_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT2_O</name>
|
|
<description>SCT0_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN8</name>
|
|
<description>Pin assign register 8. Assign movable functions</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCT1_OUT0_O</name>
|
|
<description>SCT1_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT1_O</name>
|
|
<description>SCT1_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT2_O</name>
|
|
<description>SCT1_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_OUT0_O</name>
|
|
<description>SCT2_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN9</name>
|
|
<description>Pin assign register 9. Assign movable functions</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCT2_OUT1_O</name>
|
|
<description>SCT2_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_OUT2_O</name>
|
|
<description>SCT2_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_OUT0_O</name>
|
|
<description>SCT3_OUT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_OUT1_O</name>
|
|
<description>SCT3_OUT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN10</name>
|
|
<description>Pin assign register 10. Assign movable functions</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCT3_OUT2_O</name>
|
|
<description>SCT3_OUT2 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT_ABORT0_I</name>
|
|
<description>SCT_ABORT0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT_ABORT1_I</name>
|
|
<description>SCT_ABORT1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_PIN_TRIG0_I</name>
|
|
<description>ADC0_PIN_TRIG0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN11</name>
|
|
<description>Pin assign register 11. Assign movable functions</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0_PIN_TRIG1_I</name>
|
|
<description>ADC0_PIN_TRIG1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_PIN_TRIG0_I</name>
|
|
<description>ADC1_PIN_TRIG0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_PIN_TRIG1_I</name>
|
|
<description>ADC1_PIN_TRIG1 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_PIN_TRIG_I</name>
|
|
<description>DAC_PIN_TRIG function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN12</name>
|
|
<description>Pin assign register 12. Assign movable functions</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAC_SHUTOFF_I</name>
|
|
<description>DAC_SHUTOFF function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0_OUT_O</name>
|
|
<description>ACMP0_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1_OUT_O</name>
|
|
<description>ACMP1_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMP2_OUT_O</name>
|
|
<description>ACMP2_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN13</name>
|
|
<description>Pin assign register 13. Assign movable functions</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMP3_OUT_O</name>
|
|
<description>ACMP3_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLK_OUT_O</name>
|
|
<description>CLK_OUT function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROSC0_O</name>
|
|
<description>ROSC0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROSC_RST0_I</name>
|
|
<description>ROSC_RST0 function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN14</name>
|
|
<description>Pin assign register 14. Assign movable functions</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FRAME_TOG_O</name>
|
|
<description>USB_FRAME_TOG function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI0_PHA_I</name>
|
|
<description>QEI0_PHA function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI0_PHB_I</name>
|
|
<description>QEI0_PHB function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI0_IDX_I</name>
|
|
<description>QEI0_IDX function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINASSIGN15</name>
|
|
<description>Pin assign register 15. Assign movable functions</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_INT_BMATCH_O</name>
|
|
<description>GPIO_INT_BMATCH function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SWO_O</name>
|
|
<description>SWO function assignment. The value is the pin number to be assigned to this function. PIO0_0 = 0, ..., PIO1_0 = 32, ..., PIO2_11 = 75.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINENABLE0</name>
|
|
<description>Pin enable register 0. Enables fixed-pin functions</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0_0</name>
|
|
<description>ADC0_0 pin enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_08</name>
|
|
<description>Enabled on pin P0_08.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_1</name>
|
|
<description>ADC0_1 pin enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_07</name>
|
|
<description>Enabled on pin P0_07.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_2</name>
|
|
<description>ADC0_2 pin enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_06</name>
|
|
<description>Enabled on pin P0_06.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_3</name>
|
|
<description>ADC0_3 pin enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_05</name>
|
|
<description>Enabled on pin P0_05.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_4</name>
|
|
<description>ADC0_4 pin enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_04</name>
|
|
<description>Enabled on pin P0_04.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_5</name>
|
|
<description>ADC0_5 pin enable.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_03</name>
|
|
<description>Enabled on pin P0_03.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_6</name>
|
|
<description>ADC0_6 pin enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_02</name>
|
|
<description>Enabled on pin P0_02.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_7</name>
|
|
<description>ADC0_7 pin enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_01</name>
|
|
<description>Enabled on pin P0_01.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_8</name>
|
|
<description>ADC0_8 pin enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_00</name>
|
|
<description>Enabled on pin P1_00 .</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_9</name>
|
|
<description>ADC0_9 pin enable.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_31</name>
|
|
<description>Enabled on pin P0_31.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_10</name>
|
|
<description>ADC0_10 pin enable.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_00</name>
|
|
<description>Enabled on pin P0_00.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_11</name>
|
|
<description>ADC0_11 pin enable.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_30</name>
|
|
<description>Enabled on pin P0_30.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_0</name>
|
|
<description>ADC1_0 pin enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_01</name>
|
|
<description>Enabled on pin P1_01.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_1</name>
|
|
<description>ADC1_1 pin enable.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_09</name>
|
|
<description>Enabled on pin P0_09.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_2</name>
|
|
<description>ADC1_2 pin enable.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_10</name>
|
|
<description>Enabled on pin P0_10.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_3</name>
|
|
<description>ADC1_3 pin enable.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_11</name>
|
|
<description>Enabled on pin P0_11.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_4</name>
|
|
<description>ADC1_4 pin enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_02</name>
|
|
<description>Enabled on pin P1_02.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_5</name>
|
|
<description>ADC1_5 pin enable.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_03</name>
|
|
<description>Enabled on pin P1_03.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_6</name>
|
|
<description>ADC1_6 pin enable.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_13</name>
|
|
<description>Enabled on pin P0_13.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_7</name>
|
|
<description>ADC1_7 pin enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_14</name>
|
|
<description>Enabled on pin P0_14.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_8</name>
|
|
<description>ADC1_8 pin enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_15</name>
|
|
<description>Enabled on pin P0_15.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_9</name>
|
|
<description>ADC1_9 pin enable.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_16</name>
|
|
<description>Enabled on pin P0_16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_10</name>
|
|
<description>ADC1_10 pin enable.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_04</name>
|
|
<description>Enabled on pin P1_04.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_11</name>
|
|
<description>ADC1_11 pin enable.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_05</name>
|
|
<description>Enabled on pin P1_05.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC_OUT</name>
|
|
<description>DAC_OUT pin enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_12</name>
|
|
<description>Enabled on pin P0_12.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP_I1</name>
|
|
<description>ACMP input 1 (common input) pin enable.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_27</name>
|
|
<description>Enabled on pin P0_27.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP_I2</name>
|
|
<description>ACMP input 2 (common input) pin enable.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_06</name>
|
|
<description>Enabled on pin P1_06.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0_I3</name>
|
|
<description>Analog comparator 0 input 3 pin enable.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_26</name>
|
|
<description>Enabled on pin P0_26.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0_I4</name>
|
|
<description>Analog comparator 0 input 4 pin enable.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_25</name>
|
|
<description>Enabled on pin P0_25.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1_I3</name>
|
|
<description>Analog comparator 1 input 3 pin enable.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_28</name>
|
|
<description>Enabled on pin P0_28.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1_I4</name>
|
|
<description>Analog comparator 1 input 4 pin enable.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_10</name>
|
|
<description>Enabled on pin P1_10.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP2_I3</name>
|
|
<description>Analog comparator 2 input 3 pin enable.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_29</name>
|
|
<description>Enabled on pin P0_29.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINENABLE1</name>
|
|
<description>Pin enable register 0. Enables fixed-pin functions</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMP2_I4</name>
|
|
<description>Analog comparator 2 input 4 pin enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_09</name>
|
|
<description>Enabled on pin P1_09.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP3_I3</name>
|
|
<description>Analog comparator 3 input 3 pin enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_08</name>
|
|
<description>Enabled on pin P1_08.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP3_I4</name>
|
|
<description>Analog comparator 3 input 4 pin enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_07</name>
|
|
<description>Enabled on pin P1_07.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0_SDA</name>
|
|
<description>I2C0_SDA pin enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_23</name>
|
|
<description>Enabled on pin P0_23.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0_SCL</name>
|
|
<description>I2C0_SCL pin enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_22</name>
|
|
<description>Enabled on pin P0_22.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT3</name>
|
|
<description>SCT0_OUT3 pin enable.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_00</name>
|
|
<description>Enabled on pin P0_00.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT4</name>
|
|
<description>SCT0_OUT4 pin enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_01</name>
|
|
<description>Enabled on pin P0_01.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT5</name>
|
|
<description>SCT0_OUT5 pin enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_18</name>
|
|
<description>Enabled on pin P0_18.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT6</name>
|
|
<description>SCT0_OUT6 pin enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_24</name>
|
|
<description>Enabled on pin P0_24.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_OUT7</name>
|
|
<description>SCT0_OUT7 pin enable.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_14</name>
|
|
<description>Enabled on pin P1_14.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT3</name>
|
|
<description>SCT1_OUT3 pin enable.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_02</name>
|
|
<description>Enabled on pin P0_02.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT4</name>
|
|
<description>SCT1_OUT4 pin enable.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_03</name>
|
|
<description>Enabled on pin P0_03.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT5</name>
|
|
<description>SCT1_OUT5 pin enable.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_14</name>
|
|
<description>Enabled on pin P0_14.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT6</name>
|
|
<description>SCT1_OUT6 pin enable.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_20</name>
|
|
<description>Enabled on pin P0_20.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_OUT7</name>
|
|
<description>SCT1_OUT7 pin enable.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_17</name>
|
|
<description>Enabled on pin P1_17.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_OUT3</name>
|
|
<description>SCT2_OUT3 pin enable.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_06</name>
|
|
<description>Enabled on pin P0_06.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_OUT4</name>
|
|
<description>SCT2_OUT4 pin enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_29</name>
|
|
<description>Enabled on pin P0_29.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_OUT5</name>
|
|
<description>SCT2_OUT5 pin enable.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_20</name>
|
|
<description>Enabled on pin P1_20.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_OUT3</name>
|
|
<description>SCT3_OUT3 pin enable.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_26</name>
|
|
<description>Enabled on pin P0_26.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_OUT4</name>
|
|
<description>SCT3_OUT4 pin enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_08</name>
|
|
<description>Enabled on pin P1_08.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_OUT5</name>
|
|
<description>SCT3_OUT5 pin enable.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P1_24</name>
|
|
<description>Enabled on pin P1_24.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESETN</name>
|
|
<description>RESETN pin enable.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_21</name>
|
|
<description>Enabled on pin P0_21.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWCLK_TCK</name>
|
|
<description>SWCLK_TCK pin enable.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_19</name>
|
|
<description>Enabled on pin P0_19.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWDIO</name>
|
|
<description>SWDIO pin enable.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_ON_PIN_P0_20</name>
|
|
<description>Enabled on pin P0_20.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>PMU</name>
|
|
<description>Power Management Unit (PMU)</description>
|
|
<groupName>PMU</groupName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCON</name>
|
|
<description>Power control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NODPD</name>
|
|
<description>A 1 in this bit prevents entry to Deep power-down mode. This bit is cleared by power-on reset.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLEEPFLAG</name>
|
|
<description>Sleep mode flag</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ_NO_POWER_DOWN</name>
|
|
<description>Read: No power-down mode entered. The part is in Active mode. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEP_DEEP_SLEEP</name>
|
|
<description>Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPDFLAG</name>
|
|
<description>Deep power-down flag</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ_DEEP_POWER_DOW</name>
|
|
<description>Read: Deep power-down mode not entered. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ_DEEP_POWER_DOW</name>
|
|
<description>Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GPREG%s</name>
|
|
<description>General purpose register 0</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPDATA</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DPDCTRL</name>
|
|
<description>Deep power-down control register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUPHYS</name>
|
|
<description>WAKEUP pin hysteresis enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Hysteresis for WAKEUP pin disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Hysteresis for WAKEUP pin enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEPAD_DISABLE</name>
|
|
<description>WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The wake-up function is enabled on pin PIO0_4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Setting this bit disables the wake-up function on pin PIO0_4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPOSCEN</name>
|
|
<description>Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPOSCDPDEN</name>
|
|
<description>Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Do not set this bit unless you use the self wake-up timer to wake up from Deep power-down mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USART0</name>
|
|
<description>USART0 </description>
|
|
<groupName>USART0</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>USART Configuration register. Basic USART configuration settings that typically are not changed during operation.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>USART Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The USART is enabled for operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DATALEN</name>
|
|
<description>Selects the data size for the USART.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>7_BIT_DATA_LENGTH</name>
|
|
<description>7 bit Data length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_DATA_LENGTH</name>
|
|
<description>8 bit Data length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT_DATA_LENGTH</name>
|
|
<description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITYSEL</name>
|
|
<description>Selects what type of parity is used by the USART.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PARITY</name>
|
|
<description>No parity.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY</name>
|
|
<description>Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY</name>
|
|
<description>Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPLEN</name>
|
|
<description>Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS</name>
|
|
<description>2 stop bits. This setting should only be used for asynchronous communication.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to this bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE32K</name>
|
|
<description>Selects standard or 32 kHz clocking mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UART_USES_STANDARD_C</name>
|
|
<description>UART uses standard clocking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_USES_THE_32_KHZ</name>
|
|
<description>UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 24.7.4 for more information.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_FLOW_CONTROL</name>
|
|
<description>No flow control. The transmitter does not receive any automatic flow control signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLOW_CONTROL_ENABLED</name>
|
|
<description>Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN</name>
|
|
<description>Selects synchronous or asynchronous operation.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS_MODE_IS</name>
|
|
<description>Asynchronous mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_MODE_IS</name>
|
|
<description>Synchronous mode is selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>Selects the clock polarity and sampling edge of received data in synchronous mode.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Falling edge. Un_RXD is sampled on the falling edge of SCLK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Rising edge. Un_RXD is sampled on the rising edge of SCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SYNCMST</name>
|
|
<description>Synchronous mode Master select.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>Master. When synchronous mode is enabled, the USART is a master.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOP</name>
|
|
<description>Selects data loopback mode.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOPBACK_MODE</name>
|
|
<description>Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OETA</name>
|
|
<description>Output Enable Turnaround time enable for RS-485 operation.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOADDR</name>
|
|
<description>Automatic Address matching enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OESEL</name>
|
|
<description>Output Enable Select.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard. The RTS signal is used as the standard flow control function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RS_485</name>
|
|
<description>RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEPOL</name>
|
|
<description>Output Enable Polarity.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. If selected by OESEL, the output enable is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. If selected by OESEL, the output enable is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPOL</name>
|
|
<description>Receive data polarity.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXPOL</name>
|
|
<description>Transmit data polarity.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>USART Control register. USART control settings that are more likely to change during operation.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXBRKEN</name>
|
|
<description>Break Enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS_BREAK_IS</name>
|
|
<description>Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRDET</name>
|
|
<description>Enable address detect mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The USART presents all incoming data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmit Disable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DISABLED</name>
|
|
<description>Not disabled. USART transmitter is not disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CC</name>
|
|
<description>Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLOCK_ON_CHARACTER</name>
|
|
<description>Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS_CLOCK</name>
|
|
<description>Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRCCONRX</name>
|
|
<description>Clear Continuous Clock.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_AFFECT_ON_THE_CC</name>
|
|
<description>No affect on the CC bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_CLEAR</name>
|
|
<description>Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBAUD</name>
|
|
<description>Autobaud enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. UART is in normal operating mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIDLE</name>
|
|
<description>Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIDLE</name>
|
|
<description>Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTACTS</name>
|
|
<description>This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDISSTAT</name>
|
|
<description>Transmitter Disabled Status flag. When 1, this bit indicates that the UART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUNINT</name>
|
|
<description>Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXBRK</name>
|
|
<description>Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTARXBRK</name>
|
|
<description>This bit is set when a change in the state of receiver break detection occurs. Cleared by software.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMERRINT</name>
|
|
<description>Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITYERRINT</name>
|
|
<description>Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNOISEINT</name>
|
|
<description>Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABERR</name>
|
|
<description>Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDYEN</name>
|
|
<description>When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDYEN</name>
|
|
<description>When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIDLEEN</name>
|
|
<description>When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTACTSEN</name>
|
|
<description>When 1, enables an interrupt when there is a change in the state of the CTS input.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDISEN</name>
|
|
<description>When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUNEN</name>
|
|
<description>When 1, enables an interrupt when an overrun error occurred.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTARXBRKEN</name>
|
|
<description>When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTEN</name>
|
|
<description>When 1, enables an interrupt when a received start bit has been detected.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMERREN</name>
|
|
<description>When 1, enables an interrupt when a framing error has been detected.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITYERREN</name>
|
|
<description>When 1, enables an interrupt when a parity error has been detected.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNOISEEN</name>
|
|
<description>When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 322.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABERREN</name>
|
|
<description>When 1, enables an interrupt when an auto baud error occurs.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDYCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDYCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIDLECLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTACTSCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDISCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUNCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTARXBRKCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMERRCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITYERRCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNOISECLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABERRCLR</name>
|
|
<description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDAT</name>
|
|
<description>Receiver Data register. Contains the last character received.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATSTAT</name>
|
|
<description>Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[12:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMERR</name>
|
|
<description>Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITYERR</name>
|
|
<description>Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNOISE</name>
|
|
<description>Received Noise flag. See description of the RxNoiseInt bit in Table 322.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDAT</name>
|
|
<description>Transmit Data register. Data to be transmitted is written here.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRG</name>
|
|
<description>Baud Rate Generator register. 16-bit integer baud rate divisor value.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRGVAL</name>
|
|
<description>This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt status register. Reflects interrupts that are currently enabled.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0005</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready flag.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIDLE</name>
|
|
<description>Transmitter Idle status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTACTS</name>
|
|
<description>This bit is set when a change in the state of the CTS input is detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDISINT</name>
|
|
<description>Transmitter Disabled Interrupt flag.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUNINT</name>
|
|
<description>Overrun Error interrupt flag.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DELTARXBRK</name>
|
|
<description>This bit is set when a change in the state of receiver break detection occurs.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This bit is set when a start is detected on the receiver input.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMERRINT</name>
|
|
<description>Framing Error interrupt flag.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITYERRINT</name>
|
|
<description>Parity Error interrupt flag.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXNOISEINT</name>
|
|
<description>Received Noise interrupt flag.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABERRINT</name>
|
|
<description>Auto baud Error Interrupt flag.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Oversample selection register for asynchronous communication.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSRVAL</name>
|
|
<description>Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>Address register for automatic address matching.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART1</name>
|
|
<description>USART1</description>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>SPI0 </description>
|
|
<groupName>SPI0</groupName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>SPI Configuration register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>SPI enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The SPI is disabled and the internal state machine and counters are reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The SPI is enabled for operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master mode select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE_MODE</name>
|
|
<description>Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_MODE</name>
|
|
<description>Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>LSB First mode enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard. Data is transmitted and received in standard MSB first order.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REVERSE</name>
|
|
<description>Reverse. Data is transmitted and received in reverse order (LSB first).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase select.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANGE</name>
|
|
<description>Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTURE</name>
|
|
<description>Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity select.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The rest state of the clock (between frames) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The rest state of the clock (between frames) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LOOP</name>
|
|
<description>Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL0</name>
|
|
<description>SSEL0 Polarity select.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL1</name>
|
|
<description>SSEL1 Polarity select.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL2</name>
|
|
<description>SSEL2 Polarity select.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOL3</name>
|
|
<description>SSEL3 Polarity select.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLY</name>
|
|
<description>SPI Delay register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRE_DELAY</name>
|
|
<description>Controls the amount of time between SSEL assertion and the beginning of a data frame. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POST_DELAY</name>
|
|
<description>Controls the amount of time between the end of a data frame and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_DELAY</name>
|
|
<description>Controls the minimum amount of time between adjacent data frames. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRANSFER_DELAY</name>
|
|
<description>Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>SPI Status. Some status flags can be cleared by writing a 1 to that bit position</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0102</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOV</name>
|
|
<description>Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUR</name>
|
|
<description>Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSA</name>
|
|
<description>Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSD</name>
|
|
<description>Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STALLED</name>
|
|
<description>Stalled status flag. This indicates whether the SPI is currently in a stall condition.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDTRANSFER</name>
|
|
<description>End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes Idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDYEN</name>
|
|
<description>Determines whether an interrupt occurs when receiver data is available.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when receiver data is available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated when receiver data is available in the RXDAT register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRDYEN</name>
|
|
<description>Determines whether an interrupt occurs when the transmitter holding register is available.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when the transmitter holding register is available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated when data may be written to TXDAT.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXOVEN</name>
|
|
<description>Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when a receiver overrun occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated if a receiver overrun occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXUREN</name>
|
|
<description>Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when the transmitter underruns.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated if the transmitter underruns.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSAEN</name>
|
|
<description>Determines whether an interrupt occurs when the Slave Select is asserted.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSDEN</name>
|
|
<description>Determines whether an interrupt occurs when the Slave Select is deasserted.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_WILL_BE</name>
|
|
<description>No interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AN_INTERRUPT_WILL_BE</name>
|
|
<description>An interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDYEN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDYEN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOVEN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUREN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSAEN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSDEN</name>
|
|
<description>Writing 1 clears the corresponding bits in the INTENSET register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDAT</name>
|
|
<description>SPI Receive Data</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDAT</name>
|
|
<description>Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the FLen setting in TXCTL / TXDATCTL.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSSEL0</name>
|
|
<description>Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSSEL1</name>
|
|
<description>Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSSEL2</name>
|
|
<description>Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXSSEL3</name>
|
|
<description>Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOT</name>
|
|
<description>Start of Transfer flag. This flag will be 1 if this is the first frame after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATCTL</name>
|
|
<description>SPI Transmit Data with Control</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDAT</name>
|
|
<description>Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL0</name>
|
|
<description>Transmit Slave Select . This field controls what is output for SSEL0 in master mode. The active state of the SSEL0 function is configured by bits in the CFG register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSEL0_ASSERTED</name>
|
|
<description>SSEL0 asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL0_NOT_ASSERTED</name>
|
|
<description>SSEL0 not asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL1</name>
|
|
<description>Transmit Slave Select . This field controls what is output for SSEL1 in master mode. The active state of the SSEL1 function is configured by bits in the CFG register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSEL1_ASSERTED</name>
|
|
<description>SSEL1 asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL1_NOT_ASSERTED</name>
|
|
<description>SSEL1 not asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL2</name>
|
|
<description>Transmit Slave Select . This field controls what is output for SSEL2 in master mode. The active state of the SSEL2 function is configured by bits in the CFG register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSEL2_ASSERTED</name>
|
|
<description>SSEL2 asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL2_NOT_ASSERTED</name>
|
|
<description>SSEL2 not asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL3</name>
|
|
<description>Transmit Slave Select . This field controls what is output for SSEL3 in master mode. The active state of the SSEL3 function is configured by bits in the CFG register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSEL3_ASSERTED</name>
|
|
<description>SSEL3 asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL3_NOT_ASSERTED</name>
|
|
<description>SSEL3 not asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOT</name>
|
|
<description>End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSEL_NOT_DEASSERTED</name>
|
|
<description>SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL_DEASSERTED</name>
|
|
<description>SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DATA_NOT_EOF</name>
|
|
<description>Data not EOF. This piece of data transmitted is not treated as the end of a frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_EOF</name>
|
|
<description>Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIGNORE</name>
|
|
<description>Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ_RECEIVED_DATA</name>
|
|
<description>Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGNORE_RECEIVED_DATA</name>
|
|
<description>Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLEN</name>
|
|
<description>Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by implementing multiple sequential frames. Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 2 bits in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length.</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDAT</name>
|
|
<description>SPI Transmit Data with Control</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCTL</name>
|
|
<description>SPI Transmit Control</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL0</name>
|
|
<description>Transmit Slave Select 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL1</name>
|
|
<description>Transmit Slave Select 1.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL2</name>
|
|
<description>Transmit Slave Select 2.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSSEL3</name>
|
|
<description>Transmit Slave Select 3.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EOT</name>
|
|
<description>End of Transfer.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EOF</name>
|
|
<description>End of Frame.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIGNORE</name>
|
|
<description>Receive Ignore.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLEN</name>
|
|
<description>Frame Length.</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIV</name>
|
|
<description>SPI clock Divider</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVVAL</name>
|
|
<description>Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>SPI Interrupt Status</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXRDY</name>
|
|
<description>Receiver Ready flag.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRDY</name>
|
|
<description>Transmitter Ready flag.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXOV</name>
|
|
<description>Receiver Overrun interrupt flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXUR</name>
|
|
<description>Transmitter Underrun interrupt flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSA</name>
|
|
<description>Slave Select Assert.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSD</name>
|
|
<description>Slave Select Deassert.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI1</name>
|
|
<description>SPI1</description>
|
|
<baseAddress>0x4004C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>I2C-bus interface </description>
|
|
<groupName>I2C0</groupName>
|
|
<baseAddress>0x40050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration for shared functions.</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTEN</name>
|
|
<description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The I2C Master function is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The I2C Master function is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVEN</name>
|
|
<description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The I2C slave function is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The I2C slave function is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONEN</name>
|
|
<description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The I2C monitor function is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The I2C monitor function is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUTEN</name>
|
|
<description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Time-out function is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONCLKSTR</name>
|
|
<description>Monitor function Clock Stretching.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. The monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the monitor function.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status register for Master, Slave, and Monitor functions.</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000801</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPENDING</name>
|
|
<description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IN_PROGRESS</name>
|
|
<description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTSTATE</name>
|
|
<description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle. The Master function is available to be used for a new transaction.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RECEIVE_READY</name>
|
|
<description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT_READY</name>
|
|
<description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NACK_ADDRESS</name>
|
|
<description>NACK Address. Slave NACKed address.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NACK_DATA</name>
|
|
<description>NACK Data. Slave NACKed transmitted data.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTARBLOSS</name>
|
|
<description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_LOSS</name>
|
|
<description>No loss. No Arbitration Loss has occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBITRATION_LOSS</name>
|
|
<description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MSTSTSTPERR</name>
|
|
<description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_STARTSTOP_ERROR</name>
|
|
<description>No Start/Stop Error has occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STARTSTOP_ERROR_HAS</name>
|
|
<description>Start/stop error has occurred. The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLVPENDING</name>
|
|
<description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IN_PROGRESS</name>
|
|
<description>In progress. The Slave function does not currently need service.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSTATE</name>
|
|
<description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS</name>
|
|
<description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_RECEIVE</name>
|
|
<description>Slave receive. Received data is available (Slave Receiver mode).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_TRANSMIT</name>
|
|
<description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVNOTSTR</name>
|
|
<description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STRETCHING</name>
|
|
<description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_STRETCHING</name>
|
|
<description>Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVIDX</name>
|
|
<description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS_0_WAS</name>
|
|
<description>Slave address 0 was matched.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS_1_WAS</name>
|
|
<description>Slave address 1 was matched.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS_2_WAS</name>
|
|
<description>Slave address 2 was matched.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS_3_WAS</name>
|
|
<description>Slave address 3 was matched.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSEL</name>
|
|
<description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_SELECTED</name>
|
|
<description>Not selected. The Slave function is not currently selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTED</name>
|
|
<description>Selected. The Slave function is currently selected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVDESEL</name>
|
|
<description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DESELECTED</name>
|
|
<description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESELECTED</name>
|
|
<description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONRDY</name>
|
|
<description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_DATA</name>
|
|
<description>No data. The Monitor function does not currently have data available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_WAITING</name>
|
|
<description>Data waiting. The Monitor function has data waiting to be read.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONOV</name>
|
|
<description>Monitor Overflow flag.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_OVERRUN</name>
|
|
<description>No overrun. Monitor data has not overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONACTIVE</name>
|
|
<description>Monitor Active flag. This flag indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. The Monitor function considers the I2C bus to be active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONIDLE</name>
|
|
<description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_IDLE</name>
|
|
<description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EVENTTIMEOUT</name>
|
|
<description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_TIME_OUT</name>
|
|
<description>No time-out. I2C bus events have not caused a time-out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_TIME_OUT</name>
|
|
<description>Event time-out. The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLTIMEOUT</name>
|
|
<description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_TIME_OUT</name>
|
|
<description>No time-out. SCL low time has not caused a time-out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIME_OUT</name>
|
|
<description>Time-out. SCL low time has caused a time-out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>Interrupt Enable Set and read register.</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPENDINGEN</name>
|
|
<description>Master Pending interrupt Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MSTPENDING_INTER</name>
|
|
<description>The MstPending interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MSTPENDING_INTER</name>
|
|
<description>The MstPending interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MSTARBLOSSEN</name>
|
|
<description>Master Arbitration Loss interrupt Enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MSTARBLOSS_INTER</name>
|
|
<description>The MstArbLoss interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MSTARBLOSS_INTER</name>
|
|
<description>The MstArbLoss interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MSTSTSTPERREN</name>
|
|
<description>Master Start/Stop Error interrupt Enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MSTSTSTPERR_INTE</name>
|
|
<description>The MstStStpErr interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MSTSTSTPERR_INTE</name>
|
|
<description>The MstStStpErr interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLVPENDINGEN</name>
|
|
<description>Slave Pending interrupt Enable.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SLVPENDING_INTER</name>
|
|
<description>The SlvPending interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SLVPENDING_INTER</name>
|
|
<description>The SlvPending interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLVNOTSTREN</name>
|
|
<description>Slave Not Stretching interrupt Enable.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SLVNOTSTR_INTERR</name>
|
|
<description>The SlvNotStr interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SLVNOTSTR_INTERR</name>
|
|
<description>The SlvNotStr interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLVDESELEN</name>
|
|
<description>Slave Deselect interrupt Enable.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SLVDESEL_INTERRU</name>
|
|
<description>The SlvDeSel interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SLVDESEL_INTERRU</name>
|
|
<description>The SlvDeSel interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONRDYEN</name>
|
|
<description>Monitor data Ready interrupt Enable.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MONRDY_INTERRUPT</name>
|
|
<description>The MonRdy interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MONRDY_INTERRUPT</name>
|
|
<description>The MonRdy interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONOVEN</name>
|
|
<description>Monitor Overrun interrupt Enable.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MONOV_INTERRUPT</name>
|
|
<description>The MonOv interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MONOV_INTERRUPT</name>
|
|
<description>The MonOv interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MONIDLEEN</name>
|
|
<description>Monitor Idle interrupt Enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MONIDLE_INTERRUP</name>
|
|
<description>The MonIdle interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MONIDLE_INTERRUP</name>
|
|
<description>The MonIdle interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EVENTTIMEOUTEN</name>
|
|
<description>Event time-out interrupt Enable.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_EVENT_TIME_OUT_I</name>
|
|
<description>The Event time-out interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_EVENT_TIME_OUT_I</name>
|
|
<description>The Event time-out interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLTIMEOUTEN</name>
|
|
<description>SCL time-out interrupt Enable.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SCL_TIME_OUT_INT</name>
|
|
<description>The SCL time-out interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SCL_TIME_OUT_INT</name>
|
|
<description>The SCL time-out interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>Interrupt Enable Clear register.</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPENDINGCLR</name>
|
|
<description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MSTARBLOSSCLR</name>
|
|
<description>Master Arbitration Loss interrupt clear.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MSTSTSTPERRCLR</name>
|
|
<description>Master Start/Stop Error interrupt clear.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVPENDINGCLR</name>
|
|
<description>Slave Pending interrupt clear.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVNOTSTRCLR</name>
|
|
<description>Slave Not Stretching interrupt clear.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVDESELCLR</name>
|
|
<description>Slave Deselect interrupt clear.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONRDYCLR</name>
|
|
<description>Monitor data Ready interrupt clear.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONOVCLR</name>
|
|
<description>Monitor Overrun interrupt clear.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONIDLECLR</name>
|
|
<description>Monitor Idle interrupt clear.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EVENTTIMEOUTCLR</name>
|
|
<description>Event time-out interrupt clear.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCLTIMEOUTCLR</name>
|
|
<description>SCL time-out interrupt clear.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEOUT</name>
|
|
<description>Time-out value register.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOMIN</name>
|
|
<description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVVAL</name>
|
|
<description>This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I 2C function. 0x0002 = PCLK is divided by 3 before use by the I 2C function. ... 0xFFFF = PCLK is divided by 65,536 before use by the I2C function.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTPENDING</name>
|
|
<description>Master Pending.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MSTARBLOSS</name>
|
|
<description>Master Arbitration Loss flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MSTSTSTPERR</name>
|
|
<description>Master Start/Stop Error flag.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVPENDING</name>
|
|
<description>Slave Pending.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVNOTSTR</name>
|
|
<description>Slave Not Stretching status.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLVDESEL</name>
|
|
<description>Slave Deselected flag.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONRDY</name>
|
|
<description>Monitor Ready.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONOV</name>
|
|
<description>Monitor Overflow flag.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONIDLE</name>
|
|
<description>Monitor Idle flag.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EVENTTIMEOUT</name>
|
|
<description>Event time-out Interrupt flag.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCLTIMEOUT</name>
|
|
<description>SCL time-out Interrupt flag.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTCTL</name>
|
|
<description>Master control register.</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTCONTINUE</name>
|
|
<description>Master Continue. This bit is write-only.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUE</name>
|
|
<description>Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTSTART</name>
|
|
<description>Master Start control. This bit is write-only.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTSTOP</name>
|
|
<description>Master Stop control. This bit is write-only.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTDMA</name>
|
|
<description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. No DMA requests are generated for master operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTTIME</name>
|
|
<description>Master timing configuration.</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x77</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSTSCLLOW</name>
|
|
<description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>2_CLOCKS</name>
|
|
<description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCKS</name>
|
|
<description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_CLOCKS</name>
|
|
<description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_CLOCKS</name>
|
|
<description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_CLOCKS</name>
|
|
<description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_CLOCKS</name>
|
|
<description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_CLOCKS</name>
|
|
<description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_CLOCKS</name>
|
|
<description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MSTSCLHIGH</name>
|
|
<description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>2_CLOCKS</name>
|
|
<description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCKS</name>
|
|
<description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_CLOCKS</name>
|
|
<description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_CLOCKS</name>
|
|
<description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_CLOCKS</name>
|
|
<description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_CLOCKS</name>
|
|
<description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_CLOCKS</name>
|
|
<description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_CLOCKS</name>
|
|
<description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTDAT</name>
|
|
<description>Combined Master receiver and transmitter data register.</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLVCTL</name>
|
|
<description>Slave control register.</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLVCONTINUE</name>
|
|
<description>Slave Continue.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUE</name>
|
|
<description>Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVNACK</name>
|
|
<description>Slave NACK.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NACK</name>
|
|
<description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLVDMA</name>
|
|
<description>Slave DMA enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. No DMA requests are issued for Slave mode operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLVDAT</name>
|
|
<description>Combined Slave receiver and transmitter data register.</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>SLVADR%s</name>
|
|
<description>Slave address 0.</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADISABLE</name>
|
|
<description>Slave Address n Disable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Slave Address n is enabled and will be recognized with any changes specified by the SLVQUAL0 register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGNORED_SLAVE_ADDRES</name>
|
|
<description>Ignored Slave Address n is ignored.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVADR</name>
|
|
<description>Seven bit slave address that is compared to received addresses if enabled.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLVQUAL0</name>
|
|
<description>Slave Qualification for address 0.</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUALMODE0</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SLVQUAL0_FIELD_I</name>
|
|
<description>The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SLVQUAL0_FIELD_I</name>
|
|
<description>The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVQUAL0</name>
|
|
<description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <
|
|
= received address <= SLVQUAL0[7:1]).</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MONRXDAT</name>
|
|
<description>Monitor receiver data register.</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONRXDAT</name>
|
|
<description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins, and adds indication of Start, Repeated Start, and data NACK.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MONSTART</name>
|
|
<description>Monitor Received Start.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_DETECT</name>
|
|
<description>No detect. The monitor function has not detected a Start event on the I2C bus.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_DETECT</name>
|
|
<description>Start detect. The monitor function has detected a Start event on the I2C bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONRESTART</name>
|
|
<description>Monitor Received Repeated Start.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_START_DETECT</name>
|
|
<description>No start detect. The monitor function has not detected a Repeated Start event on the I2C bus.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATED_START_DETEC</name>
|
|
<description>Repeated start detect. The monitor function has detected a Repeated Start event on the I 2C bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONNACK</name>
|
|
<description>Monitor Received NACK.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACKNOWLEDGED</name>
|
|
<description>Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_ACKNOWLEDGED</name>
|
|
<description>Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>QEI</name>
|
|
<description> Quadrature Encoder Interface (QEI) </description>
|
|
<groupName>QEI</groupName>
|
|
<baseAddress>0x40058000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>QEI</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CON</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESP</name>
|
|
<description>Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESPI</name>
|
|
<description>Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESV</name>
|
|
<description>Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESI</name>
|
|
<description>Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Encoder status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 284.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000F0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRINV</name>
|
|
<description>Direction invert. When = 1, complements the DIR bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIGMODE</name>
|
|
<description>Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPMODE</name>
|
|
<description>Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVINX</name>
|
|
<description>Invert Index. When set, inverts the sense of the index input.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRESPI</name>
|
|
<description>Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INXGATE</name>
|
|
<description>Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POS</name>
|
|
<description>Position register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>Current position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXPOS</name>
|
|
<description>Maximum position register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXPOS</name>
|
|
<description>Maximum position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS0</name>
|
|
<description>position compare register 0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP0</name>
|
|
<description>Position compare value 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS1</name>
|
|
<description>position compare register 1</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP1</name>
|
|
<description>Position compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS2</name>
|
|
<description>position compare register 2</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP2</name>
|
|
<description>Position compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCNT</name>
|
|
<description>Index count register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENCPOS</name>
|
|
<description>Current encoder position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP0</name>
|
|
<description>Index compare register 0</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP0</name>
|
|
<description>Index compare value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<description>Velocity timer reload register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELLOAD</name>
|
|
<description>Current velocity timer pre-load value.The velocity timer counts down from this value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIME</name>
|
|
<description>Velocity timer register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELVAL</name>
|
|
<description>Current velocity timer value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VEL</name>
|
|
<description>Velocity counter register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELPC</name>
|
|
<description>Current velocity pulse count.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP</name>
|
|
<description>Velocity capture register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELCAP</name>
|
|
<description>Velocity capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VELCOMP</name>
|
|
<description>Velocity compare register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELCMP</name>
|
|
<description>Velocity compare value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHA</name>
|
|
<description>Digital filter register on input phase A (QEI_A)</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTA</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHB</name>
|
|
<description>Digital filter register on input phase B (QEI_B)</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTB</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERINX</name>
|
|
<description>Digital filter register on input index (QEI_IDX)</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FITLINX</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window width</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP1</name>
|
|
<description>Index compare register 1</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP1</name>
|
|
<description>Index compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP2</name>
|
|
<description>Index compare register 2</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP2</name>
|
|
<description>Index compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEC</name>
|
|
<description>Interrupt enable clear register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_EN</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_EN</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_EN</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_EN</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_EN</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_EN</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index 0 compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IES</name>
|
|
<description>Interrupt enable set register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_EN</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_EN</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_EN</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_EN</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_EN</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_EN</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1 compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>Interrupt enable clear register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR</name>
|
|
<description>Interrupt status clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET</name>
|
|
<description>Interrupt status set register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_INT</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_INT</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_INT</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_INT</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_INT</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_INT</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_INT</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_INT</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_INT</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV0_INT</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_INT</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_INT</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set and the REV1_INT is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_INT</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set and the REV2_INT is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_INT</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_INT</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_INT</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>SYSCON</name>
|
|
<description> System configuration (SYSCON)</description>
|
|
<groupName>SYSCON</groupName>
|
|
<baseAddress>0x40074000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BOD_IRQ</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SYSMEMREMAP</name>
|
|
<description>System memory remap</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAP</name>
|
|
<description>tbd</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>RESERVED</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTCKCAL</name>
|
|
<description>System tick counter calibration</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>System tick timer calibration value</description>
|
|
<bitRange>[25:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMISRC</name>
|
|
<description>NMI Source Control</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQNO</name>
|
|
<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 3 for the list of interrupt sources and their IRQ numbers.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NMIEN</name>
|
|
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSRSTSTAT</name>
|
|
<description>System reset status register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>POR reset status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_POR_DETECTED</name>
|
|
<description>No POR detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POR_DETECTED_WRITIN</name>
|
|
<description>POR detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTRST</name>
|
|
<description>Status of the external RESET pin. External reset status.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESET_EVENT_DETEC</name>
|
|
<description>No reset event detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_DETECTED_WRIT</name>
|
|
<description>Reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Status of the Watchdog reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_WDT_RESET_DETECTE</name>
|
|
<description>No WDT reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_RESET_DETECTED_</name>
|
|
<description>WDT reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD</name>
|
|
<description>Status of the Brown-out detect reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_BOD_RESET_DETECTE</name>
|
|
<description>No BOD reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOD_RESET_DETECTED_</name>
|
|
<description>BOD reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRST</name>
|
|
<description>Status of the software system reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_SYSTEM_RESET_DETE</name>
|
|
<description>No System reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_RESET_DETECTE</name>
|
|
<description>System reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESETCTRL0</name>
|
|
<description>Peripheral reset control 0</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH_RST</name>
|
|
<description>Flash reset control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_FLASH_RESET_</name>
|
|
<description>Clear flash reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_FLASH_RESET_</name>
|
|
<description>Assert flash reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMC_RST</name>
|
|
<description>FMC reset control FMC? Is this the flash controller?</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_FMC_RESET_</name>
|
|
<description>Clear FMC reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_FMC_RESET_</name>
|
|
<description>Assert FMC reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_RST</name>
|
|
<description>EEPROM reset control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_EEPROM_RESET_</name>
|
|
<description>Clear EEPROM reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_EEPROM_RESET_</name>
|
|
<description>Assert EEPROM reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PMUX_RST</name>
|
|
<description>Pin mux reset control</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_PIN_MUX_RESET_</name>
|
|
<description>Clear pin mux reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_PIN_MUX_RESET</name>
|
|
<description>Assert pin mux reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOCON_RST</name>
|
|
<description>IOCON reset control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_IOCON_RESET_</name>
|
|
<description>Clear IOCON reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_IOCON_RESET_</name>
|
|
<description>Assert IOCON reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO0_RST</name>
|
|
<description>GPIO0 reset control</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_GPIO0_RESET_</name>
|
|
<description>Clear GPIO0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_GPIO0_RESET_</name>
|
|
<description>Assert GPIO0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO1_RST</name>
|
|
<description>GPIO1 reset control</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_GPIO1_RESET_</name>
|
|
<description>Clear GPIO1 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_GPIO1_RESET_</name>
|
|
<description>Assert GPIO1 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO2_RST</name>
|
|
<description>GPIO2 reset control</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_GPIO2_RESET_</name>
|
|
<description>Clear GPIO2 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_GPIO2_RESET_</name>
|
|
<description>Assert GPIO2 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PINT_RST</name>
|
|
<description>Pin interrupt (PINT) reset control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_PINT_RESET_</name>
|
|
<description>Clear PINT reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_PINT_RESET_</name>
|
|
<description>Assert PINT reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GINT_RST</name>
|
|
<description>Grouped interrupt (GINT) reset control</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_GINT_RESET_</name>
|
|
<description>Clear GINT reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_GINT_RESET_</name>
|
|
<description>Assert GINT reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA_RST</name>
|
|
<description>DMA reset control</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_DMA_RESET_</name>
|
|
<description>Clear DMA reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_DMA_RESET_</name>
|
|
<description>Assert DMA reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC_RST</name>
|
|
<description>CRC generator reset control</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_CRC_RESET_</name>
|
|
<description>Clear CRC reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_CRC_RESET_</name>
|
|
<description>Assert CRC reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[26:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC0_RST</name>
|
|
<description>ADC0 reset control</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_ADC0_RESET_</name>
|
|
<description>Clear ADC0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_ADC0_RESET_</name>
|
|
<description>Assert ADC0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_RST</name>
|
|
<description>ADC1 reset control</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_ADC1_RESET_</name>
|
|
<description>Clear ADC1 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_ADC1_RESET_</name>
|
|
<description>Assert ADC1 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC_RST</name>
|
|
<description>DAC reset control</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_DAC_RESET_</name>
|
|
<description>Clear DAC reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_DAC_RESET_</name>
|
|
<description>Assert DAC reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP_RST</name>
|
|
<description>Analog Comparator (ACMP) reset control for all four 4 comparators in the analog comparator block.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_CMP_RESET_</name>
|
|
<description>Clear CMP reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_CMP_RESET_</name>
|
|
<description>Assert CMP reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESETCTRL1</name>
|
|
<description>Peripheral reset control 1</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MRT_RST</name>
|
|
<description>Multi-rate timer (MRT) reset control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_MRT_RESET_</name>
|
|
<description>Clear MRT reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_MRT_RESET_</name>
|
|
<description>Assert MRT reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIT_RST</name>
|
|
<description>Repetitive interrupt timer (RIT) reset control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_RIT_RESET_</name>
|
|
<description>Clear RIT reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_RIT_RESET_</name>
|
|
<description>Assert RIT reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0_RST</name>
|
|
<description>State configurable timer 0 (SCT0) reset control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SCT0_RESET_</name>
|
|
<description>Clear SCT0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SCT0_RESET_</name>
|
|
<description>Assert SCT0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1_RST</name>
|
|
<description>State configurable timer 1 (SCT1) reset control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SCT1_RESET_</name>
|
|
<description>Clear SCT1 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SCT1_RESET_</name>
|
|
<description>Assert SCT1 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT2_RST</name>
|
|
<description>State configurable timer 2 (SCT2) reset control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SCT2_RESET_</name>
|
|
<description>Clear SCT2 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SCT2_RESET_</name>
|
|
<description>Assert SCT2 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT3_RST</name>
|
|
<description>State configurable timer 3 (SCT3) reset control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SCT3_RESET_</name>
|
|
<description>Clear SCT3 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SCT3_RESET_</name>
|
|
<description>Assert SCT3 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCTIPU_RST</name>
|
|
<description>State configurable timer IPU (SCTIPU) reset control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SCTIPU_RESET_</name>
|
|
<description>Clear SCTIPU reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SCTIPU_RESET_</name>
|
|
<description>Assert SCTIPU reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCAN_RST</name>
|
|
<description>CCAN reset control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_CCAN_RESET_</name>
|
|
<description>Clear CCAN reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_CCAN_RESET_</name>
|
|
<description>Assert CCAN reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SPI0_RST</name>
|
|
<description>SPI0 reset control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SPI0_RESET_</name>
|
|
<description>Clear SPI0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SPI0_RESET_</name>
|
|
<description>Assert SPI0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1_RST</name>
|
|
<description>SPI1 reset control</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_SPI1_RESET_</name>
|
|
<description>Clear SPI1 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_SPI1_RESET_</name>
|
|
<description>Assert SPI1 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2C0_RST</name>
|
|
<description>I2C0 reset control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_I2C0_RESET_</name>
|
|
<description>Clear I2C0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_I2C0_RESET_</name>
|
|
<description>Assert I2C0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UART0_RST</name>
|
|
<description>UART0 reset control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_UART0_RESET_</name>
|
|
<description>Clear UART0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_UART0_RESET_</name>
|
|
<description>Assert UART0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RST</name>
|
|
<description>UART1 reset control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_UART1_RESET_</name>
|
|
<description>Clear UART1 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_UART1_RESET_</name>
|
|
<description>Assert UART1 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2_RST</name>
|
|
<description>UART2 reset control</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_UART2_RESET_</name>
|
|
<description>Clear UART2 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_UART2_RESET_</name>
|
|
<description>Assert UART2 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>QEI0_RST</name>
|
|
<description>QEI0 reset control</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_QEI0_RESET_</name>
|
|
<description>Clear QEI0 reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_QEI0_RESET_</name>
|
|
<description>Assert QEI0 reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB_RST</name>
|
|
<description>USB reset control</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_USB_RESET_</name>
|
|
<description>Clear USB reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_USB_RESET_</name>
|
|
<description>Assert USB reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP0</name>
|
|
<description>POR captured PIO status 0</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIOSTAT</name>
|
|
<description>State of PIO0_31 through PIO0_0 at power-on reset</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP1</name>
|
|
<description>POR captured PIO status 1</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIOSTAT</name>
|
|
<description>State of PIO1_31 through PIO1_0 at power-on reset</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP2</name>
|
|
<description>POR captured PIO status 2</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIOSTAT</name>
|
|
<description>State of PIO2_11 through PIO2_0 at power-on reset</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKSELA</name>
|
|
<description>Main clock source select A</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Clock source for main clock source selector A</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC Oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR</name>
|
|
<description>Watchdog oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKSELB</name>
|
|
<description>Main clock source select B</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Clock source for main clock source selector B. Selects the clock source for the main clock.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MAINCLKSELA_CLOCK_S</name>
|
|
<description>MAINCLKSELA. Clock source selected in MAINCLKSELA register.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_PLL_INPUT_</name>
|
|
<description>System PLL input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_PLL_OUTPUT_</name>
|
|
<description>System PLL output.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_OSCILLATOR_32_KH</name>
|
|
<description>RTC oscillator 32 kHz output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKSEL</name>
|
|
<description>USB clock source select</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>USB clock source.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC Oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PLL_OUT</name>
|
|
<description>USB PLL out</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCASYNCCLKSEL</name>
|
|
<description>ADC asynchronous clock source select</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>USB clock source.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC Oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_PLL_OUTPUT</name>
|
|
<description>System PLL output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PLL_OUTPUT</name>
|
|
<description>USB PLL output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_PLL_OUTPUT</name>
|
|
<description>SCT PLL output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTSELA</name>
|
|
<description>CLKOUT clock source select A</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>CLKOUT clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR_</name>
|
|
<description>Crystal oscillator (SYSOSC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR</name>
|
|
<description>Watchdog oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTSELB</name>
|
|
<description>CLKOUT clock source select B</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>CLKOUT clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLKOUTSELA_CLOCK_SO</name>
|
|
<description>CLKOUTSELA. Clock source selected in the CLKOUTSELA register.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PLL_OUTPUT_</name>
|
|
<description>USB PLL output .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_PLL_OUTPUT_</name>
|
|
<description>SCT PLL output .</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_32_KHZ_OUTPUT_</name>
|
|
<description>RTC 32 kHz output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCLKSEL</name>
|
|
<description>System PLL clock source select</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>System PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR_</name>
|
|
<description>Crystal Oscillator (SYSOSC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLCLKSEL</name>
|
|
<description>USB PLL clock source select</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>USB PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_THE_USB_PLL_CLO</name>
|
|
<description>IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation.In low-speed mode IRC is ok?</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCTPLLCLKSEL</name>
|
|
<description>SCT PLL clock source select</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>SCT PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKDIV</name>
|
|
<description>System clock divider</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKCTRL0</name>
|
|
<description>System clock control 0</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYS</name>
|
|
<description>Enables the clock for the AHB, the APB bridges, the Cortex-M3 core clocks, SYSCON, reset control, SRAM0, and the PMU. This bit is read-only and always reads as 1.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Enables clock for ROM.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRAM1</name>
|
|
<description>Enables clock for SRAM1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRAM2</name>
|
|
<description>Enables clock for SRAM2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASH</name>
|
|
<description>Enables clock for flash memory.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMC</name>
|
|
<description>Enables clock for flash controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM</name>
|
|
<description>Enables clock for EEPROM.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PMUX</name>
|
|
<description>Enables clock for pin mux.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWM</name>
|
|
<description>Enables clock for switch matrix.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOCON</name>
|
|
<description>Enables clock for IOCON block.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO0</name>
|
|
<description>Enables clock for GPIO0 port registers.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO1</name>
|
|
<description>Enables clock for GPIO1 port registers.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO2</name>
|
|
<description>Enables clock for GPIO2 port registers.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PINT</name>
|
|
<description>Enables clock for pin interrupt block.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GINT</name>
|
|
<description>Enables clock for grouped pin interrupt block.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>Enables clock for DMA.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>Enables clock for CRC.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WWDT</name>
|
|
<description>Enables clock for WWDT.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Enables clock for RTC.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADC0</name>
|
|
<description>Enables clock for ADC0 register interface.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1</name>
|
|
<description>Enables clock for ADC1 register interface.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC</name>
|
|
<description>Enables clock for DAC.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Enables clock to analog comparator block. This is the clock to the register interface for all 4 comparators.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKCTRL1</name>
|
|
<description>System clock control 1</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MRT</name>
|
|
<description>Enables clock for multi-rate timer.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIT</name>
|
|
<description>Enables clock for repetitive interrupt timer.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT0</name>
|
|
<description>Enables clock for SCT0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT1</name>
|
|
<description>Enables clock for SCT1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT2</name>
|
|
<description>Enables clock for SCT2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCT3</name>
|
|
<description>Enables clock for SCT3.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCTIPU</name>
|
|
<description>Enables clock for SCTIPU.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCAN</name>
|
|
<description>Enables clock for CCAN.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>Enables clock for SPI0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1</name>
|
|
<description>Enables clock for SPI1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>Enables clock for I2C0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>Enables clock for I2C1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[16:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UART0</name>
|
|
<description>Enables clock for USART0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1</name>
|
|
<description>Enables clock for USART1.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2</name>
|
|
<description>Enables clock for USART2.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>QEI</name>
|
|
<description>Enables clock for QEI.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB</name>
|
|
<description>Enables clock for USB register interface.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTICKCLKDIV</name>
|
|
<description>SYSTICK clock divider</description>
|
|
<addressOffset>0x0CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UARTCLKDIV</name>
|
|
<description>USART clock divider. Clock divider for the USART fractional baud rate generator.</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCONCLKDIV</name>
|
|
<description>Peripheral clock to the IOCON block for programmable glitch filter</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRACECLKDIV</name>
|
|
<description>ARM trace clock divider</description>
|
|
<addressOffset>0x0D8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKDIV</name>
|
|
<description>USB clock divider</description>
|
|
<addressOffset>0x0EC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCASYNCCLKDIV</name>
|
|
<description>Asynchronous ADC clock divider</description>
|
|
<addressOffset>0x0F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTDIV</name>
|
|
<description>CLKOUT clock divider</description>
|
|
<addressOffset>0x0F8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRGCTRL</name>
|
|
<description>USART fractional baud rate generator control</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>Numerator of the fractional divider. MULT is equal to the programmed value.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKCTRL</name>
|
|
<description>USB clock control</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AP_CLK</name>
|
|
<description>USB need_clock signal control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNDER_HARDWARE_CONTR</name>
|
|
<description>Under hardware control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_HIGH_</name>
|
|
<description>Forced HIGH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL_CLK</name>
|
|
<description>USB need_clock polarity for triggering the USB wake-up interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_THE_</name>
|
|
<description>Falling edge of the USB need_clock triggers the USB wake-up (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_THE_U</name>
|
|
<description>Rising edge of the USB need_clock triggers the USB wake-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKST</name>
|
|
<description>USB clock status</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEED_CLKST</name>
|
|
<description>USB need_clock signal status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>LOW</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>HIGH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BODCTRL</name>
|
|
<description>Brown-Out Detect</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BODRSTLEV</name>
|
|
<description>BOD reset level</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_THE_RESET_A</name>
|
|
<description>Level 0: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_THE_RESET_A</name>
|
|
<description>Level 1: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_RESET_A</name>
|
|
<description>Level 2: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is .</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_RESET_A</name>
|
|
<description>Level 3: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODINTVAL</name>
|
|
<description>BOD interrupt level</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_THE_INTERRU</name>
|
|
<description>Level 0: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_THE_INTERRU</name>
|
|
<description>Level 1: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_INTERRU</name>
|
|
<description>Level 2: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is .</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_INTERRU</name>
|
|
<description>Level 3: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is .</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRSTENA</name>
|
|
<description>BOD reset enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_RESET_FUNCTI</name>
|
|
<description>Disable reset function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_RESET_FUNCTIO</name>
|
|
<description>Enable reset function.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSOSCCTRL</name>
|
|
<description>System oscillator control</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass system oscillator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_OSCILLATOR</name>
|
|
<description>Disabled. Oscillator is not bypassed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_PLL_INPUT_</name>
|
|
<description>Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FREQRANGE</name>
|
|
<description>Determines frequency range for Low-power oscillator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1__20_MHZ_FREQUENCY</name>
|
|
<description>1 - 20 MHz frequency range.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15__25_MHZ_FREQUENC</name>
|
|
<description>15 - 25 MHz frequency range</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCOSCCTRL</name>
|
|
<description>RTC oscillator control</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>RTC 32 kHz clock enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_RTC_CLOCK_</name>
|
|
<description>Disabled. RTC clock off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_RTC_CLOCK_O</name>
|
|
<description>Enabled. RTC clock on.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCTRL</name>
|
|
<description>System PLL control</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLSTAT</name>
|
|
<description>System PLL status</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLCTRL</name>
|
|
<description>USB PLL control</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLSTAT</name>
|
|
<description>USB PLL status</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCTPLLCTRL</name>
|
|
<description>SCT PLL control</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 111111: Division ratio M = 64.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCTPLLSTAT</name>
|
|
<description>SCT PLL status</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDAWAKECFG</name>
|
|
<description>Power-down states for wake-up from deep-sleep</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output wake-up configuration</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC</name>
|
|
<description>IRC oscillator wake-up configuration</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH</name>
|
|
<description>Flash memory wake-up configuration</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM</name>
|
|
<description>EEPROM wake-up configuration</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD wake-up configuration</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_PD</name>
|
|
<description>USB PHY wake-up configuration</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_PD</name>
|
|
<description>ADC0 wake-up configuration</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_PD</name>
|
|
<description>ADC1 wake-up configuration</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC_PD</name>
|
|
<description>DAC wake-up configuration</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0_PD</name>
|
|
<description>Analog comparator 0 wake-up configuration</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1_PD</name>
|
|
<description>Analog comparator 1 wake-up configuration</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP2_PD</name>
|
|
<description>Analog comparator 2 wake-up configuration</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP3_PD</name>
|
|
<description>Analog comparator 3 wake-up configuration</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREF_PD</name>
|
|
<description>Internal voltage reference wake-up configuration</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS_PD</name>
|
|
<description>Temperature sensor wake-up configuration</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDADIV_PD</name>
|
|
<description>VDDA divider what is this for? wake-up configuration</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator wake-up configuration.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>System oscillator wake-up configuration</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL wake-up configuration</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPLL_PD</name>
|
|
<description>USB PLL wake-up configuration</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCTPLL_PD</name>
|
|
<description>USB PLL wake-up configuration</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:25]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDRUNCFG</name>
|
|
<description>Power configuration register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC</name>
|
|
<description>IRC oscillator</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH</name>
|
|
<description>Flash memory</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM</name>
|
|
<description>EEPROM</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD power-down</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_PD</name>
|
|
<description>USB PHY power-down</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_PD</name>
|
|
<description>ADC0 power-down</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_PD</name>
|
|
<description>ADC1 power-down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAC_PD</name>
|
|
<description>DAC power-down</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0_PD</name>
|
|
<description>Analog comparator 0 power-down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1_PD</name>
|
|
<description>Analog comparator 1 power-down</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP2_PD</name>
|
|
<description>Analog comparator 2 power-down</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP3_PD</name>
|
|
<description>Analog comparator 3 power-down</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREF_PD</name>
|
|
<description>Internal voltage reference power-down</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS_PD</name>
|
|
<description>Temperature sensor power-down</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDADIV_PD</name>
|
|
<description>VDDA divider what is this for?</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator power-down .</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>System oscillator power-down</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL power-down</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPLL_PD</name>
|
|
<description>USB PLL power-down</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCTPLL_PD</name>
|
|
<description>USB PLL power-down</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:25]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTERP0</name>
|
|
<description>Start logic 0 wake-up enable register</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WWDT</name>
|
|
<description>WWDT interrupt wake-up.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD</name>
|
|
<description>BOD interrupt wake-up.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GINT0</name>
|
|
<description>Group interrupt 0 wake-up.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GINT1</name>
|
|
<description>Group interrupt 1 wake-up.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT0</name>
|
|
<description>GPIO pin interrupt 0 wake-up</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT1</name>
|
|
<description>GPIO pin interrupt 1 wake-up</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT2</name>
|
|
<description>GPIO pin interrupt 2 wake-up</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT3</name>
|
|
<description>GPIO pin interrupt 3 wake-up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT4</name>
|
|
<description>GPIO pin interrupt 4 wake-up</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT5</name>
|
|
<description>GPIO pin interrupt 5 wake-up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT6</name>
|
|
<description>GPIO pin interrupt 6 wake-up</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT7</name>
|
|
<description>GPIO pin interrupt 7 wake-up</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[20:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USART0</name>
|
|
<description>USART0 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode..</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1</name>
|
|
<description>USART1 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode...</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART2</name>
|
|
<description>USART2 interrupt wake-up. Configure USART in synchronous slave mode or in 32 kHz mode...</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C</name>
|
|
<description>I2C interrupt wake-up.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>SPI0 interrupt wake-up</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1</name>
|
|
<description>SPI1 interrupt wake-up</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB_WAKEUP</name>
|
|
<description>USB need_clock signal wake-up</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTERP1</name>
|
|
<description>Start logic 1 wake-up enable register</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ACMP0</name>
|
|
<description>Analog comparator 0 interrupt wake-up</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1</name>
|
|
<description>Analog comparator 1 interrupt wake-up</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP2</name>
|
|
<description>Analog comparator 2 interrupt wake-up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP3</name>
|
|
<description>Analog comparator 3 interrupt wake-up</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTCALARM</name>
|
|
<description>RTC alarm interrupt wake-up</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCWAKE</name>
|
|
<description>RTC wake-up interrupt wake-up</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<description>ADC1</description>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC1_SEQA</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC1_SEQB</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC1_THCMP</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC1_OVR</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>MRT</name>
|
|
<description>Multi-Rate Timer (MRT) </description>
|
|
<groupName>MRT</groupName>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MRT</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>INTVAL%s</name>
|
|
<description>MRT0 Time interval value register. This value is loaded into the TIMER0 register.</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IVALUE</name>
|
|
<description>Time interval load value. This value is loaded into the TIMERn register and the MRTn starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[30:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LOAD</name>
|
|
<description>Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_FORCE_LOAD</name>
|
|
<description>No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_LOAD</name>
|
|
<description>Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>TIMER%s</name>
|
|
<description>MRT0 Timer register. This register reads the value of the down-counter.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>CTRL%s</name>
|
|
<description>MRT0 Control register. This register controls the MRT0 modes.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Enable the TIMERn interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects timer mode.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>REPEAT_INTERRUPT_MOD</name>
|
|
<description>Repeat interrupt mode.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_SHOT_INTERRUPT_M</name>
|
|
<description>One-shot interrupt mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STAT%s</name>
|
|
<description>MRT0 Status register.</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTFLAG</name>
|
|
<description>Monitors the interrupt flag.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING_INTERRUPT</name>
|
|
<description>Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Indicates the state of TIMERn. This bit is read-only.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE_STATE</name>
|
|
<description>Idle state. TIMERn is stopped.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUNNING</name>
|
|
<description>Running. TIMERn is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDLE_CH</name>
|
|
<description>Idle channel register. This register returns the number of the first idle channel.</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHAN</name>
|
|
<description>Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. If all timer channels are running, CHAN = 4. To make sure that all outstanding interrupt requests have been serviced, a channel is considered idle only when both the corresponding RUN bit and the interrupt flag are zero in the STATUS register.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_FLAG</name>
|
|
<description>Global interrupt flag register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GFLAG0</name>
|
|
<description>Monitors the interrupt flag of TIMER0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING_INTERRUPT</name>
|
|
<description>Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GFLAG1</name>
|
|
<description>Monitors the interrupt flag of TIMER1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING_INTERRUPT</name>
|
|
<description>Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GFLAG2</name>
|
|
<description>Monitors the interrupt flag of TIMER2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING_INTERRUPT</name>
|
|
<description>Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GFLAG3</name>
|
|
<description>Monitors the interrupt flag of TIMER3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_PENDING_INTERRUPT</name>
|
|
<description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING_INTERRUPT</name>
|
|
<description>Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>PINT</name>
|
|
<description> Pin interrupt
|
|
and pattern match (PINT) </description>
|
|
<groupName>PINT</groupName>
|
|
<baseAddress>0x400A4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIN_INT0</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT1</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT2</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT3</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT4</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT5</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT6</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT7</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISEL</name>
|
|
<description>Pin Interrupt Mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMODE0</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE1</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE2</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE3</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE4</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE5</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE6</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE7</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENR</name>
|
|
<description>Pin interrupt level or rising edge interrupt enable register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENRL0</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL1</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL2</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL3</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL4</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL5</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL6</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL7</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENR</name>
|
|
<description>Pin interrupt level or rising edge interrupt set register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENRL0</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL1</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL2</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL3</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL4</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL5</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL6</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL7</name>
|
|
<description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENR</name>
|
|
<description>Pin interrupt level (rising edge interrupt) clear register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENRL0</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL1</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL2</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL3</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL4</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL5</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL6</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL7</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENF</name>
|
|
<description>Pin interrupt active level or falling edge interrupt enable register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENAF0</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF1</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF2</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF3</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF4</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF5</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF6</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF7</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENF</name>
|
|
<description>Pin interrupt active level or falling edge interrupt set register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENAF0</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF1</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF2</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF3</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF4</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF5</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF6</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF7</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENF</name>
|
|
<description>Pin interrupt active level or falling edge interrupt clear register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENAF0</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF1</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF2</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF3</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF4</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF5</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF6</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF7</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RISE</name>
|
|
<description>Pin interrupt rising edge register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDET0</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET1</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET2</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET3</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET4</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET5</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET6</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET7</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FALL</name>
|
|
<description>Pin interrupt falling edge register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FDET0</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET1</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET2</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET3</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET4</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET5</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET6</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET7</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IST</name>
|
|
<description>Pin interrupt status register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTAT0</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT1</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT2</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT3</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT4</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT5</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT6</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT7</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMCTRL</name>
|
|
<description>Pattern match interrupt control register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL_PMATCH</name>
|
|
<description>Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIN_INTERRUPT_INTER</name>
|
|
<description>Pin interrupt. Interrupts are driven in response to the standard pin interrupt function</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PATTERN_MATCH_INTER</name>
|
|
<description>Pattern match. Interrupts are driven in response to pattern matches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA_RXEV</name>
|
|
<description>Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_RXEV_OUTPU</name>
|
|
<description>Disabled. RXEV output to the cpu is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_RXEV_OUTPUT</name>
|
|
<description>Enabled. RXEV output to the cpu is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write 1s to unused bits.</description>
|
|
<bitRange>[23:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PMAT</name>
|
|
<description>This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMSRC</name>
|
|
<description>Pattern match interrupt bit-slice source register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Reserved</name>
|
|
<description>Software should not write 1s to unused bits.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRC0</name>
|
|
<description>Selects the input source for bit slice 0</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC1</name>
|
|
<description>Selects the input source for bit slice 1</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 1.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 1.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 1.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 1.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC2</name>
|
|
<description>Selects the input source for bit slice 2</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 2.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 2.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 2.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 2.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC3</name>
|
|
<description>Selects the input source for bit slice 3</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 3.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 3.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 3.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 3.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC4</name>
|
|
<description>Selects the input source for bit slice 4</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 4.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 4.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 4.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 4.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 4.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 4.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 4.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC5</name>
|
|
<description>Selects the input source for bit slice 5</description>
|
|
<bitRange>[25:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 5.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 5.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 5.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 5.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 5.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 5.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 5.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC6</name>
|
|
<description>Selects the input source for bit slice 6</description>
|
|
<bitRange>[28:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 6.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 6.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 6.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 6.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 6.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 6.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRC7</name>
|
|
<description>Selects the input source for bit slice 7</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_0_SELECTS_PIN</name>
|
|
<description>Input 0. Selects pin interrupt input 0 as the source to bit slice 7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_1_SELECTS_PIN</name>
|
|
<description>Input 1. Selects pin interrupt input 1 as the source to bit slice 7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_2_SELECTS_PIN</name>
|
|
<description>Input 2. Selects pin interrupt input 2 as the source to bit slice 7.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_3_SELECTS_PIN</name>
|
|
<description>Input 3. Selects pin interrupt input 3 as the source to bit slice 7.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_4_SELECTS_PIN</name>
|
|
<description>Input 4. Selects pin interrupt input 4 as the source to bit slice 7.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_5_SELECTS_PIN</name>
|
|
<description>Input 5. Selects pin interrupt input 5 as the source to bit slice 7.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_6_SELECTS_PIN</name>
|
|
<description>Input 6. Selects pin interrupt input 6 as the source to bit slice 7.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_7_SELECTS_PIN</name>
|
|
<description>Input 7. Selects pin interrupt input 7 as the source to bit slice 7.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMCFG</name>
|
|
<description>Pattern match interrupt bit slice configuration register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROD_ENDPTS</name>
|
|
<description>A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice).</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Bit slice 7 is automatically considered a product end point.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CFG0</name>
|
|
<description>Specifies the match contribution condition for bit slice 0.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG1</name>
|
|
<description>Specifies the match contribution condition for bit slice 1.</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG2</name>
|
|
<description>Specifies the match contribution condition for bit slice 2.</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG3</name>
|
|
<description>Specifies the match contribution condition for bit slice 3.</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG4</name>
|
|
<description>Specifies the match contribution condition for bit slice 4.</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG5</name>
|
|
<description>Specifies the match contribution condition for bit slice 5.</description>
|
|
<bitRange>[25:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG6</name>
|
|
<description>Specifies the match contribution condition for bit slice 6.</description>
|
|
<bitRange>[28:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFG7</name>
|
|
<description>Specifies the match contribution condition for bit slice 7.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_HIGH_THIS_</name>
|
|
<description>Constant HIGH. This bit slice always contributes to a product term match.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_EDGEMA</name>
|
|
<description>Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_FALLING_EDGE_</name>
|
|
<description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STICKY_RISING_OR_FAL</name>
|
|
<description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL_MATCH_F</name>
|
|
<description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL_MATCH_OCC</name>
|
|
<description>Low level. Match occurs when there is a low level on the specified input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONSTANT_0_THIS_BIT</name>
|
|
<description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_NON_STICKY_RI</name>
|
|
<description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>GINT0</name>
|
|
<description>
|
|
Group interrupt 0/1 (GINT0/1) </description>
|
|
<groupName>GINT</groupName>
|
|
<baseAddress>0x400A8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT0</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>GPIO grouped interrupt control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_REQUEST</name>
|
|
<description>No interrupt request is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_REQUEST_IS</name>
|
|
<description>Interrupt request is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMB</name>
|
|
<description>Combine enabled inputs for group interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR_FUNCTIONALITY_A_</name>
|
|
<description>OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND_FUNCTIONALITY_A</name>
|
|
<description>AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>Group interrupt trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_TRIGGERED</name>
|
|
<description>Edge-triggered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_TRIGGERED</name>
|
|
<description>Level-triggered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>PORT_POL[%s]</name>
|
|
<displayName>PORT_POL[%s]</displayName>
|
|
<description>GPIO grouped interrupt port 0 polarity register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL8</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL9</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL10</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL11</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL12</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL13</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL14</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL15</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL16</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL17</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL18</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL19</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL20</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL21</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL22</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL23</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL24</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL25</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL26</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL27</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL28</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL29</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL30</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL31</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>PORT_ENA[%s]</name>
|
|
<displayName>PORT_ENA[%s]</displayName>
|
|
<description>GPIO grouped interrupt port 0 enable register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA0</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA1</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA2</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA3</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA4</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA5</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA6</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA7</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA8</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA9</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA10</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA11</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA12</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA13</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA14</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA15</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA16</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA17</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA18</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA19</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA20</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA21</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA22</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA23</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA24</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA25</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA26</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA27</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA28</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA29</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA30</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA31</name>
|
|
<description>Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="GINT0">
|
|
<name>GINT1</name>
|
|
<description>GINT1</description>
|
|
<baseAddress>0x400AC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT1</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>RIT</name>
|
|
<description>Repetitive Interrupt Timer (RIT) </description>
|
|
<groupName>RIT</groupName>
|
|
<baseAddress>0x400B4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RIT</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>COMPVAL</name>
|
|
<description>Compare value LSB register. Holds the 32 LSBs of the compare value.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOMP</name>
|
|
<description>Compare register. Holds the 32 LSBs of the compare value which is compared to the counter.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK</name>
|
|
<description>Mask LSB register. This register holds the 32 LSB s of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMASK</name>
|
|
<description>Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RITINT</name>
|
|
<description>Interrupt flag</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_BIT_IS_SET_TO_1</name>
|
|
<description>This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_VALUE_DO</name>
|
|
<description>The counter value does not equal the masked compare value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITENCLR</name>
|
|
<description>Timer enable clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_WILL_BE_CL</name>
|
|
<description>The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_WILL_NOT_B</name>
|
|
<description>The timer will not be cleared to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITENBR</name>
|
|
<description>Timer enable for debug</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_IS_HALTED</name>
|
|
<description>The timer is halted when the processor is halted for debugging.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUG_HAS_NO_EFFECT</name>
|
|
<description>Debug has no effect on the timer operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITEN</name>
|
|
<description>Timer enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_ENABLED</name>
|
|
<description>Timer enabled. This can be overruled by a debug halt if enabled in bit 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_DISABLED</name>
|
|
<description>Timer disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER</name>
|
|
<description>Counter LSB register. 32 LSBs of the counter.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOUNTER</name>
|
|
<description>32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMPVAL_H</name>
|
|
<description>Compare value MSB register. Holds the 16 MSBs of the compare value.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOMP</name>
|
|
<description>Compare value MSB register. Holds the 16 MSBs of the compare value which is compared to the counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK_H</name>
|
|
<description>Mask MSB register. This register holds the 16 MSBs of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMASK</name>
|
|
<description>Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER_H</name>
|
|
<description>Counter MSB register. 16 MSBs of the counter.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOUNTER</name>
|
|
<description>16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SCTIPU</name>
|
|
<description> SCT Input Processing Unit (IPU) </description>
|
|
<groupName>SCTIPU</groupName>
|
|
<baseAddress>0x400B8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SAMPLE_CTRL</name>
|
|
<description>SCT IPU sample control register. Contains the input mux selects, latch/sample-enable mux selects, and sample overrride bits for the SAMPLE module.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IN0SEL</name>
|
|
<description>Select SCT IPU input source for output channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_A0_SELECT_</name>
|
|
<description>SAMPE_IN_A0. Select input SAMPLE_IN_A0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_B0_SELECT_</name>
|
|
<description>SAMPE_IN_B0. Select input SAMPLE_IN_B0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1SEL</name>
|
|
<description>Select SCT IPU input source for output channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_A1_SELECT_</name>
|
|
<description>SAMPE_IN_A1. Select input SAMPLE_IN_A1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_B1_SELECT_</name>
|
|
<description>SAMPE_IN_B1. Select input SAMPLE_IN_B1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2SEL</name>
|
|
<description>Select SCT IPU input source for output channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_A2_SELECT_</name>
|
|
<description>SAMPE_IN_A2. Select input SAMPLE_IN_A2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_B2_SELECT_</name>
|
|
<description>SAMPE_IN_B2. Select input SAMPLE_IN_B2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3SEL</name>
|
|
<description>Select. SCT IPU input source for output channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_A3_SELECT_</name>
|
|
<description>SAMPE_IN_A3. Select input SAMPLE_IN_A3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPE_IN_B3_SELECT_</name>
|
|
<description>SAMPE_IN_B3. Select input SAMPLE_IN_B3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_EN0SEL</name>
|
|
<description>Select the sample enable input as the latch/sample-enable control for the Sample_Output(0) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(0) latch.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(0) latch.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(0) latch.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(0) latch.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_EN1SEL</name>
|
|
<description>Select the sample enable input as the latch/sample-enable control for the Sample_Output(1) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(1) latch.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(1) latch.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(1) latch.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(1) latch.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_EN2SEL</name>
|
|
<description>Select the sample enable input as the latch/sample-enable control for the Sample_Output(2) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(2) latch.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(2) latch.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(2) latch.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(2) latch.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_EN3SEL</name>
|
|
<description>Select the sample enable input as the latch/sample-enable control for the Sample_Output(3) latch. Depending on the value of the corresponding LATCHn_EN bit, this latch is transparent when the LATCHn_EN bit is 1 or latched when the LATCHn_EN bit is 0.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_A as the latch/sample-enable control for the Sample_Output(3) latch.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_B as the latch/sample-enable control for the Sample_Output(3) latch.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_C as the latch/sample-enable control for the Sample_Output(3) latch.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SAMPLE_ENABL</name>
|
|
<description>Selects Sample_Enable_D as the latch/sample-enable control for the Sample_Output(3) latch.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LATCHEN0</name>
|
|
<description>Enable latch for output channel 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSPARENT_MODE_SA</name>
|
|
<description>Transparent mode. Sample_Output(0) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(0). The sample-enable control line selected for this latch has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCHED_MODE_THE_SA</name>
|
|
<description>Latched mode. The Sample_Output(0) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LATCHEN1</name>
|
|
<description>Enable latch for output channel 1.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSPARENT_MODE_SA</name>
|
|
<description>Transparent mode. Sample_Output(1) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(1). The sample-enable control line selected for this latch has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCHED_MODE_THE_SA</name>
|
|
<description>Latched mode. The Sample_Output(1) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LATCHEN2</name>
|
|
<description>Enable latch for output channel 2.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSPARENT_MODE_SA</name>
|
|
<description>Transparent mode. Sample_Output(2) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(2). The sample-enable control line selected for this latch has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCHED_MODE_THE_SA</name>
|
|
<description>Latched mode. The Sample_Output(2) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LATCHEN3</name>
|
|
<description>Enable latch for output channel 3.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSPARENT_MODE_SA</name>
|
|
<description>Transparent mode. Sample_Output(3) latch is forced into transparent mode. The selected Sample_Input is passed directly through to Sample_Output(3). The sample-enable control line selected for this latch has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LATCHED_MODE_THE_SA</name>
|
|
<description>Latched mode. The Sample_Output(3) latch is operational and will sample or latch based on the state of the selected sample-enable control signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>ABORT_ENABLE%s</name>
|
|
<description>SCT IPU abort enable register: Selects which input source contributes to ORed Abort Output 0.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA0</name>
|
|
<description>Enable abort source SCT_ABORT0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA1</name>
|
|
<description>Enable abort source SCT_ABORT1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA2</name>
|
|
<description>Enable abort source ACMP0 output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA3</name>
|
|
<description>Enable abort source ACMP1 output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA4</name>
|
|
<description>Enable abort source ACMP2 output.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA5</name>
|
|
<description>Enable abort source ACMP3 output.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA6</name>
|
|
<description>Enable abort source SCT0_OUT9.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA7</name>
|
|
<description>Enable abort source ADC0_THCMP_IRQ.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA8</name>
|
|
<description>Enable abort source ADC1_THCMP_IRQ.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>ABORT_SOURCE%s</name>
|
|
<description>SCT IPU abort source register: Status register indicating which input source caused abort output 0.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACT0</name>
|
|
<description>Source SCT_ABORT0 activated. This bit is set by hardware when the source is actived. Write 0 to clear. This function can be assigned to any pin via the PINASSIGN10 register in the switch matrix.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT1</name>
|
|
<description>Source SCT_ABORT1 activated. This bit is set by hardware when the source is actived. Write 0 to clear. This function can be assigned to any pin via the PINASSIGN10 register in the switch matrix.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT2</name>
|
|
<description>Source ACMP0 output activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT3</name>
|
|
<description>Source ACMP1 output activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT4</name>
|
|
<description>Source ACMP2 output activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT5</name>
|
|
<description>Source ACMP3 output activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT6</name>
|
|
<description>Source SCT0_OUT9 activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT7</name>
|
|
<description>Source ADC0_THCMP_IRQ activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACT8</name>
|
|
<description>Source ADC1_THCMP_IRQ activated. This bit is set by hardware when the source is actived. Write 0 to clear.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_ACTIVATED_</name>
|
|
<description>Not activated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVATED_</name>
|
|
<description>Activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>FLASHCTRL</name>
|
|
<description>Flash controller </description>
|
|
<groupName>FLASHCTRL</groupName>
|
|
<baseAddress>0x400BC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EE</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FMSSTART</name>
|
|
<description>Signature start address register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSSTOP</name>
|
|
<description>Signature stop-address register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPA</name>
|
|
<description>Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes.</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[30:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STRTBIST</name>
|
|
<description>When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW0</name>
|
|
<description>Signature word</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIG</name>
|
|
<description>32-bit signature.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART2</name>
|
|
<description>USART2</description>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART2</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>C_CAN0</name>
|
|
<description>Controller Area Network C_CAN0 </description>
|
|
<groupName>C_CAN0</groupName>
|
|
<baseAddress>0x400F0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>C_CAN0</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CNTL</name>
|
|
<description>CAN control</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialization</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STARTED</name>
|
|
<description>Started. Initialization is started. On reset, software needs to initialize the CAN controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Module interrupt enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_CAN_INTERRUP</name>
|
|
<description>Disable CAN interrupts. The interrupt line is always HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_CAN_INTERRUPT</name>
|
|
<description>Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIE</name>
|
|
<description>Status change interrupt enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_STATUS_CHANG</name>
|
|
<description>Disable status change interrupts. No status change interrupt will be generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_STATUS_CHANGE</name>
|
|
<description>Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ERROR_INTERR</name>
|
|
<description>Disable error interrupt. No error status interrupt will be generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ERROR_INTERRU</name>
|
|
<description>Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Disable automatic retransmission</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Automatic retransmission of disturbed messages enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Automatic retransmission disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCE</name>
|
|
<description>Configuration change enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_WRITE_ACCESS</name>
|
|
<description>No write access. The CPU has no write access to the bit timing register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE_ACCESS</name>
|
|
<description>Write access. The CPU has write access to the CANBT register while the INIT bit is one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test mode enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE</name>
|
|
<description>Test mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEC</name>
|
|
<description>Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STUFF_ERROR</name>
|
|
<description>Stuff error. More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORM_ERROR</name>
|
|
<description>Form error. A fixed format part of a received frame has the wrong format.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKERROR</name>
|
|
<description>AckError. The message this CAN core transmitted was not acknowledged.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT1ERROR</name>
|
|
<description>Bit1Error. During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT0ERROR</name>
|
|
<description>Bit0Error. During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRCERROR</name>
|
|
<description>CRCError. The CRC checksum was incorrect in the message received.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNUSED</name>
|
|
<description>Unused. No CAN bus event was detected (written by the CPU).</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOK</name>
|
|
<description>Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_TRANSMIT</name>
|
|
<description>No transmit. Since this bit was last reset by the CPU, no message has been successfully transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUCCESSFUL_TRANSMIT</name>
|
|
<description>Successful transmit. Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXOK</name>
|
|
<description>Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RECEIVE</name>
|
|
<description>No receive. Since this bit was last reset by the CPU, no message has been successfully received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUCCESSFUL_RECEIVE</name>
|
|
<description>Successful receive.Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPASS</name>
|
|
<description>Error passive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. The CAN controller is in the error active state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE</name>
|
|
<description>Passive. The CAN controller is in the error passive state as defined in the CAN 2.0 specification.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWARN</name>
|
|
<description>Warning status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BELOW_LIMIT</name>
|
|
<description>Below limit. Both error counters are below the error warning limit of 96.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_LIMIT</name>
|
|
<description>At limit. At least one of the error counters in the EC has reached the error warning limit of 96.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOFF</name>
|
|
<description>Busoff status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_CAN_MODULE_IS_NO</name>
|
|
<description>The CAN module is not in busoff.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_CAN_CONTROLLER_I</name>
|
|
<description>The CAN controller is in busoff state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EC</name>
|
|
<description>Error counter</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEC7_0</name>
|
|
<description>Transmit error counter Current value of the transmit error counter (maximum value 255)</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>REC6_0</name>
|
|
<description>Receive error counter Current value of the receive error counter (maximum value 127).</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Receive error passive</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BELOW_ERROR_LEVEL</name>
|
|
<description>Below error level. The receive counter is below the error passive level.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AT_ERROR_LEVEL</name>
|
|
<description>At error level. The receive counter has reached the error passive level as defined in the CAN2.0 specification.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BT</name>
|
|
<description>Bit timing register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x2301</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRP</name>
|
|
<description>Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>(Re)synchronization jump width Valid programmed values are 0 to 3.[1]</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG1</name>
|
|
<description>Time segment before the sample point Valid values are 1 to 15.[1]</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG2</name>
|
|
<description>Time segment after the sample point Valid values are 0 to 7.[1]</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Interrupt register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>0x0000 = No interrupt is pending. 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<description>Test register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BASIC</name>
|
|
<description>Basic mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Basic mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IF1 registers used as TX buffer, IF2 registers used as RX buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SILENT</name>
|
|
<description>Silent mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SILENT_MODE</name>
|
|
<description>Silent mode. The module is in silent mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBACK</name>
|
|
<description>Loop back mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Loop back mode is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Loop back mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Control of CAN_TXD pins</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONTROLLER</name>
|
|
<description>Controller. Level at the CAN_TXD pin is controlled by the CAN controller. This is the value at reset.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_POINT</name>
|
|
<description>Sample point. The sample point can be monitored at the CAN_TXD pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. CAN_TXD pin is driven LOW/dominant.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOGH</name>
|
|
<description>Hogh. CAN_TXD pin is driven HIGH/recessive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>Monitors the actual value of the CAN_RXD pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RECESSIVE</name>
|
|
<description>Recessive. The CAN bus is recessive (CAN_RXD = 1).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOMINANT</name>
|
|
<description>Dominant. The CAN bus is dominant (CAN_RXD = 0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>R/W</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRPE</name>
|
|
<description>Baud rate prescaler extension register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRPE</name>
|
|
<description>Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDREQ</name>
|
|
<description>Message interface command request</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MN</name>
|
|
<description>Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY flag</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DONE</name>
|
|
<description>Done. Set to zero by hardware when read/write action to this Command request register has finished.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>Busy. Set to one by hardware when writing to this Command request register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDMSK_W</name>
|
|
<description>Message interface command mask (write direction)</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA_B</name>
|
|
<description>Access data bytes 4-7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Data bytes 4-7 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer data bytes 4-7 to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_A</name>
|
|
<description>Access data bytes 0-3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Data bytes 0-3 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer data bytes 0-3 to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRQST</name>
|
|
<description>Access transmission request bit</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_TRANSMISSION_REQU</name>
|
|
<description>No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REQUEST_A_TRANSMISSI</name>
|
|
<description>Request a transmission. Set the TXRQST bit IF1/2_MCTRL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRINTPND</name>
|
|
<description>This bit is ignored in the write direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>Access control bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Control bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer control bits to message object</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Access arbitration bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Arbitration bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer Identifier, DIR, XTD, and MSGVAL bits to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Access mask bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Mask bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer Identifier MASK + MDIR + MXTD to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_RD</name>
|
|
<description>Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDMSK_R</name>
|
|
<description>Message interface command mask (read direction)</description>
|
|
<alternateRegister>IF%s_CMDMSK_W</alternateRegister>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA_B</name>
|
|
<description>Access data bytes 4-7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Data bytes 4-7 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer data bytes 4-7 to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_A</name>
|
|
<description>Access data bytes 0-3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Data bytes 0-3 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer data bytes 0-3 to IFx message buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEWDAT</name>
|
|
<description>Access new data bit</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear NEWDAT bit in the message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRINTPND</name>
|
|
<description>Clear interrupt pending bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. INTPND bit remains unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear INTPND bit in the message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>Access control bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Control bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer control bits to IFx message buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Access arbitration bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Arbitration bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Access mask bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>Unchanged. Mask bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSFER</name>
|
|
<description>Transfer. Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_RD</name>
|
|
<description>Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MSK1</name>
|
|
<description>Message interface mask 1</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSK15_0</name>
|
|
<description>Identifier mask [15:0]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Mask. The corresponding identifier bit is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MSK2</name>
|
|
<description>Message interface mask 2</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSK28_16</name>
|
|
<description>Identifier mask [28:16]</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. The corresponding bit in the identifier of the message cannot inhibit the match in the acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK</name>
|
|
<description>Mask. The corresponding identifier bit is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MDIR</name>
|
|
<description>Mask message direction</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WITHOUT_DIR_BIT</name>
|
|
<description>Without DIR bit. The message direction bit (DIR) has no effect on acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WITH_DIR_BIT</name>
|
|
<description>With DIR bit. The message direction bit (DIR) is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXTD</name>
|
|
<description>Mask extend identifier</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WITHOUT_XTD</name>
|
|
<description>Without XTD. The extended identifier bit (XTD) has no effect on acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WITH_XTD</name>
|
|
<description>With XTD. The extended identifier bit (XTD) is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_ARB1</name>
|
|
<description>Message interface arbitration 1</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID15_0</name>
|
|
<description>Message identifier [15:0] 29-bit identifier (extended frame) 11-bit identifier (standard frame)</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_ARB2</name>
|
|
<description>Message interface arbitration 2</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID28_16</name>
|
|
<description>Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Message direction</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RECEIVE</name>
|
|
<description>Receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TANSMIT</name>
|
|
<description>Tansmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTD</name>
|
|
<description>Extend identifier</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>Standard. The 11-bit standard identifier will be used for this message object.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTENDED</name>
|
|
<description>Extended. The 29-bit extended identifier will be used for this message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSGVAL</name>
|
|
<description>Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INVALID</name>
|
|
<description>Invalid. The message object is ignored by the message handler.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Valid. The message object is configured and should be considered by the message handler.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MCTRL</name>
|
|
<description>Message interface message control</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLC3_0</name>
|
|
<description>Data length code 3:0 The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EOB</name>
|
|
<description>End of buffer</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_END_OF_BUFFER</name>
|
|
<description>Not end of buffer. Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END_OF_BUFFER</name>
|
|
<description>End of buffer. Single message object or last message object of a FIFO buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRQST</name>
|
|
<description>Transmit request</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>Not waiting. This message object is not waiting for transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>Waiting. The transmission of this message object is requested and is not yet done</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMTEN</name>
|
|
<description>Remote enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TXRQST_UNCHANGED</name>
|
|
<description>TXRQST unchanged. At the reception of a remote frame, TXRQST is left unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXRQST_SET</name>
|
|
<description>TXRQST set. At the reception of a remote frame, TXRQST is set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTPND_UNCHANGED</name>
|
|
<description>INTPND unchanged. INTPND will be left unchanged after successful reception of a frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTPND_SET</name>
|
|
<description>INTPND set. INTPND will be set after successful reception of a frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTPND_UNCHANGED</name>
|
|
<description>INTPND unchanged. The INTPND bit will be left unchanged after a successful transmission of a frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTPND_SET</name>
|
|
<description>INTPND set. INTPND will be set after a successful transmission of a frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UMASK</name>
|
|
<description>Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IGNORE</name>
|
|
<description>Ignore. Mask ignored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE</name>
|
|
<description>Use. Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPND</name>
|
|
<description>Interrupt pending</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. This message object is not the source of an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>Pending. This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSGLST</name>
|
|
<description>Message lost (only valid for message objects in the direction receive).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_LOST</name>
|
|
<description>Not lost. No message lost since this bit was reset last by the CPU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOST</name>
|
|
<description>Lost. The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEWDAT</name>
|
|
<description>New data</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_NEW_DATA</name>
|
|
<description>No new data. No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEW_DATA</name>
|
|
<description>New data. The message handler or the CPU has written new data into the data portion of this message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DA1</name>
|
|
|
|
<description>Message interface data A1</description>
|
|
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Data byte 0</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DA2</name>
|
|
<description>Message interface 1 data A2</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Data byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Data byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DB1</name>
|
|
<description>Message interface 1 data B1</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Data byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Data byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DB2</name>
|
|
<description>Message interface 1 data B2</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Data byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Data byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXREQ1</name>
|
|
<description>Transmission request 1</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXRQST16_1</name>
|
|
<description>Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXREQ2</name>
|
|
<description>Transmission request 2</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXRQST32_17</name>
|
|
<description>Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ND1</name>
|
|
<description>New data 1</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEWDAT16_1</name>
|
|
<description>New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ND2</name>
|
|
<description>New data 2</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEWDAT32_17</name>
|
|
<description>New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR1</name>
|
|
<description>Interrupt pending 1</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPND16_1</name>
|
|
<description>Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR2</name>
|
|
<description>Interrupt pending 2</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPND32_17</name>
|
|
<description>Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSGV1</name>
|
|
<description>Message valid 1</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSGVAL16_1</name>
|
|
<description>Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSGV2</name>
|
|
<description>Message valid 2</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSGVAL32_17</name>
|
|
<description>Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>CAN clock divider register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIVVAL</name>
|
|
<description>Clock divider value. CAN_CLK = system clock/(CLKDIVVAL +1) 0000: CAN_CLK = system clock divided by 1. 0001: CAN_CLK = system clock divided by 2. 0010: CAN_CLK = system clockdivided by 3 0011: CAN_CLK = system clock divided by 4. ... 1111: CAN_CLK = system clock divided by 16.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>IOCON</name>
|
|
<description>I/O pin configuration (IOCON) </description>
|
|
<groupName>IOCON</groupName>
|
|
<baseAddress>0x400F8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>18</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-17</dimIndex>
|
|
<name>PIO0_%s</name>
|
|
<displayName>PIO0_%s</displayName>
|
|
<description>Digital I/O control for port 0 pins PIO0_0 to PIO0_17. With glitch filter.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>18-21</dimIndex>
|
|
<name>PIO0_%s</name>
|
|
<description>Digital I/O control for port 0 pins PIO0_18 to PIO0_21. Without glitch filter.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>22-23</dimIndex>
|
|
<name>PIO0_%s</name>
|
|
<description>I/O control for open-drain pin PIO0_22. This pin is used for the I2C-bus SCL function.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2CMODE</name>
|
|
<description>Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_MODE</name>
|
|
<description>Standard mode/ Fast-mode I2C.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDARD_IO_FUNCTIO</name>
|
|
<description>Standard I/O functionality</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_I2C</name>
|
|
<description>Fast-mode Plus I2C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>1</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>24-24</dimIndex>
|
|
<name>PIO0_%s</name>
|
|
<description>Digital I/O control for port 0 pins PIO0_24. Without glitch filter.</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>25-31</dimIndex>
|
|
<name>PIO0_%s</name>
|
|
<displayName>PIO0_%s</displayName>
|
|
<description>Digital I/O control for port 0 pins PIO0_25 to PIO0_31. With glitch filter.</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>11</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-10</dimIndex>
|
|
<name>PIO1_%s</name>
|
|
<description>Digital I/O control for port 1 pins PIO1_0 to PIO1_10. With glitch filter.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>21</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>11-31</dimIndex>
|
|
<name>PIO1_%s</name>
|
|
<description>Digital I/O control for port 1 pins PIO1_11 to PIO1_31. Without glitch filter.</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>14</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-13</dimIndex>
|
|
<name>PIO2_%s</name>
|
|
<description>Digital I/O control for port 2 pins PIO2_0 to PIO2_13. Without glitch filter.</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Only write 0 to these bits.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_MODE</name>
|
|
<description>Digital filter sample mode.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYPASS_INPUT_FILTER</name>
|
|
<description>Bypass input filter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_CLOCK_CYCLE</name>
|
|
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_CLOCK_CYCLES</name>
|
|
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_CLOCK_CYCLES</name>
|
|
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLK</name>
|
|
<description>CMP_PCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV2</name>
|
|
<description>CMP_PCLK/2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV4</name>
|
|
<description>CMP_PCLK/4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV8</name>
|
|
<description>CMP_PCLK/8.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV16</name>
|
|
<description>CMP_PCLK/16.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV32</name>
|
|
<description>CMP_PCLK/32.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMP_PCLKDIV64</name>
|
|
<description>CMP_PCLK/64.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
</peripherals>
|
|
</device>
|