20524 lines
902 KiB
XML
20524 lines
902 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>LPC11Uxx</name>
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<version>7</version>
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<description>LPC11Uxx</description>
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<cpu>
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<name>CM0</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>0</mpuPresent>
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<fpuPresent>0</fpuPresent>
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<nvicPrioBits>2</nvicPrioBits>
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<vendorSystickConfig>0</vendorSystickConfig>
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</cpu>
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<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<!--
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Software that is described herein is for illustrative purposes only
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which provides customers with programming information regarding the
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products. This software is supplied "AS IS" without any warranties.
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NXP Semiconductors assumes no responsibility or liability for the
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use of the software, conveys no license or title under any patent,
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copyright, or mask work right to the product. NXP Semiconductors
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reserves the right to make changes in the software without
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notification. NXP Semiconductors also make no representation or
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warranty that such application will be suitable for the specified
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use without further testing or modification.
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-->
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<!--
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v7 updates:
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- syscon block
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- ct16b0 block
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- ct32b1 block
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- iocon FILTR bit polarity reversed
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- readaction modify in uart rbr/thr, lsr, msr and in ssp dr registers
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- reset values in syscon updated
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-->
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<peripherals>
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<peripheral>
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<name>I2C</name>
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<description>I2C-bus controller</description>
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<groupName>I2C</groupName>
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<baseAddress>0x40000000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0xFFF</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>I2C</name>
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<value>15</value>
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</interrupt>
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<registers>
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<register>
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<name>CONSET</name>
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<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
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<addressOffset>0x000</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
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<bitRange>[1:0]</bitRange>
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</field>
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<field>
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<name>AA</name>
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<description>Assert acknowledge flag.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>SI</name>
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<description>I2C interrupt flag.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>STO</name>
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<description>STOP flag.</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>STA</name>
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<description>START flag.</description>
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<bitRange>[5:5]</bitRange>
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</field>
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<field>
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<name>I2EN</name>
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<description>I2C interface enable.</description>
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<bitRange>[6:6]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:7]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>STAT</name>
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<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
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<addressOffset>0x004</addressOffset>
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<access>read-only</access>
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<resetValue>0xF8</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>These bits are unused and are always 0.</description>
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<bitRange>[2:0]</bitRange>
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</field>
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<field>
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<name>Status</name>
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<description>These bits give the actual status information about the I2C interface.</description>
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<bitRange>[7:3]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>DAT</name>
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<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
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<addressOffset>0x008</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>Data</name>
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<description>This register holds data values that have been received or are to be transmitted.</description>
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<bitRange>[7:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>ADR0</name>
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<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
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<addressOffset>0x00C</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>GC</name>
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<description>General Call enable bit.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>Address</name>
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<description>The I2C device address for slave mode.</description>
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<bitRange>[7:1]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>SCLH</name>
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<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
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<addressOffset>0x010</addressOffset>
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<access>read-write</access>
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<resetValue>0x04</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>SCLH</name>
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<description>Count for SCL HIGH time period selection.</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>SCLL</name>
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<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
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<addressOffset>0x014</addressOffset>
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<access>read-write</access>
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<resetValue>0x04</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>SCLL</name>
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<description>Count for SCL low time period selection.</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>CONCLR</name>
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<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
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<addressOffset>0x018</addressOffset>
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<access>write-only</access>
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<resetValue>0</resetValue>
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<resetMask>0x00000000</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
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<bitRange>[1:0]</bitRange>
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</field>
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<field>
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<name>AAC</name>
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<description>Assert acknowledge Clear bit.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>SIC</name>
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<description>I2C interrupt Clear bit.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
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<bitRange>[4:4]</bitRange>
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</field>
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<field>
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<name>STAC</name>
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<description>START flag Clear bit.</description>
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<bitRange>[5:5]</bitRange>
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</field>
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<field>
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<name>I2ENC</name>
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<description>I2C interface Disable bit.</description>
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<bitRange>[6:6]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
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<bitRange>[7:7]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>MMCTRL</name>
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<description>Monitor mode control register.</description>
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<addressOffset>0x01C</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>MM_ENA</name>
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<description>Monitor mode enable.</description>
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<bitRange>[0:0]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>MONITOR_MODE_DISABLE</name>
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<description>Monitor mode disabled.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>THE_I2C_MODULE_WILL_</name>
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<description>The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>ENA_SCL</name>
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<description>SCL output enable.</description>
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<bitRange>[1:1]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>HIGH</name>
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<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>NORMAL</name>
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<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MATCH_ALL</name>
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<description>Select interrupt register match.</description>
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<bitRange>[2:2]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>MATCH</name>
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<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ANYADDRESS</name>
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<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from reserved bits is not defined.</description>
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<bitRange>[31:3]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<dim>3</dim>
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<dimIncrement>0x4</dimIncrement>
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<dimIndex>1-3</dimIndex>
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<name>ADR%s</name>
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<description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
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<addressOffset>0x020</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>GC</name>
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<description>General Call enable bit.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>Address</name>
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<description>The I2C device address for slave mode.</description>
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<bitRange>[7:1]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>DATA_BUFFER</name>
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<description>Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
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<addressOffset>0x02C</addressOffset>
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<access>read-only</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>Data</name>
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<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
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<bitRange>[7:0]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from a reserved bit is not defined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<dim>4</dim>
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<dimIncrement>0x4</dimIncrement>
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<dimIndex>0-3</dimIndex>
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<name>MASK%s</name>
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<description>I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).</description>
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<addressOffset>0x030</addressOffset>
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<access>read-write</access>
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<resetValue>0x00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>RESERVED</name>
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<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>MASK</name>
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<description>Mask bits.</description>
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<bitRange>[7:1]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved. The value read from reserved bits is undefined.</description>
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<bitRange>[31:8]</bitRange>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>WWDT</name>
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<description>Windowed Watchdog Timer (WWDT) </description>
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<groupName>WWDT</groupName>
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<baseAddress>0x40004000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0xFFF</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>WDT</name>
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<value>25</value>
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</interrupt>
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<registers>
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<register>
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<name>MOD</name>
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<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
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<addressOffset>0x000</addressOffset>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>WDEN</name>
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<description>Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
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<bitRange>[0:0]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>STOPPED</name>
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<description>The watchdog timer is stopped.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RUNNING</name>
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<description>The watchdog timer is running.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>WDRESET</name>
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<description>Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.</description>
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<bitRange>[1:1]</bitRange>
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<enumeratedValues>
|
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<name>ENUM</name>
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<enumeratedValue>
|
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<name>INTERRUPT</name>
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<description>A watchdog timeout will not cause a chip reset.</description>
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<value>0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>A watchdog timeout will cause a chip reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOF</name>
|
|
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDINT</name>
|
|
<description>Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDPROTECT</name>
|
|
<description>Watchdog update mode. This bit can be set once by software and is only cleared by a reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_LOCKED</name>
|
|
<description>The watchdog time-out value (TC) can be changed at any time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Watchdog timer constant register. This 24-bit register determines the time-out value.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Watchdog time-out value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEED</name>
|
|
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEED</name>
|
|
<description>Feed value should be 0xAA followed by 0x55.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TV</name>
|
|
<description>Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter timer value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSEL</name>
|
|
<description>Watchdog clock select register.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Selects source of WDT clock</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR_</name>
|
|
<description>Watchdog oscillator (WDOSC)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[30:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog Warning Interrupt compare value.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog warning interrupt compare value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog Window compare value.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog window value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART</name>
|
|
<description>USART</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRINTEN</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RDA_INTE</name>
|
|
<description>Disable the RDA interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RDA_INTER</name>
|
|
<description>Enable the RDA interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREINTEN</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_THRE_INT</name>
|
|
<description>Disable the THRE interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_THRE_INTE</name>
|
|
<description>Enable the THRE interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RLSINTEN</name>
|
|
<description>Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RLS_INTE</name>
|
|
<description>Disable the RLS interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RLS_INTER</name>
|
|
<description>Enable the RLS interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSINTEN</name>
|
|
<description>Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_MS_INTER</name>
|
|
<description>Disable the MS interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_MS_INTERR</name>
|
|
<description>Enable the MS interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTEN</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_END_OF_AUTO_</name>
|
|
<description>Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_END_OF_AUTO_B</name>
|
|
<description>Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTEN</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_BAUD_TI</name>
|
|
<description>Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_BAUD_TIM</name>
|
|
<description>Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_INTERRU</name>
|
|
<description>At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_IS_PEND</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_RECEIVE_LINE_S</name>
|
|
<description>1 - Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2A__RECEIVE_DATA_AV</name>
|
|
<description>2a - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2B__CHARACTER_TIME_</name>
|
|
<description>2b - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_THRE_INTERRUPT</name>
|
|
<description>3 - THRE Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_MODEM_STATUS</name>
|
|
<description>4 - Modem status</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>These bits are equivalent to FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls USART FIFO usage and modes.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>USART FIFOs are disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT</name>
|
|
<description>No impact on either of USART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT</name>
|
|
<description>No impact on either of USART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_0_1_C</name>
|
|
<description>Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_1_4_C</name>
|
|
<description>Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_2_8_C</name>
|
|
<description>Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_3_14_</name>
|
|
<description>Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT_</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS_1_5_IF_</name>
|
|
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY_NUMBER_O</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY_NUMBER_</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_1_STICK_PARIT</name>
|
|
<description>Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_0_STICK_PARIT</name>
|
|
<description>Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BREAK_TRANSM</name>
|
|
<description>Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BREAK_TRANSMI</name>
|
|
<description>Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ACCESS_TO_DI</name>
|
|
<description>Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ACCESS_TO_DIV</name>
|
|
<description>Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Modem Control Register.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTRCTRL</name>
|
|
<description>Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSCTRL</name>
|
|
<description>Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LMS</name>
|
|
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_MODEM_LOOPBA</name>
|
|
<description>Disable modem loopback mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_MODEM_LOOPBAC</name>
|
|
<description>Enable modem loopback mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_RTS_FLO</name>
|
|
<description>Disable auto-rts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_RTS_FLOW</name>
|
|
<description>Enable auto-rts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_CTS_FLO</name>
|
|
<description>Disable auto-cts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_CTS_FLOW</name>
|
|
<description>Enable auto-cts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RBR_IS_EMPTY_</name>
|
|
<description>RBR is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RBR_CONTAINS_VALID_D</name>
|
|
<description>RBR contains valid data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THR_CONTAINS_VALID_D</name>
|
|
<description>THR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THR_IS_EMPTY_</name>
|
|
<description>THR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID_D</name>
|
|
<description>THR and/or the TSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>THR and the TSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>RBR contains no USART RX errors or FCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERRO</name>
|
|
<description>USART RBR contains at least one USART RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXERR</name>
|
|
<description>Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Modem Status Register.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DCTS</name>
|
|
<description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDSR</name>
|
|
<description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, DSR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, DSR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERI</name>
|
|
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, RI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH_TRANSITI</name>
|
|
<description>Low-to-high transition detected on RI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDCD</name>
|
|
<description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, DCD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input, DCD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. Eight-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PAD</name>
|
|
<description>A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_STOP_AUTO</name>
|
|
<description>Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_BAUD_START_AUT</name>
|
|
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0_</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1_</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Start mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART</name>
|
|
<description>No restart</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART_IN_CASE_OF_T</name>
|
|
<description>Restart in case of time-out (counter restarts at next USART Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write only accessible).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write only accessible).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>IrDA Control Register. Enables and configures the IrDA (remote control) mode.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRDAEN</name>
|
|
<description>IrDA mode enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRDA_MODE_IS_DISABLE</name>
|
|
<description>IrDA mode is disabled, USARTn acts as a standard USART.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRDA_MODE_IS_ENABLED</name>
|
|
<description>IrDA mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRDAINV</name>
|
|
<description>Serial input inverter</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>The serial input is not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>The serial input is inverted. This has no effect on the serial output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIXPULSEEN</name>
|
|
<description>IrDA fixed pulse width mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>IrDA fixed pulse width mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>IrDA fixed pulse width mode enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSEDIV</name>
|
|
<description>Configures the pulse width when FixPulseEn = 1.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>3_DIV_16_X_BAUD_RATE</name>
|
|
<description>3 / (16 x baud rate)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_X_TPCLK</name>
|
|
<description>2 x TPCLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_X_TPCLK</name>
|
|
<description>4 x TPCLK</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_X_TPCLK</name>
|
|
<description>8 x TPCLK</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_X_TPCLK</name>
|
|
<description>16 x TPCLK</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_X_TPCLK</name>
|
|
<description>32 x TPCLK</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64_X_TPCLK</name>
|
|
<description>64 x TPCLK</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_X_TPCLK</name>
|
|
<description>128 x TPCLK</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Oversampling Register. Controls the degree of oversampling during each bit time.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSFRAC</name>
|
|
<description>Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSINT</name>
|
|
<description>Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDINT</name>
|
|
<description>In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off USART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HDEN</name>
|
|
<description>Half duplex enable register.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HDEN</name>
|
|
<description>Half-duplex mode enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_HALF_DUPLEX_</name>
|
|
<description>Disable half-duplex mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_HALF_DUPLEX_M</name>
|
|
<description>Enable half-duplex mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCICTRL</name>
|
|
<description>Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCIEN</name>
|
|
<description>Smart Card Interface Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SMART_CARD_INTERFACE</name>
|
|
<description>Smart card interface disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYNCHRONOUS_HALF_DU</name>
|
|
<description>Asynchronous half duplex smart card interface is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKDIS</name>
|
|
<description>NACK response disable. Only applicable in T=0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A NACK response is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A NACK response is inhibited.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTSEL</name>
|
|
<description>Protocol selection as defined in the ISO7816-3 standard.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>T_EQ_0</name>
|
|
<description>T = 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T_EQ_1</name>
|
|
<description>T = 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXRETRY</name>
|
|
<description>When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>XTRAGUARD</name>
|
|
<description>When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>NMM enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_RECEIVER_IS_ENAB</name>
|
|
<description>The receiver is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_RECEIVER_IS_DISA</name>
|
|
<description>The receiver is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>AAD enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTO_ADDRESS_DETECT_</name>
|
|
<description>Auto Address Detect (AAD) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_ADDRESS_DETECT_</name>
|
|
<description>Auto Address Detect (AAD) is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Select direction control pin</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RTS</name>
|
|
<description>If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR</name>
|
|
<description>If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Auto direction control enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_DIRECTI</name>
|
|
<description>Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_DIRECTIO</name>
|
|
<description>Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCCTRL</name>
|
|
<description>Synchronous mode control register.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Enables synchronous mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRC</name>
|
|
<description>Clock source select.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_SLAVE_MO</name>
|
|
<description>Synchronous slave mode (SCLK in)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONOUS_MASTER_M</name>
|
|
<description>Synchronous master mode (SCLK out)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FES</name>
|
|
<description>Falling edge sampling.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>RxD is sampled on the rising edge of SCLK </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>RxD is sampled on the falling edge of SCLK</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSBYPASS</name>
|
|
<description>Transmit synchronization bypass in synchronous slave mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNC</name>
|
|
<description>The input clock is synchronized prior to being used in clock edge detection logic</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOSYNC</name>
|
|
<description>The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCEN</name>
|
|
<description>Continuous master clock enable (used only when CSRC is 1)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SCLK_CYCLES_ONLY_WHE</name>
|
|
<description>SCLK cycles only when characters are being sent on TxD</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCLK_RUNS_CONTINUOUS</name>
|
|
<description>SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSDIS</name>
|
|
<description>Start/stop bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SEND_START_AND_STOP_</name>
|
|
<description>Send start and stop bits as in other modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_SEND_STARTSTOP</name>
|
|
<description>Do not send start/stop bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCCLR</name>
|
|
<description>Continuous clock clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CSCEN_IS_UNDER_SOFTW</name>
|
|
<description>CSCEN is under software control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HARDWARE_CLEARS_CSCE</name>
|
|
<description>Hardware clears CSCEN after each character is received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CT16B0</name>
|
|
<description>16-bit counter/timers CT16B0</description>
|
|
<groupName>CT16B0</groupName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT16B0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTERS_ARE_DIS</name>
|
|
<description>The counters are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>Counter reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do nothing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCVAL</name>
|
|
<description>Prescale value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16B0_CAP0_</name>
|
|
<description>CT16B0_CAP0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_CAP1_</name>
|
|
<description>CT16B0_CAP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SELCC</name>
|
|
<description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT16B</name>
|
|
<description>Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT16</name>
|
|
<description>Falling Edge of CT16B0_CCAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT16B</name>
|
|
<description>Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT16</name>
|
|
<description>Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM mode enable for channel0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT0_IS_CONTR</name>
|
|
<description>CT16Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM mode enable for channel1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT01_IS_CONT</name>
|
|
<description>CT16Bn_MAT01 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM mode enable for channel2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT2_IS_CONTR</name>
|
|
<description>CT16Bn_MAT2 is controlled by EM2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM mode enable for channel3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT3_IS_CONTR</name>
|
|
<description>CT16Bn_MAT3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CT16B1</name>
|
|
<description>16-bit counter/timers CT16B1</description>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT16B1</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTERS_ARE_DIS</name>
|
|
<description>The counters are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>Counter reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do nothing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCVAL</name>
|
|
<description>Prescale value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x2 to 0x3 are reserved.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16B1_CAP0_</name>
|
|
<description>CT16B1_CAP0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_CAP1_</name>
|
|
<description>CT16B1_CAP1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SELCC</name>
|
|
<description>When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x6 to 0x7 are reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT16B</name>
|
|
<description>Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT16</name>
|
|
<description>Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT16B</name>
|
|
<description>Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT16</name>
|
|
<description>Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM mode enable for channel0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT0_IS_CONTR</name>
|
|
<description>CT16Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM mode enable for channel1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT01_IS_CONT</name>
|
|
<description>CT16Bn_MAT01 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM mode enable for channel2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT2_IS_CONTR</name>
|
|
<description>CT16Bn_MAT2 is controlled by EM2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM mode enable for channel3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT3_IS_CONTR</name>
|
|
<description>CT16Bn_MAT3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CT32B0</name>
|
|
<description>32-bit counter/timers CT32B0</description>
|
|
<groupName>CT32B0</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT32B0</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved,</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTERS_ARE_DIS</name>
|
|
<description>The counters are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>Counter reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do nothing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCVAL</name>
|
|
<description>Prescaler value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B0_CAP1 input.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x1 and0x3 are reserved.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32B0_CAP0</name>
|
|
<description>CT32B0_CAP0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_CAP1</name>
|
|
<description>CT32B0_CAP1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SElCC</name>
|
|
<description>When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT32B</name>
|
|
<description>Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT32</name>
|
|
<description>Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved,</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT32B</name>
|
|
<description>Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT32</name>
|
|
<description>Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM mode enable for channel0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT0_IS_CONTR</name>
|
|
<description>CT32Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM mode enable for channel1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT01_IS_CONT</name>
|
|
<description>CT32Bn_MAT01 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM mode enable for channel2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT2_IS_CONTR</name>
|
|
<description>CT32Bn_MAT2 is controlled by EM2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT3_IS_CONTR</name>
|
|
<description>CT32Bn_MAT3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT132Bn_MAT3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CT32B1</name>
|
|
<description>32-bit counter/timers CT32B1</description>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT32B1</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTERS_ARE_DIS</name>
|
|
<description>The counters are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and Prescale Counter are enabled for counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>Counter reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do nothing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_COUNTER_AN</name>
|
|
<description>The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCVAL</name>
|
|
<description>Prescaler value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED_</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B1_CAP1 input.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32B1_CAP0</name>
|
|
<description>CT32B1_CAP0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_CAP1</name>
|
|
<description>CT32B1_CAP1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SElCC</name>
|
|
<description>When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT32B</name>
|
|
<description>Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT32</name>
|
|
<description>Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CT32B</name>
|
|
<description>Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CT32</name>
|
|
<description>Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM mode enable for channel0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT0_IS_CONTR</name>
|
|
<description>CT32Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM mode enable for channel1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT01_IS_CONT</name>
|
|
<description>CT32Bn_MAT01 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM mode enable for channel2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT2_IS_CONTR</name>
|
|
<description>CT32Bn_MAT2 is controlled by EM2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT3_IS_CONTR</name>
|
|
<description>CT32Bn_MAT3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT132Bn_MAT3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<description> ADC </description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 276) must be set to 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOFTWARE_CONTROLLED_</name>
|
|
<description>Software-controlled mode: Conversions are software-controlled and require 11 clocks.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HARDWARE_SCAN_MODE_</name>
|
|
<description>Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>11_CLOCKS</name>
|
|
<description>11 clocks / 10 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_CLOCKS</name>
|
|
<description>10 clocks / 9 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_CLOCKS</name>
|
|
<description>9 clocks / 8 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_CLOCKS</name>
|
|
<description>8 clocks / 7 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_CLOCKS</name>
|
|
<description>7 clocks / 6 bits</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_CLOCKS</name>
|
|
<description>6 clocks / 5 bits</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_CLOCKS</name>
|
|
<description>5 clocks / 4 bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_CLOCKS</name>
|
|
<description>4 clocks / 3 bits</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>When the BURST bit is 0, these bits control whether and when an A/D conversion is started:</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_START_THIS_VALUE</name>
|
|
<description>No start (this value should be used when clearing PDN to 0).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_CONVERSION_NOW</name>
|
|
<description>Start conversion now.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_2</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO1_5</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT0</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT0</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>This bit is significant only when the START field contains 010-111. In these cases:</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Start conversion on a rising edge on the selected CAP/MAT signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Start conversion on a falling edge on the selected CAP/MAT signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDR</name>
|
|
<description>A/D Global Data Register. Contains the result of the most recent A/D conversion.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeros.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeros.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the result bits V_VREF were converted.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeros.</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADINTEN</name>
|
|
<description>These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADGINTEN</name>
|
|
<description>When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. This bit must be set to 0 in burst mode (BURST = 1 in the CR register).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Unused, always 0.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DR%s</name>
|
|
<description>A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel N</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x11111111</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>These bits mirror the DONE status flags that appear in the result register for each A/D channel n.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADINT</name>
|
|
<description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Unused, always 0.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMU</name>
|
|
<description> Power Management Unit (PMU) </description>
|
|
<groupName>PMU</groupName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCON</name>
|
|
<description>Power control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Power mode</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEFAULT</name>
|
|
<description>Default. The part is in active or sleep mode.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEEPSLEEP</name>
|
|
<description>ARM WFI will enter Deep-sleep mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERDOWN</name>
|
|
<description>ARM WFI will enter Power-down mode.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEEPPOWERDOWN</name>
|
|
<description>ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NODPD</name>
|
|
<description>A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. Execution continues after the WFI if this bit is 1. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLEEPFLAG</name>
|
|
<description>Sleep mode flag</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOPOWERDOWN</name>
|
|
<description>Read: No power-down mode entered. LPC11U1x is in Active mode. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERDOWN</name>
|
|
<description>Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPDFLAG</name>
|
|
<description>Deep power-down flag</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DPNOTENTERED</name>
|
|
<description>Read: Deep power-down mode not entered. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPENTERED</name>
|
|
<description>Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GPREG%s</name>
|
|
<description>General purpose register 0</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPDATA</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPREG4</name>
|
|
<description>General purpose register 4</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPHYS</name>
|
|
<description>WAKEUP pin hysteresis enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Hysteresis for WAKEUP pin disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hysteresis for WAKEUP pin enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPDATA</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASHCTRL</name>
|
|
<description> Flash
|
|
controller </description>
|
|
<groupName>FLASHCTRL</groupName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH_IRQ</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>EEMSSTART</name>
|
|
<description>EEPROM BIST start address register</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTA</name>
|
|
<description>BIST start address: Bit 0 is fixed zero since only even addresses are allowed.</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEMSSTOP</name>
|
|
<description>EEPROM BIST stop address register</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPA</name>
|
|
<description>BIST stop address: Bit 0 is fixed zero since only even addresses are allowed.</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEVSEL</name>
|
|
<description>BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STRTBIST</name>
|
|
<description>BIST start bit Setting this bit will start the BIST. This bit is self-clearing.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEMSSIG</name>
|
|
<description>EEPROM 24-bit BIST signature register</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA_SIG</name>
|
|
<description>BIST 16-bit signature calculated from only the data bytes</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PARITY_SIG</name>
|
|
<description>BIST 16-bit signature calculated from only the parity bits of the data bytes</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLASHCFG</name>
|
|
<description>Flash memory access time configuration register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLASHTIM</name>
|
|
<description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_SYSTEM_CLOCK_FLASH</name>
|
|
<description>1 system clock flash access time (for system clock frequencies of up to 20 MHz).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_SYSTEM_CLOCKS_FLAS</name>
|
|
<description>2 system clocks flash access time (for system clock frequencies of up to 40 MHz).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_SYSTEM_CLOCKS_FLAS</name>
|
|
<description>3 system clocks flash access time (for system clock frequencies of up to 50 MHz).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSSTART</name>
|
|
<description>Signature start address register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSSTOP</name>
|
|
<description>Signature stop-address register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SIG_START</name>
|
|
<description>Start control bit for signature generation.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SIGNATURE_GENERATION</name>
|
|
<description>Signature generation is stopped</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INITIATE_SIGNATURE_G</name>
|
|
<description>Initiate signature generation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW0</name>
|
|
<description>Word 0 [31:0]</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW0_31_0</name>
|
|
<description>Word 0 of 128-bit signature (bits 31 to 0).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW1</name>
|
|
<description>Word 1 [63:32]</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW1_63_32</name>
|
|
<description>Word 1 of 128-bit signature (bits 63 to 32).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW2</name>
|
|
<description>Word 2 [95:64]</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW2_95_64</name>
|
|
<description>Word 2 of 128-bit signature (bits 95 to 64).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW3</name>
|
|
<description>Word 3 [127:96]</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW3_127_96</name>
|
|
<description>Word 3 of 128-bit signature (bits 127 to 96).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSTAT</name>
|
|
<description>Signature generation status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIG_DONE</name>
|
|
<description>When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSTATCLR</name>
|
|
<description>Signature generation status clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIG_DONE_CLR</name>
|
|
<description>Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>SSP0</name>
|
|
<description>SSP/SPI </description>
|
|
<groupName>SSP0</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSP0</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSS</name>
|
|
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>4_BIT_TRANSFER</name>
|
|
<description>4-bit transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT_TRANSFER</name>
|
|
<description>5-bit transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_TRANSFER</name>
|
|
<description>6-bit transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_TRANSFER</name>
|
|
<description>7-bit transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_TRANSFER</name>
|
|
<description>8-bit transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT_TRANSFER</name>
|
|
<description>9-bit transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BIT_TRANSFER</name>
|
|
<description>10-bit transfer</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BIT_TRANSFER</name>
|
|
<description>11-bit transfer</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BIT_TRANSFER</name>
|
|
<description>12-bit transfer</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BIT_TRANSFER</name>
|
|
<description>13-bit transfer</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BIT_TRANSFER</name>
|
|
<description>14-bit transfer</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BIT_TRANSFER</name>
|
|
<description>15-bit transfer</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_TRANSFER</name>
|
|
<description>16-bit transfer</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame Format.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>SPI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TI</name>
|
|
<description>TI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MICROWIRE</name>
|
|
<description>Microwire</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>This combination is not supported and should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>SPI controller maintains the bus clock low between frames.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>SPI controller maintains the bus clock high between frames.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FIRSTCLOCK</name>
|
|
<description>SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECONDCLOCK</name>
|
|
<description>SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCR</name>
|
|
<description>Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Control Register 1. Selects master/slave and other modes.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loop Back Mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DURING_NORMAL_OPERAT</name>
|
|
<description>During normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERIAL_INPUT_IS_TAKE</name>
|
|
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SPI Enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The SPI controller is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>Clock Prescale Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPSDVSR</name>
|
|
<description>This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>Interrupt Mask Set and Clear Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORRIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORMIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSPICR Interrupt Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIC</name>
|
|
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOCON</name>
|
|
<description> I/O configuration Modification </description>
|
|
<groupName>IOCON</groupName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RESET_PIO0_0</name>
|
|
<description>I/O configuration for pin RESET/PIO0_0</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESET_</name>
|
|
<description>RESET.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_0_</name>
|
|
<description>PIO0_0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_1</name>
|
|
<description>I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_1_</name>
|
|
<description>PIO0_1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKOUT_</name>
|
|
<description>CLKOUT.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT2_</name>
|
|
<description>CT32B0_MAT2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_FTOGGLE_</name>
|
|
<description>USB_FTOGGLE.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_2</name>
|
|
<description>I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_2_</name>
|
|
<description>PIO0_2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL0_</name>
|
|
<description>SSEL0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_CAP0_</name>
|
|
<description>CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_3</name>
|
|
<description>I/O configuration for pin PIO0_3/USB_VBUS</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_3_</name>
|
|
<description>PIO0_3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_VBUS_</name>
|
|
<description>USB_VBUS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_4</name>
|
|
<description>I/O configuration for pin PIO0_4/SCL</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_4_OPEN_DRAIN_P</name>
|
|
<description>PIO0_4 (open-drain pin).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SCL_OPEN_DRAIN_</name>
|
|
<description>I2C SCL (open-drain pin).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2CMODE</name>
|
|
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_MODE_FAST_</name>
|
|
<description>Standard mode/ Fast-mode I2C.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDARD_IO_FUNCTIO</name>
|
|
<description>Standard I/O functionality</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_I2C</name>
|
|
<description>Fast-mode Plus I2C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_5</name>
|
|
<description>I/O configuration for pin PIO0_5/SDA</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_5_OPEN_DRAIN_P</name>
|
|
<description>PIO0_5 (open-drain pin).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_SDA_OPEN_DRAIN_</name>
|
|
<description>I2C SDA (open-drain pin).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2CMODE</name>
|
|
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_MODE_FAST_</name>
|
|
<description>Standard mode/ Fast-mode I2C.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDARD_IO_FUNCTIO</name>
|
|
<description>Standard I/O functionality</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_I2C</name>
|
|
<description>Fast-mode Plus I2C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_6</name>
|
|
<description>I/O configuration for pin PIO0_6/USB_CONNECT/SCK0</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_6_</name>
|
|
<description>PIO0_6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_CONNECT_</name>
|
|
<description>USB_CONNECT.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK0_</name>
|
|
<description>SCK0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_7</name>
|
|
<description>I/O configuration for pin PIO0_7/CTS</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_7_</name>
|
|
<description>PIO0_7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTS_</name>
|
|
<description>CTS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_8</name>
|
|
<description>I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_8_</name>
|
|
<description>PIO0_8.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MISO0_</name>
|
|
<description>MISO0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT0_</name>
|
|
<description>CT16B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_9</name>
|
|
<description>I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_9_</name>
|
|
<description>PIO0_9.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOSI0_</name>
|
|
<description>MOSI0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT1_</name>
|
|
<description>CT16B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWCLK_PIO0_10</name>
|
|
<description>I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SWCLK_</name>
|
|
<description>SWCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_10_</name>
|
|
<description>PIO0_10.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK0_</name>
|
|
<description>SCK0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT2_</name>
|
|
<description>CT16B0_MAT2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDI_PIO0_11</name>
|
|
<description>I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TDI_</name>
|
|
<description>TDI.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_11_</name>
|
|
<description>PIO0_11.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD0_</name>
|
|
<description>AD0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT3_</name>
|
|
<description>CT32B0_MAT3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMS_PIO0_12</name>
|
|
<description>I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TMS_</name>
|
|
<description>TMS.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_12_</name>
|
|
<description>PIO0_12.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD1_</name>
|
|
<description>AD1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_CAP0_</name>
|
|
<description>CT32B1_CAP0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDO_PIO0_13</name>
|
|
<description>I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TDO_</name>
|
|
<description>TDO.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_13_</name>
|
|
<description>PIO0_13.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD2_</name>
|
|
<description>AD2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT0_</name>
|
|
<description>CT32B1_MAT0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRST_PIO0_14</name>
|
|
<description>I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRST_</name>
|
|
<description>TRST.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_14_</name>
|
|
<description>PIO0_14.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD3_</name>
|
|
<description>AD3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT1_</name>
|
|
<description>CT32B1_MAT1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWDIO_PIO0_15</name>
|
|
<description>I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SWDIO_</name>
|
|
<description>SWDIO.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIO0_15_</name>
|
|
<description>PIO0_15.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD4_</name>
|
|
<description>AD4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT2_</name>
|
|
<description>CT32B1_MAT2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_16</name>
|
|
<description>I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. This pin functions as WAKEUP pin if the LPC11Uxx is in Deep power-down mode regardless of the value of FUNC. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_16_</name>
|
|
<description>PIO0_16.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD5_</name>
|
|
<description>AD5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT3_</name>
|
|
<description>CT32B1_MAT3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_17</name>
|
|
<description>I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_17_</name>
|
|
<description>PIO0_17.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTS_</name>
|
|
<description>RTS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_CAP0_</name>
|
|
<description>CT32B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCLK_UART_SYNCHRONO</name>
|
|
<description>SCLK (UART synchronous clock).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_18</name>
|
|
<description>I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_18_</name>
|
|
<description>PIO0_18.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXD_</name>
|
|
<description>RXD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT0_</name>
|
|
<description>CT32B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_19</name>
|
|
<description>I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_19_</name>
|
|
<description>PIO0_19.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXD_</name>
|
|
<description>TXD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT1_</name>
|
|
<description>CT32B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_20</name>
|
|
<description>I/O configuration for pin PIO0_20/CT16B1_CAP0</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_20_</name>
|
|
<description>PIO0_20.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_CAP0_</name>
|
|
<description>CT16B1_CAP0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_21</name>
|
|
<description>I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PIO0_21_</name>
|
|
<description>PIO0_21.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_MAT0_</name>
|
|
<description>CT16B1_MAT0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOSI1_</name>
|
|
<description>MOSI1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_22</name>
|
|
<description>I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO0_22_</name>
|
|
<description>PIO0_22.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD6_</name>
|
|
<description>AD6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_MAT1_</name>
|
|
<description>CT16B1_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MISO1_</name>
|
|
<description>MISO1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO0_23</name>
|
|
<description>I/O configuration for pin PIO0_23/AD7</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO0_23_</name>
|
|
<description>PIO0_23.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AD7_</name>
|
|
<description>AD7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE_</name>
|
|
<description>Analog input mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTR</name>
|
|
<description>Selects 10 ns input glitch filter.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>FILTER_ENABLED_</name>
|
|
<description>Filter enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTER_DISABLED_</name>
|
|
<description>Filter disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_0</name>
|
|
<description>I/O configuration for pin PIO1_0/CT32B1_MAT0</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_0_</name>
|
|
<description>PIO1_0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT1_</name>
|
|
<description>CT32B1_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_1</name>
|
|
<description>I/O configuration for pin PIO1_1/CT32B1_MAT1</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_1_</name>
|
|
<description>PIO1_1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT1_</name>
|
|
<description>CT32B1_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_2</name>
|
|
<description>I/O configuration for pin PIO1_2/CT32B1_MAT2</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_2_</name>
|
|
<description>PIO1_2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT2_</name>
|
|
<description>CT32B1_MAT2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_3</name>
|
|
<description>I/O configuration for pin PIO1_3/CT32B1_MAT3</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_3_</name>
|
|
<description>PIO1_3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_MAT3_</name>
|
|
<description>CT32B1_MAT3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_4</name>
|
|
<description>I/O configuration for pin PIO1_4/CT32B1_CAP0</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_4_</name>
|
|
<description>PIO1_4.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_CAP0_</name>
|
|
<description>CT32B1_CAP0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_5</name>
|
|
<description>I/O configuration for pin PIO1_5/CT32B1_CAP1</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_5_</name>
|
|
<description>PIO1_5.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B1_CAP1_</name>
|
|
<description>CT32B1_CAP1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_6</name>
|
|
<description>I/O configuration for pin PIO1_6</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_6_</name>
|
|
<description>PIO1_6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_7</name>
|
|
<description>I/O configuration for pin PIO1_7</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_7_</name>
|
|
<description>PIO1_7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_8</name>
|
|
<description>I/O configuration for pin PIO1_8</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_8_</name>
|
|
<description>PIO1_8.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_9</name>
|
|
<description>I/O configuration for pin PIO1_9</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_9_</name>
|
|
<description>PIO1_9.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_10</name>
|
|
<description>I/O configuration for pin PIO1_10</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_10_</name>
|
|
<description>PIO1_10.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_11</name>
|
|
<description>I/O configuration for pin PIO1_11</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_11_</name>
|
|
<description>PIO1_11.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_12</name>
|
|
<description>I/O configuration for pin PIO1_12</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_12_</name>
|
|
<description>PIO1_12.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_13</name>
|
|
<description>I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_13_</name>
|
|
<description>PIO1_13.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR_</name>
|
|
<description>DTR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT0_</name>
|
|
<description>CT16B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXD_</name>
|
|
<description>TXD.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_14</name>
|
|
<description>I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_14_</name>
|
|
<description>PIO1_14.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSR_</name>
|
|
<description>DSR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT1_</name>
|
|
<description>CT16B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXD_</name>
|
|
<description>RXD.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_15</name>
|
|
<description>I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x4 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_15_</name>
|
|
<description>PIO1_15.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCD_</name>
|
|
<description>DCD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_MAT2_</name>
|
|
<description>CT16B0_MAT2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK1_</name>
|
|
<description>SCK1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_16</name>
|
|
<description>I/O configuration for pin PIO1_16/RI/CT16B0_CAP0</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_16_</name>
|
|
<description>PIO1_16.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RI_</name>
|
|
<description>RI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_CAP0_</name>
|
|
<description>CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_17</name>
|
|
<description>I/O configuration for PIO1_17/CT16B0_CAP1/RXD</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_17_</name>
|
|
<description>PIO1_17.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B0_CAP1</name>
|
|
<description>CT16B0_CAP1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXD</name>
|
|
<description>RXD</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_18</name>
|
|
<description>I/O configuration for PIO1_18/CT16B1_CAP1/TXD</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_18</name>
|
|
<description>PIO1_18</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_CAP1</name>
|
|
<description>CT16B1_CAP1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXD</name>
|
|
<description>TXD</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_19</name>
|
|
<description>I/O configuration for pin PIO1_19/DTR/SSEL1</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_19_</name>
|
|
<description>PIO1_19.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR_</name>
|
|
<description>DTR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL1_</name>
|
|
<description>SSEL1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_20</name>
|
|
<description>I/O configuration for pin PIO1_20/DSR/SCK1</description>
|
|
<addressOffset>0x0B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_20_</name>
|
|
<description>PIO1_20.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSR_</name>
|
|
<description>DSR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK1_</name>
|
|
<description>SCK1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_21</name>
|
|
<description>I/O configuration for pin PIO1_21/DCD/MISO1</description>
|
|
<addressOffset>0x0B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_21_</name>
|
|
<description>PIO1_21.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCD_</name>
|
|
<description>DCD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MISO1_</name>
|
|
<description>MISO1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_22</name>
|
|
<description>I/O configuration for pin PIO1_22/RI/MOSI1</description>
|
|
<addressOffset>0x0B8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_22_</name>
|
|
<description>PIO1_22.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RI_</name>
|
|
<description>RI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOSI1_</name>
|
|
<description>MOSI1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_23</name>
|
|
<description>I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1</description>
|
|
<addressOffset>0x0BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_23_</name>
|
|
<description>PIO1_23.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16B1_MAT1_</name>
|
|
<description>CT16B1_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSEL1_</name>
|
|
<description>SSEL1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_24</name>
|
|
<description>I/O configuration for pin PIO1_24/ CT32B0_MAT0</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_24_</name>
|
|
<description>PIO1_24.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT0_</name>
|
|
<description>CT32B0_MAT0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_25</name>
|
|
<description>I/O configuration for pin PIO1_25/CT32B0_MAT1</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x2 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_25_</name>
|
|
<description>PIO1_25.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT1_</name>
|
|
<description>CT32B0_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_26</name>
|
|
<description>I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_26_</name>
|
|
<description>PIO1_26.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT2</name>
|
|
<description>CT32B0_MAT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXD_</name>
|
|
<description>RXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_27</name>
|
|
<description>I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD</description>
|
|
<addressOffset>0x0CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_27_</name>
|
|
<description>PIO1_27.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_MAT3_</name>
|
|
<description>CT32B0_MAT3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXD_</name>
|
|
<description>TXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_28</name>
|
|
<description>I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_28_</name>
|
|
<description>PIO1_28.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_CAP0_</name>
|
|
<description>CT32B0_CAP0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCLK_</name>
|
|
<description>SCLK.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_29</name>
|
|
<description>I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x3 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_29_</name>
|
|
<description>PIO1_29.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK0_</name>
|
|
<description>SCK0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32B0_CAP1_</name>
|
|
<description>CT32B0_CAP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIO1_31</name>
|
|
<description>I/O configuration for pin PIO1_31</description>
|
|
<addressOffset>0x0DC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. Values 0x1 to 0x7 are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>PIO1_31_</name>
|
|
<description>PIO1_31.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INPUT_NOT_INVERTED_</name>
|
|
<description>Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED_HIGH</name>
|
|
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_MODE_ENAB</name>
|
|
<description>Open-drain mode enabled. This is not a true open-drain mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SYSCON</name>
|
|
<description>System control block </description>
|
|
<groupName>SYSCON</groupName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BOD_IRQ</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SYSMEMREMAP</name>
|
|
<description>System memory remap</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAP</name>
|
|
<description>System memory remap. Value 0x3 is reserved.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BOOT_LOADER_MODE_IN</name>
|
|
<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USER_RAM_MODE_INTER</name>
|
|
<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USER_FLASH_MODE_INT</name>
|
|
<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESETCTRL</name>
|
|
<description>Peripheral reset control</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSP0_RST_N</name>
|
|
<description>SSP0 reset control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETS_THE_SSP0_PERI</name>
|
|
<description>Resets the SSP0 peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP0_RESET_DE_ASSERT</name>
|
|
<description>SSP0 reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C_RST_N</name>
|
|
<description>I2C reset control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETS_THE_I2C_PERIP</name>
|
|
<description>Resets the I2C peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_RESET_DE_ASSERTE</name>
|
|
<description>I2C reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_RST_N</name>
|
|
<description>SSP1 reset control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETS_THE_SSP1_PERI</name>
|
|
<description>Resets the SSP1 peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_RESET_DE_ASSERT</name>
|
|
<description>SSP1 reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCTRL</name>
|
|
<description>System PLL control</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLSTAT</name>
|
|
<description>System PLL status</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLCTRL</name>
|
|
<description>USB PLL control</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLSTAT</name>
|
|
<description>USB PLL status</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSOSCCTRL</name>
|
|
<description>System oscillator control</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass system oscillator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OSCILLATOR_IS_NOT_BY</name>
|
|
<description>Oscillator is not bypassed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS_ENABLED_PLL_</name>
|
|
<description>Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FREQRANGE</name>
|
|
<description>Determines frequency range for Low-power oscillator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1__20_MHZ_FREQUENCY</name>
|
|
<description>1 - 20 MHz frequency range.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15__25_MHZ_FREQUENC</name>
|
|
<description>15 - 25 MHz frequency range</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTOSCCTRL</name>
|
|
<description>Watchdog oscillator control</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVSEL</name>
|
|
<description>Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FREQSEL</name>
|
|
<description>Select watchdog oscillator analog output frequency (Fclkana).</description>
|
|
<bitRange>[8:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>0_6_MHZ</name>
|
|
<description>0.6 MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_05_MHZ</name>
|
|
<description>1.05 MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4_MHZ</name>
|
|
<description>1.4 MHz</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_75_MHZ</name>
|
|
<description>1.75 MHz</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_1_MHZ</name>
|
|
<description>2.1 MHz</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_4_MHZ</name>
|
|
<description>2.4 MHz</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_7_MHZ</name>
|
|
<description>2.7 MHz</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_0_MHZ</name>
|
|
<description>3.0 MHz</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_25_MHZ</name>
|
|
<description>3.25 MHz</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_5_MHZ</name>
|
|
<description>3.5 MHz</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_75_MHZ</name>
|
|
<description>3.75 MHz</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_0_MHZ</name>
|
|
<description>4.0 MHz</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_2_MHZ</name>
|
|
<description>4.2 MHz</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_4_MHZ</name>
|
|
<description>4.4 MHz</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_6_MHZ</name>
|
|
<description>4.6 MHz</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSRSTSTAT</name>
|
|
<description>System reset status register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>POR reset status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_POR_DETECTED</name>
|
|
<description>No POR detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POR_DETECTED_WRITIN</name>
|
|
<description>POR detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTRST</name>
|
|
<description>External reset status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESET_EVENT_DETEC</name>
|
|
<description>No reset event detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_DETECTED_WRIT</name>
|
|
<description>Reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Status of the Watchdog reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_WDT_RESET_DETECTE</name>
|
|
<description>No WDT reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_RESET_DETECTED_</name>
|
|
<description>WDT reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD</name>
|
|
<description>Status of the Brown-out detect reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_BOD_RESET_DETECTE</name>
|
|
<description>No BOD reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOD_RESET_DETECTED_</name>
|
|
<description>BOD reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRST</name>
|
|
<description>Status of the software system reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_SYSTEM_RESET_DETE</name>
|
|
<description>No System reset detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_RESET_DETECTE</name>
|
|
<description>System reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCLKSEL</name>
|
|
<description>System PLL clock source select</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>System PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR_</name>
|
|
<description>Crystal Oscillator (SYSOSC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCLKUEN</name>
|
|
<description>System PLL clock source update enable</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable system PLL clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLCLKSEL</name>
|
|
<description>USB PLL clock source select</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>USB PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_THE_USB_PLL_CLO</name>
|
|
<description>IRC. The USB PLL clock source must be switched to system oscillator for correct full-speed USB operation. The IRC is suitable for low-speed USB operation.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPLLCLKUEN</name>
|
|
<description>USB PLL clock source update enable</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable USB PLL clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKSEL</name>
|
|
<description>Main clock source select</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Clock source for main clock</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC Oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_INPUT</name>
|
|
<description>PLL input</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR</name>
|
|
<description>Watchdog oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_OUTPUT</name>
|
|
<description>PLL output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKUEN</name>
|
|
<description>Main clock source update enable</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable main clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKDIV</name>
|
|
<description>System clock divider</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKCTRL</name>
|
|
<description>System clock control</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0801485F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYS</name>
|
|
<description>Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Enables clock for ROM.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM0</name>
|
|
<description>Enables clock for RAM.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHREG</name>
|
|
<description>Enables clock for flash register interface.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHARRAY</name>
|
|
<description>Enables clock for flash array access.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C</name>
|
|
<description>Enables clock for I2C.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO</name>
|
|
<description>Enables clock for GPIO port registers.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT16B0</name>
|
|
<description>Enables clock for 16-bit counter/timer 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT16B1</name>
|
|
<description>Enables clock for 16-bit counter/timer 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT32B0</name>
|
|
<description>Enables clock for 32-bit counter/timer 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT32B1</name>
|
|
<description>Enables clock for 32-bit counter/timer 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSP0</name>
|
|
<description>Enables clock for SSP0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART</name>
|
|
<description>Enables clock for UART.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>Enables clock for ADC.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB</name>
|
|
<description>Enables clock to the USB register interface.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WWDT</name>
|
|
<description>Enables clock for WWDT.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOCON</name>
|
|
<description>Enables clock for I/O configuration block.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SSP1</name>
|
|
<description>Enables clock for SSP1.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT</name>
|
|
<description>Enables clock to GPIO Pin interrupts register interface.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GROUP0INT</name>
|
|
<description>Enables clock to GPIO GROUP0 interrupt register interface.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GROUP1INT</name>
|
|
<description>Enables clock to GPIO GROUP1 interrupt register interface.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RAM1</name>
|
|
<description>Enables SRAM1 block at address 0x2000 0000. See Section 3.1 for availability of this bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBRAM</name>
|
|
<description>Enables USB SRAM block at address 0x2000 4000.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSP0CLKDIV</name>
|
|
<description>SSP0 clock divider</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UARTCLKDIV</name>
|
|
<description>UART clock divider</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSP1CLKDIV</name>
|
|
<description>SSP1 clock divider</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKSEL</name>
|
|
<description>USB clock source select</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>USB clock source. Values 0x2 and 0x3 are reserved.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USB_PLL_OUT</name>
|
|
<description>USB PLL out</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKUEN</name>
|
|
<description>USB clock source update enable</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable USB clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKDIV</name>
|
|
<description>USB clock source divider</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTSEL</name>
|
|
<description>CLKOUT clock source select</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>CLKOUT clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR_</name>
|
|
<description>Crystal oscillator (SYSOSC)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LF_OSCILLATOR_WATCH</name>
|
|
<description>LF oscillator (watchdog oscillator)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTUEN</name>
|
|
<description>CLKOUT clock source update enable</description>
|
|
<addressOffset>0x0E4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable CLKOUT clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTDIV</name>
|
|
<description>CLKOUT clock divider</description>
|
|
<addressOffset>0x0E8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP0</name>
|
|
<description>POR captured PIO status 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIOSTAT</name>
|
|
<description>State of PIO0_23 through PIO0_0 at power-on reset</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP1</name>
|
|
<description>POR captured PIO status 1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PIOSTAT</name>
|
|
<description>State of PIO1_31 through PIO1_0 at power-on reset</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BODCTRL</name>
|
|
<description>Brown-Out Detect</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BODRSTLEV</name>
|
|
<description>BOD reset level</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_THE_RESET_A</name>
|
|
<description>Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_THE_RESET_A</name>
|
|
<description>Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_RESET_A</name>
|
|
<description>Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_RESET_A</name>
|
|
<description>Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODINTVAL</name>
|
|
<description>BOD interrupt level</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_RESERVED_</name>
|
|
<description>Level 0: Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1THE_INTERRUP</name>
|
|
<description>Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_INTERRU</name>
|
|
<description>Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_INTERRU</name>
|
|
<description>Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRSTENA</name>
|
|
<description>BOD reset enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_RESET_FUNCTI</name>
|
|
<description>Disable reset function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_RESET_FUNCTIO</name>
|
|
<description>Enable reset function.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTCKCAL</name>
|
|
<description>System tick counter calibration</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>System tick timer calibration value</description>
|
|
<bitRange>[25:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQLATENCY</name>
|
|
<description>IQR delay. Allows trade-off between interrupt latency and determinism.</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LATENCY</name>
|
|
<description>8-bit latency value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMISRC</name>
|
|
<description>NMI Source Control</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQNO</name>
|
|
<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 58 for the list of interrupt sources and their IRQ numbers.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NMIEN</name>
|
|
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>PINTSEL%s</name>
|
|
<description>GPIO Pin Interrupt Select register 0</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPIN</name>
|
|
<description>Pin number select for pin interrupt. (PIO0_0 to PIO0_23 correspond to numbers 0 to 23 and PIO1_0 to PIO1_31 correspond to numbers 24 to 55).</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKCTRL</name>
|
|
<description>USB clock control</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AP_CLK</name>
|
|
<description>USB need_clock signal control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UNDER_HARDWARE_CONTR</name>
|
|
<description>Under hardware control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_HIGH_</name>
|
|
<description>Forced HIGH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL_CLK</name>
|
|
<description>USB need_clock polarity for triggering the USB wake-up interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_THE_</name>
|
|
<description>Falling edge of the USB need_clock triggers the USB wake-up (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_THE_U</name>
|
|
<description>Rising edge of the USB need_clock triggers the USB wake-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCLKST</name>
|
|
<description>USB clock status</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEED_CLKST</name>
|
|
<description>USB need_clock signal status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>LOW</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>HIGH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTERP0</name>
|
|
<description>Start logic 0 interrupt wake-up enable register 0</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINT0</name>
|
|
<description>Pin interrupt 0 wake-up</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT1</name>
|
|
<description>Pin interrupt 1 wake-up</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT2</name>
|
|
<description>Pin interrupt 2 wake-up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT3</name>
|
|
<description>Pin interrupt 3 wake-up</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT4</name>
|
|
<description>Pin interrupt 4 wake-up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT5</name>
|
|
<description>Pin interrupt 5 wake-up</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT6</name>
|
|
<description>Pin interrupt 6 wake-up</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINT7</name>
|
|
<description>Pin interrupt 7 wake-up</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTERP1</name>
|
|
<description>Start logic 1 interrupt wake-up enable register 1</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WWDTINT</name>
|
|
<description>WWDT interrupt wake-up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODINT</name>
|
|
<description>Brown Out Detect (BOD) interrupt wake-up</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[18:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB_WAKEUP</name>
|
|
<description>USB need_clock signal wake-up</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIOINT0</name>
|
|
<description>GPIO GROUP0 interrupt wake-up</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIOINT1</name>
|
|
<description>GPIO GROUP1 interrupt wake-up</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSLEEPCFG</name>
|
|
<description>Power-down states in deep-sleep mode</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD power-down control for Deep-sleep and Power-down mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator power-down control for Deep-sleep and Power-down mode</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDAWAKECFG</name>
|
|
<description>Power-down states for wake-up from deep-sleep</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xEDF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output wake-up configuration</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC_PD</name>
|
|
<description>IRC oscillator power-down wake-up configuration</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PD</name>
|
|
<description>Flash wake-up configuration</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD wake-up configuration</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PD</name>
|
|
<description>ADC wake-up configuration</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>Crystal oscillator wake-up configuration</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator wake-up configuration</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL wake-up configuration</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPLL_PD</name>
|
|
<description>USB PLL wake-up configuration</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USBPAD_PD</name>
|
|
<description>USB transceiver wake-up configuration</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USB_TRANSCEIVER_POWE</name>
|
|
<description>USB transceiver powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TRANSCEIVER_POWE</name>
|
|
<description>USB transceiver powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write these bits as 111.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDRUNCFG</name>
|
|
<description>Power configuration register</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xEDF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output power-down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC_PD</name>
|
|
<description>IRC oscillator power-down</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PD</name>
|
|
<description>Flash power-down</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD power-down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PD</name>
|
|
<description>ADC power-down</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>Crystal oscillator power-down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator power-down</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL power-down</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBPLL_PD</name>
|
|
<description>USB PLL power-down</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USBPAD_PD</name>
|
|
<description>USB transceiver power-down configuration</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USB_TRANSCEIVER_POWE</name>
|
|
<description>USB transceiver powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TRANSCEIVER_POWE</name>
|
|
<description>USB transceiver powered down (suspend mode)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write these bits as 111.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICE_ID</name>
|
|
<description>Device ID</description>
|
|
<addressOffset>0x3F4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEID</name>
|
|
<description>Device ID numbers for LPC11Uxx parts LPC11U12FHN33/201 = 0x095C 802B/0x295C 802B LPC11U12FBD48/201 = 0x095C 802B/0x295C 802B LPC11U13FBD48/201 = 0x097A 802B/0x297A 802B LPC11U14FHN33/201 = 0x0998 802B/0x2998 802B LPC11U14FHI33/201 = 0x2998 802B LPC11U14FBD48/201 = 0x0998 802B/0x2998 802B LPC11U14FET48/201 = 0x0998 802B/0x2998 802B LPC11U23FBD48/301 = 0x2972 402B LPC11U24FHI33/301 = 0x2988 402B LPC11U24FBD48/301 = 0x2988 402B LPC11U24FET48/301 = 0x2988 402B LPC11U24FHN33/401 = 0x2980 002B LPC11U24FBD48/401 = 0x2980 002B LPC11U24FBD64/401 = 0x2980 002B</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPIO_PIN_INT</name>
|
|
<description>GPIO pin interrupt </description>
|
|
<groupName>GPIO_PIN_INT</groupName>
|
|
<baseAddress>0x4004C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIN_INT0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISEL</name>
|
|
<description>Pin Interrupt Mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMODE0</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE1</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE2</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE3</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE4</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE5</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE6</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE7</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENR</name>
|
|
<description>Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENRL0</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL1</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL2</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL3</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL4</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL5</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL6</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL7</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENR</name>
|
|
<description>Set Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENRL0</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL1</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL2</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL3</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL4</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL5</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL6</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL7</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENR</name>
|
|
<description>Clear Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENRL0</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL1</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL2</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL3</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL4</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL5</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL6</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL7</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENF</name>
|
|
<description>Pin Interrupt Enable Falling Edge / Active Level register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENAF0</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF1</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF2</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF3</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF4</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF5</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF6</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF7</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENF</name>
|
|
<description>Set Pin Interrupt Enable Falling Edge / Active Level register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENAF0</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF1</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF2</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF3</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF4</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF5</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF6</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF7</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENF</name>
|
|
<description>Clear Pin Interrupt Enable Falling Edge / Active Level address</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENAF0</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF1</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF2</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF3</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF4</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF5</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF6</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF7</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RISE</name>
|
|
<description>Pin Interrupt Rising Edge register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDET0</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET1</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET2</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET3</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET4</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET5</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET6</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET7</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FALL</name>
|
|
<description>Pin Interrupt Falling Edge register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FDET0</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET1</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET2</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET3</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET4</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET5</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET6</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET7</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IST</name>
|
|
<description>Pin Interrupt Status register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTAT0</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT1</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT2</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT3</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT4</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT5</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT6</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT7</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSP0">
|
|
<name>SSP1</name>
|
|
<baseAddress>0x40058000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSP1</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIO_GROUP_INT0</name>
|
|
<description>GPIO group interrupt</description>
|
|
<groupName>GPIO_GROUP_INT0</groupName>
|
|
<baseAddress>0x4005C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>GPIO grouped interrupt control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_REQUEST</name>
|
|
<description>No interrupt request is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_REQUEST_IS</name>
|
|
<description>Interrupt request is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMB</name>
|
|
<description>Combine enabled inputs for group interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR_FUNCTIONALITY_A_</name>
|
|
<description>OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND_FUNCTIONALITY_A</name>
|
|
<description>AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>Group interrupt trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_TRIGGERED</name>
|
|
<description>Edge-triggered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_TRIGGERED</name>
|
|
<description>Level-triggered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PORT_POL%s</name>
|
|
<description>GPIO grouped interrupt port 0 polarity register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL_0</name>
|
|
<description>Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_1</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_2</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_3</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_4</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_5</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_6</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_7</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_8</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_9</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_10</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_11</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_12</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_13</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_14</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_15</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_16</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_17</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_18</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_19</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_20</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_21</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_22</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_23</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_24</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_25</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_26</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_27</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_28</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_29</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_30</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_31</name>
|
|
<description>Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PORT_ENA%s</name>
|
|
<description>GPIO grouped interrupt port 0/1 enable register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA_0</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_1</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_2</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_3</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_4</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_5</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_6</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_7</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_8</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_9</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_10</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_11</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_12</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_13</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_14</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_15</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_16</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_17</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_18</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_19</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_20</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_21</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_22</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_23</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_24</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_25</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_26</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_27</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_28</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_29</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_30</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_31</name>
|
|
<description>Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO_GROUP_INT0">
|
|
<name>GPIO_GROUP_INT1</name>
|
|
<baseAddress>0x40060000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description>USB2.0 device controller </description>
|
|
<groupName>USB</groupName>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB_IRQ</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_FIQ</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBWAKEUP</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DEVCMDSTAT</name>
|
|
<description>USB Device Command/Status register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_ADDR</name>
|
|
<description>USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DEV_EN</name>
|
|
<description>USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PLL_ON</name>
|
|
<description>Always PLL Clock on:</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USB_NEEDCLK_FUNCTION</name>
|
|
<description>USB_NeedClk functional</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_NEEDCLK_ALWAYS_1</name>
|
|
<description>USB_NeedClk always 1. Clock will not be stopped in case of suspend.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_SUP</name>
|
|
<description>LPM Supported:</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LPM_NOT_SUPPORTED_</name>
|
|
<description>LPM not supported.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_SUPPORTED_</name>
|
|
<description>LPM supported.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_AO</name>
|
|
<description>Interrupt on NAK for interrupt and bulk OUT EP</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACKNOW</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKNOW_NAK</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_AI</name>
|
|
<description>Interrupt on NAK for interrupt and bulk IN EP</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACKNOW</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKNOW_NAK</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_CO</name>
|
|
<description>Interrupt on NAK for control OUT EP</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACKNOW</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKNOW_NAK</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTONNAK_CI</name>
|
|
<description>Interrupt on NAK for control IN EP</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACKNOW</name>
|
|
<description>Only acknowledged packets generate an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKNOW_NAK</name>
|
|
<description>Both acknowledged and NAKed packets generate interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCON</name>
|
|
<description>Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSUS</name>
|
|
<description>Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_SUS</name>
|
|
<description>Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LPM_REWP</name>
|
|
<description>LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCON_C</name>
|
|
<description>Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSUS_C</name>
|
|
<description>Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DRES_C</name>
|
|
<description>Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VBUSDEBOUNCED</name>
|
|
<description>This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INFO</name>
|
|
<description>USB Info register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAME_NR</name>
|
|
<description>Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERR_CODE</name>
|
|
<description>The error code which last occurred:</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PID_ENCODING_ERROR</name>
|
|
<description>PID encoding error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PID_UNKNOWN</name>
|
|
<description>PID unknown</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET_UNEXPECTED</name>
|
|
<description>Packet unexpected</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOKEN_CRC_ERROR</name>
|
|
<description>Token CRC error</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_CRC_ERROR</name>
|
|
<description>Data CRC error</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIME_OUT</name>
|
|
<description>Time out</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BABBLE</name>
|
|
<description>Babble</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRUNCATED_EOP</name>
|
|
<description>Truncated EOP</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENTRECEIVED_NAK</name>
|
|
<description>Sent/Received NAK</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENT_STALL</name>
|
|
<description>Sent Stall</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVERRUN</name>
|
|
<description>Overrun</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SENT_EMPTY_PACKET</name>
|
|
<description>Sent empty packet</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BITSTUFF_ERROR</name>
|
|
<description>Bitstuff error</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC_ERROR</name>
|
|
<description>Sync error</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRONG_DATA_TOGGLE</name>
|
|
<description>Wrong data toggle</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPLISTSTART</name>
|
|
<description>USB EP Command/Status List start address</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP_LIST</name>
|
|
<description>Start address of the USB EP Command/Status List.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATABUFSTART</name>
|
|
<description>USB Data buffer start address</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[21:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DA_BUF</name>
|
|
<description>Start address of the buffer pointer page where all endpoint data buffers are located.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPM</name>
|
|
<description>Link Power Management register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HIRD_HW</name>
|
|
<description>Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIRD_SW</name>
|
|
<description>Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_PENDING</name>
|
|
<description>As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPSKIP</name>
|
|
<description>USB Endpoint skip</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SKIP</name>
|
|
<description>Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINUSE</name>
|
|
<description>USB Endpoint Buffer in use</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUF</name>
|
|
<description>Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1.</description>
|
|
<bitRange>[9:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPBUFCFG</name>
|
|
<description>USB Endpoint Buffer Configuration register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUF_SB</name>
|
|
<description>Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer.</description>
|
|
<bitRange>[9:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>USB interrupt status register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP0OUT</name>
|
|
<description>Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP0IN</name>
|
|
<description>Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP1OUT</name>
|
|
<description>Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP1IN</name>
|
|
<description>Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP2OUT</name>
|
|
<description>Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP2IN</name>
|
|
<description>Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP3OUT</name>
|
|
<description>Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP3IN</name>
|
|
<description>Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP4OUT</name>
|
|
<description>Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EP4IN</name>
|
|
<description>Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_INT</name>
|
|
<description>Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_INT</name>
|
|
<description>Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>USB interrupt enable register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_INT_EN</name>
|
|
<description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSETSTAT</name>
|
|
<description>USB set interrupt status register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAME_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_SET_INT</name>
|
|
<description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTROUTING</name>
|
|
<description>USB interrupt routing register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ROUTE_INT9_0</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROUTE_INT30</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROUTE_INT31</name>
|
|
<description>This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPTOGGLE</name>
|
|
<description>USB Endpoint toggle register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPIO_PORT</name>
|
|
<description>GPIO port </description>
|
|
<groupName>GPIO_PORT</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFfFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>B0%s</name>
|
|
<description>Byte pin registers port 0; pins PIO0_0 to PIO0_31</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBYTE</name>
|
|
<description>Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>32-63</dimIndex>
|
|
<name>B1%s</name>
|
|
<description>Byte pin registers port 1</description>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBYTE</name>
|
|
<description>Read: state of the pin P1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-31</dimIndex>
|
|
<name>W%s</name>
|
|
<description>Word pin registers port 0</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWORD</name>
|
|
<description>Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>32-63</dimIndex>
|
|
<name>W%s</name>
|
|
<description>Word pin registers port 1</description>
|
|
<addressOffset>0x1080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWORD</name>
|
|
<description>Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>DIR%s</name>
|
|
<description>Direction registers port 0/1</description>
|
|
<addressOffset>0x2000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRP0</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP1</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP2</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP3</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP4</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP5</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP6</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP7</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP8</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP9</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP10</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP11</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP12</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP13</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP14</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP15</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP16</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP17</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP18</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP19</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP20</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP21</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP22</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP23</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP24</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP25</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP26</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP27</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP28</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP29</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP30</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP31</name>
|
|
<description>Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>Mask register port 0/1</description>
|
|
<addressOffset>0x2080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASKP0</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP1</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP2</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP3</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP4</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP5</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP6</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP7</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP8</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP9</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP10</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP11</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP12</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP13</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP14</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP15</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP16</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP17</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP18</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP19</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP20</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP21</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP22</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP23</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP24</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP25</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP26</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP27</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP28</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP29</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP30</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP31</name>
|
|
<description>Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>PIN%s</name>
|
|
<description>Portpin register port 0</description>
|
|
<addressOffset>0x2100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORT0</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT1</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT2</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT3</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT4</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT5</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT6</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT7</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT8</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT9</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT10</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT11</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT12</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT13</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT14</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT15</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT16</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT17</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT18</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT19</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT20</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT21</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT22</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT23</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT24</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT25</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT26</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT27</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT28</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT29</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT30</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT31</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>MPIN%s</name>
|
|
<description>Masked port register port 0/1</description>
|
|
<addressOffset>0x2180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPORTP0</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP1</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP2</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP3</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP4</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP5</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP6</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP7</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP8</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP9</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP10</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP11</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP12</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP13</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP14</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP15</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP16</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP17</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP18</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP19</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP20</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP21</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP22</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP23</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP24</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP25</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP26</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP27</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP28</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP29</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP30</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP31</name>
|
|
<description>Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>SET%s</name>
|
|
<description>Write: Set register for port 0/1 Read: output bits for port 0/1</description>
|
|
<addressOffset>0x2200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETP0</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP1</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP2</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP3</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP4</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP5</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP6</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP7</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP8</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP9</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP10</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP11</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP12</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP13</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP14</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP15</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP16</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP17</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP18</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP19</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP20</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP21</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP22</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP23</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP24</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP25</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP26</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP27</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP28</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP29</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP30</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP31</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>CLR%s</name>
|
|
<description>Clear port 0/1</description>
|
|
<addressOffset>0x2280</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRP00</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP01</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP02</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP03</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP04</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP05</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP06</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP07</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP08</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP09</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP010</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP011</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP012</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP013</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP014</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP015</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP016</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP017</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP018</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP019</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP020</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP021</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP022</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP023</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP024</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP025</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP026</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP027</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP028</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP029</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP030</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP031</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>NOT%s</name>
|
|
<description>Toggle port 0/1</description>
|
|
<addressOffset>0x2300</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOTP0</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP1</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP2</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP3</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP4</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP5</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP6</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP7</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP8</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP9</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP10</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP11</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP12</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP13</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP14</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP15</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP16</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP17</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP18</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP19</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP20</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP21</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP22</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP23</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP24</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP25</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP26</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP27</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP28</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP29</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP30</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP31</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|